JP3174027B2 - Signal level conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a signal level conversion circuit using a thin film transistor.

[0002]

2. Description of the Related Art FIG. 2A shows an example of a conventional signal level conversion circuit. The signal level conversion circuit 201 includes an integrated circuit using a thin film transistor, such as an active matrix type liquid crystal display device, and a CMOS that generates a control signal for the integrated circuit.
It is used as an interface circuit with a controller composed of an integrated circuit such as a gate array.

The signal level conversion circuit 201 has two n-channel thin film transistor input transistors 205,
206 and load transistors 207 and 2 of p-channel thin film transistors constituting a current mirror circuit
08.

A gate of the input transistor 205 is connected to a controller 202 composed of an integrated circuit such as a CMOS gate array for generating a logic signal, to which an input signal 203 is applied. 203 inverted signal 20
4 is applied.

A thin film transistor has a threshold voltage of about 3 volts, and a power supply voltage of an integrated circuit using the thin film transistor is about 15 volts. On the other hand, the power supply voltage of the controller 202 is a power supply voltage of about 3 to 5 volts, the output signal 203 and the inverted signal 204 have the same amplitude of about 3 to 5 volts. It is smaller than the power supply voltage of the integrated circuit used.

[0006] The signal level conversion circuit 201 receives the input signal 2
When 03 is at a high level, the input transistor 205 is turned on, and a drain current flows through the load transistor 207 to turn on the transistor 208. At this time, a low level which is an inverted signal 204 of the input signal 203 is given to the input transistor 206, and the power supply voltage of the signal level conversion circuit 201 is output as the output signal 209 by turning off the input transistor 206.

When the input signal 203 is at a low level,
The input transistor 205 turns off and the load transistor 2
07, no drain current flows, and the transistor 208 is turned off. At this time, a high level which is an inverted signal 204 of the input signal 203 is given to the input transistor 206, and the ground voltage of the signal level conversion circuit 201 is output as the output signal 209 by turning on the input transistor 206.

[0008] Thus, the signal level conversion circuit 201
Is an input signal 203 having a low signal amplitude and its inverted signal 204
Is converted into an output signal 209 having a high amplitude as high as the power supply voltage of the thin film transistor integrated circuit.
Reference numeral 9 is used as an input of an integrated circuit composed of another thin film transistor.

FIG. 2B shows another example of the conventional level conversion circuit, which has the same function as that of FIG.
The same numbers as in FIG. In FIG. 2B, the gates of the load transistors 207 and 208 are connected to the drains of the other input transistors 205 and 206, respectively.

The signal level conversion circuit 2 shown in FIG.
In the case of 01, when the input signal 203 is at a high level, the input transistor 205 is turned on and the voltage at the drain of the input transistor 205 is lowered, so that the transistor 208 is turned on. At this time, the input signal 203 is input to the other input transistor 206.
When the input transistor 206 is turned off when a low level, which is the inverted signal 204, is given, the drain voltage of the input transistor 206 rises, the transistor 207 is turned off, and the output signal 209 is the power supply voltage of the signal level conversion circuit 201.

When the input signal 203 is at a low level, the input transistor 205 is turned off, and the transistor 208 is turned off by increasing the drain voltage.
At this time, the input signal 2 is applied to the other input transistor 206.
When the input transistor 206 is turned on when a high level, which is the inverted signal 204 of 03, is given, the drain voltage of the input transistor 206 is reduced, and the transistor 207 is turned on.
Is output.

Thus, in FIG. 2B, FIG.
As in (a), the signal level conversion circuit 201 converts the input signal 203 having a low signal amplitude and the inverted signal 204 thereof into an output signal 209 having a high amplitude as high as the power supply voltage of the thin film transistor integrated circuit.
This is a function of converting the signal amplitude into a value.

[0013]

However, the conventional signal level conversion circuit 201 shown in FIG. 2A or 2B is a CMOS signal level conversion circuit of a low signal amplitude input-high signal amplitude output. When used for an interface between a thin film transistor integrated circuit and a controller such as a gate array, the input transistors 205 and 20 are used.
6 is substantially equal to the input signal amplitude, and when the input signal amplitude is smaller than the threshold value of the input transistor, the input transistor cannot be turned on and does not function as a signal conversion circuit. For this reason, there is a problem that it is not possible to cope with an interface with a controller whose voltage is lowered.

FIG. 5A shows the threshold characteristics of an input transistor in which the horizontal axis represents the gate voltage and the vertical axis represents the route of the drain current. Below the threshold voltage, the drain current does not flow.
When the voltage exceeds the threshold voltage, the drain current increases in proportion to the square of the gate voltage. This indicates that the input transistor cannot be turned on when the amplitude of the input signal is equal to or less than the threshold voltage of the input transistor.

When the amplitude of the input signal is slightly larger than the threshold value of the input transistor, it is possible to turn on the input transistor. However, a sufficient drain current cannot be obtained, and a higher speed input signal can be handled. There is a problem that the signal level conversion cannot be performed.

To solve such a problem, Japanese Patent Laid-Open No.
Japanese Patent No. 216753 discloses that an input signal is supplied to a source terminal of the transistor by using a transistor, an offset voltage corresponding to a threshold voltage of the transistor is added to the input signal, and the input signal is applied to an input transistor of a level conversion circuit to reduce an ON current of the input transistor. Although the size is increased to reduce the signal amplitude of the input signal and speed up the signal level conversion, a new problem that an input drive current is required occurs in this configuration.

FIG. 3 schematically shows the embodiment described in Japanese Patent Application Laid-Open No. 6-216753, and those having the same functions as those in FIG. 2 are given the same numbers as in FIG. The configuration of FIG. 3 will be described briefly.

In FIG. 3, reference numeral 301 denotes the entire signal level conversion circuit, and reference numeral 202 denotes a controller. The signal level conversion circuit 301 and the controller 202 are connected by an input signal 203 and its inverted signal 204. Reference numeral 201 denotes a current mirror type signal level conversion circuit shown in the conventional example in FIG. 2A, which comprises n-channel input transistors 205 and 206 and p-channel load transistors 207 and 208.

The input signal 203 is connected to the source of an n-channel transistor 306, and the inverted signal 204 is connected to the source of an n-channel transistor 307. The gates and drains of the transistors 306 and 307 are connected, and the
Are connected to the gates of the input transistors 205 and 206. 302 and 303 are current sources and transistors 30
6,307 is driven.

A threshold voltage of the transistor is generated between the source and the drain of the transistors 306 and 307, and the threshold voltage is added to the input signal so that the input transistors 205 and 20
By applying the gate of 6, the on-state current of the input transistors 205 and 206 can be made sufficiently large even in the case of a low input signal amplitude, and the circuit can be speeded up.

However, transistors 306 and 30
7 is on, the currents of the current sources 302 and 303 pass through the input signals 203 and 204 to the signal level conversion circuit 301.
And flows into the controller 202.

In many cases, the controller 202 is a CMOS gate array and its output terminal is of an inverter configuration. The current flowing at the time of high level output causes such a large amount of current as to cause a problem such as latch-up due to its structure. I can't shed. In order to further increase the speed of the circuit, it is necessary to supply a sufficient current to the transistors 306 and 307, and this input drive current needs to be kept low in the controller, thus causing conflicting problems.

The signal level conversion circuit of the present invention solves the above-mentioned problems by reducing the input drive current,
It is an object of the present invention to increase the speed of a signal level conversion circuit even in the case of a low input amplitude.

[0024]

A signal level conversion circuit according to the present invention uses a source follower transistor and a current source for a signal level conversion means for converting an input signal having a low signal amplitude into an output signal having a high signal amplitude. A bias voltage is applied to the input signal having the low signal amplitude, and the bias voltage is applied to the gate of the input transistor of the level conversion means.

With this configuration, the input signal and the inverted input signal from the controller to the signal level conversion circuit become the gate input of the source follower, and do not require a drive current except for a small current for charging and discharging the gate capacitance of the transistor. A threshold voltage of the transistor is generated between the gate and the source of the transistor of the source follower, and a bias voltage corresponding to the threshold voltage is added to the input signal and applied to the gate of the input transistor of the conventional level conversion circuit.
The on-current of the input transistor can be sufficiently increased even in the case of a low input signal amplitude by increasing the gate-source voltage when the input transistor is on, and the circuit can be operated at higher speed. In this way, a signal level conversion circuit that realizes high-speed operation while reducing the input drive current is realized.

[0026]

According to a first aspect of the present invention, in an integrated circuit using thin film transistors, signal level conversion means for converting an input signal having a low signal amplitude into an output signal having a high signal amplitude is provided, and A bias means for applying a bias voltage to apply to a gate of an input transistor of the level conversion means is provided, and the bias means is constituted by using a current source and a source follower transistor. According to this configuration, the input signal and the inverted input signal from the controller to the signal level conversion circuit become the gate input of the source follower, and do not require a drive current except for a small current for charging and discharging the gate capacitance of the transistor. A threshold voltage of the transistor is generated between the gate and the source of the transistor of the source follower, and a bias voltage corresponding to the threshold voltage is added to the input signal and applied to the gate of the input transistor of the conventional level conversion circuit. In this case, the ON-state current of the input transistor can be sufficiently increased even in the case of a low input signal amplitude by increasing the gate-source voltage at the time of ON, and has the effect of increasing the speed of the circuit.

According to a second aspect of the present invention, in an integrated circuit using thin film transistors, signal level conversion means for converting an input signal having a low signal amplitude into an output signal having a high signal amplitude is provided, and a bias voltage is applied to the input signal. In addition, bias means for applying to the gate of the input transistor of the level conversion means is provided, and the bias means is constituted by using a current source and a source follower transistor, and the input signal is inverted at the source of the input transistor. A signal is applied.

According to this configuration, the input signal and the input inversion signal from the controller to the signal level conversion circuit become the gate input of the source follower, and require a drive current except for a small current for charging and discharging the gate capacitance of the transistor. do not do. A threshold voltage of the transistor is generated between the gate and the source of the transistor of the source follower, and a bias voltage corresponding to the threshold voltage is added to the input signal and applied to the gate of the input transistor of the conventional level conversion circuit.
The on-state current of the input transistor can be sufficiently increased by increasing the gate-source voltage when the input transistor is on. On the other hand, an input signal and an input inversion signal from the controller to the signal level conversion circuit are also provided to the source of the input transistor of the conventional level conversion circuit, and the input signal is subtracted from the gate-source voltage of the input transistor to thereby obtain an input signal. The off-state current of the input transistor can be sufficiently reduced by reducing the gate-source voltage when the transistor is off.
As described above, the voltage applied between the gate and the source of the input transistor is twice the amplitude of the input signal, and the ratio of the on-off current can be increased by optimally selecting the biased voltage. And has the effect that the circuit speed can be increased even in the case of a low input signal amplitude. In addition, the input drive current by applying an input inversion signal to the source terminal of the input transistor is required when the input inversion signal is at a low level, but does not require or generate a drive current when the input inversion signal is at a high level. A direct interface with is possible.

According to a third aspect of the present invention, in the first aspect, a bias voltage generated by a transistor of a source follower is set to a voltage equivalent to a threshold value of the input transistor.

According to this configuration, by setting the bias voltage applied to the input signal as the threshold value of the input transistor, the signal applied between the gate and the source of the input transistor is biased by the threshold voltage of the input transistor, and the ON-state voltage is applied. This has the effect of optimizing the ratio of off-current to a maximum.

According to a fourth aspect of the present invention, in the second aspect, the bias voltage generated by the transistor of the source follower is set to a voltage equivalent to a voltage obtained by adding the threshold value of the input transistor and the amplitude of the input signal. Features.

According to this configuration, the signal applied between the gate and source of the input transistor is biased by setting the bias voltage applied to the input signal to a voltage obtained by adding the threshold value of the input transistor and the amplitude of the input signal. , Has the effect of optimizing the ratio of the on-off current to the maximum.

According to a fifth aspect of the present invention, in the first or second aspect, the current source is constituted by a transistor element or a resistance element. According to this configuration, a desired current source can be easily formed in the same manufacturing process in the thin film transistor integrated circuit.

According to a sixth aspect of the present invention, in the first or second aspect, the level conversion means is constituted by a crossing circuit or a current mirror circuit. According to this configuration, the switching operation of the current mirror circuit is stable even if the threshold voltage of the transistor varies to some extent. Therefore, a signal level conversion circuit that operates stably even when the threshold value of the thin film transistor varies greatly is realized. Further, according to the configuration in which the signal level conversion means is a crossing circuit, the crossing circuit requires current consumption only at the time of signal switching, so that a signal level conversion circuit with low power consumption can be realized.

According to a seventh aspect of the present invention, in the active matrix type liquid crystal display device, the signal level conversion circuit according to the first or second aspect is incorporated as a signal level conversion circuit.

According to this structure, the liquid crystal display element using the thin film transistor and the signal level conversion circuit can be manufactured by the same manufacturing process, and a general low power supply voltage without a special interface element is used. A direct interface with a CMOS circuit can be made possible.

Hereinafter, embodiments of the present invention will be described. (Embodiment 1) Embodiment 1 of the present invention will be described with reference to FIGS. 1, 5, 6, and 7. FIG.

FIG. 1 shows a signal level conversion circuit according to the first embodiment of the present invention. FIG. 1 shows a conventional example in FIG.
The same parts as those in FIG.

Reference numeral 301 denotes the entire signal level conversion circuit.
Reference numeral 202 denotes a controller. Signal level conversion circuit 30
1 and the controller 202 are connected by an input signal 203 and its inverted signal 204. Reference numeral 201 denotes a current mirror type signal level conversion circuit shown in the conventional example in FIG. 2A, which comprises n-channel input transistors 205 and 206 and p-channel load transistors 207 and 208.

The input signal 203 is connected to the gate of the p-channel transistor 101, and the inverted signal 204 is connected to the gate of the p-channel transistor 102. The drains of the transistors 101 and 102 are connected to the ground, and the current sources 302 and 303 are connected to the sources of the transistors 101 and 102 to drive the transistors 101 and 102 to form a source follower circuit. The sources of the transistors 101 and 102 are connected to the gates of the input transistors 205 and 206 of the conventional signal level conversion circuit 201.

In the embodiment of the present invention, similarly to the conventional example, the thin film transistor has a threshold voltage of about 3 volts, and the power supply voltage of an integrated circuit using this thin film transistor is about 15 volts. On the other hand, the power supply voltage of the controller 202 is a power supply voltage of about 3 to 5 volts, and its output signal and its inverted signal, 20
The amplitude of 3,204 is about 3 to 5 volts, which is about the same, and is smaller than the threshold voltage of the thin film transistor and the power supply voltage of the integrated circuit using the thin film transistor.

Hereinafter, the operation of the first embodiment of the present invention will be described. Input signal 203 and input inverted signal 204
Is applied to the gates of the transistors 101 and 102 of the source follower, a threshold voltage of the transistor is generated between the gates and the sources of the transistors 101 and 102. A signal obtained by adding the threshold voltage to the input signal as a bias voltage is applied to the transistors 101 and 102. It is generated at the source of 102 and applied to the gates of input transistors 205 and 206.

When the signal voltages of the input signal 203 and the input inversion signal 204 are at low level, the voltage is set to 0 volt as the same as the ground voltage, and when the signal voltage is at high level, the input amplitude voltage V
IN and the source follower transistors 101 and 10
2 is Vtp, the signal voltage generated at the sources of the source follower transistors 101 and 102 is the input signal 203. When the input inverted signal 204 is at a low level, the voltage Voff equal to the threshold voltage Vtp is applied to the input signal 203, When the input inversion signal 204 is at a high level, the voltage V obtained by adding the input amplitude VIN to the threshold voltage Vtp
on occurs. That is, the input signal is a signal biased by the threshold voltage Vtp of the transistor.

A signal obtained by biasing the above-mentioned input signal with the threshold voltage of the source follower transistor is applied to the gates of the input transistors 205 and 206 of the signal level conversion circuit 201.

When the input signal 203 is at a high level, the voltage between the gate and the source of the input transistor 205 is Vo.
When a voltage of n = Vtp + VIN is applied and the voltage Von applied between the gate and the source is larger than the threshold voltage of the input transistor 205, the input transistor 205 is turned on, a drain current flows through the load transistor 207, and the transistor 208 Turn on.

At this time, the input inversion signal 204 becomes low level, the voltage between the gate and the source of the other input transistor 206 is Voff = Vtp, and the voltage Voff applied between the gate and the source is the input transistor 206. If it is equal to or less than the threshold voltage of 205, the input transistor 206 turns off.

The output voltage level is the load transistor 208
The output signal 209 is determined by the ratio between the ON current of the input transistor 206 and the OFF current of the input transistor 206,
A voltage substantially equal to the power supply voltage of 01 is output.

When the input signal 203 is at a low level, a voltage of Voff = Vtp is applied to the gate-source voltage of the input transistor 205, the input transistor turns off, and a drain current flows through the load transistor 207. Transistor 208 is turned off.

At this time, the input inversion signal 204 becomes high level, the voltage between the gate and the source of the other input transistor 206 is applied as Von = Vtp + VIN, and the input transistor 206 is turned on.

The output voltage level is determined by the load transistor 208
The output signal 209 is determined by the ratio of the off current of the input transistor 206 to the on current of the input transistor 206.
The output is almost equal to the ground voltage of 01.

As described above, the signal level conversion circuit of the present invention uses the input signal 203 having a low signal amplitude and its inverted signal 20.
4 can be converted into an output signal 209 having a high amplitude as high as the power supply voltage of the thin film transistor integrated circuit.

FIG. 6 shows a specific circuit configuration of the current source 302. FIG. 6 (a) shows a case where the current source is a resistance element.
(B) was made of a transistor. According to this configuration, a desired current source can be easily formed in the thin film transistor integrated circuit by the same manufacturing process.

FIG. 5B is a diagram showing the threshold characteristics and operating points of the input transistor according to the first embodiment of the present invention, and the horizontal axis indicates the gate similarly to FIG. 5A which is a conventional example. The graph shows the threshold characteristics of the input transistor, where the voltage is the voltage and the vertical axis is the route of the drain current. When the input signal 203 and the input inverted signal 204 are at a high level, a voltage of Von = Vtp + Vin is applied to the gate-source voltage of the input transistors 205 and 206, and the transistors 205 and 206 are turned on. Input signal 203,
When the input inversion signal 204 is at a low level, the voltage between the gate and source of the input transistors 205 and 206 is Vo.
When a voltage of ff = Vtp is applied, transistors 205,
206 is turned off.

In the first embodiment of the present invention, since the input signal is biased at the operating point by the threshold value of the transistor of the source follower circuit, the input signal corresponds to the on-state voltage Von as compared with the conventional example of FIG. Thus, the ratio of the on-state current to the off-state current corresponding to the off-state voltage Voff can be increased, and high-speed operation can be performed even with an input signal having a small signal amplitude.

In addition, in the first embodiment of the present invention, the threshold voltage Vtp of the source follower transistors 101 and 102 is set to a value equivalent to the threshold voltage Vtn of the input transistors 205 and 206, so that the input signal The applied bias voltage is applied to the input transistors 205 and 206.
And the ratio of the on-off current could be maximized.

In the present invention, the bias voltage is adjusted in accordance with the threshold voltage Vtp of the source follower transistors 101 and 102 according to the threshold voltage Vtn of the input transistor, but a resistor is provided between the current source and the sources of the transistors 101 and 102. Even if a bias voltage is generated by inserting a diode or a diode, and the voltage is adjusted so as to be equal to the threshold voltage of the input transistors 205 and 206, the principle does not change (the first embodiment).

FIG. 7A shows the voltage waveform of the first embodiment. Reference numerals 701 and 702 show the voltage waveforms of the input signal 203 and its inverted signal 204. Reference numerals 703 and 704 denote the source terminals of the source follower transistors 101 and 102 and the waveforms of the gate terminals of the input transistors 205 and 206. The input signal 203 and its inverted signal 204 output the threshold voltage Vt of the source follower transistors 101 and 102.
The signal waveform is biased by p. Reference numeral 706 denotes a voltage waveform of the output terminal 209 of the first embodiment.

FIG. 7B shows a drive current waveform of the input signal 203 and its inverted signal 204 in (Embodiment 1). The direction in which the current flows out of the controller 202 and flows into the signal level conversion circuit 301 is defined as the + direction. The direction in which the signal flows from the signal level conversion circuit 301 and flows into the controller 201 is defined as a negative direction.

707 is a current waveform of the input signal 203;
08 is a current waveform of the inverted input signal 204. In any of the current waveforms 707 and 708, no steady drive current flows except for a small current for charging and discharging the gate capacitance of the source follower transistors 101 and 102.

As described above, a signal level conversion circuit in which the input drive current is reduced and high-speed operation is realized can be realized. Note that FIG.
It goes without saying that the same function can be obtained by using the crossing type signal level conversion circuit shown in the conventional example of FIG.

(Embodiment 2) FIG. 4 shows a configuration of a signal level conversion circuit according to (Embodiment 2) of the present invention. explain.

Reference numeral 301 denotes the entire signal level conversion circuit.
Reference numeral 202 denotes a controller. Signal level conversion circuit 30
1 and the controller 202 are connected by an input signal 203 and its inverted signal 204. Reference numeral 201 denotes a current mirror type signal level conversion circuit shown in the conventional example in FIG. 2A, which comprises n-channel input transistors 205 and 206 and p-channel load transistors 207 and 208.

The input signal 203 is connected to the gate of the p-channel transistor 101, and the inverted signal 204 is connected to the gate of the p-channel transistor 102. The drains of the transistors 101 and 102 are connected to the ground, and the current sources 302 and 303 are connected to the sources of the transistors 101 and 102 to drive the transistors 101 and 102 to form a source follower circuit.

The sources of the transistors 101 and 102 are connected to the gates of the input transistors 205 and 206 of the conventional signal level conversion circuit 201, and the sources of the input transistors 205 and 206 receive the input inverted signal 204 and the input signal 203, respectively. It is configured to be connected.

In the embodiment of the present invention, similarly to the conventional example, the thin film transistor has a threshold voltage of about 3 volts, and the power supply voltage of an integrated circuit using this thin film transistor is about 15 volts. On the other hand, the power supply voltage of the controller 202 is a power supply voltage of about 3 to 5 volts, and its output signal and its inverted signal, 20
The amplitude of 3,204 is about 3 to 5 volts, which is about the same, and is smaller than the threshold voltage of the thin film transistor and the power supply voltage of the integrated circuit using the thin film transistor.

The operation of the second embodiment of the present invention will be described below. Input signal 203 and input inverted signal 204
Is applied to the gates of the transistors 101 and 102 of the source follower, a threshold voltage of the transistor is generated between the gates and the sources of the transistors 101 and 102. A signal obtained by adding the threshold voltage to the input signal as a bias voltage is applied to the transistors 101 and 102. It is generated at the source of 102 and applied to the gates of input transistors 205 and 206.

The case where the signal voltage of the input signal 203 and the input inverted signal 204 is the low level is the same as the ground voltage, which is 0 volt, and the case where the signal voltage is the high level is the input amplitude voltage V
IN and the source follower transistors 101 and 10
2 is Vtp, the signal voltage generated at the sources of the source follower transistors 101 and 102 is a voltage Voff equal to the threshold voltage Vtp when the input signal 203 and the input inversion signal 204 are at a low level. When the input inversion signal 204 is at a high level, the voltage V obtained by adding the input amplitude VIN to the threshold voltage Vtp
on occurs. That is, the input signal is a signal biased by the threshold voltage Vtp of the transistor.

A signal obtained by biasing the above-mentioned input signal with the threshold voltage of the source follower transistor is applied to the gates of the input transistors 205 and 206 of the signal level conversion circuit 201, and the input of the input transistors 205 and 206 is inverted. Signal 204, input signal 203
Is connected.

When the input signal 203 is at the high level, the voltage of Vtp + VIN is applied to the gate of the input transistor 205, and the ground voltage, which is the low level voltage of the input inverted signal 204, is applied to the source of the input transistor 205. Therefore, a voltage of Von = Vtp + VIN is applied to the voltage between the gate and the source, and the voltage Von applied between the gate and the source is applied to the input transistor 20.
5, the input transistor 205
Turns on, and a drain current flows through the load transistor 207 to turn on the transistor 208.

At this time, the input inversion signal 204 is at the low level, the voltage of Vtp is applied to the gate of the other input transistor 206, and the source of the input transistor 206 is VIN, which is the high level voltage of the input signal 203.
Is applied. Therefore, the other input transistor 2
The voltage between the gate and the source of 06 is Voff = Vtp−V
When the voltage of IN is applied and the voltage Voff applied between the gate and the source is equal to or less than the threshold voltage of the input transistor 205, the input transistor 20
6 turns off.

The output voltage level is determined by the load transistor 208
The output signal 206 is output at a voltage substantially equal to the power supply voltage of the signal level conversion circuit.

Similarly, when the input signal 203 is at a low level, a voltage of Voff = Vtp−VIN is applied to the gate-source voltage of the input transistor 205.
The input transistor turns off, no drain current flows through the load transistor 207, and the transistor 208 turns off.

At this time, the input inversion signal 204 becomes high level, the voltage between the gate and the source of the other input transistor 206 is applied as Von = Vtp + VIN, and the input transistor 206 is turned on.

The output voltage level is determined by the load transistor 208
The output signal 209 is substantially equal to the ground voltage of the signal level conversion circuit, and is output.

As described above, the signal level conversion circuit of the present invention comprises the input signal 203 having a low signal amplitude and the inverted signal 20 of the input signal 203.
4 can be converted into an output signal 209 having a high amplitude as high as the power supply voltage of the thin film transistor integrated circuit.

FIG. 6A shows a case where the current source 302 is made of a resistor, and FIG. 6B shows a case where the current source 302 is made of a transistor. According to this configuration, a desired current source can be easily formed in the same manufacturing process in the thin film transistor integrated circuit.

FIG. 5C is a diagram showing threshold characteristics and operating points of the input transistor according to the second embodiment of the present invention. FIG. 5A showing a conventional example and FIG. Similarly to 1), the horizontal axis represents the gate voltage, and the vertical axis represents the route of the drain current, showing the threshold characteristics of the input transistor. Input signal 203, input inverted signal 2
04 is high level, the input transistor 205,
The gate-source voltage of 206 is Von = Vtp + V
The voltage of “in” is applied to turn on the transistors 205 and 206. When the input signal 203 and the input inverted signal 204 are at a low level, a voltage of Voff = Vtp−VIN is applied to the gate-source voltage of the input transistors 205 and 206, and the transistors 205 and 206 are turned off.

In the second embodiment of the present invention, since the operating point of the input signal is biased by the threshold value of the transistor of the source follower circuit, the input signal is turned on and the input transistor is turned off. The difference is that the inverted signal is added to the source terminal of the input transistor, so that the input amplitude VIN in the case of the conventional example and the input amplitude VIN in the first embodiment of the present invention is changed in the second embodiment of the present invention. It is twice as wide as 2VIN, and compared with the conventional example and the first embodiment of the present invention,
ON current and OFF voltage Voff corresponding to ON voltage Von
Can be increased, and a high-speed operation can be performed even with an input signal having a small signal amplitude.

In addition, in the second embodiment of the present invention, the threshold voltage Vtp of the source follower transistors 101 and 102 is equal to the threshold voltage Vtn of the input transistors 205 and 206 plus the amplitude of the input signal. With this value, the off-state gate voltage Voff applied to the input transistors 205 and 206 is made equal to the threshold voltage Vtn of the input transistor, a bias voltage applied to the input signal is given, and the ratio of the on-off current is reduced. Could be maximized.

In the present invention, the bias voltage is adjusted by the threshold voltage Vtp of the source follower transistors 101 and 102.
A bias voltage is generated by inserting a resistor or a diode between the input transistor 1
Even if the adjustment is made so as to be equal to the threshold voltages 05 and 206, the present invention is not changed in principle.

FIG. 7A shows the voltage waveform of (Embodiment 2), and 701 and 702 show the voltage waveforms of the input signal 203 and its inverted signal 204. Reference numerals 703 and 704 denote the source terminals of the source follower transistors 101 and 102 and the waveforms of the gate terminals of the input transistors 205 and 206. The input signal 203 and its inverted signal 204 correspond to the threshold voltage Vt of the source follower transistors 101 and 102.
The signal waveform is biased by p. 705 is a voltage waveform of the output terminal 209.

FIG. 7C shows the drive current waveforms of the input signal 203 and its inverted signal 204.
The direction in which the signal flows out of the signal level conversion circuit 301 and flows into the signal level conversion circuit 301 is defined as a positive direction, and the direction in which the signal flows from the signal level conversion circuit 301 and flows into the controller 201 is defined as a negative direction.

709 is a current waveform of the input signal 203;
10 is a current waveform of the inverted input signal 204. 709,
710 includes source follower transistors 101 and 10
In addition to the charge / discharge current of the gate capacitance of No. 2, when the controller outputs a low level, a current flows out of the stationary signal level conversion circuit and flows into the controller. This current is allowed as a low level drive current of the controller. It does not matter.

The current flowing out of the signal level conversion circuit which has been a problem in the interface with the controller and flowing into the controller output at the time of high level output does not flow in the second embodiment, and the direct interface with the controller does not flow. Is possible.

As described above, according to the second embodiment, a signal level conversion circuit can be realized in which the input drive current of the signal level conversion circuit flowing into the controller output at the time of high level output is reduced and high-speed operation is realized. Was completed.

It should be noted that the signal level conversion circuit 201 shown in FIG.
It goes without saying that the same function can be obtained even if the crossing type signal level conversion circuit shown in the conventional example of FIG. (Embodiment 3) (Embodiment 3) will be described with reference to FIG.

FIG. 8 shows a liquid crystal display device incorporating the signal level conversion circuit according to (Embodiment 1) or (Embodiment 2). 8, reference numeral 801 denotes a liquid crystal display device constituted by an integrated circuit using thin film transistors, and 802 denotes a CMOS.
A controller IC of a liquid crystal display device including a gate array and the like, connected to the liquid crystal display device 801 by 812,
The control signal is given to the liquid crystal display device 801. A control signal 812 has a low signal amplitude.

Reference numeral 803 denotes a thin film transistor for driving a pixel of the liquid crystal display device, 804 denotes a storage capacitance of the pixel, and 805 denotes a liquid crystal. 806, a source electrode connected to the source terminal of the pixel transistor 803; 807, a gate electrode connected to the gate terminal of the pixel transistor 803;
Indicates a storage capacitor and a common electrode connected to a counter electrode of the liquid crystal.

Reference numeral 809 denotes a source drive circuit for driving the source electrode 806, and reference numeral 810 denotes a gate drive circuit for driving the gate electrode 807. Reference numeral 811 denotes the signal level conversion circuit shown in (Embodiment 1) or (Embodiment 2) of the present invention.

The pixel transistor 803, the source driving circuit 809, the gate driving circuit 810, and the signal level conversion circuit 811 are formed on the same glass substrate by the same manufacturing process as an integrated circuit composed of thin film transistors.

This thin film transistor integrated circuit has about 1
The signal level conversion circuit 811 operates as a circuit having a power supply voltage of about 5 volts and a signal amplitude. The control signal is supplied to the source drive circuit 809 and the gate drive circuit 810.

In the (Embodiment 3) of the present invention, the signal level conversion circuit of the (Embodiment 1) and (Embodiment 2) of the present invention is incorporated in an active matrix type liquid crystal display device using thin film transistors. In addition, the CMOS gate array does not require a special circuit and can be directly controlled, and the interface can be simplified.

[0093]

As described above, according to the signal level conversion circuit of the present invention, an integrated circuit using a thin film transistor is provided with signal level conversion means for converting an input signal having a low signal amplitude into an output signal having a high signal amplitude. By applying a bias voltage to the input signal using a source follower transistor and a current source and applying the bias voltage to the gate of the input transistor of the level conversion means, the on-state current of the input transistor can be reduced even in the case of a low input signal amplitude. The size can be made sufficiently large, and the speed of the circuit can be increased. Further, by adopting the circuit configuration of the source follower, a signal level conversion circuit that reduces input drive current and realizes high-speed operation is realized.

Further, by using the signal level conversion circuit of the present invention, an integrated circuit using thin film transistors and a CMOS
It is possible to directly interface with an integrated circuit such as an S gate array. Furthermore, by using the signal level conversion circuit of the present invention for an active matrix type liquid crystal display device using thin film transistors, it is possible to directly control with a CMOS gate array, and the interface circuit can be simplified.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a signal level conversion circuit according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram of a conventional signal level conversion circuit.

FIG. 3 is another configuration diagram of a conventional signal level conversion circuit.

FIG. 4 is a configuration diagram of a signal level conversion circuit according to a second embodiment of the present invention;

FIG. 5 is a diagram showing threshold characteristics and operating points of an input transistor in a conventional example and (Embodiment 1) and (Embodiment 2) of the present invention.

FIG. 6 is a diagram in which a current source in Embodiment Mode 1 and Embodiment Mode 2 of the present invention is formed of a resistor or a transistor.

FIG. 7 is a diagram showing an input signal, an output signal, and an input current waveform in (Embodiment 1) and (Embodiment 2) of the present invention.

FIG. 8 is a configuration diagram of a liquid crystal display device according to Embodiment 3 of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 101 Source follower transistor 102 Source follower transistor 201 Signal level conversion circuit 202 Controller 203 Input signal 204 Input inversion signal 205 Input transistor 206 Input transistor 207 Load transistor 208 Load transistor 209 Output signal 301 Signal level conversion circuit 302 Current source 303 Current source 304 Input Signal obtained by adding threshold voltage to signal 305 Signal obtained by adding threshold voltage to input signal 306 Source input transistor 307 Source input transistor 701 Input signal voltage waveform 702 Inverted input voltage waveform 703 Signal voltage waveform obtained by adding threshold voltage to input signal 704 Inverted Output signal voltage waveform 706 in the signal voltage waveform 705 (Embodiment 2) obtained by adding the threshold voltage to the input signal. Output signal voltage waveform 707 Input signal driving current waveform 708 in the first embodiment 708 Inverting input signal driving current waveform 709 in the first embodiment 709 Input signal driving current waveform 710 in the second embodiment 710 (Second embodiment) 801) Inverting input signal driving current waveform 801 Liquid crystal display device 802 Controller 803 Pixel driving transistor 804 Storage capacitor 805 Liquid crystal 806 Source electrode 807 Gate electrode 808 Common electrode 809 Source driving circuit 810 Gate driving circuit 811 Signal level conversion circuit 812 Low signal amplitude Control signal 813 High signal amplitude control signal

────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Makoto Yamakura 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 19/0185

Claims (7)

(57) [Claims] 1. An integrated circuit using a thin film transistor, comprising: signal level conversion means for converting an input signal having a low signal amplitude to an output signal having a high signal amplitude; A signal level conversion circuit comprising: bias means for applying a voltage to a gate of an input transistor; and wherein the bias means includes a current source and a source follower transistor. 2. An integrated circuit using a thin film transistor, comprising: signal level conversion means for converting an input signal having a low signal amplitude into an output signal having a high signal amplitude; Bias means for applying to a gate of an input transistor is provided, and the bias means is configured using a current source and a source follower transistor, and a signal level conversion is performed by applying an inverted signal of the input signal to a source of the input transistor. circuit. 3. The signal level conversion circuit according to claim 1, wherein the bias voltage generated by the transistor of the source follower is set to a voltage equivalent to the threshold value of the input transistor. 4. The signal level conversion circuit according to claim 2, wherein the bias voltage generated by the transistor of the source follower is set to a voltage equivalent to a voltage obtained by adding the threshold of the input transistor and the amplitude of the input signal. 5. The signal level conversion circuit according to claim 1, wherein the current source comprises a transistor element or a resistance element. 6. The signal level conversion circuit according to claim 1, wherein the level conversion means is constituted by a crossing circuit or a current mirror circuit. 7. A pixel driving transistor formed by a liquid crystal display pixel and a thin film transistor, a source line driving circuit driving a source line of the pixel driving transistor, and a gate line driving circuit driving a gate line of the pixel driving transistor. 3. A signal level conversion circuit for an active matrix type liquid crystal display device having the following.
An active matrix type liquid crystal display device provided with the signal level conversion circuit described in the above.