JP3155771B2 - Display control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device, and more particularly to a display control device applied to a display device of a ferroelectric liquid crystal (FLC) device.

[0002]

2. Description of the Related Art Conventionally, as a display device of a personal computer (hereinafter abbreviated as PC) or a work station (hereinafter abbreviated as WS), a CRT (Cathode Ra) is used.
y Tube) was used. However, in recent years, T
N (Twisted nematic), STN (Sup
2. Description of the Related Art A liquid crystal display device having an er Twisted nematic structure or the like has come to be used for a laptop PC or the like due to its light weight and thinness that is possible due to its configuration.

[0003] Display devices used in PCs and WSs include:
Based on ergonomics, graphic functions such as window functions have been expanded to improve visual understanding, and high resolution and large screens have been required to realize them.

Further, a standard method of a current CRT display device such as a PC or WS uses a method of supplying analog R, G, B signals as image data by a color palette and D / A conversion. Conventionally, when processing image data as a digital signal, three A / D conversion circuits are provided as shown in FIG. 21 (conversion from an analog color signal to a digital color signal), and after conversion into a digital signal, a multiplier is used. , The conversion from the luminance gradation to the area gradation on the CRT is performed.

[0005]

In view of these circumstances, there are various problems to be considered when using resources effectively and using a display control device for CRT of PC or WS and a liquid crystal display device in combination. .

In the case of FIG. 22 (when a liquid crystal display device is provided on a mother boat) used as a body built-in type in PCs and WSs, ferroelectric liquid crystals are individually formed on mother boards of the PCs and WSs. A device is provided for generating image data and control signals conforming to the input / output specifications of the drive of the display device.

In FIG. 23 (when a liquid crystal display control device is provided in an expansion slot) used in combination with an external bus (hereinafter abbreviated as BUS) of PC and WS, the BUS
Display control devices must be prepared individually so as to conform to the specifications.

Further, a CRT display control device is already prepared on the mother board of the PC or WS as shown in FIG. 24 (when the CRT display control device is provided on the mother board), and an image is provided as a BUS or a connection terminal. If the digital signal and the control signal are not output, a failure occurs when a display device having ferroelectricity is added and displayed.

In the standard image data generating means of the current PC and WS CRT display devices, the image data is supplied as analog image data by a color palette and a D / A converter. Therefore, when converting to a gradation method other than the luminance gradation of the CRT, the analog image signal must be converted to digital image data. When the circuit shown in FIG. 20 (conversion from an analog color signal to a digital color signal) is used as the means, first, three high-speed A / D converters are required. Second, a * RED + b * GREEN
The execution time of the integer operation of + c * BLUE is not enough for the image data transfer clock cycle, and when each coefficient is a floating point, it takes more execution time than the integer operation.

As described above, the liquid crystal display device requires a high resolution and a large screen. However, when a high resolution is realized by a liquid crystal display device, in the display of the TN and STN liquid crystal elements by the matrix structure of the scanning lines and the information lines, the ratio of the electric field application time to the selected point per frame due to the increase of the scanning lines and the duty ratio As a result, a decrease in image contrast becomes a problem. A display element of a type in which a switching element formed by a thin film transistor is connected to each pixel to switch each pixel is known, but there is a problem that a process of forming a thin film transistor on a substrate is difficult.

[0011]

According to the present invention, in order to effectively use existing resources, analog R, G, B image data, horizontal synchronizing signals, The vertical synchronization signal is converted and controlled so that it can be displayed on a ferroelectric liquid crystal display device. The first simplification is made by using the analog / digital combined method shown in FIG.
In particular, there is a second feature that the present system does not depend on the type of coefficients, as compared with the conventional system configuration in which the execution time differs when the coefficients a, b, and c are floating-point numbers.

The display size on the liquid crystal display, the number of gradations, and the number of colors can be selected by changing the conversion period to area gradation data or pixel-divided color data and / or controlling the output control unit. Also, by using a ferroelectric liquid crystal display device having bistability and exhibiting memory properties, the selection time / line does not substantially change and the display contrast does not decrease.

[0013]

According to the present invention, when performing an area gradation to use an analog CRT luminance signal for display of a ferroelectric liquid crystal display device having bistability, the image data transfer speed can be reduced in real time with a simplified configuration. Operation and conversion are possible.
According to the above method, the display control device can be easily connected to a physically remote location by connecting the display control device from the CRT display control device with the same number of cables as the number of cores used for CRT display.
Alternatively, it can be provided in a WS device, in the middle of a signal line, in a liquid crystal display device, or the like.

Further, by converting and controlling analog R, G, and B image data of a standard signal used for a CRT display device, a horizontal synchronizing signal, and a vertical synchronizing signal, the size of the display of the ferroelectric liquid crystal display device is adapted. It does not matter which type of computer, such as PC or WS, is applied.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) Outline of device (2) Outline of display control (3) Configuration of each part of display control device (3.1) Analog primary color signal arithmetic unit (3.1.1) Circuit configuration of analog arithmetic unit (3) .2) Area gradation data converter (3.2.1) Circuit configuration of data converter (3.3) Converter for converting CRT control signal to ferroelectric liquid crystal control signal (3.3.1) Mode determination circuit Configuration (3.3.2) Circuit configuration of liquid crystal timing generator section (3.3.3) Circuit configuration of signal skew section (3.4) Output pixel data control section (3.4.1) "2-bit pixel" output Circuit configuration (3.4.2) "4-bit pixel" output circuit configuration (3.4.3) "8-bit pixel" output circuit configuration (4) Modification (4.1) Tone converter (4.2) Control timing generator section (4.3) Pixel Over data output control unit section

(1) Outline of Apparatus FIG. 1 shows an embodiment of the present invention. Graphics attached to the expansion BUS of the personal computer (PC) 1
The adapter supplies analog R, G, and B image data, a horizontal synchronization signal CHS, and a vertical synchronization signal CVS. The graphic adapter of the PC 1 used in this example has many modes according to the display size and the number of display colors as shown in FIG.
The polarities of the horizontal and vertical synchronizing signals CHS and CVS are line mode 1, 2, 3 selection signals RMOD1, as shown in FIG.
It is possible to identify the number of display lines in a CRT display for generating RMOD2 and RMOD3. Reference numeral 50 denotes a display control device to be shown in this example, which is composed of functional blocks 100, 150, 200, and 250, respectively. The display control device 50 controls the analog RGB signals, the image data AS, the horizontal synchronizing signal CHS and the vertical synchronizing signal C which are the CRT display control signals supplied from the PC 1.
The digital pixel data FDAT and the control signals (horizontal synchronizing signal FHS, vertical synchronizing signal FHV, display timing signal FBLK, pixel data transfer clock signal FC) are controlled by performing the VS conversion control and adapted to the ferroelectric liquid crystal display of this example.
LK) to the controller 300. The controller 300 controls the line mode selection 1, 2, and 3 signals RMOD.
A control signal for simultaneously driving one or a plurality of scanning lines of the ferroelectric liquid crystal display device is supplied to the common driver 320 and image data is supplied to the segment driver 321 according to RMOD2 or RMOD3. The controller 300
Also controls the drive of the frame 352 of the display screen. Reference numeral 330 denotes a temperature sensor provided at an appropriate position on the display 340, and supplies temperature information which is very important in driving the ferroelectric liquid crystal to the controller 300. The power controller 310 appropriately transforms a signal set by the controller 300 to generate a voltage that the display drivers 320 and 321 apply to the electrodes of the display 340. The display 340 is a main body of the display device, and includes a ferroelectric liquid crystal having a bistable state between a glass plate provided with two scanning line extraction electrodes, an information line extraction electrode, and a transparent electrode such as ITO connected to the electrodes. It is sealed and a deflector is arranged on the upper surface. Pixels consist of 1024 scanning line electrodes and 2560 information line electrodes.
* Consists of 2560 dots. This pixel is driven by an electric field generated by a driving waveform supplied to the segment driver 321 and the common driver 330, and is “bright”.
Displayed in the state or "dark" state. Details regarding 310, 330 and 352 are described in detail in U.S. Pat. No. 4,922,241 proposed by Inoue et al.

(2) Outline of display control Analog operation unit 1 shown in display control device 50
Reference numeral 00 performs an integration and addition operation on the analog RGB signals supplied from the personal computer 1.
The required accuracy of the operation should be determined by the number of tones or colors that can be displayed by the ferroelectric liquid crystal.
It is determined by the number of pixels of the liquid crystal or an error of an integrated circuit element used for an analog operation described later. The area gradation data conversion unit 150 has an integrated circuit for converting the continuous analog signal into a discrete signal in order to control the analog signal after the operation by digital logic, and the rising edge of the CRT image data transfer clock. A latch circuit for holding data at a timing is provided. The upper bits of the digital data supplied from the latch circuit are used as addresses of a read only memory (hereinafter abbreviated as ROM) to generate area gradation data DIM. Said,
The precision (number of output bits) required for the conversion should be determined by the number of displayable gradations or colors of the ferroelectric liquid crystal as in the case of the analog operation unit, and the upper limit is the number of pixels or the number of pixels of the liquid crystal display device. It is determined by an A / D conversion method described later and an error of an integrated circuit element used for the conversion. The CRT control signal conversion controller 200 converts the ferroelectric liquid crystal display control signals (liquid crystal vertical synchronizing signal FVS, liquid crystal horizontal synchronizing signal FHS,
A liquid crystal image data transfer clock FCLK and a liquid crystal display timing signal FBLK) are generated. The control signal also includes a CRT image data transfer clock CCLK newly generated by the control unit 200. The clock C
By changing the cycle of CLK, interpolation and thinning of image data can be performed, and the number of pixels suitable for the display 340 can be set. The output control unit 250 converts the digital image data DIM generated by the area gradation data conversion unit 150 into line mode 1, 2, and 3 selection signals RMOD1, RMOD2.
Or, depending on the horizontal display magnification selected in RMOD3,
A plurality of pixels are packed into a data string in pixel units and supplied to the controller 300. The data is supplied to the controller 300 in a word length obtained by combining a plurality of pixels in order to secure the processing time of the controller 300. With this control, the display screen of the CRT display device can be displayed in a size suitable for a ferroelectric liquid crystal display device having 2580 * 1024 pixels as shown in the example of FIG.

(3) Configuration of each part of the display control device The problems in performing ferroelectric liquid crystal display using the standard signal of the CRT display and the function of each block will be described below. The combination of these functional blocks optimizes the display of the liquid crystal device.

(3.1) Analog Primary Color Signal Operation Unit In this embodiment, the pixels of the ferroelectric liquid crystal display device are composed of 1024 scanning line electrodes and 2560 information line electrodes. The display device performs the area gray scale display in a pixel unit composed of one set or a plurality of sets of two pixels having a ratio of 3: 2. On the other hand, the present operation unit provides a means for converting a CRT analog RGB signal for performing luminance gradation into the area gradation. The conversion formula is [RED signal value * 1 + GREEN signal value * 2 + BLUE signal value * 0.
5]. In this embodiment, an operational amplifier of an integrated circuit is used for this arithmetic circuit. This example is a configuration example, and an actual circuit can be configured using individual transistors, field-effect transistors, MOS transistors, or the like. However, in such a case, the voltage between the base and the emitter of each element, the resistance existing in the base and the emitter, and the like must be matched in order to obtain necessary accuracy and frequency band. In order to realize high-speed and high-precision operation, it is necessary to select an operation amplifier according to its structure. In a voltage feedback type operational amplifier, if a high gain is to be obtained by the finite open loop gain, a practical frequency band is limited. However, the input bias voltage is extremely reduced due to the steps such as die electric isolation, and the voltage drop error (current offset error) due to the inflow of the current is very small. The current feedback type operational amplifier is suitable for the case where high speed and high gain are required because it does not depend on the limitation of the gain bandwidth product which is a problem in the voltage feedback type amplifier. However, there is a problem that the bias current of the non-inverting input is larger than that of the inverting input due to the unbalanced input configuration of the integrated circuit. However, the required accuracy of the bias current can be ensured by considering the impedance of the supplied signal. In this example, a voltage feedback operational amplifier having excellent DC characteristics is selected.

Hereinafter, an analog primary color signal conversion unit using a voltage feedback type operational amplifier will be described in detail.

(3.1.1) Analog Arithmetic Unit Circuit Configuration In FIG. 2, reference numerals 101, 102, and 103 denote analog R, G, and B signal weighting units, respectively.
Analog signals weighted by three blocks 101 to 103 are added. The actual circuit is composed of the resistors 115-117, 121-124 and the operational amplifier 1 shown in FIG.
11-113 and 114. 1 used in the circuit
Reference numerals 15 to 124 denote resistors for determining a multiplier for integration and a ratio of addition, respectively. In order to perform the conversion equation in this analog operation unit, a relational expression between the resistors is obtained as follows: [(RED voltage value * value of resistor 118 / value of resistor 115) * (value of resistor 124 / The value of the resistor 121) + (G
REEN voltage value * value of resistor 119 resistor / resistor 11
6) * (value of resistor 124 / value of resistor 122) +
(BLUE voltage value * value of resistor 120 / value of resistor 117) * (value of resistor 124 / value of resistor 123)]. Here, in order to realize the above-mentioned conversion formula, each resistance value is set to, for example, the value of the resistor 118 = 1 KΩ and the value of the resistor 119 =
2KΩ, value of resistor 120 = 500Ω, value of resistor 115 = value of resistor 116 = value of resistor 117 = 1KΩ, value of resistor 121 = value of resistor 122 = value of resistor 123 = resistance Assuming that the value of 124 = 1 KΩ, [RED signal value * 1 + GREEN signal * 2 + BLUE signal value * 0.5]
Weighted addition. In this embodiment, [RED signal value * 1 + GREEN signal * 2 + BLUE signal value * 0.
Although the conversion of the weighted addition of [5] is used, the weighting amount can be changed by changing the value of each resistor. Further, by making each resistor a variable resistor, it is possible to linearly vary the weighting amount.

Here, the calculation formulas include an offset voltage error of the operational amplifier, a noise voltage error, an error caused by the settling time, a harmonic distortion due to a difference in phase of each amplification stage of the integrated circuit when used at a high frequency, and each voltage. This is an ideal set of elements that do not cause a relative error or the like of the value of each resistor, which is necessary for the constant of the operation due to the drop. The offset voltage error is caused by a difference between the base and the emitter voltage of the transistor pair of the differential input stage as an error occurring in the operational amplifier among the elements, but a method of trimming a resistor constituting the differential input stage. It is known that it can be reduced by. The noise voltage or current error mainly arises from the transistors used, and can be improved by using low noise transistors in the configuration. A settling time can be shortened by using a high-speed transistor and considering its configuration, and a voltage feedback operational amplifier is known in which, at a gain of −1, the settling time is set to several tens nS within a 0.1% error of 2V. If the harmonic distortion is caused by a difference in the phase of each amplification stage, it can be reduced by performing a phase correction using a capacitive passive element. If the relative error of each resistor has the same value, it can be reduced by placing it on the same substrate. However, since an error is generated between elements having different values, it is possible to obtain necessary accuracy by trimming a necessary resistor.

In the present embodiment, [2 pixels / pixel] [4 pixels / pixel] [8
Pixel / pixel]. Assuming that the gray scale and the color tone required for the area gray scale or the pixel division color display are 256 levels, the calculation accuracy required for this is 1 / when the error of the area gray scale data converter 150 is ignored.
256 (about 0.4%). The signal AIM calculated in this block is supplied to the area gradation data conversion unit 150.

(3.2) Area Grayscale Data Converter FIG. 4 shows an area grayscale data converter 151 for supplying digital / image data DIM for performing control from a continuous system to a discrete system. Analog converter 1 described in (3.1)
The analog image data AIM from 00 is supplied, and the signal AIM is converted into the pixel data DIM of the ferroelectric liquid crystal display device 340 based on the area gradation used in this example. The data DIM is supplied to the output control unit 250. The area gradation data conversion is performed by the CRT supplied from the CRT control signal unit 200.
Image data transfer clock CCLK (25.175 MH
It is necessary to perform conversion at the period of z). Also, the A / D converter 161 constituting the block is adapted to [8 pixels / pixel] at the timing suitable for this transfer rate.
It must operate to obtain a bit data width. As a conversion method capable of operating at this conversion rate, a completely parallel type and a serial / parallel type A / D conversion control are known. Complementary metal oxide film silicon (hereinafter abbreviated as CMOS) has an 8-bit data width and a conversion rate of about 30 MHz in a completely parallel system, and an emitter-coupled logic (hereinafter abbreviated as ECL) has an 8-bit data width and several hundred MHz.
A conversion rate of z has been achieved. The CMOS integrated circuit is superior in the manufacturing process and the ease of realizing the peripheral portion, and the A / D converter 161 using the CMOS integrated circuit is used in this configuration. The accuracy of this A / D converter is determined by the presence or absence of error factors of 2 ⁸ (2 8) resistor ladders and 2 ⁷ (2 7) comparator error factors. Especially CMOS
Is used for the comparator, the error of the threshold voltage and the 1 / f noise affect the accuracy of the converter. In this embodiment, the reference voltage supplied to the A / D converter 161 is set so as to output the full scale value of the digital code with respect to the maximum analog input voltage. In this case, the 1-bit weight voltage of the A / D converter 161 is a solution of the analog R, G, B conversion equation, 1V + 2V + 0.5V =
It is a value obtained by dividing 3.5 V by 256, that is, about 13.7 mV. It is considered that 3δ, which is statistically three times the standard deviation δ of the error, becomes a value smaller than 13.7 mV. Note that the accuracy of the device 50 should be evaluated based on a value obtained by adding an error of the analog operation unit 100 and the area gradation data conversion unit 150. In this example, since a voltage feedback type operational amplifier having excellent DC characteristics and a resistor having a small absolute value error are used, an error generated in the analog operation section 100 is sufficiently small. Hereinafter, the circuit of the area gradation data conversion unit 150 will be described in detail.

(3.2.1) Circuit Configuration of Data Conversion Unit FIG. 5 shows an A / D conversion circuit.
1 converts the analog image data AIM supplied from the analog operation unit 100 into digital data DIM. The converted data is held by the latch circuit 162 at the rising edge of the CRT image data transfer clock CCLK supplied from the liquid crystal timing generator unit 202. The area gradation data DIM stores upper bits supplied from the latch circuit 162 in the ROMs 163 and 16.
The horizontal display mode 1 supplied from the mode determination unit 201 using the read data as the addresses of the addresses 4 and 165,
2, 3 selection signal HMOD1, HMOD2 or HMOD
3 state buffer gate 16 selected by 3
6, 167 or 168 to the output control unit 250. FIG. 19 shows the contents of the ROM 164 in the case of [4 bits / pixel].

(3.4) Converter for Converting CRT Control Signal to Ferroelectric Liquid Crystal Control Signal FIG. 6 shows a configuration example of the CRT control signal conversion controller 200. In the case of the present embodiment, a mode determining unit is provided to determine various modes of the PC 1. The mode determination unit 201 determines the number of display lines from the polarities of the CRT vertical synchronization signal CVS and the CRT horizontal synchronization signal CHS supplied from the PC 1 as shown in FIG. The liquid crystal display timing generation unit 202 receives the CRT horizontal synchronization signal C supplied from the PC1.
25.175M transmitted by HS and voltage controlled transmitter
A phase detector 220 compares phases of the frequency-divided signal of HzCCLK, and supplies a CRT image data transfer clock CCLK in phase with the CRT horizontal synchronization signal CHS. In this example, 2 for modes 2+, 3+ and 7+
8.322MHz, mode O +, 1+ is 14.161M
Hz and 12.588M for modes 4, 5, D and 13
In other modes, the image data is transferred from the PC 1 at a transfer rate of 25.175 MHz, but the modes 2+, 3+, and 7+ of the horizontal 720 pixel display mode are thinned out by converting and sampling all the modes at 25.175 MHz. In the horizontal 360 pixel display mode 0+, 1+, the image data is interpolated to 640 pixels.
The display modes 4, 5, D and 13 for 40 pixels and horizontal 320 pixels are interpolated into 640 pixel image data. Other modes are 25.175 MH
The data is converted and sampled by z and converted as image data with 640 pixels of horizontal display. Therefore, the horizontal mode 1, 2, 3 selection signals HMOD1, HMOD2, HMOD
HMOD2 is turned on in 3 regardless of the mode. Further, by dividing the CRT image data transfer clock CCLK, a generated image data transfer clock GCLK is generated and supplied to the signal skew unit 203. Signal skew section 203
Is N at the output of [N pixels / pixel] to match the phases of the liquid crystal display image data FDAT, the liquid crystal display timing signal FBLK, the liquid crystal vertical synchronization signal FVS, the liquid crystal display horizontal synchronization signal FHS, and the liquid crystal image data transfer clock FCLK.
The clock (CRT image data transfer clock CCLK) is delayed.

Hereinafter, the CRT control signal conversion control section 200 will be described in detail.

(3.3.1) Circuit Configuration of Mode Determination Unit FIG. 7 shows the configuration of the mode determination unit 201. Counter 20
Reference numeral 6 opens the gate of 204 only during the positive polarity period of one cycle of the CRT vertical synchronization signal CVS supplied from the PC1, and counts the basic clock REFCLK. One shot
The multivibrator 205 supplies a signal for resetting the counter 206 every period. The magnitude comparison determination logic 207 compares the magnitude with a constant value based on the result to determine the polarity of the CRT vertical synchronization signal CVS. Similarly, the polarity of the CRT horizontal synchronization signal CHS is determined by a circuit composed of 208 to 201. The number of display lines and the determination logic 212 determine the mode of the display line shown in FIG. 17 from the polarities of the two synchronization signals. The logic circuit 212 performs mode determination based on the display line information,
480 line mode 1, 2, 3 selection signals RMOD
1, RMOD2 and RMOD3 are generated and supplied to the vertical synchronization front porch programmable counter 225 and the back porch programmable counter 226. In this embodiment, the horizontal display 64 is adjusted by adjusting the conversion rate.
Since the pixels are unified to 0 pixels, the horizontal display mode 1, 2, 3 selection signals HMOD1, HMO
D2 and HMOD3 are horizontal display mode 2 selection signals HMOD
Turn on 2.

(3.3.2) Circuit Configuration of Liquid Crystal Display Timing Generator Unit FIG. 8 shows the configuration of the liquid crystal display timing generator unit 202. 220 is a CRT horizontal synchronization signal CH from PC1
The phase difference between S and the clock signal obtained by dividing the signal from the voltage control transmitter 222 by the frequency divider 223 is detected. Divider 2
23 has an output of the voltage control transmitter 222 of 25.175 MH
It is set so that it becomes z and the result of frequency division becomes the same cycle as the synchronization signal CHS. The clock signal is supplied to the signal skew unit 203 and the output control unit 50 as a CRT image data transfer clock CCLK. The frequency divider 224 divides the frequency of the clock signal CCLK by 2, 4, or 8 according to the horizontal display mode 1, 2, or 3 selection signal HMOD1, HMOD2, or HMOD3 from the mode determination unit 201. The divided clock signal is a generated image data transfer clock GC
The signal is supplied to the signal skew unit 203 as LK. 225
And 226 generate a period from the start of the front porch to the end of the back porch, that is, a line display period. 225 and 226 are line mode 1, 2, 3 selection signals RMOD1, RMOD2, RMO
The value preprogrammed by D3 is counted down by the CRT horizontal synchronization signal CHS. In this embodiment, the line mode 1, 2, and 3 selection signals RMOD1, RMOD2, RMOD
The value of FIG. 18 selected by MOD3 is set, and a non-display signal is generated before and after the CRT vertical synchronization signal CVS supplied from PC1. The counters 227 and 228 are set to the values shown in FIG. 18 by the mode selection signal MOD, count down by the CRT image data transfer clock CCLK, and supply the CRT horizontal synchronization signal CVS supplied from the PC1.
Before and after generating a non-display signal. Generation display timing G
BLK is generated by logically synthesizing both non-display signals at 229. GBLK is supplied to the signal skew unit 203.

(3.3.3) Circuit Configuration of Signal Skew Unit FIG. 9 shows a circuit of the signal skew unit. 231 to 234
Are the FBLK, FVS, FHS, FCLK, and FCLK
A programmable shift register for delaying the CLK signal, and a mode 1, 2, or 3 selection signal MOD
A delay of N clocks is programmed by the 1, MOD2 or MOD3 signal. Output from programmable shift registers 231-234, liquid crystal vertical synchronizing signal F
VS, the liquid crystal horizontal synchronization signal FHS, the liquid crystal image data transfer clock FCLK, and the liquid crystal display timing signal FBLK are supplied to the controller 300. Controller 300
Sets the drive voltage based on the information of the temperature sensor 330, thins out the lines of the image data, and sets the common driver 32.
The display is performed on the display 340 by driving the 0 and the segment driver 321.

(3.5) Image Data Output Control Unit In FIG. 10, reference numeral 251 denotes a [2 pixels / pixel] output unit, 252 denotes a [4 pixels / pixel] output unit, and 25
Reference numeral 3 denotes an [8 pixels / pixel] output unit, and these blocks constitute an output control unit 250. In the control unit 250,
The horizontal display mode 1, 2, and 3 selection signals HMOD1, HMOD2, or HMOD3 supplied from the CRT control signal conversion control unit 200 from among the three control blocks,
The data output of any one block is selected and supplied to the display controller 300 in 16-bit units as image data FDAT in the form of [pixel / pixel]. This selection is related to the number of horizontal display pixels. For example, when performing display corresponding to the number of pixels of the effective display area 351 in the horizontal direction, [2 pixels / pixel] is 1280 pixels wide for the display 340. display,
[4 pixels / pixel] can display 640 pixels (see FIG. 14) on the display 340, and [8 pixels / pixel] can display 320 pixels on the display 340. The number of display lines in the vertical direction can be reduced by setting the number of scanning lines of the display 340 to one by supplying the line mode 1, 2, 3 selection signals RMOD1, RMOD2 or RMOD3 generated by the control unit 200 to the controller 300.
The adjustment is performed by simultaneously driving two, four, or four lines.

The three types of output control units will be described in detail below.

(3.4.1) Circuit Configuration of [2 Pixels / Pixel] Output Unit First, FIG. 11 shows a [2 pixels / pixel] output unit 251, and latch circuits 271 to 278 are supplied from the area gradation data conversion unit 150. The lower two pixels of the digital image data DIM to be converted from the CRT control signal conversion control unit 200 to the CRT
This is a register which is sequentially shifted by an image data transfer clock CCLK. Latch circuits 262 to 269 are [2
Pixel / pixel] data is held at the rising timing inverted by the inversion gate 261 of the liquid crystal image data transfer clock FCLK supplied from the CRT control signal conversion control unit 200. This retained data is CR
The liquid crystal image data FDAT is supplied to the controller 300 from the three-state buffer gate 270 controlled by the horizontal display mode 1 selection signal HMOD1 supplied from the T control signal conversion controller 200. [2 pixels / pixel] is selected in the case of high definition display in which the number of CRT horizontal display pixels exceeds 640 pixels. In this embodiment, modes 2+, 3+, and 7 of 720 horizontal display pixels are used.
The image data transferred at 28.322 MHz from the graphic adapter of PC1 is 25.1.
Since conversion sampling is performed at 75 MHz and thinned out, 6
Handle as a 40 pixel display. In this example, the output unit 251 is provided as a preliminary unit.

(3.4.2) [4 Pixels / Pixel] Output Unit Configuration Circuit FIG. 12 shows a [4 pixels / pixel] output unit, and digital images supplied from the area gradation data conversion unit 150 from 287 to 290 are shown. This register sequentially shifts the lower 4 bits of the data DIM by the CRT image data transfer clock CCLK from the CRT control signal conversion controller 200. The latch circuits 282 to 285 hold four sets of [4 pixels / pixel] data at the rising timing of the liquid crystal image data transfer clock FCLK supplied from the CRT control signal conversion control unit 200 inverted by the inversion gate 281. . The held data is the horizontal display mode 2 selection signal HM supplied from the CRT control signal conversion control unit 200.
The liquid crystal image data FD from the three-state buffer gate 286 controlled by OD2 to the controller 300
Supplied as AT. In this example, mode 0+, 1+, 2
+, 3+, 7+, 6, D, E, F, 10, 11, 12, and 13 [4 pixels / pixel] is selected.

(3.4.3) [8 Pixels / Pixel] Output Circuit Configuration FIG. 13 shows an [8 pixels / pixel] output unit, and latch circuits 295 and 296 are digital signals supplied from the area gradation data conversion unit 150. Lower 8 bits of image data DIM are CR
This register sequentially shifts according to the CRT image data transfer clock CCLK from the T control signal conversion control unit 200. The latches 292 and 293 hold two sets of [8 pixels / pixel] data at the rising timing of the liquid crystal image data transfer clock FCLK supplied from the CRT control signal conversion control unit 200 inverted by the inversion gate 291. The held data is a horizontal display mode 3 selection signal HMO supplied from the CRT control signal conversion control unit 200.
3-state buffer gate 2 controlled by D3
Liquid crystal image data FDAT from 94 to controller 300
Supplied as 320 CRT horizontal display pixels
Select [8 pixels / pixel] for multi-tone display with pixels or less. In this embodiment, the horizontal display pixel 320
Pixel modes 4, 5, D and 13 correspond to
Since the image data transferred at 12.588 MHz from the first graphic adapter is converted and sampled at 25.175 MHz, it is handled as a 640 pixel display. In this example, it is prepared as a preliminary means.

FIG. 15 shows the main output timing of each block of the image data output control section 250.

(4) Modifications (4.1) Gradation Conversion Unit In this embodiment, a continuous primary color signal is converted and converted into a data format which can be easily applied to an area gradation used for a ferroelectric liquid crystal display. Although the control method has been described, the conversion control of a signal having a high-speed data transfer clock such as WS can be performed by using the analog operation unit and the area gradation data conversion unit in two blocks each. In this case,
Since the calculation unit needs a time (settling time) until the signal settles to its determination accuracy, it is not effective to use it in multiplexing.

(4.2) Control Timing Generator Unit In this embodiment, the frequency division ratio of the frequency divider 223 is fixed. However, a programmable frequency divider capable of changing the frequency division ratio by an external signal, for example, a mode signal or the like is used. In such a case, any image data can be interpolated or thinned out by changing the rate when converting the analog image data into the area gradation digital data. With the above function, an arbitrary horizontal display size can be selected.

(4.3) Pixel Data Output Control Unit In this embodiment, the data output is limited to 1, 2 or 4 pixels / pixel, but pixel data which does not exceed the number of pixels in the effective display area of the liquid crystal display device is output. Any number of N pixels / pixel in the supplied integer N may be used. By the output control, the display area of the display device can be displayed in an optimal size on the display screen, and the number of displayable gradations or colors can be changed. When the size of the display screen is single, the mode determination unit 201 and the like become unnecessary, and the output from the output control unit 250 can be fixed at [N pixels / pixel].

[0040]

As described above, the color pallet + D, which is a standard method for the current PC, WS, etc., is used.
It is possible to display image data from a PC or WS on a ferroelectric liquid crystal display device that does not cause a decrease in contrast even on a large screen by using analog R, G, B signals and horizontal and vertical synchronization signals by / A conversion. It becomes possible. The display size and the number of gradations or the number of colors can be arbitrarily set by a combination of the data conversion cycle and the output control unit [N pixels / pixel].

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a control system of a display control device and a ferroelectric liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is a block diagram of an analog operation unit provided in the display device of the embodiment.

FIG. 3 is a block diagram of an analog operation unit provided in the display device of the embodiment.

FIG. 4 is a block diagram of an area gradation conversion unit;

FIG. 5 is a circuit diagram of an area gradation conversion unit,

FIG. 6 is a block diagram of a CRT control signal conversion control unit;

FIG. 7 is a circuit diagram of a mode determination unit,

FIG. 8 is a liquid crystal display timing generator block diagram.

FIG. 9 is a circuit diagram of a signal skew unit,

FIG. 10 is a block diagram of an output control unit of the display control device according to the embodiment;

FIG. 11 is a circuit diagram constituting the block of FIG. 10,

FIG. 12 is a circuit diagram constituting the block of FIG. 10,

FIG. 13 is a circuit diagram constituting the block of FIG. 10,

FIG. 14 is a CRT in mode 12 in the embodiment.
Pixel configuration of FLC by display and main display control

FIG. 15 is a timing chart of main signals supplied from the display control device;

FIG. 16 is a view showing a mode list (0-13H mode) of the PC graphic adapter used in the embodiment;

FIG. 17 is a diagram showing determination conditions for the number of display lines based on the polarities of horizontal and vertical synchronization signals;

FIG. 18 shows a horizontal and a horizontal direction for generating the display timing of the liquid crystal.
Diagram showing vertical front porch start and back porch end settings

FIG. 19 is a diagram showing area gradation ROM data of [4 bits / pixel].

FIG. 20 is a circuit diagram of a conventional analog RGB signal conversion operation unit,

FIG. 21 is a circuit diagram of an analog RGB signal conversion operation unit used in the present embodiment;

FIG. 22 is a block diagram of a conventional display control device;

FIG. 23 is a block diagram of a conventional display control device;

FIG. 24 is a block diagram of a conventional display control device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Personal computer 50 Display control device 100 Analog operation part 101 Red signal weighting part 102 Green signal weighting part 103 Blue signal weighting part 104 Signal addition part 111 Operational amplifier 112 Operational amplifier 113 Operational amplifier 114 Operational amplifier 115 Resistor 116 Resistor 117 Resistance Device 118 Resistor 119 Resistor 120 Resistor 121 Resistor 122 Resistor 123 Resistor 124 Resistor 150 Area grayscale data converter 151 Digital converter 161 A / D converter 162 Latch circuit 163 [2 bits / pixel] Area grayscale Data ROM 164 [4 bits / pixel] Area gradation data ROM 165 [8 bits / pixel] Area gradation data ROM 166 3-state buffer gate 167 3-state buffer gate 1 68 3-state buffer gate 200 CRT control signal conversion control unit 201 mode determination unit 202 liquid crystal display timing generator unit 203 signal skew unit 204 AND logic 205 one-shot multivibrator 206 counter 207 magnitude comparison determination logic 208 AND logic 209 one-shot Multivibrator 210 counter 211 magnitude comparison decision logic 212 display line number decision logic 220 phase detector 221 loop filter 222 voltage controlled oscillator 223 divider 224 programmable divider 225 vertical synchronous front porch programmable
Counter 226 Vertical Synchronous Back Porch Programmable Counter 227 Horizontal Synchronous Front Porch Programmable Counter
Counter 228 Horizontal synchronous back porch programmable counter 229 Display timing synthesis logic 231 Programmable shift register 232 Programmable shift register 233 Programmable shift register 234 Programmable shift register 205 AND logic 250 Output control unit 251 2-bit / pixel output unit 252 4-bit / pixel output unit 253 8-bit / pixel output unit 261 Inverted logic 262 Latch circuit 263 Latch circuit 264 Latch circuit 265 Latch circuit 266 Latch circuit 267 Latch circuit 268 Latch circuit 269 Latch circuit 270 3-state buffer 271 Latch circuit 272 Latch circuit 273 Latch circuit 274 Latch circuit 275 Latch circuit 276 Latch circuit 277 Latch circuit 278 Latch circuit 281 Inversion logic 282 Latch circuit 283 Latch circuit 284 Latch circuit 285 Latch circuit 286 3-state buffer 287 Latch circuit 288 Latch circuit 289 Latch circuit 290 Latch circuit 291 Inversion logic 292 Latch circuit 293 Latch circuit 294 3-state Buffer 295 Latch circuit 296 Latch circuit 300 Controller 310 Power supply controller 320 Common driver 321 Segment driver 330 Temperature sensor 340 Display 350 Display screen 351 Effective display area 352 Frame 501 Operational amplifier 502 Operational amplifier 503 Operational amplifier 504 Operational amplifier 505 Resistor 506 Resistance Resistor 507 resistor 508 resistor 509 resistor 510 resistor 511 resistor 512 resistor 513 resistor Resistor 514 Resistor 515 A / D converter 551 Operational amplifier 552 Operational amplifier 553 Operational amplifier 554 A / D converter 555 A / D converter 556 A / D converter 557 Digital multiplier 600 Ferroelectric liquid crystal display device 601 Strong Dielectric liquid crystal display control device 602 Mother board 603 Personal computer 610 Ferroelectric liquid crystal display device 611 Ferroelectric liquid crystal display control adapter 612 Expansion slot 613 Personal computer 620 CRT display device 621 CRT display control device 622 Mother board 623 Personal computer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G09G 3/20 G02F 1/133 G09G 1/16 G09G 3/36

Claims (2)

(57) [Claims] 1. A ferroelectric liquid crystal display device in which a ferroelectric liquid crystal element having a bistable state with respect to an electric field is disposed between a scanning electrode group and two insulating substrates having an information electrode group. Converts the continuous CRT analog primary color signal to the ferroelectric
CRT control signal to convert to area gray scale signal of transparent liquid crystal display device
In the signal conversion control unit, according to the N pixel / pixel display mode
To change the cycle of the CRT image data transfer clock
Display control apparatus characterized by comprising means. 2. A CRT control signal conversion control unit comprising:
LCD image data according to the pixel / pixel display mode
2. The method according to claim 1, further comprising means for changing a period of the transfer clock.
The display control device according to the above.