JP3004650B2 - Optimized integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION   The invention is optimized for integrated circuits, especially for specific conditions
The design and manufacture of integrated circuits. Technology background   Large-scale integrated circuits (VLSI) have hundreds of thousands in a single chip
The ability of this technology to generate electronic circuits with transistors
It can be created by force. Efficiency of such VLSI circuits
Good design involves generating active elements in the circuit
For interconnection pattern design and circuit layout design
It is impossible without some automatic means. Follow
Technology that assists in the design of VLSI circuits.
Note that a number of products are obtained. like that
The integrated part of the design tool is a tool for evaluating the efficiency of the design.
It is a step. This is in terms of power consumption, operating speed, and active elements.
Includes means for measuring products and the like.   Timing analysis is one such tool,
Essential algorithm for measuring transistor size
Because it is an element, it is an important one. Of course Taimin
Log analysis is itself important in circuit design. “MOS circuit
Synthetic Path Analysis in Simulator "
EE PROCEEDING, 19 times, Design O
Tomeation Conference (IEEE, Proc 19th De
sign Automation Conf. (1982, pp. 629-635;
A. Agrawal has a digital circuit
Algorithm for Evaluating Time Delay
Has been extended. It is the first of such algorithms
It is not, but one of the important things. Because
If there is a latch (memory) in the circuit under investigation
Can be identified as any input of the combined part of the circuit
Can evaluate the time delay from output to any output.
The other two timing analyzers are N. Joup
pi) “Timing analysis for NMOS VLSI”
ー Eee Proceeding ・ 20 Design O
Tomesion Conference (IEEE Proc, 20th Desi
gn ・ Automation Conf. ) (June 1983), pp. 411-418.
Verification (TV) program and JO
—Starhout (J. Ousterhout), “Designing MOS VLSI
Switch-level delay model for "IEE
EProceding, 21 times, Design Automation
Yong Conference (IEEE, Proc, 21st, Design Aut)
Crystal by omation Conf (June 1984) 542-548
It is a program.   Crystal and TV programs are offered by Agrowal Algo
Rhythms and their use of more detailed timing evaluation methods
Is different. The evaluation method is based on a single
It takes into account the different gut delays of the signal gates. TV
The disadvantages of both the Crystal and Crystal programs are
It does not address the existence of feedback in the integrated circuit,
Except for almost all digital integrated circuits
I will remove it.   Another important aspect of integrated circuit design is the transistor used.
This is a star area evaluation method. Of course many deterministic areas
There is an evaluation method. One simple scheme is, for example,
Transistor is one size that satisfies the speed condition of the whole circuit
Is to make it. In another, more complex scheme,
The size of the transistor is the power rail (battery or ground)
And how close they can be. Also, specific
Based on the circuit design, evaluate the dimensions of the transistors in the integrated circuit.
There are a number of algorithms to value. One of the earliest
One is the work of Ruchhi et al.
Analytical power / timing optimization techniques for stems
Surgery ”, IEE Proceeding 14 times
Zain Automation Conference (IEEE, Pr
oc, 14th Design Automation) (June 1977) 142-146
Page. They have their own timing analysis
Devising instruments and helping their analyzers, they
An algorithm for measuring the size of the star has been devised. Only
And their timing analyzers have memory in the circuit
Does not have the ability to recognize and handle It is also a tiger
The size of the transistor gate increases and
Also take into account the extra delays resulting from the required capacity increase
Absent. Algorithm that does not consider increased gate capacitance
Is "Digital MO" by M. Matson
S VLSI circuit optimization "Proceeding chapel
Hill Conference on VLSI (Proc ・ Chapel Hill
Conf on VLSI) (University of North Carolina, May 1985), 10
Proposed on pages 9-126. Matson's algorithm also
Using a more accurate delay model of the active element,
Take into account the slope.   Matson algorithm and all other known dimensions
The biggest shortcomings of the evaluation algorithm are generally feedback and features.
Have no ability to automatically recognize and handle memory elements
It is. Essentially all digital integrated circuits are cycled
This is a critical shortcoming, because sequential circuits include memory.
There is a point. Another drawback of these algorithms is that they
Uses an unnecessarily accurate optimization algorithm,
Analysis of large scale integrated circuit designs becomes unnecessarily slow.   Overcoming one or more limitations of prior art methods
Is the object of the present invention. Configuration of the present invention   The design of the present invention for an integrated circuit, for example,
Iterative analysis to meet pre-selected constraints
It is improved every time. Design improvement is an active factor
Each function of a circuit characterized by being a convex function of the size
By choosing a model for the delay through the moving element
Is achieved. Using a convex function model, every iteration
Static timing analysis of the circuit is the most critical
Used to identify large outputs. That selected
Use the output to analyze the timing structure of that path
And the change in magnitude causes the greatest improvement in operating characteristics
Active elements of the path are identified. Therefore the active element
Is adjusted and repeated.   To further improve, in the selected iterations,
The interconnection patterns of the sub-networks of the circuit are evaluated and actuated
Rearranged to improve properties. Generally, that
Those active elements whose inputs arrive late are sub-networks
Be placed as close as possible electrically to the output section of the
To taste. Embodiment of the invention   Electronic circuits are purely combined circuits and circuits with return paths
Can be divided into In a purely combined circuit, the signal
Flows only in one direction, combines from different directions, and
Reach logical state. In the circuit including the return path, the memory
And the presence of the memory allows the circuit to
It becomes a circuit. Sequential circuits always contain pure combinatorial logic
Minutes and multiple basic methods such as flip-flops
What can be divided into parts that contain nothing but the moly element
Well known.   Size is X₁, X_Two, ... X_NN transistors in total
(Eg, a MOS transistor) as shown in FIG.
Given a circuit such as this, the method of the present invention calculates the Xi value
The adjustment improves the circuit characteristics. Two indications
Gender is of particular interest. One is T, which is a circuit
The minimum clock cycle that operates or the propagation delay for non-clock paths.
You. The other is A, which is simply the size of the transistor or
Stated another way, it is the sum of all areas of the active element.
Area A is a minimum or a number of other factors in the circuit to be held down.
It can be seen that they have a positive relationship. First, as A increases,
The circuit requires a larger silicon area. Second, all games
The charge capacity is proportional to A, so charge or discharge the capacity
The power required to do so increases with A.
Third, in the case of a static CMOS gate, pull-up and pull-up
Transition where both loop-down networks are partially turned off
There is a short period of time. This short-circuit power is also A
Also increase. Similarly, the distributed load NMOS gate is
As transistor size increases, more
Consumes power. Fourth, most important in many situations
However, the probability of device failure during a chip is
It is strongly dependent on the entire active area of the tip. As the active area increases
As a result, the probability of chip malfunction increases.   The point that requires the rigor of any optimization method
The form of the expression or function to be optimized, more specifically the function
Property or behavior. According to the principles of the present invention, good results
Functions that produce results and can reach them efficiently and quickly
look for. And the result is close to the absolute minimum and quickly
Can be reached, and the process has some local minimum of the function
It means that you can't use it. Has hundreds of thousands of transistors
Integrating Circuits
The conversion process is not a luxury but an absolute necessity
is there.   Therefore, as a preliminary step, the factors and
The constraints to be chosen must be selected. Three Formulations
think of: 1) The maximum delay at any output is predetermined
Function in an integrated circuit constrained to be less than the constant K
Minimize the area of the moving element: 2) The area of the active element is smaller than a preselected constant
The maximum delay at any output constrained by
Minimize: 3) Coefficient AT^KIs minimized.   The first formulation is that if the desired operating speed (clocking frequency)
It is probably the most useful because it is often given. So
In such a case, the first formulation gives the circuits in the system
It is used to match the obtained clocking cycle K. Ma
Also, unlike the other two formulations, the same value of K is separately computed.
Two different circuits to be optimized are best considered together
It is. This fact leads to a loss of optimality in the final circuit.
Without optimization, the sub-circuits are optimized separately.   The second formulation is used to make the circuit as fast as possible,
Subject to silicon area, power or yield constraints.   The third formulation, where both A and T are important,
This is a comprehensive method when relative weights can be divided
You. For example, even if A increases by 5%, T
T may be more important than you want to decrease by cents
Not. In such a situation, K is set to 5.   Probably the heaviest to consider to minimize the process
An important second factor is that which is used to represent the active elements of the circuit.
Model. In the case of a MOSFET integrated circuit,
Selected model. Where 10, 11, and 12 are
Represents the gate, drain and source nodes of the MOSFET, respectively.
You. The capacitance Cg13 is a capacitance between the gate and the ground, and the capacitance Cd14 is
The capacitance between the drain and ground, Cs16 is between the source and ground
Capacity. Switch 17 where FET turns off is closed
The resistor Rds15 is connected to the drain and source when the FET is on.
Resistance between Gate, source and drain capacitances are
All are directly proportional to transistor size x (channel width)
By way of example, the source-drain resistance is inversely proportional to x.   Fig. 3 shows the case of the "totem pole" configuration of three FETs.
Of gate delay according to the distributed RC model in Fig. 2
Represents Penfield-Rubinstein distribution RC model
Dell states that the upper limit of the discharge time for the circuit of FIG.
Suggests that   (R₁+ R_Two) C_Two+ (R₁+ R_Two+ R_Three) C_Three            (1)   Where R₁, R_TwoAnd R_ThreeIs the transistor x₁, X_Two
as well as_x3Equal to the resistance Rds of C₁Is the transistor x₁Cd and
Transistor x_TwoEqual to the sum of Cs of C_TwoIs the transistor x_Two
Cd and transistor x_ThreeEqual to the sum of Cs of C_ThreeIs trans
Star x_ThreeCd and C_LIt is. C₁Is below the closing switch,
When closing a switch, it slows down the game rather than slowing it down.
Speed up the operation. This means that the first current is capacitance C₁Inside
You can clearly see it when you see it.
The capacitance looks like a short circuit and the resistance R₁Through the current
Not flowing. Therefore, the upper bound on the delay (as described above)
When asked, C₁Can be ignored, so C₁Is given by equation (1)
Does not appear.   Equation (1) is calculated using the transistor size x_iTable as a function of
When I passed, each R_iIs 1 / x_iIs proportional to each C_iIs a certain constant
x_iIs the sum of the terms proportional to C_iWhere the constant term is the wire volume
Variable, and the variable term may be gate, drain or
Represents the capacity of the source. Equation (1) can be written as
You.   Here, A, B, C and D are constants.   The delay through a circuit is the sum of the delays that occur in that circuit.
Recognize that the general form of circuit delay in a circuit
And then:   Where a_ijAnd b_iIs a non-negative constant,
Is almost zero for this circuit. From equation (3)
The function represented is shown to be convex. This is
A straight line in N + 1-dimensional space whose terminal point is in the graph of the function
All of the part itself is on the graph or from the graph
Means on top. In addition, equation (3) is Posino
It belongs to a particular kind of convex function called minal.   As a result, all three formulations of the constraint find the convex function
It turns out to be small, which is another upper limit on the convex function. Convex
Can be realized by the minimization function used in the prior art.
Creates significant advantages. The biggest advantage is the local best
Any point that is considered a small value is also the minimum of the whole
is there.   The field of convex programming has been enthusiastically explored in recent decades
And many computing techniques can be used. For example,
R.T.Rockafelle (R.T.Rockafelle)
r), Convex Analysis (Pro
See Linston University Press 1970).   The desired optimization is the chip, the entire VLSI chip or the system.
Since the optimization is a part of the whole, the optimization method is acceptable.
It must be as effective as possible and must be
It can even sacrifice counteraccuracy. Optimal value for it
Have an efficient way to approximate
The process generally proceeds according to the following steps:
Thereby, the optimal solution is reached very quickly.   The process covers all active elements in the VLSI circuit design.
Start by setting these minimum possible dimensions (fourth
Block 100 in the figure). This reduces the minimum active area
Including the most reliable (larger active area
However, chip defects are more likely to occur during manufacturing. )
The first design occurs.   Next, the equation (specification) representing the circuit conforms to the structure of FIG.
Will be adjusted to (Block 100 in Fig. 4)   Following the preliminary steps above, (the specific
A) circuit analysis to identify and select the worst output
The return process begins (block 110 in FIG. 4).
"The worst" means, for example, that T is one microphone
One second has a delay of 1.2 microseconds,
Output has a delay of 1.5 microseconds,
The output of the crosecond is selected as the worst output.   In the next stage, each transition that can have an effect on its output
By examining the source, the source of the delay in the selected output is
The cause is examined (block 120 in FIG. 4). I checked
For each electrical node, two numbers are assigned: t_l
(Slowest time to go low) and t_h(The highest
Is too late). When examining the “poor point” of the delay,
t_hIs the cause of the "poor point", the proof-up circuit
Bet, t_lIs the cause of the "poor point",
Circuit is examined. Active in the test
Both the element and its supporting element are included. Support element
Of course, all the functions that contribute to the input signal of the element
There is a moving element. This creates a chain test, which is
Characterized by "walking" backwards, delaying during selected output
Identify the critical path that controls elongation. For example,
In Figure 3, examining results in the slowest input
In addition to examining the critical path, all three transistors
Department is included.   Of each such transistor i examined in the previous step
About the case, only the determined amount x_iArising from increasing
The increase in time spent is calculated. Cause such a maximum increase
One transistor in the critical path is determined
It is increased by the amount that was given. (Block 130 in FIG. 4)   Variables that reduce the amount by which the imposed constraints are satisfied but minimized
Return to the point of output delay determination until
(Return to block 110 in FIG. 4)
The return loop is closed (block 140 in FIG. 4).   Many paths through the circuit are less than the size of the circuit itself
It can always be large, so actually spread the circuit over many paths
This results in the gain of the method. In addition,
Constant x_iChanges only change the two gate delays
: Change and delay of gate including changed transistor
This is the delay of the gate that drives the transistor. Follow
And calculate the delay to find the worst output delay.
Return, the amount that can change as a result of a single variable change
Only recalculate.   Delay as a function of magnitude, as shown in the above equation
The curve follows the relationship Ax + B / x + C. Where A, B and
And C is greater than zero. This means that from some minimum value of x,
As x increases, the delay increases until a certain minimum delay is reached.
Decrease. The magnitude continues to increase beyond the minimum delay magnitude
Delay increases delay.   Beyond the point of minimum delay,
You will not want to increase. However, the present invention
According to one perspective, this is exactly what happens. So
The reason is that the size of the transistor is not only the speed
Observing that it also affects the speed around it
Power and the “totem pole” configuration
The capacitance of the transistor located close to the rail (ie,
Increase the size), the output of the "totem pole"
Reduced switching transistor delay
(Observed earlier in relation to Fig. 3)
You. Thus, according to this aspect of the invention, the method includes
Steps (within block 120) are included. It is one or more
The input affects the output, with the output coming before the slowest input
Look to increase the size of the transistor that affects it
The signal on the gates of these transistors
Analyze all situations that increase to a point. Transistor
When the size x is small, the delay increases as the area increases.
Decrease rapidly. When x is large, the delay is
Increase linearly, which is relatively slower than the rate of increase of the delay.   In yet another aspect of the invention, the method includes one step.
(Block 150 in FIG. 4). It is a feature of sub-networks
In order to improve performance (speed), the order of partial circuits in the VLSI circuit
Find the introduction. A concrete example best explains this,
For the sake of clarity, FIG.
Draw a road network. In this case, the input to transistor 20 is 7nse
c, and the input to transistor 21 is delayed by 3 nsec.
Reach in Nobu. In the timing configuration shown in FIG.
And if each capacitance (in the distributed RC model) has the value C
And if each resistor has a value R, then
Output discharge time is 7nsec + R2C +
2R (C + C_load). Reverse input leads, slower
When an input is applied to the transistor 21, the output discharge time
Is 7nsec + 2R (C + C_load). These two delays
Transistor difference, 2RC, means transistor 20 is two transistors
It represents the time required to discharge the capacitance of the node between them. This
Discharge must occur in both configurations of the circuit of FIG.
Absent. However, in the latter configuration, the slower input arrives.
"None" time gap between 3nsec and 7nsec before reaching
It happens during.   Generalizing the above with respect to FIG. 6, the static
CMOS complex gates have a pull-up network 25 and pull-down
Network 26 is included. The pull-up network contains only PFETs
Only, the pull-down network includes many NFETs. Two times
The inputs to the road network are the same, two (duplicate of each other)
The network is V_ddAnd interconnected in series between ground
I have. The connection between the two networks forms the output of the gate
You. A network with two nodes and any number of inputs is
By any combination of the following three rules
Therefore, it can be synthesized with a single transistor. 1) A single transistor is a circuit. For example, in FIG.
Source and drain are two connection points,
A port is a single input of the network. 2) Any number of networks connect their connection points in series
However, another network can be formed (for example, the fifth network).
Figure). The input of the new network is a combination of the inputs of the element network
It is. The connection points of the new network remain free.
Are the two connection points of the element. 3) Arbitrary number of networks connect their connection points in parallel
Then another network can be created. New network entry
Force is the combination of the inputs of the element network. New network connections
A connection point is a connection point of a connected element network.   Following on, by a series of composition rules, N sub-networks
Whenever a network is formed from
Logic functions can affect the order of the sub-networks
Not receive. However, as shown in the simple example of FIG.
In addition, the gate timing characteristics are generally
Is different. Improvement of the present invention to minimize delay
In the proposed method, the slowest one for each subnetwork is
Order the sub-networks according to the
You. The sub-network with the earliest of such time is
Power rail (sometimes V_ddOr ground)
The part that has been placed and has the slowest of such time
The road network is placed closest to the output. Given the network
The slowest time turns on
Is the slowest turn-on of the constituent transistors
It is the maximum value between The slowest turn-on time of an NFET is
It is the latest time to go high on that gate. PFET
Even the slowest turn-on times go most of that gate low
It is late time.   7 and 8 show a complex transistor containing 14 transistors.
This process is illustrated for a report. Figure 7 shows the classification
FIG. 8 shows the state after the classification. Inputs A, B, C and D
The latest time to go to i and the latest time to go to low
A_l<B_l<C_l<D_lAnd A_h<C_h<B_h<D_hIt is the order of. part
In network 30, three transistors in series
Are already in optimal order. A is V_ddClosest to
Should be. Because the slowest time to go to that low
Because the earliest, B follows, C follows.
is there. However, the pull-up is in series with the sub-networks 30 and 31.
And these networks are in their own order.
is there. When turning on the latest, earlier than the subnetwork 30
The sub-network 31 with_ddShould be closest to
is there. Accordingly, in FIG.
The position is reversed. On the other hand, in the pull-down partial network 32
Need re-ordering. It consists of three tigers in series.
About transistor. Transistor B has the highest output
Should be nearby, followed by C, followed by A.
This configuration in the sub-network 32 is also shown in FIG.
You.   To implement the above method, the usual requirements well known to those skilled in the art
Requires a combination of primes. What to do about the system
Is controlled by special purpose hardware or software.
In systems consisting of controlled generalized circuits.
Noh. With current technology, the latter method is easy to realize
In particular, the number of steps that are required
Because it can be used in the form of software for those skilled in the art.
It is.   The structure of a system that implements the principles of the present invention is illustrated in FIG.
It is shown. Block 151 is a timing analyzer
It takes as input the specification of the circuit whose placement should be optimized.
Receive. It is the active element of the circuit that produces the convex delay function
Is included. With the help of the model, the block
Under the control of 157, block 151 (eg,
-Analyze conditions (as taught by V. Agrawal)
And correlate the output of the circuit with the approximated delay time.
create. The table is stored in the memory 156. To block 152
Control goes, it should be filled from control block 157
And remove the maximum amount of speed condition to block 151
Select the output from the table created by Then control
Go to block 153, where the output associated with the selected output
A critical path is identified. Identified Criticala
Each active element in the pass has a given increase in dimensions (currently
Estimate the increase in delay for an increase from a certain magnitude).
To determine its sensitivity to changes in size
To be evaluated. Where all active elements have some
You will notice that it starts at the first minimum dimension. Late
Active elements that can be improved to maximize
Element is selected, and the condition of the magnitude of the change is stored in the memory 156.
Found in another table in. Next, control goes to block 155.
Where the change in size caused by block 155
The effect of the same output delay is evaluated. The result of this evaluation
Is supplied to block 157, where (a table in memory 156
Et al.) The results of circuit output delay and active element dimensions are collected and
It is compared with the operating conditions supplied to lock 157. On condition
Until so, control is returned to block 152.   Above, the points of the system of the embodiment introducing the principle of the present invention
About To further help,
Here are steps of a method that may be used to implement the principles of the present invention.
Think about the floor.   The step of selecting the minimum dimensions of the transistor is simply an integration
Used as a reference for circuit fabrication. The circuit conditions are combined
The step of separating memory and memory is well known and has been described earlier.
Agrawal's timing analyzer incorporates this stage
Therefore, to implement the system and method of the present invention,
Can be used.   The output of the timing analyzer is the output of the circuit
It is a table relating to force delay. From this table, the worst
The output is selected and "walking" backwards begins. worst
Distributed RC model based on the conditions of the partial network that generates the output
With the help of, the effect of each transistor in the sub-network is calculated
Is done. Also, as long as the delay is concerned, configure the key input
The input to the sub-network is identified. The biggest break in properties
Transistors in a subnetwork known to produce good
Is stored and the process provides a key input
Continue analyzing the road network. Analyze each partial circuit,
The transistor with the transistor that gives the greatest improvement is stored
Greater improvement in characteristics compared to transistor
Things are maintained. As a result, the (worst output) key
After all paths that hold the
Transistors offer the greatest improvement in operating characteristics
One of Cal Pas. The size of the transistor
And analyze the current timing of the output
I do. The process then selects and analyzes the new worst output
Repeat by doing.   The range of repetition every M times from each repetition
At a determined rate, the classification process begins. Classification group
The process itself is completely normal. Each logical part
Distribution networks have a limited number of inputs, which are generally compared
Very few (eg <10), so the number of possible
Easy to handle. Each sub-network in the critical path is reviewed.
And the classification of the input is the slowest time of each subnetwork.
Is turned on.   A simple “bubble-sort” algorithm is
Used to perform distribution network classification.   FIG. 10 shows an example of an arrangement resulting from the application of the present invention. Show
What is being combined is the area given the maximum speed
Different sizes (channel width) determined to occur in
MOS transistor.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a generalized diagram of a digital circuit divided into a combination of a logic portion and a memory portion; FIG. 2 is a diagram of a MOS transistor used in connection with an embodiment of the present invention. FIG. 3 shows a distributed RC model; FIG. 3 is an equivalent circuit showing a "totem pole" interconnection of three transistors and the delay through the circuit; FIG. 4 is a diagram illustrating the method used in the system of the present invention. FIG. 5 is a diagram showing a two-transistor circuit configuration in which the arrival times of input signals to two transistors are different; FIG. 6 is a diagram showing a PFET network used in a pull-up circuit;
FIG. 7 shows the general structure of a CMOS integrated circuit in which the network is used in a pull-down circuit; FIGS. 7 and 8 show the need to classify the elements in the sub-network of the circuit in order to optimize the operating characteristics; FIG. 9 is a diagram showing an embodiment of the system of the present invention; FIG. 10 is a diagram showing an arrangement of a part of an integrated circuit realized in accordance with the principle of the present invention. Description of main symbols 13, 14, 16: Capacitance 15: Resistor 20, 21: Transistor 25: Pull-up network 26: Down network 30, 31, 32: Partial network

Continuation of front page    (72) Inventor John Philip Fevern               United States 07060 New Jar               Shey, North Plainfield, No               Sous Jackson Avenue 236                (56) References JP-A-48-79984 (JP, A)

Claims (1)

(57) [Claims] An integrated circuit manufacturing method comprising the steps of arranging a memory element, an input section, an output section and a plurality of active elements, wherein a maximum delay for an output signal from at least one of the output sections is key. Characterized in that a value level is pre-selected, each of said key-holding output parts has a corresponding critical path, said critical path including said active element, and a change in size of said active element holding said key Affecting the signal delay of the output portion, wherein at least some of the active elements in the critical path have a size larger than a minimum size, and when the size of any active element in the critical path is reduced. The active element so that at least one signal delay of the keying output portion exceeds the preselected maximum delay. A method of manufacturing an integrated circuit, wherein a size is selected and at least one of the critical paths includes a circuit including a return path. 2. 2. The integrated circuit manufacturing method according to claim 1, wherein said feedback path is arranged on a latch circuit. 3. The method of claim 1 wherein the dimensions of the active element are selected according to a model characterizing the delay of the active element by a function that is convex in the critical area. 4. 4. The integrated circuit manufacturing method according to claim 3, wherein the model is based on distributions R and C representing the active elements. 5. The model represents the delay through one of the active elements based on the formula Ax + B / x + C, where A, B, and C are positive constants and x is a count of the dimensions of the active element. 5. The method of claim 4, wherein the counts of all other dimensions of the other active elements of the circuit are constant. 6. 2. The method of claim 1 wherein the dimensions of the active element are selected according to a technique that first assigns a minimum dimension to the active element. 7. 2. The integrated circuit of claim 1 wherein the dimensions of the active elements are selected based on a technique for sorting the sub-networks of the electronic circuit and selecting a replacement of the sub-network that best improves the performance of the circuit with respect to the specified criteria. Production method.