JP3070542B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for application to a high-density integrated circuit.

[0002]

2. Description of the Related Art As a conventional semiconductor device of this kind, for example, as described in Japanese Patent Application Laid-Open No. Sho. By arranging them on the center line of the cell, regions without patterns are formed above and below the cell, and this portion is used as a wiring region, thereby contributing to a reduction in chip area. However, if a component constituting a wiring is formed of a material other than a component constituting a transistor, such a device can be said to be meaningless. Incidentally, Japanese Patent Application Laid-Open No.
Japanese Patent No. 174445 discloses that a standard cell has a configuration in which a power supply line and a ground line are horizontally arranged in a central portion, and the height of the standard cell is not constant. The standard cell has been proposed, which can sufficiently allocate a part of the conventional wiring area since the height is sufficiently lower than the height of the standard cell, thereby realizing high integration.

FIG. 3 is a diagram showing a layout of a conventional semiconductor device. As shown in FIG. 3, all of the transistors T1 to T5 can be arranged below the power supply line G formed by the second-layer metal wiring. Further, transistors can be arranged under signal lines A to F formed by the second-layer metal wiring other than the power supply line G.

FIG. 4 is a diagram showing a layout in which the arrangement of transistors in a conventional semiconductor device is changed. FIG.
As shown in the figure, by arranging the transistors T3 to T5 and the like also under the signal lines A to F formed by the second layer metal wiring, the width of the cell having this transistor can be reduced, and the cell width can be reduced. By arranging another transistor in the set area, a function equivalent to the original function can be obtained with a small chip area.

FIG. 5 is a diagram showing a layout of the conventional semiconductor device in which the arrangement of signal lines A to F formed by the second-layer metal wiring is changed from that of FIG. Line groups A to F are arranged at positions not overlapping the channels of the transistors.

[0006]

However, the above-mentioned conventional semiconductor device has the following problems.

That is, since the transistor is arranged under the signal line formed by the second-layer metal wiring, when a signal line connected to the gate input of the transistor passes over the transistor, the transistor is connected to the transistor. When connecting the first-layer metal wiring connected to the gate input from a portion other than the channel to the signal line formed by the second-layer metal wiring, the first-layer metal wiring is passed through between the transistors. Must be kept apart, which hinders high integration.

The reason is that when a first-layer metal wiring connected to a signal line formed by a second-layer metal wiring is arranged on a channel of a transistor, the first-layer metal wiring is connected to a source and a drain of the transistor. In order to avoid this, the first layer connected to the signal line formed by the second layer metal wiring is connected to a portion other than the channel of the transistor in order to avoid this. This is because it is necessary to arrange metal wiring.

As a method for avoiding an increase in the interval between transistors, it is conceivable to move a signal line formed of the second-layer metal wiring to a position not overlapping the channel of the transistor. Before moving, the portion where the signal line formed by the second-layer metal wiring is located becomes a region where the second-layer metal wiring is not provided, which also becomes an obstacle to high integration. .

SUMMARY OF THE INVENTION Therefore, the present invention has been made in view of the above-described problems, and has as its object to reduce the chip area by efficiently arranging transistors and associated signal lines. Is to provide.

[0011]

In order to achieve the above object, the present invention has a first layer and a second layer of metal wiring,
In a semiconductor device in which the second-layer metal wiring is used for a power supply line or a signal line, and a transistor is arranged below a power supply line or a signal line formed by the second-layer metal wiring, a gate of the transistor A signal line formed of the second-layer metal wiring to be connected to an input passes through a channel of the transistor. The second-layer metal is connected to the transistor so as to be adjacent to the transistor. A small transistor that fits in a power supply line formed by wiring is arranged, and a drain of the small transistor is not connected to all signal lines formed by the second-layer metal wiring. .

[0012]

Embodiments of the present invention will be described below. In a preferred embodiment of the semiconductor device of the present invention, a signal line (A in FIG. 1) formed by a second-layer metal wiring connected to the gate input of the transistor (T4 in FIG. 1) is connected to the transistor (T4). When passing over the channel of T4 in FIG. 1, this transistor (T4 in FIG. 1)
4), a small transistor (T1 in FIG. 1) sized to fit within the power supply line (G in FIG. 1) is arranged, and the small transistor (T1 in FIG. 1) is replaced by a drain of the small transistor. Are connected to none of the signal lines (A to F in FIG. 1) formed by the second-layer metal wiring.

In the embodiment of the present invention, a blank portion below the signal line formed by the second-layer metal wiring formed by the small transistor (T1 in FIG. 1) is provided with the transistor (T4 in FIG. 1). The first-layer metal wiring directly connected to the gate input can be arranged.

According to the embodiment of the present invention, there is no need to increase the interval between transistors, and further, it is not necessary to change the position of the signal line formed by the second-layer metal wiring.

[0015]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 is a plan view showing the structure of a semiconductor device according to one embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a contact connecting a first-layer metal wiring and a second-layer metal wiring;
2 is a contact connecting the first-layer metal wiring to the polycrystalline silicon or the diffusion layer, 3 is a diffusion layer, 4 is polycrystalline silicon, 5 is a first-layer metal wiring, and A to F are second-layer metal wirings. G indicates a signal line formed of a metal wiring, G indicates a power supply line formed of a second-layer metal wiring, and T1 to T5 indicate transistors.

As shown in FIG. 1, when a signal line A formed by a second-layer metal wiring connected to the gate input of the transistor T4 passes over the channel of the transistor T4, it is adjacent to the transistor T4. In place, second
The small transistor T1 that fits within the power supply line G formed by the metal wiring of the layer is arranged. The drains of the small transistors T1 are connected to signal lines A to A formed by the second level metal wiring.
F is used only for the gate input of the transistor T2 adjacent to the small transistor T1 without being connected to any of F.

For this reason, when viewed from the small transistor T1 in the direction of the signal line formed by the second-layer metal wiring, there is a blank portion in all the signal lines A to F formed by the second-layer metal wiring. it can.

In this blank portion, a first-layer metal wiring directly connected to the gate input of the transistor T4 is arranged.

The same processing is performed on all the transistors having the same conditions as the transistor T4.

As another embodiment of the present invention, as shown in FIG. 2, instead of the transistor T4, a small transistor T1 is formed on the first layer metal wiring side directly connected to the gate input of the transistor T5. The first-layer metal wiring directly connected to the gate input of the transistor T5 may be arranged in a blank portion below the signal line B formed by the second-layer metal wiring.

[0022]

As described above, according to the present invention,
Since the width of the cell is not widened by the first-layer metal wiring directly connected to the gate input of the transistor, the chip area can be reduced and high integration can be achieved.

The reason is that, according to the present invention, the width of the cell is determined only by the arrangement of the transistors, and the first-layer metal wiring directly connected to the gate input of the transistor does not contribute to the chip area. is there.

[0024]

[Brief description of the drawings]

FIG. 1 is a layout diagram showing one embodiment of a semiconductor device of the present invention.

FIG. 2 is a layout diagram showing another embodiment of the semiconductor device of the present invention.

FIG. 3 is a layout diagram showing a conventional semiconductor device.

FIG. 4 is a layout diagram in which the arrangement of transistors in a conventional semiconductor device is changed.

FIG. 5 is a layout diagram in which a transistor arrangement and a signal line are changed in a conventional semiconductor device.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 contact connecting first-layer metal wiring to second-layer metal wiring 2 contact connecting first-layer metal wiring to polycrystalline silicon or diffusion layer 3 diffusion layer 4 polycrystalline silicon 5 first layer A to F, A ', B' Signal line formed by second-layer metal wiring G Power supply line formed by second-layer metal wiring T1 to T5 Transistors

Claims (3)

(57) [Claims] 1. A semiconductor device comprising: a first layer and a second layer metal wiring, wherein the second layer metal wiring is used for a power supply line and a signal line, and is formed by the second layer metal wiring. In a semiconductor device in which a transistor is arranged under a power supply line or a signal line to be connected, a signal line formed of the second-layer metal wiring to be connected to a gate input of the transistor passes over a channel of the transistor. A small transistor that fits within a power supply line formed by the second-layer metal wiring is disposed so as to be adjacent to the transistor for the transistor, and the drain of the small transistor is connected to the second-layer metal wiring. A semiconductor device which is configured not to be connected to all of the signal lines formed by the metal wirings. 2. The first layer of the first layer which is directly connected to a gate input of the transistor in a blank portion below a signal line formed by the metal wiring of the second layer on the extension of the drain portion of the small transistor. 2. The semiconductor device according to claim 1, wherein a metal wiring is arranged. 3. A semiconductor device comprising a first layer and a second layer metal wiring, wherein the second layer metal wiring is used for a power supply line and a signal line, and is formed by the second layer metal wiring. A semiconductor device in which one or a plurality of transistors are arranged below a power supply line or a signal line, wherein a signal line formed by the second-layer metal wiring connected to a gate input of the transistor is provided above a channel of the transistor. A transistor (hereinafter referred to as a “small transistor”) having a size within the line width of the power supply line is disposed next to the transistor, and the wiring of the diffusion layer of the small transistor is formed of the metal of the second layer. The connection structure is such that it does not connect to a signal line formed by a wiring. When viewed from the small transistor in a signal line direction formed by the second metal wiring, the small transistor is formed by the second metal wiring. Can blank space below the signal line, the white space formed by arranging the first-layer metal wiring directly connected to the gate input of the transistor, it wherein a.