JP3055320B2 - Video signal transmitting device and video signal receiving device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of video transmission in which digital data and audio data and control data are multiplexed and transmitted.

[0002]

2. Description of the Related Art Various proposals have been made for a method of multiplexing audio data and control data with a digital video signal and transmitting the multiplexed data. For example, when transmitting all video data including the blanking interval, an extra 1 bit is used to transmit auxiliary data and a synchronization signal in addition to the video signal transmission word (usually 8 to 10 bits / word). There is an additional transmission method.

[0003] As another method, a blanking interval of a video signal,
In particular, there is a method of multiplexing auxiliary data during a synchronization signal portion, a so-called sync chip period. In this method, since the video signal level of the portion of the sync chip is substantially constant, several level values of the sync chip are transmitted in this section, and auxiliary data is stored and transmitted in other portions.

[0004] With this transmission, the auxiliary data is extracted on the receiving side, and the period during which the auxiliary data is extracted is synchronized with the sync data.
By replacing with the chip level value, the original video signal can be reproduced. Moreover, the synchronization signal attached to the video signal is not affected at all. In this case, the amount of transmission information is exactly the same as when transmitting only the video signal, which is effective in terms of transmission efficiency.

[0005] Currently, multiplexing of video signals and auxiliary data using this method is used as a multiplexing method of video signals and auxiliary signals in serial transmission of NTSC composite signals.

At this time, the sampling frequency of the video signal is a clock (hereinafter abbreviated as 4 fsc) four times the subcarrier frequency.

[0007] The serial transmission system of this NTSC composite signal is currently SMPTE (Society of Motion Pict).
ure and Television Engineers: An organization that discusses and sets standards for movies, television broadcasts, etc. in the United States).

The multiplexing and demultiplexing of auxiliary data in an NTSC composite signal will be described with reference to FIGS.

In this method, (1) auxiliary data is compressed on a time axis to form a packet format. (2) The data in the sync chip period of the video signal is replaced with a synchronization pattern and a packet, converted into a serial signal, and transmitted. (3) Then, on the receiving side, after detecting the synchronization pattern and taking the word synchronization to convert it into a parallel signal, the packet is separated, the auxiliary data is taken out, the time axis is extended, and the auxiliary data is reproduced. (4) The video signal is reproduced by removing multiplexed synchronization patterns and packets from the video signal. (Table 1) shows the configuration of the packet.

[0010]

[Table 1]

In Table 1, ADF is a flag indicating a packet, DID is an identifier indicating a data type, and DB
N is the serial number of the packet with the same DID, DC
Is the number of data, and CS is the checksum.

In FIG. 5, reference numeral 501 denotes a time axis conversion memory; 502, a packet generator; 503, a synchronous pattern generator; 504, a timing signal generator;

The video signal converted to a digital signal by the quadrupled subcarrier frequency is input to a multiplexing unit 505. In addition, auxiliary data such as audio data and control data
It enters the time axis conversion memory 501 together with the clock of the auxiliary data, and performs the time axis conversion processing so as to enter the period of the sync chip of the video signal at a rate of four times the subcarrier frequency. The auxiliary data that has been subjected to the time axis conversion processing enters the packet generation unit 502 and is formed into a packet.
Enter 05.

FIG. 6 shows a specific example of the time axis conversion memory 501 using a dual port memory. 601 is a write address generator, 602 is a read address generator, 603 is a dual port memory, and 604 is a read / write control circuit.

The input clock of the audio signal on the write side enters the write address generator 601, generates an address corresponding to the audio input signal, and writes the address to the memory 603. At a stage where the input data is written to some extent, a read clock that continues for the retrace period at the sampling clock rate of the video signal on the read side is input, the read address generator 602 is operated, and the value corresponding to the address is stored in the memory 603. By reading from, time axis conversion becomes possible. Note that the read / write control circuit 604 starts reading after initially writing data to some extent earlier, and checks whether the write address does not match the read address (if the write address does not match, the device operates correctly. Not checked). In addition, when data for reading is not stored, control is performed so that nothing is read. The configuration of the address generators 601 and 602 may use, for example, a binary counter.

The synchronization pattern generation unit 503 determines a specific pattern in the video signal so that the receiving side can reliably detect the position where the auxiliary data (hereinafter, abbreviated as compressed auxiliary data) stored on the time axis is stored. Place
Thereafter, the compression auxiliary data is stored. With this configuration, if the specific pattern can be detected on the receiving side, the position of the compressed auxiliary data is determined, and the auxiliary data can be extracted. For this purpose, the specific pattern needs to be a pattern that cannot exist in a video signal or auxiliary data. The number of specific patterns may be one or more.

The timing signal generator 504 counts by inputting the quadrupled subcarrier frequency and clears the internal counter at the cycle of the horizontal synchronizing signal. NT
Since the 4fsc frequency of the SC and the horizontal synchronization signal fh have an integer multiple relationship, the position of the same counter output (address) in any line corresponds to the same position in the horizontal synchronization signal. Specifically, for example, the falling position of the horizontal synchronizing signal always has the same address on any line. For this reason, in the output of the internal counter, the position of the synchronization pattern signal and the position of the auxiliary data are equal to each other in any line (for example, if the auxiliary data, the position of the counter 7
95 to 855) can be selected and multiplexed. Also, at some points (for example, 788 to 789), if the section of the synchronization pattern signal and the section of the compression auxiliary data are selected so as to transmit the level of the sync chip, the level of the sync chip can be reproduced on the receiving side. Will be possible. By decoding the output of the counter with a specified value, a selection signal for selecting a synchronization pattern signal and compression auxiliary data is created.

These selection signals enter a packet = synchronization pattern multiplexing unit 505, and receive a video signal, a synchronization pattern signal,
Multiplexing is performed by selecting auxiliary data.

Packet generator 502, synchronization pattern generator 503, timing signal generator 504, packet
= A slightly more detailed circuit configuration example of the synchronization pattern multiplexing unit 505 is shown in FIG.

In FIG. 7, 701 is a checksum calculation circuit, 702 is a DBN counter, 703 is an ADF register, 704 is a DID register, 705 is a DC register, 706 is an address counter, 707 is an address decoder, and 708 Denotes a first selector, 709 denotes a register for a synchronization pattern, and 710 denotes a second selector.

The time-converted audio data is added by the checksum calculation circuit 701 every time data is input. Each time data is read from the time axis conversion memory, the DBN counter 702 increments the counter to obtain the value of DBN. The ADF indicating the head of the packet is a fixed value. Number of data DC
Becomes a fixed value if the number of readouts per operation is fixed. The value of DID is also a fixed value. Therefore, each value is set in each register (702 to 705). Also, the value of the checksum is obtained when all data is input. Accordingly, a packet is generated by decoding the output of the address counter 706 by the address decoder 707, generating a timing pulse for selection corresponding to each data, and selecting the necessary data by the first selector 708. The synchronization pattern is also a fixed value, and a value is set in the synchronization pattern register 709 in advance. The packet from the packet generator, the video signal and the synchronization pattern are
The multiplexing is performed by switching with the selector timing pulse from the address decoder 707 in the selector 710.

Next, the separation of the compressed auxiliary data from the multiplexed signal will be described with reference to FIG. In FIG. 8, reference numeral 801 denotes a synchronization pattern detection unit, 802 denotes a timing signal generator, 803 denotes a packet separation unit, 804 denotes a hold unit, 805 denotes a packet check unit, and 806 denotes a time axis conversion memory.

An NTSC video signal obtained by multiplexing a packet and a synchronization pattern signal from a multiplexer enters a synchronization pattern detection section 801 to detect a synchronization pattern and perform correct word sequence conversion.

FIG. 9 shows a specific configuration example of the synchronization pattern detection unit 801. If the number of bits in one word is large, the description will be enormous. Therefore, the case of four bits will be described as an example (usually, one word width is 8 bits or 10 bits in the standard).

Reference numeral 901 denotes a one-bit shift circuit;
A bit shift circuit, 903 is a 3-bit shift circuit, 90
4, 905, 906, and 907 are synchronous pattern match detection circuits, and 908 is a selector.

[0026] The inserted synchronization pattern to _{F H, 0 H, 0 H} , 0 H 4 words. The other data (video data) to any other value (1 _H to E _H). The 4-bit word input of the serial / parallel converter output is 1
A bit shift circuit 901, a 2-bit shift circuit 902,
The data enters the 3-bit shift circuit 903, respectively. Now, the serial data string including the synchronization pattern is ****** 1111000000
It is assumed to be in the form of 000000 ******. If the word synchronization is not obtained If the 4-bit word after serial / parallel conversion is, for example, ** 11,1100,0000,0000,00 **, the output of 1-bit shift is *** 1,1110 , 0000,0000,000
*, **** Output of 2-bit shift is ****, 1111,0000,0000,
0000, ****, 3-bit shift output is ****, * 111,1000,00
00,0000,0 ***. Here, * indicates data bits other than the synchronization pattern, and, indicates a word delimiter.

The bit shift circuits 901 to 903 can be realized by using two stages of one-clock delay circuits (which can be realized by D flip-flops) having a width of 4 bits and selecting output bits of each stage. Synchronous pattern match detection circuit 904
907 detects whether four consecutive words are F _H , 0 _H , 0 _H , and 0 _H. This circuit has four stages of 4-bit D flip-flop circuits and a logic circuit for checking whether the output of each D flip-flop has the above-mentioned value (in this example, two 4-input ANDs, 4
(It can be realized with three inputs NOR). In the above example of bit shifting, when two bits are shifted, the synchronization pattern match detection circuit 906 becomes 1 (others are 0, and the combination of normal data does not generate the synchronization pattern and does not match). Therefore, correct word synchronization is obtained when two-bit shifting is performed, and a word-synchronized output is obtained by selecting a two-bit shifted output from the output of each bit shifting circuit by the selector 908.

When a synchronization pattern is detected, its position is always stored at a fixed position (address) on the multiplex side. Therefore, in the timing signal generator 802 to which the transmission clock is input, the detection position is stored in an internal counter. Is loaded, the internal counter operates in the same way as the counter on the transmitting side, and indicates the same position for the same address. Therefore, it becomes possible to decode the output of the internal counter, create a corresponding timing signal, and extract the packet portion by the packet separating unit 803. After the extracted packet is checked by the packet check unit 805, the auxiliary data portion therein is written into the time axis conversion memory 806 together with the clock of the video sampling frequency rate existing only in the sync chip period. The data written in the time axis conversion memory 806 is read out at the original clock of the transmitted auxiliary data to expand the time axis and reproduce it as the original auxiliary data. Although the configuration of the time axis conversion memory 806 is the same as that of the time axis conversion memory 501 of the video signal transmitting apparatus,
The write clock and read clock are reversed.

In the hold unit 804, the synchronization pattern signal and the compression auxiliary data in the video signal are masked and removed by the select pulse from the timing signal generator 802, and the value of the section holds the value of the sync chip. Thus, the video signal can be reproduced.

Auxiliary data can be multiplexed on the composite video signal digitized in this way.

[0031]

However, when this method is developed and applied to a component signal or R, G, B signals, the concept of a subcarrier frequency does not exist, and a synchronization signal is used as a reference. It is. Also CCD
A camera using a digital process that digitizes and processes a CCD output using an element is currently in practical use. In this case, the drive frequency of the CCD is often used as it is as a sampling frequency for digitization. Although the driving frequency of the CCD changes depending on the number of pixels of the CCD, the driving frequency is always an integral multiple of the horizontal synchronization frequency.

Therefore, component signals, R, G, B
Sampling frequency (f
s) becomes fs = n * fh (fh: horizontal synchronization frequency). Here, n is an integer and varies depending on the case. Therefore, it is necessary to be able to cope with the case where n is an arbitrary integer without a significant change in the circuit.

In the case of component signals or R, G, B signals, if all channels are supplemented with auxiliary signals and synchronization signals and transmitted, each processing circuit requires the number of channels. In addition, it is necessary to divide auxiliary data into each channel at the time of transmission, and to adjust and multiplex the timing of auxiliary signals from each channel at the time of reception, which makes the circuit very complicated.

[0034]

A video signal transmitting apparatus according to the present invention has a sampling frequency of an integral multiple of a horizontal synchronizing frequency.
Multiple signal component channels converted to digital signals
A device for transmitting video signals consisting of
Data on the time axis to the rate of the sampling frequency.
A time axis conversion memory, a packet generation unit for converting the time axis converted auxiliary data into a packet form, a synchronization pattern generation unit for generating a synchronization pattern required for data separation, and information on a multiplex position of the auxiliary data. Predefined settings, including
An external data input device for providing a value and a hole for the set value
Based on the set of registers to be
To specify the multiplex position of the packet and the synchronization pattern.
A timing signal generator for determining
Based on the output of the generator, the packet and the synchronization pattern
And the synchronization signal of one channel in the video signal.
Packet multiplexed during the signal period = synchronization pattern multiplexing section
Packet = packet and packet
Of the video signal in which the
Video multiplexing unit that multiplexes with other video signal channels
Is constituted by a, it is to solve the above problems.

Further, the video signal receiving apparatus of the present invention inputs the multiplexed signal from the video signal transmitter, the multiple
Including a synchronization pattern detecting unit for detecting a synchronization pattern in the signal, and the image separation unit for separating each channel of the video signals using the synchronization pattern detection signal from the synchronization pattern detection unit, the information of the multiple positions of the auxiliary data and the external data input device that provides a predetermined setting value, and registers for storing the setting value, using the sync pattern detection signal, or
One the reference to the stored set values and packet <br/> timing signal generator for generating a timing signal to take out for assistive data, auxiliary in the channels of demultiplexed video signal
From the channel where the auxiliary data packet is multiplexed,
A packet separating unit retrieving the packet by the timing signal, and a packet check unit for checking the extracted packet, in one channel of video signal
Packets are multiplexed, it is removed at the timing signal, by holding the signal level of the synchronizing signal portion, and a hold unit for reproducing video signals, the packet
A time axis conversion memory for converting the auxiliary data in the packet output from the check unit to the original time axis and outputting it back to the original time axis solves the above-mentioned problems, and reproduces the video signal and the auxiliary data. Becomes possible.

[0036]

In the present invention, the component signal, R,
For a video signal having a plurality of channels such as G and B signals, the video signal is quantized using a sampling frequency that is an integral multiple of the horizontal synchronization frequency, and only one of the channels is used during a synchronization signal period (eg, a blanking period). The auxiliary data and the synchronization pattern are multiplexed and not multiplexed to other channels, and then each video channel is multiplexed for transmission. Thus, when multiplexing auxiliary data to a video signal such as a component signal or R, G, B signal and transmitting the same, the circuit scale is almost the same as that of a conventional composite signal and a sufficient amount (48 kHz sampling for an audio signal) 2
It becomes possible to transmit the 0-bit quantized monaural signal on 4 ch).

Further, by adopting a configuration in which various set values are inputted from the outside, stored in a register, and the stored values are processed with reference to the values, even when the sampling frequency of the video is changed, the external setting is required. It is possible to deal with all cases by changing the set value without changing the hardware configuration. In this case, since the video signal is not limited at all, it is possible to deal not only with the signal of the current broadcasting system but also with the HDTV signal in the same manner.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a video signal transmitting apparatus according to the present invention will be described with reference to FIG.

In FIG. 1, 101 is an external data input device, 102 is a register group, 103 is a time axis conversion memory,
104 is a packet generator, 105 is a synchronous pattern generator, 106 is a packet = synchronous pattern multiplexer, 107 is a timing signal generator, and 108 is a video multiplexer.

Digital video signal quantized at a sampling frequency that is an integral multiple of the horizontal synchronizing frequency (this embodiment will be described for the case of three video signal channels).
, The video signal of channel 1 enters the packet = synchronization pattern multiplexing unit 106, and a packet and a synchronization pattern are added.

Auxiliary data, such as audio data and control data, enters the time axis conversion memory 103 together with the clock of the auxiliary data, and at the rate of the video sampling frequency,
A time axis conversion process is performed so as to enter a blanking period of the video signal. The auxiliary data that has been subjected to the time axis compression processing enters the packet generation unit 104, and the header (ADF to DC) and the checksum (C
S) is added to form a packet and input to the packet = synchronization pattern multiplexing unit 106. Synchronization pattern generator 105
Then, a specific pattern is placed at a predetermined position in a video signal so that the storage position of the packet can be reliably detected on the receiving side, and then the packet is stored. As for the specific pattern, it is necessary to adopt a pattern that does not occur in the combination of the video signal and the auxiliary data, just like the case of the NTSC composite signal.

On the other hand, the external data input device 101 fetches the set value of each mode given from the outside, and stores the value in the register group 102. Then, the timing signal generator 107 creates a timing signal with reference to the set values stored in the register group 102.

As the external data input device 101, for example, a microcomputer, a PROM (Programmable Read Only Memory)
Can be used. In the case of a microcomputer, each set value is given by software, and the value is written from a port of the microcomputer to each register of the register group. When a PROM is used, each set value is written in the PROM, and the value is written in each register of the register group at the time of reading.
As a result, it is possible to externally provide a set value corresponding to each case.

External data input device 101, register group 1
02, an example of the operation of the timing signal generator 107 is shown in FIG.
This will be described with reference to FIG.

In FIG. 2, the external data input device 101
Shows the case where a microcomputer is used. 201 is a microcomputer, 202 is a PROM storing processing software of the microcomputer, 203 is a counter for timing generation, 20
4 is a first match detection circuit, 205 is a second match detection circuit, 206 is a third match detection circuit, 102-1, 102
Reference numerals -2 and 102-3 denote registers, respectively, and reference numeral 207 denotes a set-reset type flip-flop.

The microcomputer 201 reads the processing software from the PROM 202, reads the value of each set value, and outputs the value to the output port of the microcomputer. At the same time, a chip select signal for selecting each register and a strobe pulse for writing data to the register are output from the output port. After writing the set value to each register, the output port is set to high impedance. Thus, the set values are written to the registers 102-1, 102-2, and 102-3.

In the example of this description, the value of the period -1 of the counter 203 (that is, fs = n * f) is stored in the register 102-1.
The value of n-1 in the case of h) and 102-2 are the start address of the position where the synchronization signal and the packet signal are stored, and 102-2.
In -3, the end address of the position where the synchronization signal and the packet signal are stored is entered. The counter 203 counts using a sampling clock as an input. Counter 203
The output is the coincidence circuit 2 with the register output of 102-1.
04, and if there is a match, the counter 2
Clear 03. Thus, the address of the counter 203 and each data of the video signal correspond one-to-one. Also,
The output of the counter 203 enters the matching circuit 205 together with the output of the register 102-2, and outputs a match signal when the output of the counter 203 matches the start address. Similarly, the output of the counter 203 enters the matching circuit 206 together with the output of the register 102-3, and outputs a match signal when the output of the counter 203 matches the end address. The output of the coincidence circuit 205 is set-reset flip-flop (hereinafter referred to as RS-F).
By connecting the output terminal of the match circuit 206 to the reset terminal of the flip-flop 207,
, A timing signal indicating the position of the packet and the synchronization pattern is obtained.

Although this example has been described in connection with a very simple case, by adopting such a setting method, it is possible to externally provide various designations and setting values of various methods without changing the hardware of the main body. Becomes In the case of changing, it is possible to cope only by changing the PROM of the microcomputer.

In this way, the timing signal generator 1
The packet from the packet generation unit 104 and the synchronization pattern from the synchronization pattern generation unit 105 are converted to the packet = synchronization pattern multiplexing unit
In step 6, multiplexing is performed by switching to a video signal.

The video channel (channel 1 in this example) to which the packet and the synchronization pattern are added is multiplexed with the remaining video channels by the video multiplexing unit 108 and output.

For this multiplexing, simple time division multiplexing (switching at a frequency three times the sampling frequency in the case of this example) is sufficient. FIG. 3 shows the configuration of the multiplexed signal.

FIG. 3 shows an example of R, G, B signals.
After multiplexing a synchronization pattern (4 words in this example) and a packet only on the G signal, the R, G, and B signals are further multiplexed.

The multiplexed signal is subjected to parallel / serial conversion if serial transmission is performed, scrambled to remove a DC component, and then driven by a coaxial driver to perform coaxial transmission, or The light is converted into an optical signal by an optical converter and transmitted.

Next, an embodiment of a video signal receiving apparatus for separating a signal multiplexed by this method into a video signal and auxiliary data again will be described with reference to FIG.

In FIG. 4, reference numeral 401 denotes a synchronization pattern detection unit, 402 denotes a video separation unit, 403 denotes a packet separation unit,
04 is an external data input device, 405 is a register group, 40
6 is a timing signal generator, 407 is a hold unit,
08 is a packet check unit, and 409 is a time axis conversion memory.

A multiplex signal serially transmitted by optical transmission or coaxial transmission first extracts a clock to reproduce a sampling clock of a video signal. Further, the multiplexed signal is subjected to serial / parallel conversion and descrambling, and then a synchronization pattern is detected by a synchronization pattern detection unit 401 to perform correct word sequence conversion. The basic configuration of the synchronization pattern detection unit 401 is basically the same as that shown in FIG. 9 of the conventional example. However, in this example, since the synchronization pattern exists every three words, the detection position is separated by three words for processing. Just do it.

The video separation section 402 separates each video channel and detects an address in each channel using the synchronization pattern detection signal. In synchronization detection, 1c
Since the synchronization pattern is stored only in h, and the detection position of the synchronization pattern in that case is determined, the video channel can be separated by looking at the synchronization pattern detection position. Further, since the storage position of the synchronization pattern is determined on the transmission side, the data and the address of each video channel can be determined on a one-to-one basis from the detection position.

On the other hand, the external data input device 404 takes in the set value of each mode given from the outside, and stores the value in the register group 405. Then, the timing signal generator 406 creates a timing signal with reference to the set values stored in the register group 405. The configuration is the same as that of the video signal transmission device.
The set value given by the OM is stored in the register group 405, and is used for controlling the counter in the timing signal generator 406, for comparing with the counter output, and for generating the necessary timing signal in the packet separation unit 403. It is to let.

Next, the video channel multiplexing the packet and the synchronization pattern enters the packet separation unit 403,
The packet portion is extracted by the gate pulse generated by the timing signal generator 406.

The packet check unit 408 checks the header and checksum of the extracted packet.
Then, the data in the packet existing only in the retrace interval is written to the time axis conversion memory 409 at a clock of the video sampling frequency. The reading is performed by extending the time axis by using the original clock of the auxiliary data.

The hold unit 407 masks and removes the synchronization pattern and the packet from the video channel with the gate signal from the timing signal generator 406, and holds the value of the sync chip as the value in that section. Thus, it is reproduced as a video signal.

Then, each channel of the original video signal can be completely reproduced together with the other two non-multiplexed video signals from the video separation unit 402.

[0063]

According to the present invention, when multiplexing video signals having a plurality of channels such as component signals, R, G, and B signals and performing serial transmission, a sampling frequency that is an integral multiple of the horizontal synchronization frequency is used. Perform quantization,
Auxiliary data (packets) and a synchronization pattern are multiplexed in a synchronization signal period (for example, a blanking period) of only one of the channels, and are not multiplexed in other channels. This makes it possible to transmit a sufficient amount of auxiliary data with a circuit size that is almost the same as that of a conventional composite signal when multiplexing auxiliary data on video signals such as component signals and R, G, and B signals. (Considering an audio signal as auxiliary data, in the case of transmitting a component signal of the current system, it is possible to transmit a monaural signal 4ch with 48 kHz sampling and 20-bit quantization).

In the present invention, various setting values are input from the outside, stored in an internal register, and processing is performed by referring to the stored values, so that the sampling frequency changes (for example, as in a digital camera). In the case where the sampling frequency changes depending on the size of the CCD), it is possible to deal with all cases simply by changing the set value from the outside without any circuit change.

In addition, not only signals of the current broadcasting system but also HDTV signals can be handled in the same manner as video signals.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a video signal transmission device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a more detailed configuration of a main part in the embodiment.

FIG. 3 is a timing waveform chart for explaining the operation of the embodiment.

FIG. 4 is a block diagram showing a configuration of a video signal receiving apparatus according to another embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional video signal transmission device.

FIG. 6 is a block diagram showing an internal configuration of a time axis conversion memory 501 in FIG. 5;

FIG. 7 is a block diagram showing a more detailed configuration of a main part in FIG. 5;

FIG. 8 is a block diagram showing a configuration of a conventional video signal receiving device.

FIG. 9 is a block diagram showing the internal configuration of a synchronization pattern detection unit 801 in FIG.

[Explanation of symbols]

 101, 404 External data input device 102, 405 Register group 103, 409 Time axis conversion memory 104 Packet generation unit 105 Synchronization pattern generation unit 106 Packet = synchronization pattern multiplexing unit 107, 406 Timing signal generation device 108 Video multiplexing unit 401 Synchronization pattern detection Unit 402 video separation unit 403 packet separation unit 407 hold unit 408 packet check unit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04N ^7/ 025-7/088 H04N 5/04

Claims (2)

(57) [Claims] 1. Sampling of an integral multiple of a horizontal synchronization frequency
Multiple signal components converted to digital signals by frequency
Device for transmitting video signals consisting of
The auxiliary data to the rate of the sampling frequency
A time axis conversion memory for conversion, a packet generator for converting the time axis converted auxiliary data into a packet form, a synchronization pattern generator for creating a synchronization pattern necessary for data separation, and a multiplex position of the auxiliary data. Set value including information
An external data input device, a register group for holding the set value, and the packet based on the held set value.
Timing signal for specifying a multiplex position of the synchronization pattern
A packet generator based on an output of the timing signal generator.
And the synchronization pattern in one of the video signals.
Packets multiplexed during the synchronization signal period of the channel = synchronization packet
A turn multiplexing unit and a packet
The channel of the video signal with the multiplexed sync pattern
Video multiplexing to multiplex with other video signal channels
Video signal transmission apparatus and a part. 2. The video signal transmitting apparatus according to claim 1,
The multiplexed signal as an input, and a synchronization pattern detection unit for detecting a synchronization pattern in the multiplexed signal, and the image separation unit for separating each channel of the video signals using the synchronization pattern detection signal from the synchronization pattern detection unit, the auxiliary and the external data input device that provides a predetermined set value including information of multiple positions of the data, the register group for storing the setting value, using the sync pattern detection signal, and said stored
A timing signal generator for generating a timing signal for extracting a packet of auxiliary data with reference to the set value, and a packet of the auxiliary data in a channel of the separated video signal.
From the channel on which the
A packet separating unit retrieving the packet by the signal, and a packet check unit for checking the retrieved packets, packets are multiplexed into one channel of video signal
And the removal by the timing signal, by holding the signal level of the synchronizing signal portion, and a hold unit for reproducing video signals, the packet checking unit original time the auxiliary data and converts the time axis in the output of the packet video signal receiving apparatus and a time-axis conversion memory for output back to the shaft.