JP2967126B2 - Semiconductor integrated circuit device for flat light valve substrate - Google Patents

Description

The present invention relates to a substrate device for driving a flat light valve used in a direct-view display device, a projection display device, or the like. More specifically, the present invention relates to a semiconductor integrated circuit board device in which a pixel electrode group, a switch element group, and a drive circuit element group are formed on a semiconductor thin film coated on a substrate surface. This substrate device is integrated with a liquid crystal panel, for example, to constitute a so-called active matrix device.

[Conventional technology]

The principle of an active matrix device is simple: a switching element is provided for each pixel, the corresponding switching element is turned on when a specific pixel is selected, and the switching element is turned off when not selected. It is. In addition, each switch element is driven by a peripheral circuit element forming a drive circuit. These switch elements and peripheral circuit elements are formed on a glass substrate constituting a liquid crystal panel. Therefore, a technique for thinning the switch element and the peripheral circuit element is important. Usually, a thin film transistor is used as this element.

Conventionally, in an active matrix device, a thin film transistor is formed on the surface of an amorphous silicon thin film or a polycrystalline silicon thin film deposited on a glass substrate. Since these amorphous silicon thin films and polycrystalline silicon thin films can be easily deposited on a glass substrate by using a vacuum evaporation method or a chemical vapor deposition method, they are suitable for manufacturing an active matrix device having a relatively large screen. Therefore, it is suitable for a direct-view display device and the like.

In recent years, apart from the direct-view display device, there has been an increasing demand for a high-speed microminiature display device or a light valve device having miniaturized high-density pixels. Such a micro light valve device is used, for example, as a primary image forming surface of a projection type image device, and can be applied as a projection type high vision television. For this purpose, a semiconductor integrated substrate device for a high-speed microminiature light valve having a pixel size of the order of 1 μm and a size of several cm as a whole by using a fine semiconductor manufacturing technology is desired.

However, when a conventional amorphous or polycrystalline silicon thin film is used, the current drive is low and the high-speed operation is difficult because the material is not single crystal. Is not formed. For example, in the case of an amorphous silicon thin film, the film formation temperature is about 300 ° C., so that high-temperature processing required for a miniaturization technique cannot be performed. In the case of a polycrystalline silicon thin film, the size of crystal grains is several μm.
Therefore, miniaturization of the transistor element is inevitably limited. The deposition temperature of the polycrystalline silicon thin film is 600 ° C.
Therefore, it is impossible to sufficiently apply a miniaturization technique that requires a high-temperature treatment of 1000 ° C. or more. As described above, in a conventional semiconductor integrated circuit substrate device for an active matrix display device using an amorphous or polycrystalline silicon thin film, the integration density, the high-speed operation, and the chip are almost the same as those of a normal semiconductor integrated circuit element. There is a problem that it is extremely difficult to realize the dimensions.

In particular, in order to reduce the size of a semiconductor integrated circuit substrate device, it is necessary to integrate a peripheral circuit element group at a very high density in addition to the switch element group. However, it has been difficult to form a peripheral circuit element group requiring a higher level of miniaturization technology on a polycrystalline silicon thin film or an amorphous silicon thin film at an ultra high density. For this reason, it has not been possible to realize a semiconductor integrated circuit substrate device for an active matrix device having the same size as a normal LSI chip.

In view of the above-mentioned problems of the prior art, the present invention can form, on the same substrate surface, a group of peripheral circuit elements requiring higher-speed and higher-density integration, in addition to a group of switch elements for selectively supplying power to pixels. An object of the present invention is to provide a structure and a manufacturing method of a semiconductor substrate device.

[Means to solve the problem]

In order to achieve the above-mentioned object of the present invention, a semiconductor device for a light valve substrate according to the present invention defines at least a part of an electrically insulating substrate and a peripheral circuit area arranged at least on a part of the substrate surface. Semiconductor single crystal thin film.
A pixel array area is provided adjacent to the peripheral circuit area, and a pixel electrode group and a switch element group for selectively supplying power to each pixel electrode are formed. As a feature of the present invention, a circuit element group is formed in an integrated manner on the semiconductor single crystal thin film defining the peripheral circuit area by using, for example, an VLSI manufacturing technique. This circuit element group constitutes a peripheral circuit having various functions, and includes, for example, a drive circuit for driving the switch element group.

In order to manufacture a semiconductor device for a light valve substrate having such a structure, first, a high-quality material generally used for forming a semiconductor single crystal plate, for example, a super LSI, on a substrate surface on which at least a part of an electrically insulating film is provided. Bonding the silicon single crystal wafer
The wafer is mechanically or chemically polished to entirely form a semiconductor single crystal thin film. Next, the semiconductor single crystal thin film is selectively processed to form a peripheral circuit area made of the semiconductor single crystal thin film and a pixel array area adjacent thereto. For example, a peripheral circuit area is constituted by a portion where the semiconductor single crystal thin film is partially removed, and a thin film made of semiconductor polycrystal or semiconductor amorphous is formed on a substrate surface portion where the semiconductor single crystal thin film is removed. The pixel array area is formed by coating. Subsequently, a pixel electrode group and a switch element group for selectively supplying power to each pixel electrode group are formed in the pixel array area. Further, at the same time as or before or after the step of forming the switch element group, the circuit element groups are densely integrated in the peripheral circuit area using the super LSI technology or the LSI technology to form a peripheral circuit. This peripheral circuit includes, for example, a drive circuit for driving the switch element group.

[Function of the invention]

As described above, according to the present invention, the semiconductor substrate is divided into the peripheral circuit area and the pixel array area, and at least the peripheral circuit area is coated with the semiconductor single crystal thin film. The peripheral circuit element group is integrated on the semiconductor single crystal thin film at an extremely high density. Therefore, the semiconductor integrated circuit board device according to the present invention can realize an extremely small chip size as a whole. This circuit element group includes, for example, a complementary insulated gate field effect transistor formed on a silicon single crystal thin film. Such a CMOS transistor can operate at high speed with low power consumption. Although CMOS transistors can be formed at a high density with respect to a silicon single crystal thin film, a CMOS transistor having sufficient performance (especially speed) and small size can be formed with respect to a silicon polycrystalline thin film or a silicon amorphous thin film. Things are difficult in practice.

The circuit elements formed in the peripheral circuit area constitute a peripheral circuit having various functions. For example, the peripheral circuit includes a driving circuit for driving a switch element group formed in the pixel array area. Further, it includes a control circuit for controlling the drive circuit according to an image signal or the like input from the outside. Alternatively, it includes a DRAM sensor amplifier circuit for detecting the charge temporarily stored in each pixel electrode formed in the pixel array area as storage information. Further, it includes a temperature sensor for detecting the ambient temperature, an optical sensor for detecting the intensity of incident light, a solar cell for supplying power, and the like. These additional circuits can be manufactured very easily on silicon single crystal thin films using conventional semiconductor manufacturing techniques.

Incidentally, the pixel array area adjacent to the peripheral circuit area may be formed using a semiconductor single crystal thin film, but only a semiconductor polycrystalline thin film or a semiconductor amorphous thin film may be used in this area. These thin films are less suitable for high-density integration of circuit elements than semiconductor single-crystal thin films, but are relatively insensitive to incident light. Therefore, it is possible to form a switch element that is not adversely affected by the incident light. The integration density of the switch element group is lower than the integration density of the peripheral circuit element group. As such a switch element, an insulated gate field effect type thin film transistor can be used, but a thin film diode having a smaller element size may be used.

〔Example〕

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic partial sectional view showing a typical example of a structure of a semiconductor integrated circuit device for a flat light valve substrate according to the present invention. In this typical example, an electrically insulating transparent substrate 1 is used. As shown, the surface of the substrate 1 is divided into a peripheral circuit area and a pixel array area adjacent thereto. The peripheral circuit area is covered with a semiconductor single crystal thin film 2. The semiconductor single crystal thin film 2 is selectively etched to form a plurality of island-shaped element regions. In the figure, only a pair of element regions are shown for simplicity. In each of these element regions, a circuit element constituting a peripheral circuit is formed. In one element region, an N-type insulated gate field effect transistor 3 is formed, and in the other element region, a P-type insulated gate field effect transistor 4 is formed. The pair of the N-type transistor 3 and the P-type transistor 4 constitute a set of so-called CMOS transistors. CMOS transistors are extremely high-performance circuit elements, and are characterized by high-speed operation and low power consumption. The N-type MOS transistor 3 is composed of a pair of N ⁺ -type drain regions D and source layers S formed separately on the surface of a P ⁻ -type element region and a gate electrode G laminated and arranged via an insulating film 5. It is configured. On the other hand, the P-type transistor 4
Is composed of a pair of P ⁺ -type drain regions D and source regions S formed separately on the surface of the N ⁻ -type device region, and a gate electrode G stacked with the insulating film 5 interposed therebetween. .

On the other hand, a pixel electrode and a switch element group are formed in the pixel array area. In the figure, one pixel electrode 6
Only one switch element corresponding to is shown for simplicity. The switch element is constituted by an insulated gate field effect thin film transistor 7. The thin film transistor 7
It comprises a gate electrode G formed on the surface of the substrate 1 and a pair of drain region D and source region S formed on a semiconductor polycrystalline thin film 8 laminated via a gate insulating film 5 '. The semiconductor polycrystalline thin film 8 forming the source region S extends and forms the pixel electrode 6. By setting the thickness of the semiconductor polycrystalline thin film 8 to several hundred degrees, a substantially transparent pixel electrode 6 can be formed.

Next, FIG. 2 shows a schematic planar device structure of a semiconductor integrated circuit device for a flat light valve substrate. As shown, the substrate 1 is divided into a peripheral circuit area covered by a semiconductor single crystal thin film 2 and a pixel array area covered by a semiconductor polycrystalline thin film 8. Its boundaries are indicated by dotted lines.

In the pixel array area 8, a group of thin film transistors 7 arranged in a matrix is formed similarly to a group of pixel electrodes 6 arranged in a matrix. Thin film transistor 7
Are connected to the corresponding pixel electrodes 6, and
Similarly, the gate electrode is connected to the scanning line 9, and the drain electrode is also connected to the signal line 10.

On the other hand, in the peripheral circuit area, an X driver circuit 11 composed of a CMOS transistor or the like shown in FIG. 1 is formed. The X driver circuit 11 is connected to a column-shaped signal line 10. Further, a row-shaped scanning line 9 including the Y driver circuit 12 is connected. The X driver circuit 11 and the Y driver circuit 12 drive a switch element group including the thin film transistor 7. The Y driver circuit 12 is for sequentially selecting a switch element group via each scanning line 9, and the X driver circuit 11 is for supplying an image signal to the selected switch element via a signal line 10. is there. X
The driver circuit 11 and the Y driver circuit 12 both have similar circuit configurations.

FIG. 3 shows a circuit block configuration of the Y driver circuit 12 as an example. In this example, a total of 55 scanning lines indicated by Y1 to Y55 are selected in a line-sequential manner. As a basic configuration, it has shift registers F1 to F55 connected in 55 stages. These shift registers include:
A clock signal YC, a drive signal YD, a frame signal FSY, a synchronizing signal YSTB, and the like are input, and a timing signal for controlling the selection timing of the scanning lines Y1 to Y55 is output via an AND gate circuit. Level shifters LU1 to LU55 are individually connected to the output terminals of the respective gate circuits. Each level shifter converts the voltage level of the timing signal and outputs the converted signal.
A high voltage is applied to the gate electrode of each switch element via Y55. Normally, a voltage of about 15 V is required to drive a pixel array, whereas a voltage of about 4.5 V is sufficient to operate peripheral circuits including a driver circuit. Therefore, using the level shifters LU1 to LU55, the primary voltage V _DD −V _GND = 4.5V and the secondary voltage V _DD −V
_The voltage has been boosted to _SS = 15V. With this configuration, power consumption of peripheral circuits can be reduced as a whole.

Next, FIG. 4 shows a detailed circuit configuration example of each shift register Fn. As shown, the shift register includes a plurality of inverters. This inverter has the N
It can be easily configured by a CMOS transistor pair formed of a combination of the type MOS transistor 3 and the P-type MOS transistor 4.

FIG. 5 shows a detailed circuit configuration example of each level shifter LUN. As shown, the level shifter includes a plurality of inverters, a plurality of N-type MOS transistors, P-type MOS transistors, and the like. Therefore, the level shifter can be integrated and formed on the semiconductor single crystal thin film 2 at a high density similarly to the shift register.

FIG. 6 is a schematic exploded perspective view showing an example of a light valve device configured using the semiconductor integrated circuit board device according to the present invention. As shown in the drawing, the light valve device includes a substrate 1, an opposing substrate 61 disposed opposite to the substrate 1, and an electro-optical material such as a liquid crystal 62 disposed between the substrate 1 and the opposing substrate 61. . As described above, the pixel array area and the peripheral circuit area are defined on the surface of the substrate 1. On the surface of the semiconductor polycrystalline thin film 8 covering the pixel array area, a plurality of pixel electrodes 6 and a plurality of switch elements 7 corresponding to the plurality of pixel electrodes 6 are formed. Also, a silicon single crystal thin film 2 covering the peripheral circuit area
An X driver circuit 11 and a Y dry circuit 12 are formed on the surface of the device. The surfaces of these two areas are covered with a liquid crystal alignment film 63. A polarizing plate is provided on the back side of the substrate 1.
64 are glued.

On the other hand, the alignment substrate 61 includes a glass carrier 65, a polarizing plate 66 adhered to the outer surface of the glass carrier 65, and a counter electrode 67 formed on the inner surface of the glass carrier 65. further,
The surface of the counter electrode 67 is covered with a liquid crystal alignment layer 68.

The operation of the light valve device having such a configuration will be briefly described. The gate electrode of each switch element 7 composed of a polycrystalline thin film transistor is connected to a scanning line 9, and a scanning signal is applied by a Y driver circuit 12 to control conduction and cutoff of each switch element 7 in line order. An image signal output from the X driver circuit 11 is applied to a selected switch element 7 in a conductive state via a signal line 10. The applied image signal is transmitted to the corresponding pixel electrode 6, which excites the pixel electrode and acts on the liquid crystal 62 to substantially reduce its transmittance.
100%. On the other hand, at the time of non-selection, the switch element 7 is turned off, and the image signal written to the pixel electrode 6 is maintained as electric charge. The liquid crystal 62 has a high specific resistance and normally operates as a capacitive element. As the liquid crystal 62, for example, a liquid crystal exhibiting a nematic layer is used, and a pair of upper and lower alignment films 63 and
68, so-called twisted orientation. The twist-aligned monetic liquid crystal has optical rotation with respect to incident light. This optical rotation is lost when a voltage is applied to the liquid crystal. This change is converted into a change in light intensity through a pair of polarizing plates 64 and 66 to perform a light valve function.

Next, a method of manufacturing the semiconductor integrated circuit device shown in FIG. 1 will be described in detail with reference to FIGS. 7 (A) to 7 (J). First, in the step shown in FIG. 7A, a transparent electrically insulating substrate 71 made of quartz glass or the like and a single crystal semiconductor substrate 72 made of silicon are prepared. The single crystal silicon substrate 72 is preferably a high quality silicon wafer used for LSI manufacturing, and its crystal orientation is <100> 0.0
It has a uniformity in the range of ± 01.0, and its single crystal lattice defect density is not more than 500 / cm ² . First, the surface of the prepared quartz glass substrate 71 and the surface of the silicon wafer 72 are precisely smoothed. Then, both substrates are thermocompression-bonded by overlapping and heating both surfaces which have been smoothed. By this thermocompression bonding, the two substrates 71 and 72 are firmly fixed to each other.

In the step shown in FIG.
Polish the surface of. As a result, a single-crystal silicon thin film 73 polished to a desired thickness of about several μm is formed on the surface of the quartz glass substrate 71. The silicon wafer substrate 72
A chemical etching process may be used instead of a mechanical polishing process in order to make the film thinner. Since the quality of the silicon wafer 72 is substantially preserved in the single-crystal silicon thin film 73 obtained in this way, a composite substrate material with excellent crystal orientation uniformity and lattice defect density can be obtained.

On the other hand, an SOI substrate having a two-layer structure of a substrate and a silicon single crystal thin film is conventionally known. For example, an SOI substrate is formed by depositing a polycrystalline silicon thin film on a carrier surface made of an insulating material by chemical vapor deposition, etc. It was obtained by converting it to a structure. However, in general, a single crystal obtained by recrystallization of a polycrystal does not always have a uniform crystal orientation and has a large lattice defect density. Therefore, the carrier lifetime is short, and it is difficult to form a DRAM. For these reasons, it is difficult to apply the miniaturization technology to a SOI substrate manufactured by a conventional method, like a silicon wafer. further,
It was also difficult to obtain high-speed quality. On the other hand, the composite substrate used in the present invention has a two-layer structure consisting of the substrate and a high-quality silicon wafer single-crystal thin film.
LSI manufacturing technology can be applied directly. In addition, performance can be obtained similarly to bulk silicon.

Subsequently, in the step shown in FIG. 7 (C), the single crystal silicon thin film 73 covering the entire surface of the substrate 71 is processed to set a peripheral circuit area and a pixel array area. In the figure, only the boundary between the two areas is partially shown. In this example, the silicon single crystal thin film existing in the pixel array area is entirely removed by etching to expose the surface of the substrate 71. On the other hand, in the peripheral circuit area, a plurality of island-like element regions made of a silicon single crystal thin film 73 are selectively removed by plasma ion etching or the like through a mask 74 patterned in a predetermined shape.
Form 75. In the figure, only one element region is shown for simplicity.

In the step shown in FIG. 7D, a thermal oxidation process is performed to form a gate insulating film 76 made of silicon dioxide on the surface and side surfaces of the silicon single crystal thin film 73 patterned in an island shape.

In the step shown in FIG. 7E, a polycrystalline silicon film is deposited so as to cover the entire surface of the substrate 71 by a chemical vapor deposition method. The polycrystalline silicon film is selectively etched using a resist mask (not shown) patterned in a predetermined shape to form a first gate electrode G1 on the surface of the gate insulating film. At this time, also in the pixel array area, the polycrystalline silicon film is simultaneously selectively etched to form the second gate electrode G2.

Subsequently, in a step shown in FIG.
Impurity ions are implanted through the gate insulating film 76 using G1 as a mask to form a first drain region D1 and a first source region S1 on the surface of the silicon single crystal thin film 73. As a result, a transistor channel formation region where impurities are not implanted is provided below the gate electrode G1 between the drain region D1 and the source region S1. Accordingly, an insulated gate field effect type single crystal thin film transistor is formed in the island-shaped element region 75. This transistor constitutes a peripheral circuit element as described above.

Next, the entire surface of the substrate 71 is covered with a silicon dioxide film 77 by a chemical vapor deposition method or the like. The silicon dioxide film 77 forms a gate insulating film for the second gate electrode G2.

Subsequently, in a step shown in FIG. 7H, a polycrystalline silicon thin film 78 is formed on the entire surface of the silicon dioxide film 77 by using a chemical vapor deposition method or the like. The thickness of the polycrystalline silicon thin film 78 is preferably set to about several hundred degrees and is substantially transparent. Through a mask (not shown) patterned in a predetermined shape, selective etching is performed to partially remove the polycrystalline silicon thin film 78.

Further, in the step shown in FIG. 7 (I), an impurity is selectively implanted into the patterned polycrystalline silicon thin film 78 to form a second drain region D2 and a second drain region D2 on both sides of the second gate electrode G2. The source region S2 is formed. This impurity implantation is performed by impurity ion implantation or impurity diffusion. As a result, the second
The gate electrode G2, the second drain region D2, and the second source region S2 form an insulated gate field effect type polycrystalline thin film transistor. At the same time, the source area
The portion of the polycrystalline silicon thin film 78 extending from S2 forms a transparent pixel electrode 79.

Finally, in a step shown in FIG. 7 (J), after a metal wiring step for predetermined electrical connection is performed, the entire surface of the substrate 71 is covered with a transparent protective film 80. As a result, in the pixel array area, a switch element composed of a polycrystalline thin film transistor and a pixel electrode also composed of a polycrystalline silicon thin film are formed.

In the embodiment described above, the pixel array area is covered with a polycrystalline silicon thin film. However, the present invention is not limited to this. The pixel array area may be covered with a silicon amorphous thin film, and a switching element or the like may be formed on the amorphous thin film. Alternatively, a silicon single crystal thin film may be left in the pixel array area, and a switch element or the like may be formed here. However, since the silicon single crystal thin film is obtained by polishing a silicon wafer as described above, the film thickness is about several μm. Therefore, it is substantially opaque and cannot be used directly as a transparent pixel electrode. Therefore, it is necessary to perform a process such as converting a silicon single crystal thin film in a portion where a pixel electrode is formed into a field oxide film by selective thermal oxidation. On the other hand, since a silicon polycrystalline thin film or a silicon amorphous thin film can be formed extremely thin by a vacuum deposition method or a chemical vapor deposition method, it can be used as a transparent pixel electrode as it is. Further, a silicon single crystal thin film transistor has a larger leakage current due to incident light than a silicon polycrystal thin film transistor or a silicon amorphous thin film transistor. For this reason, an insulated gate field effect type thin film transistor composed of polycrystal or amorphous is preferable to a switch element rather than a single crystal. further,
As described above, since the silicon polycrystalline thin film or the silicon amorphous thin film can be deposited very thinly, the step size on the surface is small, and the disconnection of the wiring pattern or the like can be effectively prevented.

In this embodiment, the first gate electrode G1 and the second gate electrode G2 are obtained by patterning the same polycrystalline silicon thin film at the same time. However, the present invention is not limited to this, and the second gate electrode G2 may be formed using this film at the same time as, for example, selectively etching the silicon single crystal thin film 73 to form an island-shaped element region. It is possible.

Next, another embodiment of the semiconductor integrated circuit device for a flat light valve substrate according to the present invention will be described with reference to FIG. Also in this embodiment, the substrate 1 is divided into a pixel array area and a peripheral circuit area as shown by a dotted line. Pixel electrode groups and switch element groups arranged in a matrix are formed in the pixel array area. The peripheral circuit area is covered with a silicon single crystal thin film. This thin film has an X driver circuit 11 and a Y driver circuit 12 as in the previous embodiment.
Are formed, and additional circuits 81 having various functions are also formed at the same time. Since this additional circuit can also be formed on a high-quality silicon single crystal thin film, various additional circuit element groups can be integrated at a high density using ordinary LSI technology. For example, the additional circuit 81 includes a control circuit for controlling the X driver circuit and the Y driver circuit. The control circuit comprises a video signal processing circuit, which processes an image signal or a video signal input from an external signal source and transfers the processed signal to the X driver circuit 11. In this manner, by adding a video signal processing circuit on a semiconductor integrated circuit board device, the board device can be directly adjacent to an external image signal source. Therefore, it is possible to obtain an ultra-compact, high-speed image apparatus that is extremely versatile. A circuit having various functions in addition to the video signal processing circuit can be considered as a circuit additionally incorporated.

An example of the additional circuit includes, for example, a DRAM sense amplifier circuit. This DRAM sense amplifier circuit is for detecting electric charge temporarily stored in each pixel electrode as storage information, and can be used for detecting a defect of each pixel. First,
The principle will be briefly described with reference to FIG. FIG. 9 is a diagram showing a case where a signal line Xi and a scanning line Yj exist at an intersection.
2 shows an equivalent circuit of the pixels. Each pixel includes a switch element 91 including a transistor, a liquid crystal 92, a capacitor 93, and the like. The switch element 91 is formed on the surface of the semiconductor substrate device, and the liquid crystal 92 is sandwiched between a pixel electrode 94 formed on the surface of the semiconductor substrate device and a counter electrode 95 formed on the counter substrate. In addition, the capacitor 93 is formed between the pixel electrode 94 and another electrode, for example, a signal line electrode or a scanning line electrode. Alternatively, it can be provided on single crystal silicon. The gate electrode of the switch transistor 91 is connected to the scanning line Yj, the drain region is connected to the signal line Xi, and the source region is also connected to the pixel electrode 94. When the switch transistor 91 is turned on via the scanning line Yj, a predetermined charge is charged in the capacitor 93 via the signal line Xi. Thereafter, the switch transistor 91 immediately becomes non-conductive via the scanning line Yj, and the charge is accumulated in the capacitor 93. The liquid crystal 92 is driven by a voltage appearing at both ends of the capacitive element to perform a light valve function. Therefore, the equivalent circuit shown in FIG.
It is equivalent to one memory cell of DRAM. That is, the capacitive element
Reference numeral 93 has a function of temporarily storing an image signal supplied via the signal line Xi as electric charge. In the present invention, the temporary storage time can be maintained as long as that of a conventional DRAM using bulk silicon. This is because the materials are the same. As long as each pixel has no defect, the memory cell operates normally. Therefore, by reading out the charge held in the capacitor as stored information, it is possible to inspect each pixel for the presence of a defect very simply and at high speed. For this reason, the additional circuit 81 includes a DRAM sense amplifier circuit for reading information stored in a memory cell. DR
When polycrystalline silicon is used as the AM capacitor and transistor, it is difficult to operate the DRAM because the information retention time is short.

FIG. 10 shows a detailed circuit configuration example of such a DRAM sense amplifier circuit. FIG. 10 shows one DRAM sense amplifier circuit corresponding to each column component of the matrix pixel array. This circuit corresponds to the X driver circuit 11 shown in FIG.
And the Y driver circuit 12. It has a three-stage structure, and the first stage 101 and the second stage 102 become operable according to a read signal. That is, when reading information stored in a pixel array equivalently regarded as a memory array, the DRAM sense memory circuit to which a read signal is output is placed in a readable state. A pair of input terminals of the first stage 101 are supplied with data DXi read out on the signal line Xi via the X driver circuit 11 and ▲ i which is inverted information thereof. The first stage 101 amplifies the supplied data.
Further, the input signal of the second stage 102 is supplied with the scanning signal SYi appearing on the scanning line via the Y driver circuit 12 and the inverted signal ▲ ▼ j. This second stage 102
The data supplied from the first stage is further amplified in synchronization with the scanning signal. Finally, the third stage 103 is a buffer,
The read data is sequentially supplied to the output terminal.
Although not shown, the read data is successively compared and evaluated with reference data to detect the presence or absence of a defect in each pixel. As is apparent from the figure, the DRAM sense amplifier circuit includes a number of transmission gates, inverters, N-type and P-type transistors, and the like. All of these circuit elements can be constituted by insulated gate field effect transistors. The silicon single crystal thin film is most suitable for integrating such a transistor element group with high density, low leaf current and high speed operation. In particular, in order to guarantee high-speed operation and low power consumption, it is possible to use a single crystal silicon CMOS transistor. In the case of a single crystal, the lifetime is more than one order of magnitude longer than that of a polycrystal, so that the DRAM function can be easily provided.

FIG. 11 shows an optical sensor circuit as another example of the peripheral circuit included in the additional circuit. This optical sensor circuit is for detecting the intensity of incident light applied to a semiconductor integrated circuit board device. Generally, a light valve device includes a light source.
This light source has a lifetime, and the emission intensity gradually decreases.
By constantly monitoring the decrease in the light emission intensity, maintenance and inspection or replacement of the light source can be facilitated.
As shown, the light sensor circuit includes a photodiode 111 connected between a power supply voltage _VDD and a ground terminal. This photodiode can be easily obtained by forming a PN junction by introducing an impurity of the opposite conductivity type into a single-crystal silicon thin film of one conductivity type. One end of the photodiode is connected to the current-voltage conversion resistor 112. This resistor 112 can be easily formed by introducing impurities into the silicon single crystal thin film. One end of the resistor 112 is connected to the positive input terminal of the differential amplifier 113. The negative input terminal of the differential amplifier 113 is connected to the output terminal of the differential amplifier 113. As a result, the differential amplifier 113 forms a buffer.
The optical sensor circuit further includes another differential amplifier 114. The positive input terminal is connected to the output terminal of the buffer 113 via the diffusion resistor 115, and the negative input terminal is supplied with the reference voltage Vref. This differential amplifier 114
Compares a detection voltage proportional to the intensity of incident light detected by the photodiode 111 with a reference voltage, and outputs a warning signal when the detection voltage falls below the reference voltage.
That is, when the intensity of the incident light reaches a certain level, the maintenance or inspection or replacement of the light source of the light valve device is prompted. Eleventh
All the components of the optical sensor circuit shown in the figure can be formed on a silicon single crystal thin film in a suitable manner.

Next, a temperature sensor circuit will be described as an example of a peripheral circuit included in the additional circuit with reference to FIG. When the semiconductor substrate device is incorporated in a light valve, the temperature sensor circuit comes into surface contact with an electro-optical material, for example, a liquid crystal, and monitors a temperature change thereof. When there is a possibility that the operating range is exceeded due to overheating of the liquid crystal or the like, a warning signal is issued to maintain the normal operation of the light valve. In this example, the optical sensor circuit includes a series connection between a power supply V _DD and a ground V _SS.
It is composed of NPN transistors 121 and a constant current circuit 122. As is well known, the base-emitter voltage Zf of an NPN transistor has voltage dependency. Therefore, by supplying a constant current If between the base and the emitter by using the constant current source 122, an output voltage Vf depending on the temperature appears at one end of the constant current source 122. By comparing the output voltage Vf with a predetermined reference voltage, it is possible to detect overheating of the liquid crystal used in the light valve device. This NPN transistor 121 is CM
It can be easily manufactured during the OS process.
Also, the constant current circuit 122 can be easily configured using a plurality of insulated gate field effect transistors.

FIG. 12 (B) shows an optical sensor circuit having higher sensitivity temperature characteristics. The difference from the example shown in FIG. 12 (A) is that two NPN transistors are Darlington connected. This temperature sensor circuit can also be built in a CMOS IC, and a temperature sensor circuit having the same sensitivity as a thermistor at 1.5 V operation can be obtained. This temperature sensor circuit
It can guarantee a temperature sensitivity of -6mV / ° C in the temperature range of -10 ° C to + 60 ° C, and has excellent linearity and is suitable for mass production with small variations. As shown, NPN transistors 121 and 123
Are connected so that the voltage between the base and the emitter is added, the collector is common, so that the connection is inevitably Darlington. A constant current If is supplied to this through a constant current source 122 to obtain a sensor output voltage Vf.

FIG. 13 is a schematic diagram showing a cross-sectional structure of a semiconductor integrated circuit substrate device on which an NPN transistor used as a temperature sensor element is formed. As shown in the figure, a single-crystal silicon thin film 2 is formed on the surface of an electrically insulating quartz glass substrate 1 to constitute the above-described composite substrate. An NPN transistor is formed in the left half of the composite substrate, and an N-type MOS transistor is formed in the right half. As is clear from the figure, the NPN transistor and the N-type MOS transistor can be formed simultaneously. The NPN transistor is used as a temperature sensor element, and the N-type MOS transistor is used as an element forming a constant current circuit, for example. A P ⁻ type base diffusion layer is provided on the N ⁻ type single crystal silicon thin film layer 2. An N ⁺ -type emitter region is formed in the base diffusion layer. P ^- type base diffusion layer is N in CMOS process
The N ⁺ type emitter region can be formed simultaneously with the N ⁺ type source region and the drain region of the N type MOS transistor.

Next, with reference to FIG. 14, a flat-type light valve substrate-like semiconductor integrated circuit device incorporating a solar cell as a peripheral circuit is shown.
As shown, the substrate 1 is divided into two sections.
An area surrounded by a dotted line is a pixel array area, and a pixel electrode group and a switch element group are formed integrally. The area other than the area surrounded by the dotted line is the peripheral circuit area, in which the X driver circuit 11 and the Y driver circuit 12 are formed. At the same time, solar cells 141 are formed along the peripheral edge of the peripheral circuit area. The solar cell 141 converts incident light applied to the light valve device into electric energy, and supplies driving power to the pixel array, the X driver circuit 11, and the Y driver circuit 12. As in the various examples described above, the peripheral circuit area is covered with a high quality silicon single crystal thin film. This silicon single crystal thin film is obtained by bonding a silicon wafer to the surface of a substrate and polishing the silicon wafer. The solar cell 141 is a semiconductor element that converts light energy of incident light into electric energy using a PN junction. At present, a solar cell having the highest conversion efficiency is obtained using a silicon single crystal. Therefore, it is extremely effective to form a solar cell element on the periphery of the semiconductor integrated circuit substrate device according to the present invention.

FIG. 15 schematically shows a cross-sectional structure of such a solar cell. The single-crystal silicon thin film 2 adhered to the surface of the substrate 1 has been subjected to diffusion treatment with N-type impurities in advance, and has a resistivity of 0.1 to 1 Ωcm. A P-type impurity such as borane is diffused into the surface portion to
Form 2. As a result, a PN junction having photovoltaic power is obtained. Further, the surface of the substrate 1 is protected by an antireflection film 143 made of silicon monoxide or the like. This antireflection film can be formed by vacuum evaporation. Subsequently, a contact hole is formed in a part of the antireflection film 143, and a negative electrode terminal 144 made of metal is connected to the N-type silicon single crystal thin film 2. or,
Contact holes are also opened in other portions of the antireflection film 143, and a positive electrode terminal 145 made of metal is connected to the P-type diffusion layer 142. These electrode terminals 144 and 145 are used as power supply terminals for peripheral circuits.

FIG. 16 is a schematic plan view showing an example of patterns of external connection terminals drawn from the X driver circuit 11 and the Y driver circuit 12. As shown in FIG.
Are formed intensively at one peripheral portion of the surface of the substrate 1.
As a result, electrical connection with an external circuit becomes extremely easy. For example, when the light valve device is manufactured by stacking the substrate 1 and the opposing substrate (not shown) and performing heat sealing, the electrical connection processing to the external connection terminal wiring 161 can be performed at the same time. At this time, since the external connection terminal wiring 161 is formed at the peripheral corner of the substrate 1, a heating member for performing heat sealing does not directly contact the X driver circuit 11 or the Y driver circuit 12. Therefore, there is no fear that the circuit element formed on the semiconductor integrated circuit board device is thermally destroyed during the assembly of the light valve device.

Finally, an example of a switch element for selectively supplying power to a pixel electrode will be described with reference to FIGS. 17 and 18. FIG. 17 is a schematic partial plan view showing one pixel electrode and one switch element existing at the intersection of a certain signal line Xi and a certain scanning line Yj. As illustrated, one diode 172 is connected between one side of the pixel electrode 171 and the corresponding signal line Xi. The other diode 173 is connected between the other side of the pixel electrode 171 and the corresponding scanning line Yj. The pair of diodes 172 and 173 constitute a switch element for selectively supplying power to the pixel electrode 171. In the embodiment described above, an insulated gate field effect transistor is used as a switch element. The diode has a smaller element area than the transistor, so that the aperture ratio per pixel can be increased. That is, the ratio of the area occupied by the transparent pixel electrode 171 per pixel is increased, and a transmission type light valve device excellent in image display performance can be obtained. As shown, by supplying an image signal to the signal line Xi in synchronization with a selection signal applied to the scanning line Yj, a charge is supplied to the pixel electrode 171 via a pair of diodes 172 and 173 and stored. Things become possible. 18th
The figure shows a cross-sectional structure of one pixel portion shown in FIG. In this embodiment, the diodes 172 and 173 are used by using the silicon single crystal thin film 2 bonded and formed on the surface of the substrate 1 as it is.
Is formed. However, after removing the silicon single crystal thin film from the pixel array area, a silicon other crystal thin film or an amorphous thin film may be formed, and a diode may be formed on this thin film. The crystal thin film 2 is selectively etched to form a pair of island-shaped element regions. Diodes are obtained by introducing impurities of different conductivity types into each island-shaped element region to form a PN junction composed of a P ⁺ region and an N region. A pixel electrode 171 made of a transparent material is provided between the pair of diodes 172 and 173.
Is formed by vacuum evaporation or the like. As is apparent from the figure, the size of the island-shaped element region for forming the diode is extremely small, and the aperture ratio of each pixel can be increased accordingly. Incidentally, when the insulated gate field-effect thin film transistor is used, the aperture ratio is 50% to 60%, whereas when a pair of diodes is used, the aperture ratio can be improved to about 80%. .

〔The invention's effect〕

As described above, according to the present invention, the surface of the light valve device substrate is divided into the pixel array area and the peripheral circuit area adjacent thereto. At least the peripheral circuit area is covered with a high-quality semiconductor single crystal thin film adhered to the substrate. A pixel electrode group and a switch element group can be formed in a pixel array area, and a circuit element group constituting a peripheral circuit having various functions can be integrally formed on a semiconductor single crystal thin film in a peripheral circuit area. . That is, since a transistor using single crystal silicon can be formed within a chip with a threshold voltage of, for example, about 100 mV or less, a highly accurate peripheral circuit can be easily formed. Peripheral circuits having various functions comparable to the VLSI can be easily added to this semiconductor single crystal thin film because it is a single crystal using an integrated circuit technology. Therefore, there is an effect that a high-speed, ultra-compact and multifunctional semiconductor integrated circuit substrate for a light valve can be obtained. As the peripheral circuit, for example, an X driver for driving a switch element group and a Y driver circuit, a DRAM sense amplifier circuit, a light detection circuit, a temperature detection circuit, a solar cell, and the like can be freely formed.

[Brief description of the drawings]

1 is a partial sectional view showing a typical structure of a semiconductor device for a light valve substrate, FIG. 2 is an overall plan view of the semiconductor device for a light valve substrate, and FIG. 3 is a peripheral circuit of the semiconductor device for a light valve substrate. FIG. 4 is a block diagram showing a circuit configuration of a Y driver circuit formed in a section; FIG. 4 is a circuit diagram showing a detailed circuit configuration of a shift register forming parts of the Y driver circuit shown in FIG. 3;
FIG. 6 is a circuit diagram showing a detailed circuit configuration of a level shifter, which is one of the components of the Y driver circuit. FIGS. 6A to 6J are diagrams of the light valve substrate semiconductor device shown in FIG. FIG. 7 is a process diagram showing a manufacturing method, FIG. 7 is a schematic plan view showing another embodiment of the semiconductor device for a light valve substrate, and FIG. 8 shows the operation of the DRAM sense amplifier circuit included in the additional circuit shown in FIG. 9 is a circuit block diagram showing a detailed circuit configuration of the DRAM sense amplifier circuit included in the additional circuit shown in FIG. 7, and FIG. 10 is included in the additional circuit shown in FIG. Circuit diagram showing a specific configuration example of an optical sensor circuit,
FIG. 11 (A) is a circuit diagram showing a specific configuration of a temperature sensor circuit included in the additional circuit shown in FIG. 7, and FIG. 11 (B) is a circuit diagram showing an improved example of the temperature sensor. 12 is a schematic partial cross-sectional view showing the structure of the NPN transistor shown in FIG. 11 (A), FIG. 13 is a schematic plan view showing still another embodiment of the semiconductor device for a light valve substrate, FIG. Is a schematic partial cross-sectional view showing the structure of the solar cell shown in FIG. 13,
15 is a schematic plan view showing another embodiment of the light valve substrate semiconductor device, FIG. 16 is a schematic diagram showing an example of a switch element group formed in the pixel array area of the light valve substrate semiconductor device, 17 is a schematic diagram showing a cross-sectional structure of the switch element shown in FIG. DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... Semiconductor single crystal thin film 3 ... N-type MOS transistor 4 ... P-type MOS transistor 5 ... 1st insulating film, 5 '... 2nd insulating film 6 ... Pixel electrode, 7 ... ... Thin film transistor 8 ... Semiconductor polycrystalline thin film, D ... Drain region S ... Source region, G ... Gate electrode

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tsuneo Yamazaki 6-31-1, Kameido, Koto-ku, Tokyo Inside Seiko Electronics Corporation (72) Inventor Hiroshi Suzuki 6-31, Kameido, Koto-ku, Tokyo Seiko Electronics Co., Ltd. (72) Inventor Masaaki Taguchi 6-31-1, Kameido, Koto-ku, Tokyo Seiko Electronics Co., Ltd. (56) References JP-A-59-45486 (JP, A) JP-A-58-117584 (JP, A) JP-A-58-85478 (JP, A) JP-A-64-6927 (JP, A) JP-A-57-97582 (JP, A) JP-A-58-128475 (JP, A) , U) Actually open 58-54679 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) G02F 1/136 G02F 1/1345

Claims (6)

(57) [Claims] A substrate including at least a portion of an electrically insulating film, a semiconductor single crystal thin film disposed on at least a portion of a surface of the substrate, defining a peripheral circuit area, and polished to a desired thickness; A pixel element group formed in a pixel array area adjacent to the peripheral circuit area and a switch element group for selectively supplying power to each search electrode; and a circuit integratedly formed on a semiconductor single crystal thin film in the peripheral circuit area And a peripheral circuit including a drive circuit for driving the switch element group. The circuit element group formed integrally on the semiconductor single crystal thin film has a DRAM function. -Type light valve substrate semiconductor integrated circuit device. 2. The semiconductor integrated circuit device for a flat light valve substrate according to claim 1, wherein said circuit element group includes a complementary insulated gate field effect transistor formed on a single crystal thin film made of silicon. 3. The semiconductor integrated circuit device according to claim 1, wherein said peripheral circuit includes a control circuit for controlling a driving circuit. A substrate including at least a portion of an electrically insulating film, a semiconductor single crystal thin film disposed on at least a portion of the substrate surface, defining a peripheral circuit area, and polished to a desired thickness; A pixel element group formed in a pixel array area adjacent to the peripheral circuit area and a switch element group for selectively supplying power to each search electrode; and a circuit integratedly formed on a semiconductor single crystal thin film in the peripheral circuit area And a peripheral circuit including a driving circuit for driving the switch element group. The peripheral circuit includes a DRAM for detecting electric charge temporarily stored in each pixel electrode as stored information. A semiconductor integrated circuit device for a flat light valve substrate, comprising a sense amplifier circuit. 5. The semiconductor integrated circuit device for a flat light valve substrate according to claim 4, wherein said circuit element group includes a complementary insulated gate field effect transistor formed on a single crystal thin film made of silicon. 6. The semiconductor integrated circuit device according to claim 4, wherein said peripheral circuit includes a control circuit for controlling a driving circuit.