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JP2838703B2 - Semiconductor package manufacturing method - Google Patents

Semiconductor package manufacturing method

Info

Publication number
JP2838703B2
JP2838703B2 JP10027166A JP2716698A JP2838703B2 JP 2838703 B2 JP2838703 B2 JP 2838703B2 JP 10027166 A JP10027166 A JP 10027166A JP 2716698 A JP2716698 A JP 2716698A JP 2838703 B2 JP2838703 B2 JP 2838703B2
Authority
JP
Japan
Prior art keywords
conductive material
semiconductor
semiconductor package
manufacturing
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP10027166A
Other languages
Japanese (ja)
Other versions
JPH10229095A (en
Inventor
ヨン チョ キュン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ERU JII SEMIKON CO Ltd
Original Assignee
ERU JII SEMIKON CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ERU JII SEMIKON CO Ltd filed Critical ERU JII SEMIKON CO Ltd
Publication of JPH10229095A publication Critical patent/JPH10229095A/en
Application granted granted Critical
Publication of JP2838703B2 publication Critical patent/JP2838703B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
    • H01L23/4334—Auxiliary members in encapsulations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/0554—External layer
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    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
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    • H01L2924/0001—Technical content checked by a classifier
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体パッケージ
の製造方法に係るもので、詳しくは、熱的特性を向上し
得る半導体パッケージの製造方法に関するものである。The present invention relates to a method for manufacturing a semiconductor package, and more particularly to a method for manufacturing a semiconductor package capable of improving thermal characteristics.

【０００２】[0002]

【従来の技術】従来半導体パッケージにおいては、図４
に示したように、複数のボンディングパッド１ａを有す
る半導体チップ１と、該半導体チップ１の下面に付着さ
れた熱伝導性物質２と、前記半導体チップ１の上面に第
１接着部材３を介して接着され、各内部リード４ａ及び
該各内部リード４ａから上向きに屈曲された各外部リー
ド４ｂを有するリード４と、前記半導体チップ１の各ボ
ンディングパッド１ａと前記内部リード４ａとに夫々電
気的に連結されたワイヤー５と、前記半導体チップ１、
前記各内部リード４ａ、外部リード４ｂ及び熱伝導性物
質２が包含された所定部位に密封されたモールディング
樹脂６と、から構成され、前記熱伝導性物質２の下面及
び前記各外部リード４ｂの上面は、前記モールディング
樹脂６から露出されていた。2. Description of the Related Art In a conventional semiconductor package, FIG.
As shown in FIG. 1, a semiconductor chip 1 having a plurality of bonding pads 1a, a heat conductive substance 2 attached to a lower surface of the semiconductor chip 1, and a first adhesive member 3 on an upper surface of the semiconductor chip 1 The leads 4 having the respective internal leads 4a and the respective external leads 4b bent upward from the respective internal leads 4a are electrically connected to the respective bonding pads 1a of the semiconductor chip 1 and the internal leads 4a. Wire 5 and the semiconductor chip 1,
A molding resin 6 hermetically sealed at a predetermined portion containing the inner leads 4a, the outer leads 4b, and the thermally conductive material 2; a lower surface of the thermally conductive material 2 and an upper surface of the outer leads 4b. Was exposed from the molding resin 6.

【０００３】以下、このように構成された従来の半導体
パッケージ７の製造方法に対し、図５（Ａ）〜（Ｃ）、
及び図６（Ａ）〜（Ｃ）を用いて説明する。先ず、図５
（Ａ）に示したように、半導体ウェーハ８の下面に第２
接着部材９を形成する。次いで、図５（Ｂ）に示したよ
うに、前記第２接着部材９の形成された前記半導体ウェ
ーハ８を、ダイヤモンドホイール（Wheel ）を用いて半
導体チップ１別に分離する。[0005] Hereinafter, a method for manufacturing the conventional semiconductor package 7 configured as described above will be described with reference to FIGS.
This will be described with reference to FIGS. First, FIG.
As shown in (A), a second surface is formed on the lower surface of the semiconductor wafer 8.
An adhesive member 9 is formed. Next, as shown in FIG. 5B, the semiconductor wafer 8 on which the second adhesive member 9 is formed is separated into semiconductor chips 1 using a diamond wheel.

【０００４】前記第２接着部材９は、前記半導体ウェー
ハ８を切断して各半導体チップ１を分離するとき半導体
チップ１の飛散を防止するため、暫定的に使用するもの
である。このとき、前記半導体チップ１の上面には、ボ
ンディングパッド（図示されず）が形成されている。The second adhesive member 9 is used temporarily to prevent the semiconductor chips 1 from scattering when the semiconductor wafer 8 is cut to separate the semiconductor chips 1. At this time, bonding pads (not shown) are formed on the upper surface of the semiconductor chip 1.

【０００５】その後、図５（Ｃ）に示したように、分離
された各半導体チップ１の下面に形成された前記第２接
着部材９を夫々除去し、前記半導体１のチップ上面に接
着部材３を介して各内部リード４ａ及びそれら内部リー
ド４ａから上方向きに屈曲形成された外部リード４ｂを
有するリードを接着する。次いで、図６（Ａ）に示した
ように、図５（Ｃ）に示した半導体チップ１の下面に熱
伝導性物質２を付着し、図６（Ｂ）に示したように、前
記半導体チップ１の各ボンディングパッド１ａと前記内
部リード４ａとを夫々ワイヤー５を用いて電気的に連結
する。Thereafter, as shown in FIG. 5C, the second adhesive members 9 formed on the lower surface of each separated semiconductor chip 1 are removed, and the adhesive members 3 are attached to the upper surface of the semiconductor 1 chip. Then, the leads having the internal leads 4a and the external leads 4b bent upward from the internal leads 4a are adhered. Next, as shown in FIG. 6A, a thermally conductive substance 2 is attached to the lower surface of the semiconductor chip 1 shown in FIG. 5C, and as shown in FIG. The bonding pads 1a and the internal leads 4a are electrically connected to each other using wires 5.

【０００６】その後、図６（Ｃ）に示したように、前記
半導体チップ１、熱伝導性物質２、内部リード４ａ、外
部リード４ｂ及びワイヤー５を包含した所定部位をモー
ルディング樹脂６を用いて密封する。このとき、前記熱
伝導性物質２の下面及び外部リード４ｂの上面を前記モ
ールディング樹脂６から露出させて密封し、従来の半導
体パッケージ７の製造工程を終了していた。Thereafter, as shown in FIG. 6C, a predetermined portion including the semiconductor chip 1, the heat conductive material 2, the inner leads 4a, the outer leads 4b, and the wires 5 is sealed using a molding resin 6. I do. At this time, the lower surface of the heat conductive material 2 and the upper surface of the external lead 4b are exposed and sealed from the molding resin 6, and the conventional manufacturing process of the semiconductor package 7 has been completed.

【０００７】[0007]

【発明が解決しようとする課題】然るに、このような従
来の半導体パッケージ７の製造方法においては、半導体
ウェーハ８から分離された各半導体チップ１に熱伝導性
物質２を一々付着するため、工程が煩雑となってしまう
とともに、半導体チップ１の占有面積よりも熱伝導性物
質２の占有面積が大きいため、パッケージの容積が不意
に増加するという不都合な点があった。However, in such a conventional method of manufacturing a semiconductor package 7, since the heat conductive material 2 is attached to each of the semiconductor chips 1 separated from the semiconductor wafer 8, a step is required. In addition to being complicated, the area occupied by the heat conductive substance 2 is larger than the area occupied by the semiconductor chip 1, and there is an inconvenience that the volume of the package suddenly increases.

【０００８】そこで、本発明は、このような従来の課題
に鑑みてなされたもので、半導体ウェーハに熱伝導性物
質を付着した後、該半導体ウェーハを熱伝導性物質と一
緒に切断することにより工程を簡略化し、熱伝導性物質
の面積及び半導体パッケージの容積を最小化し得る半導
体パッケージの製造方法を提供することを目的とする。Accordingly, the present invention has been made in view of such conventional problems, and has been made by attaching a heat conductive substance to a semiconductor wafer and then cutting the semiconductor wafer together with the heat conductive substance. An object of the present invention is to provide a method of manufacturing a semiconductor package that simplifies a process and minimizes the area of a heat conductive material and the volume of a semiconductor package.

【０００９】[0009]

【課題を解決するための手段】このような目的を達成す
るため、請求項１に係る半導体パッケージの製造方法に
おいては、半導体ウェーハの下面に熱伝導性物質を付着
する工程と、前記半導体ウェーハを前記熱伝導性物質と
ともに所定長さに切断し、複数のボンディングパッドを
有する半導体チップ別に分離する工程と、前記分離され
た各半導体チップの上面に接着部材を介して、内部リー
ドと該内部リードから上方向きに屈曲形成された外部リ
ードとを有するリードを接着する工程と、前記各ボンデ
ィングパッドと前記各内部リードとを通電部材により夫
々連結する工程と、前記熱伝導性物質の下面及び前記各
外部リードの上面を露出させて前記半導体チップ、前記
内部リード、外部リード及び前記熱伝導性物質を包含し
た所定部位をモールディング樹脂を用いてモールディン
グする工程と、を順次行うことを特徴とする。According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor package, comprising: attaching a thermally conductive substance to a lower surface of a semiconductor wafer; Cutting to a predetermined length together with the heat conductive material, separating the semiconductor chips having a plurality of bonding pads into individual semiconductor chips, and bonding the internal leads and the internal leads to the upper surface of each of the separated semiconductor chips via an adhesive member. Bonding a lead having an external lead bent upward, connecting each of the bonding pads and each of the internal leads with a current-carrying member, and connecting a lower surface of the heat conductive material and each of the outer leads. By exposing the upper surfaces of the leads, a predetermined portion including the semiconductor chip, the inner leads, the outer leads, and the heat conductive material is exposed. Wherein the successively performed a step of molding, the using loading resin.

【００１０】また、請求項２に係る半導体パッケージの
製造方法においては、前記接着部材は、ポリイミド膜
（Polyimide Film）であることを特徴とする。また、請
求項３に係る半導体パッケージの製造方法においては、
前記熱伝導性物質が、導電性物質であることを特徴とす
る。また、請求項４に係る半導体パッケージの製造方法
においては、前記導電性物質は、銅、銅とニッケルとの
合金、及びアルミニウム中、何れか一つを用いることを
特徴とする。Further, in the method of manufacturing a semiconductor package according to the present invention, the adhesive member is a polyimide film. In the method of manufacturing a semiconductor package according to claim 3,
The heat conductive material is a conductive material. According to a fourth aspect of the present invention, in the method for manufacturing a semiconductor package, any one of copper, an alloy of copper and nickel, and aluminum is used as the conductive material.

【００１１】また、請求項５に係る半導体パッケージの
製造方法においては、前記通電部材が、ワイヤー又はバ
ンプ（bump）であることを特徴とする。また、請求項６
に係る半導体パッケージの製造方法においては、前記半
導体ウェーハを切断する工程の前に、前記熱伝導性物質
に絶縁層（Insulating Layer）を付着する工程と、該
絶縁層を付着する工程の後であって前記モールディング
する工程の前に、前記熱伝導性物質の絶縁層を除去する
工程と、を更に付加して行うことを特徴とする。According to a fifth aspect of the present invention, in the method of manufacturing a semiconductor package, the conductive member is a wire or a bump. Claim 6
In the method of manufacturing a semiconductor package according to the above, before the step of cutting the semiconductor wafer, a step of attaching an insulating layer (Insulating Layer) to the heat conductive substance and a step of attaching the insulating layer. Removing the insulating layer of the heat conductive material before the molding step.

【００１２】また、請求項７に係る半導体パッケージの
製造方法においては、前記絶縁層が、ポリイミド層（Po
lyimide Layer ）であることを特徴とする。Further, in the method of manufacturing a semiconductor package according to claim 7, the insulating layer is made of a polyimide layer (Po
lyimide layer).

【００１３】[0013]

【発明の実施の形態】以下、本発明の実施の形態に対
し、添付の図面を用いて説明する。本発明に係る半導体
パッケージおいては、図１に示したように、上面に複数
のボンディングパッド１１ａが形成された半導体チップ
１１と、該半導体チップ１１の下面に付着された熱伝導
性物質１２と、前記半導体チップ１１の上面に接着部材
１３により夫々付着された各内部リード１４ａ及び該各
内部リード１４ａから屈曲形成された外部リード１４ｂ
を有するリード１４と、前記ボンディングパッド１１ａ
と内部リード１４ａとを電気的に連結するように配設さ
れた通電部材としてのワイヤー（又は、バンプ（bum
p））１５と、前記チップ１１、前記内部リード１４
ａ、外部リード１４ｂ及び熱伝導性物質１２を包含した
所定部位に密封されたモールディング樹脂１６と、を備
えて構成され、前記熱伝導性物質１２の下面及び前記各
外部リード１４ｂの上面が、前記モールディング樹脂１
６から露出されている。Embodiments of the present invention will be described below with reference to the accompanying drawings. In the semiconductor package according to the present invention, as shown in FIG. 1, a semiconductor chip 11 having a plurality of bonding pads 11a formed on an upper surface, and a heat conductive material 12 attached to a lower surface of the semiconductor chip 11 are provided. Internal leads 14a respectively attached to the upper surface of the semiconductor chip 11 by an adhesive member 13, and external leads 14b bent from the internal leads 14a.
And the bonding pad 11a
Wires (or bumps) as current-carrying members arranged to electrically connect the internal leads 14a to the internal leads 14a.
p)) 15, the chip 11, the internal leads 14
a, a molding resin 16 hermetically sealed at a predetermined location containing the external leads 14b and the heat conductive material 12, wherein the lower surface of the heat conductive material 12 and the upper surface of each of the external leads 14b are Molding resin 1
6 is exposed.

【００１４】以下、このように構成された本発明に係る
半導体パッケージ１７の製造方法に関し、図２（Ａ）
（Ｂ）及び図３（Ａ）〜（Ｃ）を用いて説明する。先
ず、図２（Ａ）に示したように、半導体ウェーハ１８の
下面に熱伝導性物質１２を付着し、該熱伝導性物質１２
の下面に絶縁層１９を付着する。このとき、前記熱伝導
性物質１２は、導電性物質であって、銅Ｃｕ、銅Ｃｕと
ニッケルＮｉとの合金、及びアルミニウムＡｌ中、何れ
か一つを用いるのが好ましい。Hereinafter, a method for manufacturing the semiconductor package 17 according to the present invention having the above-described structure will be described with reference to FIG.
This will be described with reference to FIG. 3B and FIGS. First, as shown in FIG. 2A, a heat conductive material 12 is adhered to the lower surface of a semiconductor wafer 18 and the heat conductive material 12
An insulating layer 19 is attached to the lower surface of the substrate. At this time, the heat conductive material 12 is a conductive material, and it is preferable to use any one of copper Cu, an alloy of copper Cu and nickel Ni, and aluminum Al.

【００１５】次いで、図２（Ｂ）に示したように、前記
半導体ウェーハ１８を各半導体チップ１１別に分離する
ため、ダイヤモンドホイールを用いて前記半導体ウェー
ハ１８，熱伝導性物質１２及び絶縁層１９を一緒に切断
する。このとき、該絶縁層１９は、半導体ウェーハ１８
を切断するとき分離された半導体チップ１１の飛散を防
止するため用いられ、ポリイミドなどにより形成される
のが好ましい。尚、前記半導体チップ１１上には、パッ
ド（図示されず）が夫々形成される。Next, as shown in FIG. 2B, in order to separate the semiconductor wafer 18 into the individual semiconductor chips 11, the semiconductor wafer 18, the thermally conductive material 12 and the insulating layer 19 are separated using a diamond wheel. Disconnect together. At this time, the insulating layer 19 is
It is used to prevent the separated semiconductor chip 11 from scattering when cutting, and is preferably formed of polyimide or the like. Note that pads (not shown) are formed on the semiconductor chip 11, respectively.

【００１６】その後、図３（Ａ）に示したように、前記
絶縁層１９を除去し、前記半導体チップ１１の上面に接
着部材１３を用いて各内部リード１４ａと、該各内部リ
ード１４ａから屈曲形成された各外部リード１４ｂを有
するリード１４を夫々接着する。尚、前記接着部材１３
は、ポリイミドフィルム（Polyimide Film）が用いられ
るのが好ましい。Thereafter, as shown in FIG. 3A, the insulating layer 19 is removed, and the internal leads 14a are bent from the internal leads 14a on the upper surface of the semiconductor chip 11 using an adhesive member 13. The leads 14 having the formed external leads 14b are respectively bonded. The adhesive member 13
Preferably, a polyimide film is used.

【００１７】次いで、図３（Ｂ）に示したように、前記
半導体チップ１１上のボンディングパッド１１ａと前記
各内部リード１４ａとを通電部材としてのワイヤー１５
（又は、バンプ）を用いて電気的に連結する。その後、
図３（Ｃ）に示したように、前記半導体チップ１１、熱
伝導性物質１２、内部リード１４ａ、外部リード１４ｂ
及びワイヤー１５を包含した所定部位をモールディング
樹脂１６を用いて、前記熱伝導性物質１２の下面及び各
外部リード１４ｂの上面を露出させて密封する。Next, as shown in FIG. 3B, the bonding pad 11a on the semiconductor chip 11 and each of the internal leads 14a are connected to a wire 15 as a current-carrying member.
(Or bumps) for electrical connection. afterwards,
As shown in FIG. 3C, the semiconductor chip 11, the thermally conductive material 12, the internal leads 14a, and the external leads 14b
A predetermined portion including the wire 15 is sealed with a molding resin 16 by exposing the lower surface of the heat conductive material 12 and the upper surface of each external lead 14b.

【００１８】以上で、本発明に係る半導体パッケージの
製造工程を終了する。Thus, the semiconductor package manufacturing process according to the present invention is completed.

【００１９】[0019]

【発明の効果】以上説明したように、本発明に係る半導
体パッケージの製造方法においては、半導体ウェーハの
下面に熱伝導性物質を付着した後、該半導体ウェーハ及
び熱伝導性物質を一緒に切断するようになっているた
め、半導体パッケージの製造工程を簡略化し、前記熱伝
導性物質の面積を最小化して半導体パッケージの容積を
減らし得るという効果がある。As described above, in the method of manufacturing a semiconductor package according to the present invention, after attaching a heat conductive material to the lower surface of a semiconductor wafer, the semiconductor wafer and the heat conductive material are cut together. As a result, the manufacturing process of the semiconductor package can be simplified, the area of the heat conductive material can be minimized, and the volume of the semiconductor package can be reduced.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に係る半導体パッケージの構造を示した
縦断面図である。FIG. 1 is a longitudinal sectional view showing a structure of a semiconductor package according to the present invention.

【図２】本発明に係る半導体パッケージの製造工程を示
した縦断面図である。FIG. 2 is a longitudinal sectional view showing a manufacturing process of the semiconductor package according to the present invention.

【図３】本発明に係る半導体パッケージの製造工程を示
した縦断面図である。FIG. 3 is a longitudinal sectional view showing a manufacturing process of the semiconductor package according to the present invention.

【図４】従来の半導体パッケージの構造を示した縦断面
図である。FIG. 4 is a longitudinal sectional view showing a structure of a conventional semiconductor package.

【図５】従来の半導体パッケージの製造工程を示した縦
断面図である。FIG. 5 is a longitudinal sectional view showing a manufacturing process of a conventional semiconductor package.

【図６】従来の半導体パッケージの製造工程を示した縦
断面図である。FIG. 6 is a longitudinal sectional view showing a manufacturing process of a conventional semiconductor package.

【符号の説明】[Explanation of symbols]

１１：半導体チップ １１ａ：ボンディングパッド １２：熱伝導性物質 １３：接着部材 １４：リード １４ａ：内部リード １４ｂ：外部リード １５：ワイヤー １６：モールディング樹脂 １８：半導体ウェーハ １９：絶縁層 11: Semiconductor chip 11a: Bonding pad 12: Thermal conductive material 13: Adhesive member 14: Lead 14a: Internal lead 14b: External lead 15: Wire 16: Molding resin 18: Semiconductor wafer 19: Insulating layer

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平７−211673（ＪＰ，Ａ) 特開 平４−315446（ＪＰ，Ａ) 特開 平２−271558（ＪＰ，Ａ) 特開 昭56−4246（ＪＰ，Ａ) 特開 平８−241937（ＪＰ，Ａ) 特開 平７−273250（ＪＰ，Ａ) 特開 平４−85837（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/50 H01L 21/60 311 H01L 21/78──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-211673 (JP, A) JP-A-4-315446 (JP, A) JP-A-2-271558 (JP, A) JP-A-56-167 4246 (JP, A) JP-A-8-241937 (JP, A) JP-A-7-273250 (JP, A) JP-A-4-85837 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/50 H01L 21/60 311 H01L 21/78

Claims (7)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】半導体ウェーハの下面に熱伝導性物質を付
着する工程と、 前記半導体ウェーハを前記熱伝導性物質とともに所定長
さに切断し、複数のボンディングパッドを有する半導体
チップ別に分離する工程と、 前記分離された各半導体チップの上面に接着部材を介し
て、内部リードと該内部リードから上方向きに屈曲形成
された外部リードとを有するリードを接着する工程と、 前記各ボンディングパッドと前記各内部リードとを通電
部材により夫々連結する工程と、 前記熱伝導性物質の下面及び前記各外部リードの上面を
露出させて前記半導体チップ、前記内部リード、外部リ
ード及び前記熱伝導性物質を包含した所定部位をモール
ディング樹脂を用いてモールディングする工程と、 を順次行うことを特徴とする半導体パッケージの製造方
法。A step of attaching a thermally conductive substance to a lower surface of a semiconductor wafer; a step of cutting the semiconductor wafer together with the thermally conductive substance into a predetermined length, and separating the semiconductor wafer into semiconductor chips having a plurality of bonding pads. Bonding a lead having an internal lead and an external lead bent upward from the internal lead via an adhesive member on the upper surface of each of the separated semiconductor chips; and Connecting each of the internal leads with an electrically conductive member; and exposing the lower surface of the thermal conductive material and the upper surface of each external lead to include the semiconductor chip, the internal leads, the external leads, and the thermal conductive material. A step of molding a predetermined portion by using a molding resin; and Method. 【請求項２】前記接着部材は、ポリイミド膜（Polyimid
e Film）であることを特徴とする請求項１記載の半導体
パッケージの製造方法。2. The bonding member according to claim 1, wherein said adhesive member is a polyimide film.
3. The method of manufacturing a semiconductor package according to claim 1, wherein: 【請求項３】前記熱伝導性物質は、導電性物質であるこ
とを特徴とする請求項１又は請求項２記載の半導体パッ
ケージの製造方法。3. The method according to claim 1, wherein the heat conductive material is a conductive material. 【請求項４】前記導電性物質は、銅、銅とニッケルとの
合金、及びアルミニウム中、何れか一つを用いることを
特徴とする請求項３記載の半導体パッケージの製造方
法。4. The method according to claim 3, wherein the conductive material is one of copper, an alloy of copper and nickel, and aluminum. 【請求項５】前記通電部材は、ワイヤー又はバンプ（bu
mp）であることを特徴とする請求項１〜請求項４のいず
れか１つに記載の半導体パッケージの製造方法。5. The current-carrying member may be a wire or a bump.
mp). The method of manufacturing a semiconductor package according to claim 1, wherein 【請求項６】前記半導体ウェーハを切断する工程の前
に、前記熱伝導性物質に絶縁層（Insulating Layer ）
を付着する工程と、 該絶縁層を付着する工程の後であって前記モールディン
グする工程の前に、前記熱伝導性物質の絶縁層を除去す
る工程と、を更に付加して行うことを特徴とする請求項
１〜請求項５のいずれか１つに記載の半導体パッケージ
の製造方法。6. The method according to claim 1, wherein the step of cutting the semiconductor wafer includes applying an insulating layer to the heat conductive material.
And a step of removing the insulating layer of the heat conductive material after the step of attaching the insulating layer and before the molding step. The method of manufacturing a semiconductor package according to claim 1. 【請求項７】前記絶縁層は、ポリイミド層（Polyimide
Layer ）であることを特徴とする請求項６記載の半導体
パッケージの製造方法。7. The insulating layer comprises a polyimide layer.
7. The method for manufacturing a semiconductor package according to claim 6, wherein:
JP10027166A 1997-02-11 1998-02-09 Semiconductor package manufacturing method Expired - Fee Related JP2838703B2 (en)

Applications Claiming Priority (2)

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KR1019970003990A KR19980067735A (en) 1997-02-11 1997-02-11 Manufacturing method of semiconductor package
KR3990/1997 1997-02-11

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Publication Number Publication Date
JPH10229095A JPH10229095A (en) 1998-08-25
JP2838703B2 true JP2838703B2 (en) 1998-12-16

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JP (1) JP2838703B2 (en)
KR (1) KR19980067735A (en)
DE (1) DE19801488B4 (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10451897B2 (en) 2011-03-18 2019-10-22 Johnson & Johnson Vision Care, Inc. Components with multiple energization elements for biomedical devices
US9804418B2 (en) * 2011-03-21 2017-10-31 Johnson & Johnson Vision Care, Inc. Methods and apparatus for functional insert with power layer
US8857983B2 (en) 2012-01-26 2014-10-14 Johnson & Johnson Vision Care, Inc. Ophthalmic lens assembly having an integrated antenna structure
US9715130B2 (en) 2014-08-21 2017-07-25 Johnson & Johnson Vision Care, Inc. Methods and apparatus to form separators for biocompatible energization elements for biomedical devices
US9941547B2 (en) 2014-08-21 2018-04-10 Johnson & Johnson Vision Care, Inc. Biomedical energization elements with polymer electrolytes and cavity structures
US9793536B2 (en) 2014-08-21 2017-10-17 Johnson & Johnson Vision Care, Inc. Pellet form cathode for use in a biocompatible battery
US9599842B2 (en) 2014-08-21 2017-03-21 Johnson & Johnson Vision Care, Inc. Device and methods for sealing and encapsulation for biocompatible energization elements
US9383593B2 (en) 2014-08-21 2016-07-05 Johnson & Johnson Vision Care, Inc. Methods to form biocompatible energization elements for biomedical devices comprising laminates and placed separators
US10627651B2 (en) 2014-08-21 2020-04-21 Johnson & Johnson Vision Care, Inc. Methods and apparatus to form biocompatible energization primary elements for biomedical devices with electroless sealing layers
US10361405B2 (en) 2014-08-21 2019-07-23 Johnson & Johnson Vision Care, Inc. Biomedical energization elements with polymer electrolytes
US10361404B2 (en) 2014-08-21 2019-07-23 Johnson & Johnson Vision Care, Inc. Anodes for use in biocompatible energization elements
US10381687B2 (en) 2014-08-21 2019-08-13 Johnson & Johnson Vision Care, Inc. Methods of forming biocompatible rechargable energization elements for biomedical devices
US10345620B2 (en) 2016-02-18 2019-07-09 Johnson & Johnson Vision Care, Inc. Methods and apparatus to form biocompatible energization elements incorporating fuel cells for biomedical devices

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0740600B2 (en) * 1987-04-30 1995-05-01 三菱電機株式会社 Semiconductor device
JPH02271558A (en) * 1989-04-12 1990-11-06 Mitsubishi Electric Corp Semiconductor device and its manufacture
JP2665062B2 (en) * 1991-02-12 1997-10-22 三菱電機株式会社 Method for manufacturing semiconductor device
DE4231705C2 (en) * 1992-09-22 1998-04-30 Siemens Ag Semiconductor device with a system carrier and an associated semiconductor chip and method for their production
JPH06209054A (en) * 1993-01-08 1994-07-26 Mitsubishi Electric Corp Semiconductor device
US6300167B1 (en) * 1994-12-12 2001-10-09 Motorola, Inc. Semiconductor device with flame sprayed heat spreading layer and method

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DE19801488A1 (en) 1998-08-20
KR19980067735A (en) 1998-10-15
JPH10229095A (en) 1998-08-25
DE19801488B4 (en) 2004-10-21

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