JP2833669B2 - Pixel density conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel density conversion system, and more particularly to a pixel density conversion system for performing a scaling process on binary image data to an arbitrary magnification and outputting binary image data having different pixel densities. is there.

[0002]

2. Description of the Related Art Conventionally, as a pixel density conversion method of a binary image represented by binary data of white and black, SPC (Selected) is used.
A Pixel Coding method, a logical sum method, a projection method, a nine-division method, and the like are known. Each pixel density conversion method is intended for characters and line drawings. In a facsimile or word processor, etc., simple pixel thinning for each pixel represented by the SPC method and pixel density conversion processing by overlapping processing are performed because of the simple device configuration. Is being done.

Further, as a pixel density conversion method for an organized dither image, a method of obtaining a scaled image without moiré fringes by thinning out each dither matrix and scaling by overlapping processing has been proposed.

[0004]

However, in the above-described conventional example, a relatively good image can be obtained for a character or a line image when simple thinning and overlapping processing are performed for each pixel. However, when the above-described processing is performed on a pseudo halftone image in which the density is expressed by the density of black pixels in a certain area, the pattern of black pixels is lost, and the gradation is blurred and moire fringes are generated. was there. For example, if simple thinning-out and overlapping processing for each pixel are performed on a pseudo halftone image obtained by the error diffusion method, a gradation characteristic is seen and a noise-like image is obtained. Similarly, when processing is performed on the dither image, the period of the dither matrix is thinned out, and the period is interfered by the overlap processing, and moire fringes are generated.

[0005] On the other hand, in the thinning and duplication processing using the dither matrix as a unit, since the dither image expresses the density in the dither matrix unit, it is possible to obtain a relatively good scaled image with preserved gradation. it can. However, there is a drawback that the conversion magnification is limited and the image that can be handled is limited to a pseudo halftone image by dither.

The present invention has been made to solve the above problems.
The input binary digital image is pseudo
Even in the case of halftones and text images, the weighted average is calculated after enlargement.
After converting binary data to multi-valued density,
It is possible to obtain a high-quality image of any scale,
At the time of enlargement, the input binary data is converted to an integer in the form of binary data.
After multiplying by two, it is converted to multi-value density, so
Image blurring at the edge of the image
It is an object of the present invention to provide a pixel density conversion method that can be used.

[0007]

In order to achieve the above object, the present invention provides a method for receiving binary image data consisting of x pixels in the main scanning direction × y pixels in the sub-scanning direction, In a pixel density conversion method of converting binary image data to an arbitrary size in the direction Y and outputting binary image data,
Main scan with the image size of value image data as binary data
2 times and n times the sub-scanning to an arbitrary integer multiple, and an integer multiple 2
The enlargement means for obtaining the value image data, and the pixel of interest and the input binary image data for the integer-multiplied binary image data obtained by the enlargement means at the time of enlargement processing and the input binary image data at the time of reduction processing. Find the weighted average value of surrounding pixels
Because, the 2 multi-value density conversion means for converting the binary image data into multi-value density data, said binary multi-value density conversion size in the main scanning direction of the multi-level density data obtained by means subscanning directions an optional scaling means for reducing an arbitrary magnification, prior to
Serial characterized by chromatic and binarizing means for binarizing the multi-value density data obtained by any scaling means.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment according to the present invention will be described below in detail with reference to the drawings. <Explanation of the scaling process (FIG. 2)> First, the flow of the scaling process in this embodiment will be described in detail with reference to FIG. FIG. 2 is a flowchart showing a process for scaling binary data of x pixels in the main scanning direction and y pixels in the sub-scanning direction to binary data of X pixels in the main scanning direction and Y pixels in the sub-scanning direction. At first,
In step S1, it is determined whether to perform the enlargement processing in either the main scanning or the sub-scanning. If the enlargement processing is not performed, that is, if both the main scanning and the sub-scanning are the reduction processing, the process proceeds to step S3. If so, the process proceeds to step S2.

(1) Enlargement processing In the case of enlargement processing, binary digital data of x pixels in the main scanning direction x y pixels in the sub-scanning direction are subjected to overlapping processing in the main scanning direction in the binary integer multiple enlargement processing in step S2. To n times (n = [X / x], where [a] represents an integer not less than a), and m times (m = [Y / y], where Y> y) in the sub-scanning direction. And convert the data to binary data of nx × my pixels. In step S3, the binary data obtained in step S2 is scanned for each pixel using a window corresponding to the magnification, and multi-value density data is calculated from the pixel pattern of the binary image in the window. , Nx × m
The image data is converted into multi-value density image data of y pixels. In the next step S4, the image data of multi-valued density of nx × my pixel size converted in step S3 is thinned out by a clock and a line synchronization signal, reduced and scaled to an arbitrary size, and multiplied by X × Y pixels. The image data is converted into image data of the value density. Then, in step S5, a multi-valued binary image of X × Y pixels is obtained by binarizing the image data of the multi-value density of X × Y pixels.

(2) Reduction Processing On the other hand, in the case of reduction processing, in step S3, binary data of x × y pixels is scanned for each pixel using a window corresponding to the scaling factor, and 2 × The multi-value density data is calculated from the pixel pattern of the value image, and converted into multi-value density image data of x × y pixels. Next, step S4
In step S3, the image data of the multivalued density of the xy pixel size converted in step S3 is thinned out by the clock and the line synchronizing signal, and reduced and scaled to an arbitrary size to obtain the XY image.
The image data is converted into image data of multi-value density of pixels. Then, in step S5, the multi-value density image data of X × Y pixels is
By performing the binarization processing, a scaled binary image of X × Y pixels is obtained.

In the above flow, when a binary image is converted into image data having a multi-valued density, a window scan with different reference pixels and different weights is performed depending on the scaling factor. After that, by converting the binary image into image data of multi-value density, it is possible to obtain a scaled image in which the blur of the edge portion of the image generated at the time of multi-value conversion is minimized. Here, by performing the contour smoothing enlargement process at the time of enlargement, it is possible to interpolate the step of the hatched portion generated at the time of the overlap enlargement and obtain a higher-quality character image.

<Description of Configuration (FIG. 1)> Next, a specific apparatus for performing the above-described scaling processing will be described in detail. FIG. 1 is a block diagram illustrating a configuration of a pixel density conversion device according to the present embodiment. Hereinafter, the components will be described in order. In FIG. 1, reference numeral 100 denotes a data line input to the apparatus, and binary digital data represented by one bit of white and black (here, black is "1" and white is "0"). Is entered. When the enlargement process is performed, the binary data input from the data line 100 in the binary enlargement circuit 2 is n-fold (n is an integer) in the main scanning direction and m-fold (m Are integers),
The signal is output from a later-described selector 6 to the multi-level circuit 3 via a signal line 200. In the case of performing reduction / magnification, the binary data input from the data line 100 is input from the selector 6 to the multi-value conversion circuit 3 as it is. In selector 6,
At the time of the enlargement processing, the binary data input from the signal line 200 is selected, and at the time of the reduction processing, the binary data input from the signal line 100 is selected and input to the multi-level circuit 3.

In the multi-level conversion circuit 3, data is temporarily stored in a memory (not shown), and image data in an arbitrary area is extracted.
Then, referring to an area composed of the pixel of interest and its surrounding pixels, based on the window output from the load table, multi-value density image data (for example, in the case of 6-bit output,
("0" to "63", white is "0", black is "63")
And outputs the multi-value data to the scaling circuit 4 via the signal line 300. Next, the scaling circuit 4 reduces and scales the multi-valued image data output from the multi-level conversion circuit 3 to an arbitrary size by thinning out the image clock and the line synchronizing signal. To the binarization circuit 5 via In the binarizing circuit 5, the above-described scaling circuit 4 is used.
The multi-level data output from the multi-level data is converted into binary data and output to the data line 500.

The detailed configuration of the pixel density converter having the above configuration will be described below in detail with reference to the related drawings. <Description of Binary Expansion Circuit (FIGS. 3 to 5)> FIG.
FIG. 3 is a block diagram showing a specific configuration of a binary expansion circuit 1 shown in FIG. As shown in the figure, the binary enlargement circuit 1 includes a line buffer 210, a line buffer control unit 220, and a D flip-flop 230.
1, a simple overlapping process is performed by controlling the CLK2 and the line synchronization signals DB1 and DB2, and the binary image is enlarged. First, binary image data in which one pixel is represented by one bit is input to the line buffer 210 in synchronization with an image clock CLK1 and a line synchronization signal DB1 output from a timing control circuit 1 described later. Here, when the image clock CLK1 and the line synchronization signal DB1 are enlarged by, for example, n times in the main scanning direction and m times in the sub scanning direction, the image clock CLK2 after the overlap processing is divided by n, and the line synchronization signal The data obtained by dividing DB2 by m is selected by the timing control circuit and input to the binary expansion circuit.

Next, the binary image data input from the signal line 100 is written into the line buffer 210 by the line buffer control unit 220 in synchronization with the image clock CLK1 and the line synchronization signal DB1, and simultaneously with the clocks CLK1 and DB2. And read out to the signal line 240. Here, due to the relationship between DB2 and DB1, image data is read m times each time one line is written, and m-times enlargement processing is performed in the sub-scanning difference direction. As an example, FIG. 4 shows a case in which enlargement processing is performed twice in the sub-scanning direction. As shown in the figure, the image data input in synchronization with DB1 is
The data is read from the memory in synchronization with DB2, and the data of the same line is output twice.

The image data read from the line buffer 210 in synchronization with the image clock CLK1 is
The signal is input to the D flip-flop 230 via the signal line 240, and is sub-sampled by the image clock CLK2. That is, the 1-bit binary data input in synchronization with CLK1 is sampled n times by CLK2, so that the data is magnified n times in the main scanning difference direction. FIG. 5 is a timing chart showing a case where the image is enlarged twice in the main scanning direction.

<Description of Multi-Valued Circuit (FIGS. 6 to 9)> Next, a specific configuration of the multi-valued processing circuit 3 shown in FIG.
This will be described below with reference to FIG. The multi-level conversion circuit 3 in the present embodiment includes line memories 31a to 31d, a shift register group 320, a load table 330, a data selector multiplexer 340, a gate group 350, an adder 360,
A data line 370 for outputting data from the load table, and a data line 380 for selecting a data group of the load table 330 according to the scaling factor.
Based on the value data, an area consisting of the pixel of interest (i, j) and its surrounding pixels is referenced, and a weight mask (here, matrix data output from the load table 330) corresponding to each pixel in the reference area is used. A weighted average density is calculated, and multi-value density data (in the case of 6 bits, the maximum value is 63)
Output as

Next, the operation of the multi-level conversion circuit 3 will be described in detail. First, when enlargement processing is performed in either the main scanning direction or the sub-scanning direction, binary image data is input from the input line 200 in synchronization with the image clock CLK2 and the line synchronization signal DB2. In the case of performing the reduction processing, the binary image data is supplied from the input line 100 to the image clock CLK2.
= CLK1, and the line synchronization signal DB2 is input as it is in synchronization with DB1. The input binary image data is first read into the line memory 31a of the line memory group 310, and sequentially shifted in the sub-scanning difference direction from the line memories 31b → 31c → 31d for each line in synchronization with the line synchronization signal DB2. To go.

Then, parallel data for four pixels in the sub-scanning difference direction is read out from each of the line memories 31a to 31d in synchronization with the image clock CLK2, and the shift register group 3 is read.
20 is shifted and input. This shift register group 320
, The image data is sequentially shifted in synchronization with the image clock CLK2, and image data having a matrix of 4 pixels × 4 lines is extracted and input to the gate group 350 as 16 1-bit matrix data. Here, assuming that the data latched in the shift register C3 is the pixel of interest (i, j), as shown in FIG. 8, in each peripheral pixel, A1 is (i-2, j-2) and A2 is (i, j-2). -1,
j-2), A3 is (i, j-2), A4 is (i + 1, j
Similarly, B1 is (i-2, j-1), B2 is (i-1, j-1), B3 is (i, j-1), and B4 is (i + 1, j-1). , C1 is (i−2, j), C2 is (i−1, j), C4 is (i + 1, j), and D1 is (i−2, j).
2, j + 1), D2 is (i-1, j + 1), D3 is (i, j + 1), and D4 is (i + 1, j + 1).

On the other hand, several types of matrix data having a size of 4 × 4 are stored in the load table 330 in advance. In the load table 330, the gate group 350
Are standardized so that the total sum of the matrix data output to is the maximum value of the multi-level output (in the case of 6-bit output, the maximum is 63). FIG. 9 shows an example of weighting the individual pixels of the load table 330. For example, 90%
In the case of the reduction ratio, as shown in FIG. 9B, a 3 × 3 window (here, 3 × 3
(The window size is set to 3 × 3 by setting the weight of pixels around the × 3 window to “0”.) When the reduction ratio is large, a flat window as shown in (c) is used, and when the reduction ratio is 50% or less, the window size is increased according to the reduction ratio.

Here, address data for selecting a window corresponding to the magnification is input to the data multiplexer 340 via a signal line 380, and one of the matrix data groups of the load table 330 is changed according to the address data. Selected and input to the gate group 350.
Next, in the gate group 350, when the image data extracted from the latches A1 to D4 is a black pixel, the gate corresponding to each latch is opened, and the numerical data output from the data selector multiplexer 340 is output to the adder 360. Is done. When the image data is a white pixel, the gate corresponding to each latch is closed, and “0” is output to the adder 360.

Next, in adder 360, gate group 3
The sum total of the data output from 50 is calculated, and the result is output to the signal line 300 as multi-value data of the pixel of interest. Although the data is input to the signal line 380 according to the magnification in this embodiment, for example, windows having appropriate weights are respectively stored in the load table 330 for characters, line drawings, and pseudo halftone images in advance. In addition, input data to which the judgment result from image area separation for identifying whether the pixel of interest is a pseudo halftone area or a character line drawing area, and select separate matrix data for each image area. Thus, a higher-quality multi-valued image can be obtained.

In this embodiment, the reference pixel area for calculating multi-value data is 4 pixels × 4 lines. However, the present invention is not limited to this.
The reference pixel area can be easily increased or decreased by increasing or decreasing the gate and the load table. <Explanation of the Magnification Circuit (FIGS. 10 to 15)> Next, details of the magnification circuit 4 for reducing the multivalued image data will be described below.

First, the image reduction processing by the scaling circuit 4 is performed by thinning out an image clock and a line synchronization signal. Here, since the configuration is simple, the converted image takes the pixel value closest to the original pixel (SPC method).
Coding) as an example. Prior to the description, the timing control circuit 1 that outputs the reduced image clock CLK3 and the line synchronization signal DB3 will be described in detail with reference to FIG.

In FIG. 1, reference numeral 110 denotes a crystal oscillator for generating a basic clock, and 120 denotes an image clock CLK1,
CLK2 and an image clock and line synchronizing signal selector for outputting the line synchronizing signals DB1 and DB2, a main scanning image clock control circuit 130 for arbitrarily thinning out the clock according to the main scanning reduction ratio of the magnification circuit, and 140 a magnification A sub-scanning line synchronizing signal control circuit that performs a thinning process of an arbitrary line synchronizing signal according to the sub-scanning reduction ratio of the circuit.

In the above configuration, based on the reference clock CLK0 input from the outside, the image clock and line synchronizing signal selector 120 divides the basic clock in accordance with the enlargement ratio of the binary enlargement circuit 2 in the main scanning direction. The image synchronizing signals DB1 and DB2 determined by the image clocks CLK1 and CLK2 and the enlargement ratio in the sub-scanning direction in the binary enlargement circuit 2 are selected and output. Then, the output image clock CLK2 is input to the main scanning image clock control unit 130, where the input image clock CLK2 is thinned out according to the reduction ratio in the scaling circuit 4, and the image clock of the reduced image data is output. CLK3 is output. Similarly, the sub-scanning line synchronizing signal control circuit 140 performs a thinning process of the line synchronizing signal DB2, which is a sub-scanning direction reduction process in the scaling circuit 4, and outputs the line synchronizing signal DB3 of the scaled image data. Is output.

Next, the detailed operation of the main scanning image clock control circuit 130 will be described below with reference to FIG. For example, when the main scanning direction is reduced to γx / Rx (γx and Rx are arbitrary integers determined by the reduction ratio) (γ
x <Rx), as shown in FIG. 11, when the original pixels are arranged at every distance γx, the converted pixels are arranged at every distance Rx. Here, △ X = Rx−γx, and when the coordinates of the first original pixel and the converted pixel are aligned with the origin, the difference between the distance between the second original pixel and the converted pixel is △ x, and the third distance Is 2 △ X, and △ X is added for each original pixel.
Here, every time the added result becomes larger than the distance γx between the original images, the distance γx is subtracted from the added result, and one coordinate of the original image is sent at that time. As described above, when the difference between the distance between the original image and the converted image is sequentially calculated and the coordinates of the original image are sent according to the calculation result, the original image is sent at a certain rate according to the reduction ratio, and the remaining pixels are sent. Is a conversion pixel,
The thinning process according to the reduction ratio is performed. Here, the difference between the distance between the original image and the converted image at the coordinate origin is 2
/ Γx, the converted image is decimated so that the closest pixel to the original image is selected, and the SPC method (Selected Pixel Coding) is performed.
).

Here, assuming that the pixel size of the original image in the main scanning direction is γx = 256, the main scanning image clock control circuit 1
The operation of 30 will be described in detail with reference to FIGS. In FIG. 12, 410 and 420 are D flip-flops, 430 is an 8-bit output adder having a carry signal line, and 440 is a gate circuit for applying a gate to the clock CLK2. As shown, ΔX is input to the adder 430 in synchronization with CLK2. Here, ΔX is a value determined according to the scaling factor. For example, in the case of reducing to 8/11, ΔX = 256 × 1 / 8−256 = 96. At the time of reset, the output of the adder 430 is γx / 2 = 12
It becomes 8. The result of the addition processing output to the output line 405 is input to the D flip-flop 420 and input to the adder 430 in synchronization with CLK2. In the adder 430, the D flip-flop 420 and the value output from the D flip-flop 420 are added in synchronization with the image clock CLK2, and △ X is sequentially added to the previous addition result. Here, only the 8-bit data of the output of the adder 430 is supplied to the D flip-flop 4 via the signal line 405.
Returned to 20.

Therefore, every time the addition result becomes γx (256) or more, γx is subtracted. Also, the image clock CLK2 input to the gate 440
Is subjected to mask processing by the carry signal of the adder 430 output from the output line 406, and the image clock CLK3 thinned out from the clock CLK2 is output. As shown in FIG. 13, the thinning-out process in the main scanning direction is performed by sampling the image data input in synchronization with the image clock CLK2 by CLK3. The sub-scanning line synchronizing signal control circuit 140 is configured similarly to the main-scanning image clock control circuit 130, thins out the line synchronizing signal DB2, and outputs DB3.
Then, as in the main scanning direction, reduction in the sub-scanning direction is performed by thinning out the line synchronization signal.

In this embodiment, the case where the original image is thinned out and reduced by thinning out the image clock and the line synchronizing signal as the scaling circuit 4 has been described. It is also possible to perform Hereinafter, the scaling process in this case will be described. As described above, the main scanning image clock control circuit 130 and the sub-scanning line synchronization signal control circuit 140 shown in FIG.
As an output, the difference between the distance between the original image and the scaled image can be obtained. Therefore, by weighting the original image data in the vicinity of the converted pixel based on the positional relationship between the original image and the scaled image, and calculating the converted pixel density, scaled multivalued density data having better density preservation than the SPC method is obtained. be able to. As a method of weighting, an inversely proportional distance method or an area occupation ratio of the converted pixel to the original pixel as shown in FIG. 15 can be used. Here, a portion surrounded by a broken line in the figure is an original pixel, and a portion surrounded by a solid line is a converted pixel.

FIG. 14 is a block diagram showing the configuration of the density calculation circuit when the area occupancy is used. In the figure, reference numeral 610 denotes each line memory 610a, 610b, 61
0c, 620 is a shift register group, 630 is a weight coefficient calculation circuit that calculates the weight of each pixel from the positional relationship between the converted pixel and the original pixel, and 640 is a plurality of multipliers 640a, 640b, 640c, 640
d, 640e, 640f, 640g, 640h, 640
A multiplier group composed of i, and 650 is an adder. In such a configuration, data of an original pixel (peripheral pixel) in the vicinity of the conversion pixel (pixel of interest) can be obtained by the line memory group 610 and the shift register group 620 as in the case shown in the multi-level circuit 3. . In this embodiment, an example will be described in which matrix data of 3 pixels × 3 lines is extracted by the above-described circuit in consideration of the fact that converted pixels are affected by up to 9 pixels with respect to original pixels at the time of reduction of 50% or more. Further, as in the case of the multi-value coding circuit 3, the reference pixel can be arbitrarily taken.

Next, a method of calculating the weight coefficient output by the weight coefficient calculation circuit 630 will be described below. As shown in FIG. 15, the main scanning image clock control circuit 13 described above is used.
Using the 0 and the addition result output from the sub-scanning line synchronization signal control circuit 140 and the carry signal ($ xx, $ yy), the length of each side (Rx- $ xx, γx, △ xx-γx, RY- △ yy,
γy, △ yy-γy) are obtained. Where △ x
x, △ yy is the difference between the distance between the original pixel including the carry signal and the converted pixel. If the converted pixel does not extend over the three original pixels, the length of each side is Rx- △ x
x, Δxx, RY−Δyy, Δyy. Next, the area occupied by the converted pixel in the original pixel is calculated from the length of each side described above. For example, the area a of the converted pixel occupying the original pixel A is (Rx- △ xx) × (RY- △ yy), and the original pixel B
Is the area b of the conversion pixel occupied by γx × (RY− △ y
y) Similarly, c, d, e, f, g, h, and i are calculated. And individual areas a, b, c, d, e, f,
The values obtained by normalizing g, h, and i with the area of the converted pixel are used as weighting factors for the corresponding pixels. The weighting is uniquely determined by the difference △ xx, △ yy between the original image and the scaled image output from the main scanning image clock control circuit 130 and the sub-scanning line synchronization signal control circuit 130. The weighting data may be stored in a ROM table having Δyy as the address of the table, and may be used instead of the weighting coefficient calculation circuit 630. Also in the case of the distance inverse proportional method, it can be similarly constituted by a ROM.

Next, the weighting of the original pixel density is performed based on the weighting data obtained from the weighting coefficient calculation circuit 630 described above. This processing is performed by the multipliers 640a to 640.
This is a process in which the sum of the outputs from the individual multipliers is obtained by the adder 650, which is obtained as a product of the original pixel density value by i, and is finally output as the density value of the converted image. <Description of Binarization Circuit (FIGS. 16 to 18)> FIG. 16 is a diagram illustrating a specific configuration example of the binarization circuit 5 illustrated in FIG. The binarization circuit 5 includes the multi-level conversion circuit 4 described above.
, The image data converted into the multi-valued data is converted again into binary data, and binary resized image data is output. 2
As a binarization method, any binarization method such as a dither method or an average error minimization method can be used. Here, the error generated when binarizing is diffused to surrounding pixels and binarized,
An error diffusion method that can obtain a scaled image with good density preservation is used.

Hereinafter, a binarizing circuit 5 using error diffusion processing
Will be described with reference to the drawings. In FIG. 16, 5
1a to 51d are D flip-flops for latching data, 52a to 52d are adders, 530 is a line memory for delaying one line, 540 is a comparator, and 560 is an error distribution control circuit. In the above configuration, first, the multi-value (for example, 6 bits, 0 to 6) output from the scaling circuit 4 is used.
3) Density image data is input via the signal line 400 in synchronization with the image clock CLK3 and the line synchronization signal DB3. The input multi-value density data (original image multi-value density data corresponding to the target pixel position (i, j)) is added by the adder 52d to the sum of errors distributed to the pixel position, and the value is added. Is output from the signal line to the comparator 540 and the error distribution control circuit 560, respectively. And the comparator 5
At 40, the data on the signal line is compared with a certain threshold value TH (for example, 32 in the case of 6-bit data), and if the data on the signal line is larger than the threshold value TH, “1” (black) is set.
If it is smaller, “0” (white) is output to the signal line 500 in synchronization with the image clock CLK3 and the line synchronization signal DB3.

Next, in accordance with the binarization result, the error distribution control circuit 560 receives data input from the signal line 550 if the output is white, and the signal line 550 and a constant T (if the output is black. The difference from (63) in the case of 6-bit data is used as an error, and error amounts 56a to 56d to be distributed to surrounding pixels are calculated. As shown in FIG. 17, when the target pixel position is (i, j) as shown in FIG. 17, the error amount signals 56a to 56d are the surrounding pixels (i-1, j + 1), (i, j + 1), (i + 1, j +).
1) and the error amounts already distributed to (i + 1, j) are added by the adders 52a to 52d, respectively. Further, although the number of pixels to which the error is distributed is four pixels of the pixel of interest here, the number of pixels is not limited to this and can be easily increased or decreased.

The detailed configuration of the above-described error distribution circuit 560 will be described below with reference to FIG. In the figure, 561 is a subtractor, 562 is a selector, and 563a to 563d are multipliers for performing a predetermined multiplication. First, the subtractor 561 calculates the difference (signal 5) between the signal 550 of the corrected density obtained by adding the distribution error to the original image density and the signal (constant T = 63) from the signal line 570.
50−constant T) is calculated and output to the selector 562. The selector 562 outputs the second signal input from the signal line 500.
If the binarization result is "0" (white) according to the binarization result, the former (signal 550) is selected, and if the binarization result is "1" (black), the latter (signal 550-T) is selected. , Multiplier 563a-
563d. Here, the multipliers 563a to 563
As shown in FIG. 18, d is a peripheral pixel (i−1, j +) having a weight of w1 to w4 with respect to the pixel of interest (i, j), respectively.
1), (i, j + 1), (i + 1, j + 1), (i +
1, j), and performs the following multiplication in accordance with the weight to perform signal lines 56a, 56b, 56c and 56
Output the result to d.

[0037]

## EQU1 ## According to the binarization method described above, it is possible to obtain a scaled binary image having excellent density preservation with respect to a pseudo halftone.

[0038]

As described above, according to the present invention,
Even if the input binary digital image is a pseudo halftone or a character image, the binary data is obtained by obtaining a weighted average after enlargement.
After converting to multi-value density, the magnification is changed, so any high-quality
A scaled image can be obtained. Especially when expanding,
After expanding the binary data to an integer multiple in the form of binary data
In addition, since it is converted to multi-value density, the image generated at the time of multi-value conversion
Can be suppressed as much as possible .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a pixel density conversion device according to an embodiment.

FIG. 2 is a flowchart illustrating a scaling process according to the embodiment.

FIG. 3 is a block diagram showing a configuration of a binary expansion circuit shown in FIG. 1;

FIG.

FIG. 5 is a timing chart for explaining the operation of the binary expansion circuit;

FIG.

FIG. 7 is a block diagram showing a configuration of a multi-level circuit shown in FIG. 1;

FIG. 8 is a diagram illustrating the relationship between 4 × 4 image data and coordinates.

FIG. 9 is a diagram illustrating a weighting ratio of a window in the multi-value processing.

FIG. 10 is a block diagram showing a configuration of a timing control circuit shown in FIG. 1;

FIG. 11 is a diagram illustrating a positional relationship between an original image and a converted image in a scaling circuit.

FIG. 12 is a diagram illustrating clock thinning at the time of reduction at an arbitrary magnification.

FIG. 13 is a timing chart illustrating reduction in the main scanning direction.

FIG. 14A,

FIG. 14-2 is a block diagram showing a configuration of a circuit for calculating a reduced pixel density by calculation.

FIG. 15 is a diagram for explaining weighting during reduction / magnification;

FIG. 16 is a block diagram showing a configuration of a binarization circuit shown in FIG. 1;

FIG. 17 is a diagram illustrating a relationship between a pixel of interest and a pixel to which an error is distributed.

18 is a block diagram showing a configuration of the error distribution control circuit shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Timing control circuit 2 Binary expansion circuit 3 Multi-value conversion circuit 4 Magnification circuit 5 Binarization circuit 6 Selector

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 1/393 G06T 3/40

Claims (3)

(57) [Claims] 1. Binary image data consisting of x pixels in the main scanning direction × y pixels in the sub-scanning direction is input and converted into an arbitrary size of X pixels in the main scanning direction × Y pixels in the sub-scanning direction to convert the binary image data. In the output pixel density conversion method, the image size of the input binary image data is enlarged to an arbitrary integral multiple of m times in the main scanning and n times in the sub-scanning as binary data ,
Enlarging means for obtaining integer-multiplied binary image data ; for enlarging processing, for the integer-multiplied binary image data obtained by the enlarging means, and for reducing processing, for the input binary image data. The weighted average value of the pixel of interest and its surrounding pixels is obtained, and the binary image data is converted to a multi-valued density data.
And 2 multi-value density conversion means for converting the over data, the binary multilevel density conversion size in the main scanning direction of the multi-level density data obtained by means of any reduced at any magnification to each sub scanning direction variable A pixel density conversion method, comprising: a multiplication means; and a binarization means for binarizing the multi-value density data obtained by the arbitrary magnification means. 2. The method according to claim 1, wherein the binary / multi-level density converting means changes a window size and weighting when converting from binary to multi-level density in accordance with a scaling factor of an image size. The pixel density conversion method according to claim 1. 3. A further or the target pixel is included in the character image area, has a determination means for determining whether contained in a pseudo-halftone area, said binary multi-value density conversion means based on the determination result, 2 2. The pixel density conversion method according to claim 1, wherein a window size and a weight at the time of converting the value to the multi-value density are changed.