JP2833030B2 - Manufacturing method of nonvolatile semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a nonvolatile semiconductor device, and more particularly to a method for manufacturing a nonvolatile semiconductor memory device having a double gate electrode transistor.

[Prior Art] Conventionally, as an example of a manufacturing method for highly integrating such a storage device, the one shown in FIG. 4 is known. According to this method, an insulating film is buried in a groove formed by etching a substrate to form an element isolation region.
86 VLSI SYMPOSIUM (Digest Te
chnology Paper, 1986, VLSI SYMPOSIUM, P87, K. Sekiya et.
al.).

Hereinafter, this manufacturing method will be described with reference to FIGS. 4 (a) to 4 (i).
This will be described with reference to FIG.

As shown in FIGS. 4 (a) and 4 (b), ((b) is (a)
Cross-section along the line BB) of FIG.
A first gate oxide film 102 is formed, and a first gate oxide film 102 is further formed thereon.
Polycrystalline silicon layer 103, insulating film 104, polycrystalline silicon layer
Then, a photoresist 106 is patterned by a well-known PR (photolithography) technique so as to expose only a portion to be an element isolation region later, and using this as a mask, the polycrystalline silicon layer 105 is formed. Insulating film 104,
The first polycrystalline silicon layer 103 and the first gate oxide film 102 are sequentially and selectively etched to expose the substrate surface, and the substrate is etched in a groove shape.

Next, as shown in FIG.
After removing 6, an oxide film 107 is deposited on the entire surface by a vapor phase growth method or the like, and this is etched back to form a polycrystalline silicon layer 10.
By exposing the surface of 5, an oxide film is embedded in the groove.

Next, as shown in FIG.
After removing the insulating film 104 and the insulating film 104, a second gate oxide film 108 is newly formed on the first polycrystalline silicon layer by, for example, a thermal oxidation method. The silicon layer 109 is stacked.

Next, as shown in FIG. 4 (e), a photoresist 110 is formed at a predetermined position by a well-known PR technique. Further, a plurality of polycrystalline silicon lines 111 separated from each other are formed. Here, the polycrystalline silicon line 111
The photoresist 110 for patterning is left.

Next, as shown in FIG.
Using the mask 0 as a mask, the second gate insulating film 108 and the first polycrystalline silicon layer 103 are removed by etching in a self-aligned manner with respect to the line 111, and a plurality of floating layers are formed by the first polycrystalline silicon layer 103. A gate is formed. For example, a floating gate is formed at the segment 112.

Next, as shown in FIG. 4 (g), an n-type drain region 113 and an n-type source region 114 are formed by introducing an n-type impurity into the line 111 in a self-aligning manner by, for example, an ion implantation method. Form.

Next, as shown in FIG. 4 (h), an interlayer insulating film is formed on the entire surface.
115 is formed, and then a contact hole is formed on the N-type drain region.

Finally, as shown in FIG. 4 (i), an aluminum wiring 117 is formed by a well-known PR technique and etching technique, and the cell array 118 is completed.

[Problem to be Solved by the Invention] In the above-described conventional manufacturing method, it is necessary to provide an X shown in FIG. 4 (e), that is, an overlapping margin between a word line and an element isolation region. However, there is a disadvantage that it is difficult to measure the amount. 4 (e), that is, when an attempt is made to achieve high integration by reducing the distance between the source diffusion layers, the source resistance is increased, and the write characteristics and read characteristics of the cell are deteriorated. There is. Thus, in the conventional manufacturing method,
It is difficult to achieve high integration without deteriorating cell characteristics.

[Differences of the Invention from the Prior Art] In contrast to the above-described conventional manufacturing method, the present invention forms a plurality of linear trench element isolation regions, and forms a plurality of word lines orthogonal to these. Exposing the side surface of the substrate only on the source region side, introducing an n-type impurity into the substrate in a self-aligned manner with respect to the word line, forming a side wall of an insulating film on the side wall of the word line, and then forming on the exposed silicon substrate By performing selective growth of the conductor material, n adjacent to the source region only via the element isolation region can be formed.
The difference is that the mold regions are connected.

[Means for Solving the Problems] The present invention provides a first line having at least two layers of a first insulating film and a first conductor layer on a semiconductor substrate of one conductivity type, and extending in one direction. Forming a plurality of lines separated from each other, forming a linear groove extending in one direction in the substrate between the first lines, and embedding an insulating material in the groove to form an element isolation region. Forming a plurality of second lines composed of at least two layers of a second conductor layer and a second insulating film that are insulated from the first lines and that are separated from each other, Forming a plurality of floating gates from the first line by etching the first line in a self-aligned manner with respect to the second line; Between a plurality of formed second lines A step of partially removing an insulating material in an element isolation region of a region to be a source in the region to be exposed, and exposing a part of a side surface of the substrate in the region; Forming a reverse conductivity type doped region on the substrate surface by introducing the second line in a self-aligned manner; depositing an insulating film over the entire surface and etching the insulating film to form a side wall of the second line; Forming a sidewall of an insulating film on the substrate, and selectively growing a conductive material only on a portion where the substrate is exposed. Connecting the adjacent doped regions to each other and preventing connection in a region to be a drain.

Next, the present invention will be described with reference to the drawings. FIG. 1 (a) is a plan view of a memory cell array manufactured by the method of the present invention, and FIGS. 1 (b), (c), (d) and (e) are BB, FIG. 1 (a), respectively. It is sectional drawing along CC, DD, EE. FIG. 1B shows the source region of the array. Here, adjacent n-type source diffusion layers are connected by CVD tungsten 3 via the element isolation region 1. On the other hand, FIG. 1 (c) shows the drain region of the array, but the adjacent N-type drain diffusion layer 4 via the element region 1 is separated. This is the point of the present invention.

Next, an embodiment of the manufacturing method according to the present invention will be described with reference to a plan view and a sectional view shown in FIG.

First, as shown in FIG. 2A, a P-type semiconductor substrate 5 is formed.
A first gate oxide film 6, a first polycrystalline silicon layer 7, an insulating film 8, and a polycrystalline silicon layer 9 are sequentially formed thereon.

Next, as shown in FIGS. 2 (b) and 2 (c), a well-known PR
A photoresist 10 is formed by a technique, and using this as a mask, the polycrystalline silicon layer 9, the insulating film 8, the first polycrystalline silicon layer 7, and the first gate oxide film 6 are sequentially etched to form four layers. A plurality of stacked first lines 11 are formed parallel to and separated from each other, and the silicon substrate between the lines is etched in a groove shape.

Next, as shown in FIG. 2 (d), after removing the photoresist, a CVD oxide film 12 is deposited on the entire surface by vapor phase epitaxy, and then etched back until the surface of the polycrystalline silicon layer is exposed. Then, a CVD oxide film 12 is buried in the trench to form a linear element isolation region 13. At this time, the polycrystalline silicon layer 9 has a role of protecting the underlying first polycrystalline silicon layer and preventing the surface of the CVD oxide film from becoming deeper than the first polycrystalline silicon layer 7 during the etch back.

Next, as shown in FIG. 2 (e), after the polycrystalline silicon layer 9 and the insulating film 8 are removed by, for example, anisotropic etching using RIE, a new layer is formed on the first polycrystalline silicon layer 7. 2
The gate insulating film 14 is formed. As this insulating film, for example, there is ONO (oxide film-nitride film-oxide film). Next, a second polycrystalline silicon layer 15 and a second insulating film 16 are deposited.

Next, as shown in FIG. 2 (f), a photoresist 17 is formed by a well-known PR technique, and the second insulating film 16 and the second polysilicon layer 15 are sequentially etched using the photoresist 17 as a mask. A plurality of mutually parallel and separated second lines 18 are formed by laminating the two layers. These second lines 18 are orthogonal to the first lines 11 and cross over the first lines 11 via the second gate insulating film. Here, the photoresist 19 on the second line is left.

Next, as shown in FIG. 2 (g), the second gate insulating film and the first polycrystalline silicon layer are removed by etching in a self-aligned manner with respect to the second line 18 to form a first polycrystalline silicon layer. A plurality of floating gates made of a silicon layer are formed, for example, in the region of the segment 20.

On the other hand, the second gate insulating film and the first polysilicon layer in the region between the second lines 18 are removed. Also here, the photoresist 19 on the second line is left.

Next, as shown in FIGS. 2 (h) and 2 (i), of the region between the second lines, the drain region side is made of photoresist.
By covering with 21 and performing moderate anisotropic etching,
Partially remove the oxide film in the element isolation region on the source region side,
The substrate surface and side surfaces are exposed. FIG. 2 (i) is a sectional view taken along the line II of FIG. 2 (h).

Next, as shown in FIG. 2 (j), after the photoresist is removed, an n-type impurity is ion-implanted, for example, using the second line 18 as a mask, and the substrate between the second lines is self-aligned. And a plurality of N-type drain diffusion layer regions 22,
An N-type source diffusion layer region 23 is formed. For convenience, the display of the first gate oxide film on the drain diffusion layer region is omitted.

Next, an oxide film is deposited on the entire surface as shown in FIG.
A sidewall 24 is formed on the side surface of the line 18. Second
Figures (l), (m), and (n) correspond to those in FIG.
It is sectional drawing which follows LL, MM, NN. Here, FIG. 2 (l)
In the source region shown in FIG. 2, a part of the side wall of the substrate is exposed, but on the drain region side shown in FIG. 2 (m), the side surface of the substrate is not exposed and is surrounded by the side wall.

Next, as shown in FIGS. 2 (o) and 2 (p), CVD tungsten 3 is selectively grown. At this time, in the source region, as shown in FIG. 2 (o), the CVD tungsten grows not only upward but also laterally from the exposed substrate side surface Z as a starting point, and finally through the element isolation region. Adjacent N type source diffusion layer regions 23 are connected by CVD tungsten 3. On the other hand, in the drain region, as shown in FIG. 2 (p), since the drain diffusion layer region is surrounded by the wall of the insulating film, the CVD tungsten 3 grows only upward and is adjacent via the element isolation region. The N-type drain diffusion layer region 23 remains separated. FIG. 2 (q) is a plan view of the final state.
Shown in

Next, as shown in FIG. 2 (r), after depositing an interlayer insulating film 26, a contact hole 27 is formed on the drain region. Finally, as shown in FIG. 1 (c), after filling the contact hole with an n-type doped polycrystalline silicon layer 28, an aluminum wiring 29 is formed.

FIG. 3 is a view for explaining a second embodiment of the present invention. Up to FIG. 2 (h), it is the same as the first embodiment. Here, the silicon substrate in the source region is also partially etched to form a shallow groove. However, care must be taken so that it does not become deeper than the oxide film surface in the element isolation region. Next, when the process is advanced in the same manner as in the first embodiment, FIG.
In the step corresponding to (a), the result is as shown in FIG.

Next, as shown in FIG. 3B, selective growth of CVD tungsten is performed. Then, the substrate surface of the drain region is higher than the substrate surface of the drain region.
Tungsten 50 projects more than tungsten 51 on the source region. Next, a flat interlayer insulating film 52 is formed using, for example, a silica coating film.

Next, as shown in FIG. 3C, the interlayer insulating film 52 is appropriately etched back to expose only the CVD tungsten on the drain region, and an aluminum wiring 53 is formed thereon. In this embodiment, the drain contact is
Since it is formed in a self-alignment manner with respect to D tungsten, it is not necessary to secure an overlapping margin between the drain contact and the CVD tungsten on the drain region, so that a more highly integrated cell array can be manufactured.

[Effects of the Invention] As described above, according to the present invention, a plurality of linear trench element isolation regions are formed, and a plurality of word lines are formed so as to be orthogonal to the plurality of trench element isolation regions. Then, the n-type impurity is introduced into the substrate in a self-aligned manner with respect to the word line, a sidewall of an insulating film is formed on the side wall of the word line, and then a conductive material is selectively grown on the exposed silicon substrate. By connecting adjacent n-type regions only through the element isolation region only on the source region side, the overlapping margin of the word line and the element isolation region, which was required in the past, becomes unnecessary, and a more highly integrated EPROM cell array Is obtained. Also, since the source side is connected with a low-resistance conductor material,
Even if the width of the source diffusion layer is reduced, the source resistance can be kept low, and there is an effect that the cell array can be highly integrated without deteriorating the write characteristics and read characteristics of the cell.

[Brief description of the drawings]

1 (a) to 1 (e) are a plan view and a sectional view of a cell array manufactured according to a first embodiment of the present invention, and FIG.
FIGS. 2A to 2R illustrate a first embodiment of the present invention, and FIGS. 2A to 2C illustrate a second embodiment of the present invention. 4 (a) to 4 (i) are views for explaining a conventional manufacturing method. 1,13 ... element isolation region, 2,23 ... n-type source diffusion layer, 3
... CVD tungsten, 4,22 N-type drain diffusion layer, 5,101 P-type semiconductor substrate, 6,102 first gate oxide film, 7,103 first polycrystalline silicon layer, 8,104 insulating film , 9,105 …… Polycrystalline silicon layer, 10,17,21,106,110…
... photoresist, 11 ... first line, 12,107 ... CV
D oxide film, 14,108 ... second gate insulating film, 15,109 ...
Second polycrystalline silicon layer, 16 second insulating film, 18
2nd line, 19 ... photoresist on 2nd line, 20,112 ... segment, 24 ... sidewall, 2
6, 52, 115 ... interlayer insulating film, 27, 116 ... contact hole, 29, 53, 117 ... aluminum wiring, 50 ... CVD tungsten on drain region, 51 ... CVD tungsten on source region, 111 ... polycrystalline silicon line (Word line), 118
... cell array.

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 27/115 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claims] 1. A plurality of first lines having at least two layers of a first insulating film and a first conductor layer on a semiconductor substrate of one conductivity type and extending in one direction are separated from each other. Forming a linear groove extending in one direction in the substrate between the first lines; forming an element isolation region by embedding an insulating material in the groove; A plurality of second lines insulated from the lines and separated from each other and formed of at least two layers of a second conductor layer and a second insulating film are formed on the first lines and the element isolation regions. Forming a plurality of floating gates from the first line by etching the first line in a self-aligned manner with respect to the second line; and forming a plurality of floating gates from the first line. Of the area between the two lines Removing part of the insulating material in the element isolation region of the region to be etched to expose a part of the side surface of the substrate in the region, and removing impurities of the opposite conductivity type to the substrate with respect to the second line. Forming a reverse conductivity type doped region on the substrate surface by introducing it in a self-aligned manner; depositing an insulating film on the entire surface and etching the insulating film to form the second
Forming a side wall of an insulating film on the side wall of the line; and selectively growing a conductive material only on a portion where the substrate is exposed. Connecting the doped regions adjacent to each other via an isolation region and preventing connection in a region to be a drain.