JP2829949B2 - Level conversion circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level conversion circuit used to convert a TTL logic signal level to a CML logic signal level. 2. Description of the Related Art As a peripheral circuit for a logic circuit for digital operation, a logic level of TTL (Transistor Transistor Logic) is set to CML (Current-Mode Logic) or ECL (Emitter C).
A level conversion circuit for converting the data into a logic level called “upled logic” is used. As shown in FIG. 2, a typical type of such a level conversion circuit is a level shift circuit, a current switch circuit, and a reference circuit disposed between an input terminal IN of a TTL signal and an output terminal OUT of a CML signal. It consists of a voltage generating circuit. That is, transistors Q11, Q12, Q13 and resistors R11, R
A current switch circuit is constituted by 12. The base terminal of transistor Q12 is connected to transistor Q14 and resistor R1.
3, the base terminal of the transistor Q11 is connected to the transistors Q15 and Q16,
It is connected to a level shift circuit composed of resistors R14, R15, R16, and R17. The above-described current switch circuit, level shift circuit, and reference voltage generation circuit minimize the AC coupling of the respective ground potentials so that the ground potential noise due to the input signal does not affect the output signal. ing. The base potential of the transistor Q12 is an intermediate potential between the TTL high level and low level (normally
It is adjusted to be equal to the base potential of the transistor Q11 in a state of about 1.5 volts. Therefore, if the input is normally at a high level of TTL of about 3.5 volts, the base potential of the transistor Q12 becomes lower than that of the transistor Q11 and becomes non-conductive.
Outputs CML high level of about lt. On the other hand, if the input is normally a low level of TTL of about 0 volt, the base potential of the transistor Q12 becomes higher than that of the transistor Q11 and becomes conductive, and the CM of about -0.5 volt is normally applied to the output terminal OUT.
Outputs low level of L. Problems to be Solved by the Invention In the above-described level conversion circuit, it is necessary to reduce power consumption as much as possible in order to achieve high integration, and for that purpose, it is necessary to reduce power supply voltage _VEE as much as possible. However, the power supply voltage V of the level conversion circuit of FIG.
_EE is subject to the following restrictions: | V _EE |> | V _BEQ14 + V _BEQ12 + V _CESATQ13 + V _R12 + (ground noise difference of ground system) | The value on the right side is typically | 0.8 + 0.8 + 0.4 + 0.25 + 0.5 | ≒ 2.75volt It can be estimated. After all, in the level conversion circuit of FIG. 2, the power supply voltage | V _EE |
Cannot be reduced to 2.75 volts or less. Means for Solving the Problems A level conversion circuit according to the present invention includes a pair of emitter terminals connected in common and connected to a first voltage terminal through a current circuit, and at least one of the pair of emitter terminals is connected to a second voltage terminal through a resistor. A current switch circuit including a pair of first and second transistors having a pair of collector terminals connected to the first and second voltage terminals and also connected to the output terminal, and connected in series between the first and second voltage terminals. A reference voltage generating circuit comprising two resistors connected to each other and having a first connection point connected to a base terminal of a second transistor of the current switch circuit, between the first and second voltage terminals; And two resistors whose second connection points are connected to the base terminal of the first transistor of the current switch circuit, and another resistor is connected to the second connection point through another resistor. Contact A level shift circuit comprising a third transistor having a continuous emitter terminal, a base terminal connected to the input terminal, and a collector terminal connected to the third voltage terminal; and a level shift circuit connected to the collector terminal of the first transistor. A diode having a cathode terminal and an anode terminal connected to the second connection point. Hereinafter, the operation of the present invention will be described in detail with examples. Embodiment FIG. 1 is a circuit diagram showing a configuration of a level conversion circuit according to an embodiment of the present invention. In this level conversion circuit, a current switch circuit, a reference voltage generation circuit, and a level shift circuit are formed between an input terminal IN of a TTL level signal and an output terminal OUT of a CML level signal. The current switch circuit includes transistors Q1, Q2, Q3 and resistors R1, R2. That is, the emitter terminal pair of the transistor pair Q1 and Q2 is connected in common, and is connected to the power supply terminal of the voltage _VEE via a constant current circuit configured by a series connection circuit of the transistor Q3 and the resistor R2. . The collector terminal of one transistor Q1 of the transistor pair is connected to the ground potential via the resistor R1, and is also connected to the output terminal OUT. The other Q of the transistor pair
The collector terminal of 2 is directly connected to the ground potential without passing through a resistor. The reference voltage generation circuit is composed of two resistors R3 and R4 connected in series between the ground potential and the power supply terminal. The divided voltage value appearing at the connection point between the two is connected to the transistor Q2 of the current switch circuit. Supply to base terminal. The level shift circuit includes a resistor supply R6, R7 connected in series between a ground potential and a power supply terminal, and a base connected to an emitter terminal and an input terminal IN connected to a connection point of these resistors via a resistor R5. And a transistor Q4 having a terminal. Resistors R5, R6, R7 of this level shift circuit
Is connected to the base terminal of the transistor Q1 of the current switch circuit. The base potential of the transistor Q1 of the current switch circuit is -0.25 vol when the voltage value on the input terminal IN is about 1.5 volt which is an intermediate value between the high level and the low level of TTL.
It is set to be about t. Further, the base potential of the transistor Q2 is also set to -0.25 volt by a reference voltage generating circuit composed of the resistors R3 and R4. Power supply voltage V supplied to the base terminal of transistor Q3
_CC is a voltage that determines the current of the current switch circuit,
This is set to a value such that the voltage value of the output terminal OUT becomes approximately -0.5 volt when the transistor Q2 is turned on. The diode D1 is for preventing the saturation of the transistor Q1 when a high level appears at the input terminal IN,
The diode D2 is for preventing the input voltage from becoming negative. When a TTL high level of about 3.5 volts appears on the input terminal IN, the base potential of the transistor Q1 changes to the level of the transistor Q2.
And the transistor Q2 becomes non-conductive. Accordingly, a high level of CML of about 0 volt is output on the output terminal OUT. On the other hand, when a low level of TTL of about 0 volt appears on the input terminal IN, the base potential of the transistor Q2 becomes higher than that of the transistor Q1, and the transistor Q2 conducts. Along with this, CML of about -0.5volt is placed on the output terminal OUT.
Is output at a low level. Thus, when the TTL high level appears on the input terminal IN, the CML high level is output on the output terminal OUT, and when the TTL low level appears on the input terminal IN, the output terminal OUT
The low level of CML is output to the
Level conversion to the L signal level is performed. In this level conversion circuit, the power supply voltage V _EE becomes | V _EE |> | V _R3 + V _BEQ2 + V _CESATQ3 + V _R2 |, and a typical value on the left side is | 0.25 + 0.8 + 0.4 + 0.25 | ≒ 1.7 volt Becomes Therefore, the lower limit of the power supply voltage | V _EE | is approximately 1.7 volt,
40% higher than that of the conventional level conversion circuit shown in FIG.
It is about low value. As a result, power consumption is reduced by almost 40%. As described above, the pair of transistors Q1 and Q
The case where the constant current circuit installed between the power supply voltage _VEE and the power supply voltage _VEE is constituted by a series connection circuit of the transistor Q3 and the resistor R2 is exemplified. However, the transistor Q3 is omitted and the resistor
Such a constant current circuit may be constituted only by R2. Further, although the configuration in which the collector terminal of the transistor Q1 is directly connected to the ground potential has been described as an example, a configuration in which this collector terminal is connected to the ground potential via a resistor may be employed. Effects of the Invention Since the level conversion circuit of the present invention has the above-described configuration, the power supply voltage is significantly reduced as compared with the conventional circuit, and a large reduction in power consumption and high integration are realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a configuration of a level conversion circuit according to an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a configuration of a conventional level conversion circuit. IN: TTL level signal input terminals, Q1, Q2, Q3: transistors forming a current switch circuit, R3, R4 ... resistors forming a reference voltage generating circuit, Q4, Q5, R6, R7 ... levels Transistor and resistor that constitute the shift circuit, OUT
…… CML level signal output terminal.

Claims (1)

(57) [Claims] A pair of emitter terminals commonly connected and connected to the first voltage terminal via a current circuit, and at least one of the collectors connected to the second voltage terminal via a resistor and also connected to the output terminal A first having a pair of terminals;
A current switch circuit including a second transistor pair; a first connection point connected in series between the first and second voltage terminals;
A reference voltage generating circuit comprising two resistors connected to a base terminal of the transistor of the current switch circuit; a second connection point connected in series between the first and second voltage terminals; First
Resistors connected to the base terminal of the transistor, an emitter terminal connected to the second connection point via another resistor, a base terminal connected to the input terminal, and a third voltage terminal A level shift circuit comprising a third transistor having a collector terminal connected to the first transistor; a cathode terminal connected to the collector terminal of the first transistor; and an anode terminal connected to the second connection point. A level conversion circuit comprising a diode.