JP2823361B2 - Semiconductor integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device.

[0002]

BACKGROUND OF THE INVENTION a data holding node N _D, and the data lines DL are precharged to a predetermined potential, the data line DL
Connected to the data holding node N _D and the data line DL, respectively.
OS transistor (hereinafter also referred to as transfer transistor)
A semiconductor integrated circuit device including a booster circuit connected to the gate of the NMOS transistor is well known. In this integrated circuit device, and the node N _D,
Data transfer to and from the data line DL is performed in the following procedure.

[0003] First, the node N the data of the _D data line DL
To output, when a high potential by the boosting circuit of the gate of the initial operation 0V and a transistor, the node N _D data lines DL transistor is turned on leads to an electrical. Data line D by the data in this way the node N _D
The potential of L changes from the precharge potential. Next, the sense amplifier is activated to amplify the level change of the data line and determine the data line to be high or low. In this state, node N
_This means that data has been output from _D to the data line DL.

[0004] Next, input the data to the node N _D through the data line DL. Keeping the gate of the transistor as it is a high potential, the node N _D data lines DL data for the node N _D since terminals are electrically connected by the transfer Toranjita becomes identical to the data lines DL. If the data is inverted data line DL, those from the node N _D in the previous transfer data identical to that output to the data line DL is transferred from the data line DL to the node N _D, data for one data line DL Conversely data is sent to the node N _D when inverting input circuit. At the end of the transfer operation, set the gate voltage to 0V
Turning off the transfer transistor to comprise a node N _D and the data line DL to electrically cut off, also the next data transfer to charge the data line DL to a predetermined potential.

A typical example of the transfer transistor described above is a DRAM memory cell transistor. This will be described below as an example. FIG. 5 shows a conventional semiconductor integrated circuit device. This semiconductor integrated circuit device is a DRAM, and has only two rows and one column of memory cells in order to simplify the description. The memory cell is composed of one transistor and one capacitor.
The transistor and the capacitor constituting each memory cell are referred to as MC0, CM0, and TM1, respectively.
1, CM1. The memory cell transistor TM0 has a gate connected to the word line WL0, and a source and a drain connected between the bit line BL0 and the capacitor CM0. Similarly, the gate of the memory cell transistor TM1 has the word line WL.
1, the source and the drain are connected between the bit line BBL0 and the capacitor CM1. Bit lines BL0, BBL
0 is connected to the sense amplifier SA, and the word lines WL0 and WL1 are connected to the output node WD of the word line boosting circuit WLDV via the decoder DC. Word line booster circuit WLDV
Is a positive power supply Vc
c, the other being the output node W of the word line booster circuit WLDV.
Type transistor T10 entered an active signal phi _A gate connected to D, the source, any ground one drain, in connecting the other to the output node WD of the word line boosting circuit WLDV gate a reset signal phi _R Transistor T20. Active signal phi _A is transmitted as inverters INV1 and delay circuit DLY, the output of the inverter INV1 is supplied to the unipolar phi _A 'boost capacitor CB1 via the inverter INV2. The other pole of the boosting capacitor CB1 is connected to the word line boosting circuit W
It is connected to the output node WD of the LDV.

The memory cell MC0 of the DRAM shown in FIG.
The operation up to the output of the data to the bit line via the transfer transistor TM0 will be described. Here, the memory cell MC
It is assumed that row data is stored in bit line B
It is assumed that L0 and BBL0 are precharged to half the level of the operating voltage Vcc. The general flow of the operation is as follows. First, the word line WL0 connected to the memory cell MC0 to be activated is changed from the ground level to the operating voltage Vcc level or higher. Then, the memory cell transistor TM0
Is conducted, the electric charge stored in the capacitor CM0 flows to the bit line BL0, and slightly lowers the potential of the bit line BL0.
When the slight potential change is amplified by the sense amplifier SA, the bit line BL0 becomes the ground level, and the cell data is read.

At the beginning of the reading operation, a potential higher than the Vcc level is generated by the word line booster circuit WLDV, and the decoder DC receives the address A and transmits the output WD of the word line booster circuit WLDV to the target word line WL0. It is. The reset signal phi _R to the row transistor T10 is turned on by an active signal phi _A to Vcc level, T20 is turned off, the output WD of the word line boosting circuit WLDV becomes the level of Vcc-Vt (period in FIG. 6 t1 reference). Here, Vt is the threshold value of the transistor T10. Active signal φ _A is supplied to boosting capacitor CB via delay circuit DLY and inverters INV1 and INV2.
1, and φ _A 'changes to high with a delay. Then, the output WD of the word line boosting circuit WLDV is boosted from the level charged in the period t2 in FIG. 6 to a high potential by the coupling of the capacitor CB1. In parallel with the operation, the decoder DC receives the address A and the word line WL
0 is selected, the output WD of the word line boosting circuit WLDV is transmitted to the word line, and the word line WL0 is at the boosted level Vb (see period t2 in FIG. 6).

When the level of word line WL0 exceeds the threshold value of memory cell transistor TM0, transistor TM
When 0 is turned on, the data stored in the capacitor CM0 flows to the bit line BL0, and the potential of the bit line BL0 slightly lowers from the precharge level Vcc / 2. Next, the sense amplifier SA is activated by setting the sense amplifier activation signal φ _SA to high, and the level change of the bit line BL0 is amplified to ground level (BBL0 is set to Vcc level). In this state, the cell data has been read out to the bit line (see period t3 in FIG. 6).

The gate of the cell transistor (word line WL
Since 0) is kept at a high potential, the potential of the bit line BL0 is written to the cell capacitor CM0 through the cell transistor. If the data on the bit line BL0 is not inverted, the data on the row is low, and if the data on the bit line BL0 is inverted on an input circuit, the data on the high is the cell capacitor CM0.
Is written to.

In the reset operation, the active signal φ
_{When A is set} to the ground level, the transistor T10 is turned off. In response to the active signal φ _A going low, φ _A ′ goes low with a delay, and the level of the word line WL0 and output WD drops to near Vcc due to the coupling of the capacitor CB1. At the same time when the reset signal phi _R high, the word line WL0, the level of the output node WD becomes the ground, the memory cell transistor TM0 is turned off and the bit line BL0, Serukyabashita CM0 is in a state of being electrically disconnected from each other ( (See period t4 in FIG. 6).

In the description here, the transfer transistor is NM
Although it is assumed that the transistor is an OS transistor, a case where the transistor is a PMOS transistor is naturally considered. However, NMOS
If a transistor is described as an example, the case of a PMOS transistor is self-evident, and a description thereof will be omitted. In the following text, only the NMOS transistor will be described as an example, but for the same reason, the present invention is not limited to being applied only to the transfer transistor using the NMOS transistor.

[0012]

A transfer transistor must transfer data as quickly as possible to a precharged data line. For this purpose, it is preferable that the boosted potential applied to the gate be as high as possible. However, this level must be suppressed to such an extent that the gate oxide film of the transistor is not destroyed.

Now, consider when a high voltage is applied to the gate oxide film of the transfer transistor, taking the DRAM shown in FIG. 5 as an example. When the word line WL0 reaches the boosted level Vb, cell data is output to the bit line BL0 (see period t2 in FIG. 6). At this time, the gate-source voltage Vgs of the cell transistor TM0 is Vgs = Vb-Vcc /
2. Even if the gate is boosted to a high potential, the potential applied to the transfer transistor is reduced by the precharge potential of the bit line. Subsequently, when the sense amplifier is activated to amplify the bit line level change (period t3 in FIG. 6), in the worst case, that is, when low data is being output, Vgs
= Vb-0, and the boosted level is applied between the gate and source of the transfer transistor as it is, and during this period the highest electric field is applied to the gate oxide film.

On the other hand, in the period t2 in FIG. 6, it is desirable to increase the conductance of the transfer transistor by raising the word line boosting level as high as possible, and to output cell data to the bit line at high speed. However, in the conventional semiconductor integrated circuit device, after the activation of the sense amplifier as described above,
Since a high potential difference is generated, the boosting level has to be suppressed. That is, the gate oxide film may be destroyed, and the transfer efficiency cannot be sufficiently increased.

According to the present invention, the transfer voltage is sufficiently increased before the activation of the sense amplifier, and the level thereof is decreased after the activation of the sense amplifier, so that the transfer efficiency is high and the gate oxide film is not destroyed. It is an object to provide a semiconductor integrated circuit device.

[0016]

A semiconductor integrated circuit device according to the present invention comprises a data holding node, a data line precharged to a predetermined potential, a MOS transistor having a source and a drain connected to a data line and a data holding node, respectively. Transistors and
Triggered by the activation of the sense amplifier, a sense amplifier that amplifies the data transferred to the data line via the MOS transistor, a booster circuit that applies a voltage equal to or higher than the drain voltage compared to the absolute value of the gate of the MOS transistor, and And means for reducing the absolute value of the gate voltage of the MOS transistor.

[0017]

According to the semiconductor integrated circuit device of the present invention configured as described above, the absolute value of the gate voltage of the MOS transistor is reduced by the activation of the sense amplifier. As a result, the transfer efficiency can be increased and the gate oxide film can be prevented from being destroyed.

[0018]

FIG. 1 shows a first embodiment of a semiconductor integrated circuit device according to the present invention. This semiconductor integrated circuit device is different from the semiconductor integrated circuit device shown in FIG. 5 in the structure of the word line boosting circuit WLDV, and further includes a step-down circuit DWN that lowers the voltage at the output node WD of the word line boosting circuit WLDV at the timing of activation of the sense amplifier. Is added.

The word line boosting circuit WLDV are connected in series between the conventional circuit and the same power source Vcc and the power supply Vss, shown in FIG. 5, the gates active signal .phi.A, NMOS transistors have entered the reset signal phi _R T1
A node WD having 0 and T20 and connecting T10 and T20 to each other is output. And the delay circuits DLY1,
_A signal φ obtained by delaying the active signal φA by DLY2
_A 'is formed and added to one pole of the boosting capacitor CB1. The other pole of the capacitor CB1 is connected to the output WD. The delay circuit DLY2 includes three stages of inverters INV1,
INV2 and INV3, and PMOS transistors T30 and NMOS connected in series between the power supply Vcc and the power supply Vss
It comprises transistors T31 and T32. Transistor T
The gate of 30 is the output node N2 of the inverter INV1.
The gates of the transistors T31 and T32 are connected to the output node N4 of the inverter INV3.

The step-down circuit DWN receives a sense amplifier activation signal φ _SA and the output node N2 of the inverter INV1 as inputs and outputs a NOR circuit NOR1 to the node N5, an inverter INV4 receiving an output of the NOR circuit NOR1, an power supply Vcc and a power supply Vss. PMOS transistor T40, NMOS transistors T41, T42 connected in series between
And The gates of the transistors T40 and T41 are connected to the output N6 of the inverter INV4, and the gate of the transistor T42 is connected to the output N1 of the delay circuit DLY1. Further, the output WD of the word line booster circuit WLDV
And transistor T40, step-down capacitor CB2 connected between the node phi _D which are connected to each other to T41,
The gate is connected to the node N2 as the source, and the drain as φ _A ′ -φ _D
An NMOS transistor T50 connected between the gate,
The drain power supply Vss, and a NMOS transistor T60 having a source connected to node phi _D.

The operation of the semiconductor integrated circuit device shown in FIG. 1 will be described below. When the active signal φ _A changes from the ground level to V
becomes cc level, the reset signal phi _R becomes the ground level, the transistor T10 is turned on, T20 is the output node WD off to the word line boosting circuit WLDV Vcc-
The battery is charged to the level of Vt (period t1 in FIG. 2). Here, Vt is the threshold value of the transistor T10. In parallel with the charging of the output node WD, delay signals φ _A ′ and φ _{D of} the active signal φ _A are generated. When the active signal phi _A goes high, node N1 becomes high along with a delay by the delay circuit DLY1. When the node N1 changes to high, the node N2 goes low by the inverter INV1. At this time, the transistors T30 and T42 are turned on and the transistors T30, T31, T32 and T4
0, T41, and T42 each form an inverter, and the transistor T50 is off. The NOR circuit NOR1 from the sense amplifier activation signal phi _SA not already high is equivalent to an inverter, the node N2 is almost the same time a high delay signal phi _D in varying the delay of the inverter 3 stages in a row. At this time, capacitors CB1 and CB
Since the voltage at one of the electrodes 2 changes from 0V to the Vcc level, the output WD of the word line boosting circuit WLDV is boosted to the Vb1 level by coupling. And the decoder DC
Receives the address A and selects the selected word line, eg, WL
The boost level is transmitted to 0 (period t2 in FIG. 2).

When the level of the word line WL0 becomes Vb1, the memory cell transistor TM0 turns on and the electric charge stored in the memory cell capacitor CM0 flows to the bit line BL0. If the data is LOW, the bit line BL
0 is slightly lower than the precharge level Vcc / 2. Subsequently, when the sense amplifier is activated by setting φ _SA high, the bit line BL0 is at the ground level, and the bit line BBL0 is at the V level.
cc level. Further, the output node N5 of the NOR circuit NOR1 becomes low, and the voltage drop signal φ
_D changes to low. In response, node WD is lowered from Vb1 to Vb2 by the coupling of capacitor CB2 (period t3 in FIG. 2). At this time, the level of Vb2 is set to be equal to or higher than the sum of Vcc (data high level) and the threshold value of transistor TM0, and bit line BL0
Is written in the cell capacitor CM0 through the cell transistor TM0.

Since the word line is maintained at the level of Vb2, the potential of bit line BL0 is
The data is written to the cell capacitor CM0 through M0.
If the data of the bit line BL0 is not inverted by a certain input circuit, low data is written, and if inverted, high data is written.

In the reset operation, the active signal φ
_{When A} goes low, the node N1 goes low with a delay by the delay circuit DLY1. In response, the node N2
Goes high, at which point the transistors T30, T42
Are both off, and the transistor T50 is on. Therefore node phi _D, which has been once wax is charged to a positive potential by the delay signal phi _A '. After the node N2 changes to high, the node N4 changes to high with a delay of two stages of the inverter, the transistor T32 turns on, the node φ _A 'goes low, and the node φ _D goes low.

The node φ _D once at 0V was charged by the transistor T50 because of coupling of the capacitor CB2 when discharging the node WD to 0V.
In order node phi _D is prevented from being a negative potential, the transistor T60 is connected for the same purpose also.

When node φ _A 'goes low, capacitor C
Node WD coupling of B1 decreases until near the Vcc level, the transistor T20 when high reset signal phi _R is node WD turned on, the word line WL0 is the ground level. When the word line WL0 goes low, the memory cell transistor TM0 is turned off, and the capacitor CM0 is electrically disconnected from the bit line BL0.

In the conventional semiconductor integrated circuit device, the boost level of the word line is one level of Vb. This level is such that the gate oxide film is not destroyed after the activation of the sense amplifier in consideration of the high electric field applied to the cell transistor. It was suppressed to. In the semiconductor integrated circuit device of this embodiment, the word line level is set to V before and after activation of the sense amplifier.
b1 and Vb2 were set separately for two levels. Thus, if the level of Vb2 is set to a level that does not destroy the gate oxide film, Vb1 can be set sufficiently high (Vb1> Vb: higher than the conventional level), so that the transfer efficiency can be improved without lowering the reliability.

Next, a second embodiment of the semiconductor integrated circuit device according to the present invention will be described with reference to FIGS. The semiconductor integrated circuit device of the second embodiment is obtained by adding the step-down circuit DWN2 of FIG. 3 to the conventional semiconductor integrated circuit device shown in FIG. This step-down circuit DWN2 is connected to a word line booster WL.
It is connected to the output node WD of the DV and receives the sense amplifier activation signal φ _SA as an input. Hereinafter, how this circuit lowers the gate voltage of the transfer transistor at the timing of the activation of the sense amplifier will be described.

The step-down circuit DWN2 has an NMOS transistor T70 having a source connected to the power supply Vcc and a gate and a drain both connected to the node Na, and a gate and a drain commonly connected like the T70 and connected in series between the node Na and the node WD. NMOS transistors T71, T72
have. The transistors T71 and T72 are connected to the output node WD
And a node Na, so that a current flows from the transistor T72 to the node Na, and the gate and the drain of the transistor T72 are connected to the node WD. Node Na, Node WD
There are NMOS transistors T73 and T74 connecting the source and the drain between them. The gate of the transistor T73 is connected to the power supply Vcc, and the gate of the transistor T74 is connected to the node Nb. One pole of the capacitor CD is connected to the node Nb, and a sense amplifier activation signal φ _SA is input to the other pole of the capacitor CD.
There are NMOS transistors T75 and T76 whose sources and drains are connected between the node Nb and the node WD.
The gate of the transistor T75 is connected to the node WD, and the gate of the transistor T76 is connected to Vcc.

Referring to the time chart of FIG.
The operation of N2 will be described. Here, for simplicity, the step-down circuit DW
It is assumed that the threshold values of the transistors constituting N2 are all the same value Vtn. First, after the period t1, the period t2
When the voltage of the node WD is boosted, the level thereof is
And the upper limit determined by the MOS diode connected in series between the node and the node WD, up to the level of Vcc + 3Vtn. Then, although the node Nb was at the same level of 0 V as the node WD by the operation initial transistor T76, the node Nb is charged to the level of Vcc + 2Vtn by the transistor T75 (period t2 in FIG. 4). Next, when the sense amplifier activation signal φ _SA is made high, the potential of the node Nb rises by about Vs (here, Vs >> Vtn) due to the coupling of the capacitor CD, and the transistor T7
4 turns on. Thus, a current path is formed between the power supply Vcc and the node WD through the transistors T70 and T74, and the node WD is discharged to the level of Vcc + Vtn (period t3 in FIG. 4).

At the end of the operation, as described in the semiconductor integrated circuit device of FIG.
When the voltage is lowered to V, the nodes Na and Nb become 0 V by the transistors T73 and T76, respectively, and prepare for the next operation (period t4 in FIG. 4). The transistors T73 and T76 are
That is, this is for setting the initial voltages of the nodes Na and Nb to 0V.

As described above, according to the second embodiment, the word line is set to the level of Vcc + Vtn after the activation of the sense amplifier to prevent a high electric field from being applied to the oxide film of the transfer transistor. The word line up to the activation was boosted to a high level of Vcc + 3Vtn to positively increase the conductance of the transfer transistor. Therefore, a semiconductor integrated circuit device which transfers data at high speed without reducing reliability can be realized.

[0033]

According to the present invention, the transfer efficiency can be increased by sufficiently increasing the gate voltage of the transfer transistor before activation of the sense amplifier and lowering the level after activation of the sense amplifier. Destruction of the gate oxide film can be prevented.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the first embodiment.

FIG. 3 is a block diagram showing a step-down circuit according to a second embodiment.

FIG. 4 is a time chart for explaining the operation of the second embodiment.

FIG. 5 is a block diagram showing a conventional semiconductor integrated circuit device.

FIG. 6 is a time chart illustrating the operation of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

WL0 word line WL1 word line MC0 memory cells MC1 memory cell BL0 bit line BBL0 bit lines CM1 cell capacitors CM1 cell capacitors CB1 boost capacitor CB2 boost capacitor CD boost capacitor T ₁₀ through T ₄₂ transistor

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hiroyuki Koinuma 580-1 Horikawa-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba Corporation Semiconductor System Technology Center (56) References JP-A-2-247892 (JP) , A) (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/40-11/409

Claims (1)

(57) [Claims] A data holding node; a data line precharged to a predetermined potential for transferring data; a data line for transferring data to the data holding node and receiving data from the data holding node; A MOS transistor having a source connected to a data line and a drain connected to the data holding node; amplifying the data transferred from the data holding node to the data line via the MOS transistor; A sense amplifier that holds the data line at the set potential, a boosting unit that sets the gate potential of the MOS transistor to a first boosted potential, and a gate potential of the MOS transistor at the timing of activation of the sense amplifier. A step-down means for changing the first boosted potential to the second boosted potential; The pressure potential is a potential at which the MOS transistor can transfer all of the amplified potentials of the data line to the data holding node, and the absolute value of the second boosted potential is the absolute value of the first boosted potential. A semiconductor integrated circuit device characterized by being smaller than a value.