JP2877641B2 - Semiconductor memory device and driving method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a driving method thereof. More specifically, a virtual ground array type semiconductor memory device having a structure in which the drain of each memory cell arranged in a matrix and the source of an adjacent memory cell are connected to form a bit line. The present invention relates to a semiconductor memory device that achieves low power consumption and prevents deterioration of a tunnel insulating film by using the method described above, and a driving method thereof.

[0002]

2. Description of the Related Art EEPROMs capable of electrically rewriting data and retaining data even without power are widely used. This EEPROM has a flash memory type in which hot electrons are injected into a floating gate, and a MONOS (metal-oxide film-nitride film-oxide film-semiconductor structure) in which electrons are injected into an insulating film by FN tunneling or direct tunneling. oxide ni
MNOS (metal nitride oxidesemico) of tride oxide semiconductor type or metal-nitride film-oxide film-semiconductor structure
nductor) type.

On the other hand, in order to reduce the size of elements, a flash memory type is arranged in an array, and the drains and sources of adjacent memory transistors are connected, and no contact is formed at both the drain and the source. A ground array type semiconductor memory device is described in, for example, a document “A Novel Memory Cell Using Flash Array Con- tact EPROM (FACE) technology”.
tactless EPROM (FACE) Technology) ", (IEDM, 1990, pp. 91-94) and" An asymmetry lightly-doped source (ALDS) cell for virtual ground high.
Density EPROMs (An Asymmetrical Lightly-D
oped Source (ALDS) Cell for Virtual Ground High Dens
ity EPROMs.) ”, (IEDM, IEDM, 19
1988, pp. 432-435).

FIG. 6 is a sectional explanatory view of one cell portion of a conventional virtual ground array type semiconductor memory device. FIG. 7 shows the driving method, (a) is an explanatory diagram of a writing method,
(B) is an explanatory view of the erasing method.

In the memory cell of the semiconductor memory device shown in FIG. 6, a semiconductor substrate 1 is provided with a source region 2, a drain region 3, and a channel region 4 interposed between the source region 2 and the drain region 3. Further, a tunnel insulating film 5, a floating gate 6, an interlayer insulating film 7, and a control gate 8 are sequentially provided on the channel region 4 by using a CVD method or the like.

For writing, a high potential Vpp of about 12 V is applied to the control gate 8 as shown in FIG.
To be applied to high potential V _d of about 6V electric current is carried out by injecting hot electrons into the floating gate 6.

[0007] the potential of the control gate 8 as erased FIG. 7 (b) and to 0V, and carried out by withdrawing from the floating gate 6 electrons FN current by applying a high potential V _s of about 12V to the source 2.

[0008]

As described above, in the conventional virtual ground array type semiconductor memory device, writing and reading are performed by using a flash type memory transistor using a floating gate. However, in a flash memory transistor, hot electrons are injected with high energy, so electrons and
The hole trap density increases, and the potential distribution in the oxide film changes with the increase in the hole trap density. As a result, the oxide film may be destroyed due to an increase in re-injection with positive feedback.

Also, since only a part of the drain current of hot electrons is injected into the floating gate, the writing efficiency is low and a large current consumption is required.

An object of the present invention is to provide a semiconductor memory device which solves such a problem, consumes less current, has less deterioration of a tunnel insulating film, and has improved reliability, and a driving method thereof.

[0011]

A semiconductor memory device according to the present invention comprises (a) a drain region, (b) a source region, and (c) provided between a drain region and a source region provided on a semiconductor substrate. And (b) sequentially provided on the surface of the semiconductor substrate on the channel region.
Tunnel insulating film, (e) floating gate, (f)
Memory cells each including an interlayer insulating film and a control gate are arranged in a matrix, and the drain region of one memory cell and the source region of an adjacent memory cell adjacent to the one memory cell are arranged in a matrix. a semiconductor memory device formed by interconnected or shared, said tunnel either side of the drain region side or the source region side of the insulating film is thick rather formed Rutotomoni other side of each memory cell
The tunnel of the one memory cell, which is formed thinly
One side of the drain region or the SO
Source region and the tunnel insulating film of the adjacent memory cell
Source or drain region on the other side
Are connected or shared with each other .

Each of the memories arranged in a matrix
The cell precedes the electrons of the semiconductor substrate by tunneling.
Injection into the floating gate
State, and the electrons of the floating gate are tunneled.
To the drain region or source region
The semiconductor memory device that is in a write state
For example, both writing and erasing should be performed only with FN current
Writing to only one memory cell
Can be done .

Further, in the driving method of the semiconductor memory device according to the present invention, (c) a memory is erased by applying a high potential to the semiconductor substrate to the control gate and injecting electrons from the channel region to the floating gate.
(D) A memory is written by applying a high potential to the control gate to the source region or the drain region on the side where the gate insulating film is not formed thick and extracting electrons from the floating gate. Things.

[0014]

According to the present invention, there is provided a virtual ground array type semiconductor memory device in which memory cells having floating gates are arranged in a matrix, and the drain of each memory cell is connected to the source of an adjacent memory cell. Since the tunnel insulating film on either the drain region side or the source region side is thickened, floating is applied to the cell on the thinner side of the insulating film due to the high potential applied to the bit line connecting the connection part of the source and the drain. Electrons move between the gate and the gate, but electrons do not move between the floating gate and the cells on the thicker side of the tunnel insulating film, so that only one cell can be selectively written.

Further, by forming a low impurity concentration region at least around the source region or the drain region on the thin side of the tunnel insulating film to form a double impurity region, a withstand voltage with respect to a substrate such as a junction leak or a breakdown is formed. Deterioration of characteristics can be prevented.

In the driving method, an erase state is obtained by injecting electrons into the floating gate, a write state is obtained by extracting electrons from the floating gate, and a write state is obtained by extracting electrons from the floating gate. In either case, the FN current, which is a current flowing based on the voltage applied to both ends, can be performed. Since the injection of hot electrons having high energy is not performed, there is no useless current, and the current consumption is reduced. Also, the deterioration of the tunnel insulating film is small.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor memory device according to the present invention will be described with reference to the drawings.

FIG. 1 is an explanatory view of a sectional structure of one cell portion of a semiconductor memory device of the present invention, FIG. 2 is a plan explanatory view showing one embodiment of a semiconductor memory device of the present invention, and FIG. 2 II
FIG. 4 is a view for explaining an erasing, writing, and reading method of the semiconductor memory device of the present invention. FIG. 4A is an erasing method, FIG. 4B is a writing method, and FIG. Illustration of,
FIG. 5 is an equivalent circuit diagram of a virtual ground array type semiconductor memory device in which memory transistors having floating gates are arranged in a matrix.

In FIGS. 1 to 3, a semiconductor substrate (for example, p-type) 1 has a high concentration region 2a, which is an n ⁺ region with a relatively high impurity concentration, and an n ⁻ region with a relatively low impurity concentration around it. A source region 2 of a double diffusion layer composed of a low concentration region 2b and a drain region 3 of a double diffusion layer composed of a high concentration region 3a of n ⁺ type and a low concentration region 3b of n ⁻ type. A channel region 4 is provided between them.

A tunnel insulating film 5 made of an oxide film, a nitride film, or the like is provided on a semiconductor substrate 1, and further, one of a drain region 3 side and a source region 2 side (in this embodiment, a source region 2 side). Thick oxide film 5a is formed on
The thickness t of the region is about two to three times the thickness of the thin tunnel insulating film portion. The thick oxide film 5a may be provided so as to cover the lower part of the floating gate in the source regions 2a and 2b formed of the double diffusion layer, and it is not necessary to make the entire upper part of the source region 2 thick. A floating gate 6 made of a first polysilicon layer, a silicon oxide film 7a, a silicon nitride film 7b, and a silicon oxide film 7c are formed on the tunnel insulating film.
An interlayer insulating film 7 having an ONO3 layer structure and a control gate 8 including a second polysilicon layer are provided.

As described above, the source region 2 of the tunnel insulating film
By providing the thick oxide film 5a on one of the side and the drain region 3, the extraction of electrons from the floating gate of the memory cell on the side of the thick oxide film 5a of the memory cells arranged in a matrix described later is prevented. Only the cells on the side of the thin tunnel insulating film 5 can be selectively written by extracting electrons.

In order to manufacture this semiconductor memory device, first, as shown in the plan view of FIG. 2, a field insulating film 10 is provided on the surface of the semiconductor substrate 1 by an oxidation method or the like, and then, for example, the cross section of FIG. 1 and FIG. As shown in the figure, a tunnel insulating film 5 made of, for example, a silicon oxide film is formed on the active region by an oxidation method or a CVD method at 60 to 150.degree.
0 mm). At this time, 200 ~ 400 全体
A thick oxide film (for example, about 300 °) is provided, and for example, etching is performed so that the thick oxide film 5a remains on the end of the source region 2 and the tunnel insulating film 5 on most of the channel region 4 is usually formed. About 50 to 150 mm.

Next, for example, the first polysilicon to be used as the floating gate 6 is formed by CVD, for example, for 10 minutes.
A three-layer insulating film of ONO consisting of silicon oxide, silicon nitride, and silicon oxide, which is deposited to a thickness of 00 to 2000 mm and is used as the interlayer insulating film 7, is similarly formed so that the total thickness becomes 200 to 300 mm.
It is deposited by a VD method or the like. Further, a second polysilicon layer serving as a control gate 8 is similarly provided with a thickness of 3000 to 4000 ° and then patterned to provide a floating gate 6, an interlayer insulating film 7, and a control gate 8 of each memory cell. At this time, patterning is performed so that a floating gate or the like overlaps a part of the thick oxide film 5a. After that, in order to form the low concentration regions 2b and 3b of the source region and the drain region, for example, phosphorus ions are implanted with a dose of 5E13 to 5E14 / cm ² and an energy of 100 to 150 keV by using the control gate 8 and the like as a mask. 1E18~1E19 / cm ³
Are the low concentration regions 2b and 3b. In this embodiment, in order to reduce the cell area, the source region 2 of one memory cell is used.
Becomes common with the drain region 3 of the memory cell on the left,
Although the drain region 3 of one memory cell is common to the source region 2 of the memory cell on the right, it may be formed separately. Next, arsenic ions or the like are implanted at a dose of 1E15 to 5E15 / cm ² with an implantation energy of 50 to 100 keV using the control gate 8 or the like as a mask, thereby forming a high concentration region 2a of each of the source region and the drain region. , 3a are each formed at an impurity concentration of about 1E20 / cm ³ . Further, a word line W connecting the control gates of the cells arranged in the horizontal direction and a bit line B ₁ connecting the source regions (drain regions) of the memory cells arranged in the vertical direction are formed by coating an insulating film made of silicon oxide or the like entirely. B ₂ (not shown in FIG. 3) is provided with a thickness of about 7000 ° using Al-Si or Al-Si-Cu or the like.

The reason why the interlayer insulating film between the floating gate 6 and the control gate 8 has a three-layer structure of ONO is to improve the insulating property. Is also good. In the above embodiment, the source region and the drain region use the double diffusion layers of the high-concentration region and the low-concentration region, respectively. However, the provision of the low-concentration region improves the breakdown voltage. Is preferred, but not required. Even when a low-concentration region is provided, only the region (drain region in the above embodiment) in which the thick oxide film 5a is not provided may be provided. This is because writing is performed on the non-thick side of the oxide film to improve the withstand voltage against a high voltage at the time of writing. Furthermore, while the low-concentration regions of the source and drain regions were implanted with phosphorus ions, and the high-concentration regions were implanted with arsenic ions, phosphorus impurities diffuse easily to the surroundings, and arsenic impurities hardly diffuse and maintain a high concentration. However, it is not necessarily limited. Furthermore, p
Although the example in which the n-type source and drain regions are provided on the type semiconductor substrate has been described, the conductivity types may be opposite to each other. Further, in the above embodiment, a thick oxide film is provided on the drain region side or the source region side. I just need.

Next, the driving method of the semiconductor memory device of the present invention will be described.

In a conventional flash memory having a floating gate, writing is performed by injecting hot electrons into the floating gate, and erasing is performed by extracting electrons. In the present invention, however, it is necessary to inject electrons into the floating gate. , And the electrons are drawn out of each cell to make the written state, whereby the movement of the electrons is performed by the FN current based on the voltage applied between the two electrodes.

First, the method of erasing the storage state is shown in FIG.
As shown in FIG. 3A, a voltage is applied such that the control gate 8 has a high potential Vpp with respect to the semiconductor substrate 1, and electrons are injected from the substrate into the floating gate 6. For example, 18 V is applied to the control gate 8, and the source region 2, the drain region 3 and the semiconductor substrate 1 are grounded (0
As a result, the FN current flows from the semiconductor substrate 1 to the control gate 8, and electrons are injected into the floating gate 6 through the tunnel insulating film 5. This erasing is performed collectively for each word line. Therefore, other word lines (control gates of the memory transistors in other rows) are set to 0V.

Next, write the electron in the floating gate to potential V _c of the control gate 8, by the potential of the drain region and V _d the V _d to higher potential than V _c as shown in FIG. 4 (b) Is drawn into the drain region to perform writing. At this time, electrons are tunneled only from the thin tunnel insulating film 5, and tunneling from the thick oxide film of the memory cell on the right which is connected or shared with the drain region is prevented, so that only desired cells can be written. For example, grounding the control gate 8 of the selected cell P _1, the drain region 3 performed by extracting electrons from the floating gate 6 by applying a voltage V _d to be the high potential of about 12V. At this time, the control gate 8 of the unselected cells (other cells in the row) to prevent the writing is applied to inhibit potential V _i of about 6V.

The application state of the potential at the time of writing is not limited to this example. For example, instead of grounding the control gate 8, a low potential of about 6V is applied to the drain region 3 by applying a negative potential of about -6V. It can also be applied. As a result, the potential difference between the drain region 3 and the substrate 1 is reduced, the leakage current is reduced, and the breakdown voltage is improved.

In FIG. 4C, assuming that the potential of the control gate 8 is V _c and the potential of the drain region is V _d ,
About 5V is applied as the potential V _c of the control gate,
The order of 1V is applied as a potential V _d of the drain region, by grounding the source region 2, since the threshold voltage is high in erase state where electrons are injected into the floating gate 6, the current between the source and the drain If the current does not flow and the electrons are drawn out to be in the written state, the threshold voltage becomes low and a current flows. Therefore, by determining whether a current flows or not, reading is performed to determine whether the current is “1” or “0”.

The cells of the memory transistors are arranged in a matrix as shown in FIG. 5, and the control gates of the cells in each row are connected to form word lines W ₁ , W ₂ }, and the source of the cells in each column is formed. (Drain) are connected to form bit lines B ₁ , B ₂ }, thereby forming a virtual ground array type semiconductor memory device.

The erasure of the selected cell P ₁ among the cells formed in a matrix of the semiconductor memory device, write, method of reading will be described.

First, regarding erasing, a high voltage (about 18 V) is applied to the word line W ₂ where the selected cell P ₁ exists, and 0 V or W is applied to the word lines W ₁ , W ₃ ... By applying a low voltage close to that, electrons are injected by FN tunneling and erased in word line units.

Next, when writing to the memory transistors of the cell P _1, and grounding the word lines W _2, the word line W ₁ of the other row, W ₃ ... To apply the inhibit voltage Vi (about 6V) . The drain side of the cell P ₁ high voltage to the bit line B ₃ of (a thick oxide film is side not formed) (about 12V)
, And the other bit lines B ₁ , B ₂ , B ₄ ... Are open. The substrate is set to 0V. Then, the transistor is the drain of the cell P ₁ becomes a high level to the control gate, and electrons are extracted to the drain side of the floating gate write is performed. On the other hand, other cells, it is forbidden in all the cells of different rows word line voltage Vi are applied, a low voltage between the drain, the write is not performed, on the same line as the cell P _1, cell P ₁ In the cell on the right, a high voltage of 12 V is applied to the source side with respect to the control gate,
As described above, since the insulating film having a thickness about three times the thickness of the tunnel insulating film is formed, electrons are not extracted from the floating gate. In the other cells in the other columns, the bit lines B ₁ , B ₂ , B _4, ... Are open, so that no current flows and no writing is performed. Thus, writing is not performed in the cell other than the cell P ₁ is, writing is performed only in the cell P _1.

As another example of writing, when the control gate (word line W ₂ ) is set to a negative potential (about −6 V), 6 V is applied to the bit line B ₃ and the other bit lines B By opening ₁ , B ₂ , B _4, ..., The word lines W ₁ , W ₃ ,. The source and substrate are also at 0V in this case.

For reading, for example, when reading the cell P _1, a voltage (about 5 V) lower than the high voltage at the time of writing is applied to the word line W ₂ and the bit line B
₂ to 0V, the about 1V is applied to the bit line B _3, as well as other bit lines B _1, B ₄ ... to open (open), the word line W ₁ of the other row, W ₃ ... and substrate 0V Can be read out. That is, only cell P ₁
The potential of the drain is about 1 V higher than the potential of the source, and a current can flow through this transistor. The transistor is turned on according to the voltage applied to the control gate and the threshold voltage due to the state of electrons injected into the floating gate. By turning off or turning off, the state of “1” or “0” can be read.

Table 1 summarizes these relationships.

[0038]

[Table 1]

[0039]

According to the present invention, since the source or drain side tunnel insulating film of the memory transistor having the floating gate is formed thick, the source and drain of the adjacent memory transistor are arranged in a matrix. In the virtual ground array type semiconductor memory device to be connected, electrons can be selectively extracted from the floating gates of adjacent cells. as a result,
Erasing is performed by injecting electrons into the floating gate, writing is performed by extracting electrons from the floating gate, and both writing and erasing can be performed by FN current. Also, since the FN current is used, the electron injection efficiency becomes almost 100%, there is no wasted current, low power consumption can be achieved, and battery replacement or charging can be significantly reduced even in a battery-powered personal computer or the like. Further, F
Since electrons are injected and extracted by N current and hot electrons having high energy are not injected, deterioration of the tunnel insulating film is small and the number of rewrites is greatly improved.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a cross-sectional structure of one cell portion of a semiconductor memory device of the present invention.

FIG. 2 is an explanatory plan view showing one embodiment of the semiconductor memory device of the present invention.

FIG. 3 is a sectional view taken along line III-III in FIG. 2;

4A and 4B are diagrams for explaining an erasing and writing method of the semiconductor memory device of the present invention, wherein FIG. 4A is an explanatory diagram of an erasing method, FIG. 4B is an explanatory diagram of a writing method, and FIG. FIG.

FIG. 5 is an equivalent circuit diagram of a semiconductor memory device in which memory transistors each having a floating gate are arranged in a matrix.

FIG. 6 is an explanatory sectional view of one cell portion of a conventional semiconductor memory device.

7 shows a driving method of the semiconductor memory device of FIG. 6,
(A) is an explanatory diagram of a writing method, and (b) is an explanatory diagram of an erasing method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Source region 3 Drain region 4 Channel region 5 Tunnel insulating film 5a Thick insulating film 6 Floating gate 7 Interlayer insulating film 8 Control gate

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/8247 G11C 16/04 H01L 27/115 H01L 29/788 H01L 29/792

Claims (3)

(57) [Claims] 1. A semiconductor device comprising: (a) a drain region, (b) a source region, and (c) a channel region sandwiched between the drain region and the source region, and (b) a channel region provided between the drain region and the source region. in said sequentially provided on a semiconductor substrate surface (d) a tunnel insulating film, (e) a floating gate, arranged memory cells in a matrix consisting of (f) an interlayer insulating film and (g) a control gate, one memory cell A semiconductor memory device in which the drain region and the source region of an adjacent memory cell adjacent to the one memory cell are mutually connected or shared, and the drain region of the tunnel insulating film of each memory cell is provided. When either side of the side or the source region side Ru is thick rather formed
In both cases, the other side is formed thin and the one memory cell
One side drain where the tunnel insulating film is formed thick
Region or source region and the transistor of the adjacent memory cell.
The source region or the other side where the channel insulating film is thinly formed
Is a semiconductor memory device in which the drain region is connected or shared with each other . 2. The memos arranged in a matrix.
Recell is a method of tunneling electrons from the semiconductor substrate.
By injecting it into the floating gate,
State, and the electrons of the floating gate are tunnelled.
Into the drain or source region by
2. The semiconductor according to claim 1, wherein the semiconductor device is brought into a writing state by performing
Storage device . 3. The semiconductor memory device according to claim 1, wherein (c) applying a high potential to the semiconductor substrate to the control gate and injecting electrons from the channel region to the floating gate to erase the storage; (D) A memory is written by applying a high potential to the control gate to the source region or the drain region on the side where the gate insulating film is not formed thick and extracting electrons from the floating gate. Driving method of semiconductor memory device.