JP2841380B2 - Heterojunction bipolar transistor - Google Patents

Description

The present invention relates to a high-speed semiconductor device.

(Prior art) Heterojunction bipolar transistors (HBTs) are attracting attention as next-generation ultra-high-speed devices due to their excellent high-speed performance and current drive capability.
The range of applications from microwave devices to optical integrated circuits is expanding. Conventionally, the mainstream of the HBT manufacturing process has been to process wafers on which all crystal layers have been epitaxially grown in advance using mainly mesa etching technology and ion implantation technology. Manufacturing processes using growth methods have also been realized.

It is known that the HBT has a collector top type in which the collector is located above the emitter, as opposed to a normal type in which the emitter is located above the collector. In the case of a normal HBT structure, the parasitic collector dose generated in the structure has a bad influence on the high frequency characteristics. FIG. 5 shows a conventional HB manufactured using the crystal regrowth method as a means for reducing the parasitic collector capacitance.
It is a figure showing a T structure. In this conventional example, a collector contact layer (n ⁺ -GaAs) 2, a collector layer (n ^- GaAs) 3, a high resistance layer (i-GaAs) 3i, and an external base layer (p ⁺ -) are formed on a semi-insulating substrate 1. The collector layer 3 is exposed in a predetermined region of the wafer on which GaAs) 4c has been sequentially grown, and then the base layer 4, the emitter layer 5, and the emitter contact layer 6 are regrown. After that, the external base layer 4c and the collector contact layer 6
Exposed emitter electrode 7e, base electrode 7b, collector electrode
By providing 7c, a high resistance layer is sandwiched between the base layer and the collector layer in the external transistor region, and an HBT with reduced parasitic collector capacitance is manufactured. In addition, 1 in the figure
Reference numeral 0 denotes an insulating film for minimizing injection of electrons into the external transistor region.

On the other hand, the collector-top type HBT does not have parasitic collector capacitance due to its structure without taking the above measures.
As shown in the drawing, in the external transistor region 12, if the injection of the minority carrier 11 from the emitter to the base (parasitic injection) is not suppressed, the current gain is significantly reduced. Therefore, a pn junction between semiconductors having a large band gap is formed at the emitter in the external transistor region 12 to increase the threshold voltage of the base-emitter diode in the external transistor region, and minority carriers are injected into the external transistor region. Kroemer has proposed a structure that is difficult to handle (1982 Proceedings of IEE, vol. 70, p. 30). FIG. 6 is a structural diagram of an HBT formed by a conventional crystal regrowth method having such a structure. An emitter contact layer (n ⁺ -GaAs) 6 and an emitter layer (n- Al _0.3 Ga _0.7 As) 5,
An emitter layer 5 is exposed in a predetermined area of a wafer on which an external base layer (p ⁺ -Al _0.3 Ga _0.7 As) 4c made of a material having a large forbidden band width is grown in the same manner as the emitter layer. Layer 3, Collector contact layer 2
To regrow. The p ⁺ -Al _0.3 Ga _0.7 As layer 4c has both functions of forming the Kroemer structure and extracting the base electrode. After the crystal regrowth step, the external base layer 4
c, the collector contact layer 2 is exposed and the emitter electrode 7e is exposed.
By providing the base electrode 7b and the collector electrode 7c, a base-emitter diode having a large threshold voltage is formed in the transistor region, and an HBT in which current gain deterioration is prevented is manufactured.

(Problems to be Solved by the Present Invention) However, according to the above-described HBT structure or manufacturing method, the portion where the base layer and the external base layer are in contact has a steep step shape, so that the base layer is regrown. In this case, there is a possibility that a step break occurs. In recent years, the base layer has been increasingly required to be a thin film in order to increase the speed of the HBT. However, when the base layer is relatively thin with respect to the depth of the above-mentioned step, step breakage is more likely to occur. In the above-described manufacturing method, a step of forming an emitter mesa (a collector mesa in the case of a collector top type) requires an exposure alignment step, so that a margin must be provided for the size of the mesa. As a result, the mesa becomes unnecessarily large, and there is no point in using advanced manufacturing techniques.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a highly reliable and fine HBT structure in producing a high-performance HBT utilizing the advantages of the crystal regrowth method.

(Means for Solving the Problems) According to the present invention, in a heterojunction bipolar transistor having a semiconductor layer on a semiconductor substrate serving as a collector, a base and an emitter, a mesa-shaped projection in which the collector layer is an intrinsic transistor region is formed. An external base layer or an external collector layer and an external base layer are formed on both sides of the mesa-shaped protrusion so that the surface is substantially flattened, and a part of the external base layer is included in the mesa of the collector layer. A hetero-junction bipolar transistor characterized in that a base layer and an emitter layer are sequentially formed in a mesa shape on a convex portion. Alternatively, the collector layer and the emitter layer are exchanged in the above configuration.

(Operation) In the hetero-junction transistor of the present invention, the external collector layer (or the external emitter layer) is embedded with a parasitic capacitance for deteriorating the intrinsic characteristics of the transistor to reduce the parasitic injection. Despite this, the crystal plane on which the base layer is grown is almost flat and there are almost no steps, so that the contact between the base layer and the external base layer is ensured, and high reliability and high reliability without disconnection of the base layer occur. A high performance heterojunction transistor is realized.

(Example) A manufacturing method of the present invention will be described with reference to FIGS. 1 (a) to 1 (f). First, on a semi-insulating substrate 1, n ⁺ GaAs is 200 nm thick as a collector contact layer 2 and n ⁻ G is formed as a collector layer 3.
aAs was sequentially grown to a thickness of 500 nm. Next, a thin film made of 500 nm of SiO ₂ was formed as a first protective film 81 in a predetermined region of the wafer (FIG. 1A). Using this SiO ₂ film as a mask, the collector layer 3 was etched by 500 nm (FIG. 1B). Then, a 400-mm-thick layer is formed as a high-resistance layer 3i by a metal organic chemical vapor deposition method (MOCVD method) on the etched portion.
The n-mi-GaAs layer is used as the external base layer 4C as a 100 nm-thick p ⁺
-Embed GaAs so that the semiconductor crystal plane becomes almost flat (FIG. 1 (c)). At this time, the thickness of the external base layer 4c is
The upper surface of the crystal layer is controlled to be substantially the same height as the upper surface of the collector layer 3 below the SiO ₂ film 81. Even if a step is formed, the upper surface of the crystal layer is kept within the thickness of the intrinsic base layer to be formed later. Make it fit. The thickness of the regrown crystal layer can be controlled by the crystal growth conditions and time. Next, an SiO ₂ film having a thickness of 200 nm was grown on the entire surface of the wafer as the second protective film 82, and a photoresist was applied and flattened as the third protective film 9. Thereafter, the photoresist 9 is etched by reactive ion etching (RIF) or the like until the second protective film is exposed (FIG. 1 (d)). Then the second expressed
The protective film 82 and the first protective film 81 are exposed by dry etching such as RIE or etching with diluted hydrofluoric acid to expose the semiconductor crystal plane (FIG. 1 (e)). The remaining third protective film 9 is cleaned and removed, and p ⁺ -GaAs is formed as a base layer 4 having a thickness of 100 nm in a region where the second protective film 82 is not formed.
-Al _0.3 Ga _0.7 As is re-grown into n ⁺ -GaAs 6 as an emitter contact layer 6 having a thickness of 100 nm (FIG. 1 (f)). FIG. 2 is a completed view showing the HBT manufactured in this manner, but the parasitic collector capacitance in the external transistor region is effectively reduced, and the thin base layer 4 is grown on a substantially flat crystal plane. Therefore, it can be seen that the base layer 4 and the external base layer 4c are in reasonable contact with each other.

FIG. 3 is a structural diagram showing a collector top type HBT manufactured by the same manufacturing method as described above. 150 nm layer thickness embedded in the external transistor region of the emitter layer 5 of 300 nm
The m p ⁺ -Al _0.3 Ga _0.7 As layer 4c functions to prevent electrons from being injected from the emitter layer 5 thereunder, draw out the base layer 4, and make contact with the base electrode 7b. Generally p ⁺
-Al _0.3 Ga _0.7 As makes it more difficult to make good ohmic contact with the electrode than p ⁺ -GaAs. Therefore, as shown in FIG. 4, a p ⁺ -GaAs layer 42c can be further grown on the p ⁺ -Al _0.3 Ga _0.7 As layer 41c as an external base layer.

In the above embodiment, SiO ₂ was used as the first and second protective films.
Although a photoresist was used as the third protective film, the effect of the present invention is not limited to this material. Not only GaAs / AlGaAs HBTs but also InP / InGaAs,
HB using various hetero junctions such as AlAs / InGaAs and Si / SiGe
The present invention is applicable to T.

(Effect of the Invention) Since the crystal growth of the base layer is performed on a flat crystal plane, the contact between the base layer 4 and the external base layer 4c in FIG. 1 is reasonable. At the same time, the base layer 4 and the external base layer
The contact area with 4c is determined by the thickness 14 of the side wall of the first protective film 81 formed when the second protective film 82 is formed. For this reason, the controllability of the contact area is good, and the region where the second crystal regrowth for forming the base layer and the emitter layer 5 (or the collector layer) (that is, the size of the mesa) is minimized. it can. In this case, a new exposure mask is unnecessary. Therefore, the present invention makes it possible to manufacture a high-performance HBT with high reliability utilizing the advantages of the crystal regrowth method with high reliability.

[Brief description of the drawings]

1 (a) to 1 (f) are views showing the steps of manufacturing a heterojunction bipolar transistor according to the present invention.
FIGS. 3 and 4 are views showing the structure of the heterojunction bipolar transistor of the present invention. 5 and 6 are views showing the structure of a heterojunction bipolar transistor manufactured by a conventional manufacturing method. FIG. 7 is a view showing a state in which a minority carrier (electron) is injected from the emitter to the base in the collector top type HBT. 1 ... Semi-insulating substrate, 2 ... Collector contact layer, 3
…… Collector layer, 3i …… High resistance layer, 4 …… Base layer, 4
c, 41c, 42c: external base layer, 5: emitter layer, 6
…… Emitter contact layer, 7e …… Emitter electrode, 7b…
... base electrode, 7c ... collector electrode, 81, 82 ... first and second protective films, 9 ... third protective film, 10 ... insulating film,
11 ... injected electrons, 12 ... external transistor area,
13: intrinsic transistor region; 14: sidewall thickness.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-62-271466 (JP, A) JP-A-62-271468 (JP, A) JP-A-62-104168 (JP, A) JP-A 63-271468 78571 (JP, A) JP-A-63-252475 (JP, A) JP-A-2-16739 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 29 / 68-29 / 737 H01L 21/31-21/33

Claims (2)

(57) [Claims] 1. A heterojunction bipolar transistor having a semiconductor layer serving as a collector, a base and an emitter on a semiconductor substrate, wherein the collector layer has a mesa-shaped protrusion serving as an intrinsic transistor region, and wherein the mesa-shaped protrusion is provided. An external base layer or an external collector layer and an external base layer are formed on both sides of the base layer so that the surface is substantially flat, and the base layer includes a part of the external base layer, on the convex portion of the mesa of the collector layer, A heterojunction bipolar transistor, wherein an emitter layer is sequentially formed, and a high-resistance semiconductor layer having a lower impurity concentration than a collector layer in an intrinsic transistor region is provided under the external base layer. 2. A heterojunction bipolar transistor having a semiconductor layer forming a collector, a base and an emitter on a semiconductor substrate, wherein the collector layer has a mesa-shaped protrusion serving as an intrinsic transistor region, and the mesa-shaped protrusion is provided. An external base layer or an external collector layer and an external base layer are formed on both sides of the base layer so that the surface is substantially flat, and the base layer includes a part of the external base layer, on the convex portion of the mesa of the collector layer, A heterojunction bipolar transistor, wherein a collector layer is formed in order, and the external base layer includes a semiconductor layer having a larger bandgap than the base layer in the intrinsic transistor region.