JP2696578B2 - Data processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a data processing device, and more particularly, to a data processing device which can reduce the time required for task switching by being incorporated in a task switching memory. Related to the device.

[Prior Art] With the recent increase in the operation speed of data processing devices, the speed of the main memory has been required to increase, and this has caused a problem that the realization cost of the memory system increases. As a technique for solving this problem, a technique is used in which a cache memory that is a high-speed memory is interposed between the data processing device and the main memory to make up the speed difference between the data processing device and the main memory. .

A proposal for realizing a high-speed cache memory by realizing the cache memory in the same integrated circuit as the data processing device is also disclosed in detail in, for example, Japanese Patent Application Laid-Open No. 63-193230.

However, simply shortening the memory access time on average by using a cache memory requires particularly high-speed operation such as task switching when a plurality of data processing processes are executed in a time-division manner. In such a case, a cache miss may occur, and as a result, the maximum value of the time required for task switching cannot be reduced.

In order to solve this problem, the memory for context saving at the time of task switching is defined separately from the normal memory space, and the memory used as the memory space for context saving is constituted by a high-speed memory, or Proposals have also been made to shorten the time required for task switching, for example, by realizing it in the same integrated circuit as the data processing device. Such a technique is disclosed in detail, for example, in JP-A-64-91253.

[Problems to be Solved by the Invention] However, even if a high-speed memory is used as a cache memory, high-speed memory access cannot be realized when a cache miss occurs. Also, even if a memory space different from the normal memory space is defined for context saving, the time required for task switching should be reduced unless the memory that configures the memory space can operate at higher speed than other memories. Can not.

The problem is that the cache memory is used to reduce the access time on average for all memory accesses. This is because it cannot be guaranteed reliably.

By the way, although a cache memory is a high-speed memory device, it is expensive, so that a single function alone cannot be used effectively for its cost. In particular, when the cache memory is built in the same integrated circuit as the data processing device, effective use of the expensive cache memory is desired.

Means for Solving the Problems A data processing apparatus according to the present invention has been made in view of the above circumstances, and has an instruction execution unit that executes an instruction in accordance with an output of the instruction decoding unit that decodes the instruction. An address decoder, a tag address memory for storing a tag address, and a data memory for storing data or an instruction code, a memory operating in the first mode or the second mode, and a first memory defining an operation mode of the memory A memory control information holding unit for holding a value or a second value; a bus connected between the instruction execution unit and the memory for transferring data or an instruction code; and an address generated by support from the instruction execution unit An address generation unit for outputting to the memory, and when the memory control information holding unit holds the first value, the address generation unit outputs the first value. Means for comparing the received address with a tag address stored in the tag address memory, and outputting a corresponding data or instruction code from the data memory to the bus when the address matches one of the addresses, and the memory control information holding means Is the second
Is held, the address output by the address generator is compared with the address allocated to the memory as a part of the memory space accessible by the instruction, and when the address is within the range of the address. Means for outputting the corresponding data or instruction code from the data memory to the bus.

The memory space is a memory space used by a system program. It is also a memory space used for instructions to save context.

[Action]

In the data processing device of the present invention, when the memory control information holding unit holds the first value, the memory stores at least an instruction code to be decoded by the instruction decoding unit or an operand of an instruction to be executed by the instruction execution unit. It operates as a cache memory that holds one of the data, compares the address output by the address generation unit with the tag address stored in the tag address memory, and, when the address matches one of them (at the time of a cache hit), The corresponding data or instruction code is output from the memory to the bus. In the case of data, it is supplied to the instruction execution unit, and in the case of the instruction code, it is supplied to the instruction fetch unit.

On the other hand, when the memory control information holding unit holds the second value, the memory becomes at least one of the instruction code to be decoded by the instruction decoding unit or the operand of the instruction to be executed by the instruction execution unit. It operates as a random access memory in which an address is allocated as a part of a memory space that holds data and is accessible by an instruction, compares an address output from an address generation unit with an address allocated to the memory, , The corresponding data or instruction code is output from the data memory to the bus.

Hereinafter, the present invention will be described in detail with reference to the drawings showing the embodiments.

(1) “Configuration of system using data processing device of the present invention” FIG. 6 shows a configuration example of a system using the data processing device of the present invention.

In this configuration example, the data processing device 100, the instruction cache 106, the data caches 107 and 108, the main memory 109 of the present invention
Are connected by an address bus 101, a data bus 102, an instruction bus 103, a memory address bus 104, and a memory data bus 105.

The address bus 101 inputs an address output from the data processing device 100 of the present invention to the instruction cache 106 and the data caches 107 and 108. The instruction bus 103 transfers the instruction code output from the instruction cache 106 to the data processing device 100 of the present invention. The data bus 102 stores data output from the data processing device 100 of the present invention in the data cache 10.
7, and the data output from the data caches 107 and 108 is transferred to the data processing device 100 of the present invention. The memory address bus 104 transfers an address output from the instruction cache 106 or the data caches 107 and 108 to the main memory 109. The memory data bus 105 includes the main memory 109 and the instruction cache 106 or the data cache 10
Transfer instructions or data between 7,108.

When the instruction cache 106 and the data caches 107, 108 miss, the respective caches 106 or 107 arbitrate the bus right between the memory address bus 104 and the memory data bus 105 to access the main memory 109.

The data caches 107 and 108 are the data processing device 1 of the present invention.
On the 00 side, the two chips work together to couple to a 64-bit bus. The data cache 107 stores the upper 32 bits of the 64 bits of each data,
The data cache 108 shares the lower 32 bits of data.

Hereinafter, an instruction system and a processing mechanism of the data processing device 100 of the present invention will be described first, and then a task switch processing method using the built-in control space memory will be described.

(2) "Instruction format of data processing device of the present invention" The instruction of the data processing device of the present invention has a variable length in 16-bit units, and there is no odd byte length instruction.

The data processing apparatus of the present invention has a specially designed instruction format system in order to convert frequently used instructions into a short format. For example, for a two-operand instruction, only a general format having a configuration of "4 bytes + extension part" and all addressing modes can be used, and only a high-frequency instruction and an addressing mode can be used. And two short formats.

The meanings of the symbols appearing in the instruction format of the data processor of the present invention shown in FIGS. 9 to 13 are as follows.

−: Part where the operation code is entered Ea: Part where the operand is specified in the general addressing mode of 8 bits Sh: Part where the operand is specified in the short addressing mode of 6 bits Rn: The operand in the register file is a register As shown in FIG. 9, the partial format specified by the number has the LSB side on the right side and a high address.

The instruction format cannot be determined without looking at the two bytes of address N and address N + 1.
This is because it is assumed that instructions are always fetched and decoded in 16-bit (halfword) units.

Regardless of the format of the instruction of the data processing apparatus of the present invention, the extension of Ea or Sh of each operand is always placed immediately after 16 bits (half word) including the basic part of Ea or Sh. This overrides immediate data implicitly specified by the instruction and the extension of the instruction. Therefore, in the case of an instruction of 4 bytes or more, the operation code of the instruction may be divided by the extension of Ea.

Further, as described later, even when an extension is further added to the extension of Ea in the multistage indirect mode, that extension has priority over the next instruction opcode.

For example, consider the case of a 6-byte instruction that includes Ea1 in the first halfword, Ea2 in the second halfword, and extends to the third halfword. Since the multi-stage indirect mode is used for Ea1, an extension in the multi-stage indirect mode is added in addition to the normal extension. At this time, the actual instruction bit pattern includes the first halfword of the instruction (including the basic part of Ea1), the extended part of Ea1, the multistage indirect mode extended part of Ea1, and the second halfword of the instruction (the basic part of Ea2). ), The extension of Ea2, and the third halfword of the instruction.

(2.1) “Short-form two-operand instruction” FIG. 10 is a schematic diagram showing a short-form format of a two-operand instruction.

This format includes an L-format in which the source operand is a memory and an S-format in which the destination operand is a memory.

In the L-format, Sh indicates a source operand specification field, Rn indicates a destination operand register specification field, and RR indicates a Sh operand size specification.

The size of the destination operand placed in the register is fixed at 32 bits. Sign extension is performed when the size of the register side is different from that of the memory side and the size of the source side is small.

In the S-format, Sh indicates a destination operand specification field, Rn indicates a source operand register specification field, and RR indicates a Sh operand size specification.

The size of the source operand placed in the register is 32
Bits have been fixed. If the size of the register side is different from the size of the memory side and the size of the source side is large, the overflow portion is truncated and an overflow check is performed.

(2.2) "General form one-operand instruction" Figure 11 shows the general form of a one-operand instruction (G1
-format).

MM is an operand size specification field. Some G1-format instructions have an extension in addition to the extension of Ea. In some cases, MM is not used.

(2.3) "In the case of general-type two-operand" FIG. 12 is a schematic diagram showing a general-type format of a two-operand instruction.

This format includes a maximum of 2 operands in the general addressing mode specified by 8 bits.
There are two existing instructions. The total number of operands itself may be three or more.

EaM is the destination operand specification field, MM is the destination operand size specification field, EaR is the source operand specification field, RR
Indicates a source operand size specification field.

Some G-format instructions have an extension in addition to the EaM and EaR extensions.

FIG. 13 is a schematic diagram showing the format of a short branch instruction.

cccc indicates a branch condition specification field, and disp: 8 indicates a displacement specification field with respect to a jump destination.

In the data processing apparatus of the present invention, when a displacement is designated by 8 bits, the designated value in the bit pattern is doubled to obtain a displacement value.

(2.4) "Addressing mode" The addressing mode of the instruction of the data processing device of the present invention is classified into a short form in which the instruction is specified by 6 bits including a register, and a general form in which the instruction is specified by 8 bits.

If an undefined addressing mode is specified, or if a semantically apparently unreasonable combination of addressing modes is specified, a reserved instruction exception is generated as in the case of executing an undefined instruction, Exception processing is started.

This corresponds to a case where the destination is the immediate mode, a case where the immediate mode is used in the addressing mode designation field to be accompanied by the address calculation, and the like.

The meanings of the symbols used in the schematic diagrams of the formats shown in FIGS. 14 to 24 are as follows.

Rn: Register specification (Sh): Specification method in 6-bit compact addressing mode (Ea): Specification method in 8-bit general addressing mode In the schematic diagram showing the format, the part enclosed by a dotted line is the extension part. Is shown.

(2.4.1) “Basic Addressing Mode” The instructions of the data processing device of the present invention support various addressing modes. Among them, the basic addressing modes supported by the data processing device of the present invention include:
Register direct mode, register indirect mode, register relative indirect mode, immediate mode, absolute mode, PC relative indirect mode, stack pop mode, and stack push mode.

In the register direct mode, the contents of the register are used as operands as they are. FIG. 14 shows a schematic diagram of the format. In the figure, Rn indicates the number of a general-purpose register or an FPU register.

In the register indirect mode, the contents of a memory having the contents of a general-purpose register as an address are used as operands. A schematic diagram of the format is shown in FIG. In the figure, Rn indicates the number of a general-purpose register.

The register relative indirect mode is classified into two types depending on whether the displacement value is 16 bits or 32 bits. Each operand is the contents of a memory whose address is a value obtained by adding a 16-bit or 32-bit displacement value to the contents of a general-purpose register. A schematic diagram of the format is shown in FIG. In the figure, Rn indicates the number of a general-purpose register. disp: 16 and disp: 32 indicate a 16-bit displacement value and a 32-bit displacement value, respectively. Displacement values are treated as signed.

In the immediate mode, the bit pattern specified in the instruction code is regarded as a binary number and used as an operand. A schematic diagram of the format is shown in FIG. In the figure, imm_data indicates an immediate value, and its size is specified in the instruction as an operand size.

Absolute mode indicates whether the address value is represented by 16 bits or 32 bits.
It is divided into two types depending on whether it is indicated by a bit. The contents of the memory whose address is a 16-bit or 32-bit bit pattern specified in the instruction code are used as operands. A schematic diagram of the format is shown in FIG. In the figure,
abs: 16 and abs: 32 indicate 16-bit and 32-bit address values, respectively. If the address is indicated by abs: 16, the specified address value is sign-extended to 32 bits.

The PC relative indirect mode is divided into two types depending on whether the displacement value is 16 bits or 32 bits. Operands are the contents of a memory whose address is a value obtained by adding a 16-bit or 32-bit displacement value to the contents of the program counter. A schematic diagram of the format is shown in FIG. In the figure, disp: 16 and disp: 32 are each 16
The bit displacement value and the 32-bit displacement value are shown. Displacement values are treated as signed. The value of the program counter referred to in the PC relative indirect mode is the start address of the instruction including the operand. Also when the value of the program counter is referred to in the multi-stage indirect addressing mode, the head address of the instruction is similarly used as the reference value relative to the PC.

In the stack pop mode, the contents of a memory having the contents of the SP (stack pointer) as an address are used as operands. After the operand access, the SP is incremented by the operand size. For example, when handling 32-bit data, SP is updated by +4 after operand access.
It is also possible to specify the stack pop mode for operands of 8, 16, and 64 bits, and the SP is +1 and +
Updated by 2, + 8. A schematic diagram of the format is shown in FIG. If the stack pop mode has no meaning for the operand, a reserved instruction exception is generated. The reserved instruction exception is specifically the stack pop mode specification for the write operand and the read-modify-write operand.

In the stack push mode, the contents of the memory whose address is the contents of the contents of the SP decremented by the operand size are used as the operands. In the stack push mode, SP is decremented before operand access. For example, when handling 32-bit data, SP is updated by -4 before operand access. It is also possible to specify the stack push mode for operands of 8, 16 and 64 bits, and the SP is updated by -1, -2 and -8, respectively. FIG. 21 shows a schematic diagram of the format. For those in which the stack push mode has no meaning for the operand, the reserved instruction exception in which the reserved instruction exception occurs is specifically the read operand and the read-modify-
This is the stack push mode specification for the write operand.

(2.4.2) "Multi-stage indirect addressing mode" Complex addressing can be basically decomposed into a combination of addition and indirect reference. Therefore, if the addition and indirect reference operations are given as addressing primitives and can be arbitrarily combined, any complicated addressing mode can be realized. The multi-stage indirect addressing mode of the instruction of the data processing device of the present invention is an addressing mode based on such a concept. The complex addressing mode is particularly useful for data reference between modules and an AI language processor.

When the multi-stage indirect addressing mode is specified, the basic addressing mode specification field specifies one of three types of specifying methods: a register-based multi-stage indirect mode, a PC-based multi-stage indirect mode, and an absolute-based multi-stage indirect mode.

The register-based multistage indirect mode is an addressing mode in which the base value of multistage indirect addressing for expanding the value of a general-purpose register is used. The schematic diagram of the format
See Figure 22. In the figure, Rn indicates the number of a general-purpose register.

The PC-based multi-stage indirect mode is an addressing mode in which the base value of the multi-stage indirect addressing that extends the value of the program counter is used. The schematic diagram of the format
See Figure 23.

The absolute-based multistage indirect mode is an addressing mode in which the base value of the multistage indirect addressing that extends zero is used. FIG. 24 shows a schematic diagram of the format.

The extended multistage indirect mode designation field has a unit of 16 bits, and this is repeated arbitrarily. Addition of displacement,
Index register scaling (× 1, × 2, × 4, ×
8) is added, and the memory is indirectly referenced. FIG. 25 shows a schematic diagram of the format of the multistage indirect mode. Each field in the figure has the following meaning.

E = 0: Continue multi-stage indirect mode E = 1: End address calculation tmp ==> address of operand I = 0: No memory indirect reference tmp + disp + Rx * Scale ==> tmp I = 1: With memory indirect reference mem [tmp + disp + Rx * Scale ] ==> tmp M = 0: <Rx> is used as the in-desk M = 1: Special in-desk <Rx> = 0 Do not add the in-desk value (Rx = 0) <Rx> = 1 Index the program counter Used as a value (Rx = PC) <Rx> = 2 to reserved D = 0: The value of the 4-bit field d4 in the multistage indirect mode is multiplied by 4 to obtain a displacement value, which is added. d4 is treated as signed and always used by 4 regardless of the size of the operand. D = 1: dispx (16/32) specified in the extension of the multistage indirect mode
Bit) as a displacement value and add it. The size of the extension is specified in the d4 field. D4 = 0001 dispx is 16 bits d4 = 0010 dispx32 bits XX: Scale of in-desk (scal = 1/2/4/8) x2, x4, When the scaling of × 8 is performed, an undefined value is entered as an intermediate value (tmp) after the processing of the stage is completed.

The effective address obtained by the multistage indirect mode has an unpredictable value, but no exception occurs. Do not specify scaling for the program counter.

Variations of the instruction format in the multistage indirect mode are shown in the schematic diagrams of FIGS. 26 and 27.

FIG. 26 shows a variation of whether the multi-stage indirect mode continues or ends. FIG. 27 shows variations in displacement size.

If a multi-stage indirect mode with an arbitrary number of stages can be used, it is not necessary to divide the number of stages in the compiler, so that there is an advantage that the load on the compiler is reduced. This is because even if the frequency of multi-stage indirect references is extremely low, the compiler must always be able to generate correct code. For this reason, any number of stages is possible on the format.

(3) “Memory space and context switch” The data processing device 100 of the present invention includes a logical space, which is a memory space for storing programs and data, and a memory space for storing various registers and data operated by some instructions. , And two memory spaces.

The logical space of the data processing device 100 of the present invention is the same as the memory space for storing programs and data in a conventional data processing device.

The control space of the data processing device 100 of the present invention can write and read data by a control space operation instruction, and stores data in a register area where various registers are mapped by byte addresses. Data area. Note that the data area of the control space can be accessed by a context operation instruction.

A technique for supporting a logical section and a control space in a manner similar to that of the data processing apparatus of the present invention to hold a context in the control space is disclosed in detail, for example, in Japanese Patent Application Laid-Open No. 64-91253.

(3.1) “Context block format” FIG. 30 is a schematic diagram showing a format of a context block operated by an LDCTX instruction and an STCTX instruction which are context switching instructions of the data processing device of the present invention.

The context block is composed of a floating-point register 12, general-purpose registers 10, 11 and the like, and the start address is held in a CTXBB register whose configuration is shown in the schematic diagram of FIG.

The format of the context block operated by the LDCTX instruction and the STCTX instruction is specified by the CSW register whose configuration is shown in the schematic diagram of FIG.

FR bit 13 and RG bit 15 of CSW register are both "1"
, The context block has the format shown in FIG.

If FR bit 13 is “0” and RG bit 14 is “1”,
The floating point register 12 shown in FIG. 30 is not operated by the LDCTX instruction and the STCTX instruction.

If both FR bit 13 and RG bit 14 are “0”,
The floating-point register 12 and the general-purpose registers 10 and 11 shown in FIG. 30 are not operated by the LDCTX instruction and the STCTX instruction. In this case, the CSW register, the four stack pointers SPI (SP0, SP1, SP2, SP3), and the UATB register indicating the address conversion table base are to be operated.

The structure of the UATB register is shown in the schematic diagram of FIG.

(3.2) “Context operation instruction” The bit pattern of the LDCTX instruction is shown in the schematic diagram of FIG.

The CTXBADR field 16 of the LDCTX instruction is a field for designating the start address of the context block to be loaded in the 8-bit general addressing mode.

The X bit 15 is a bit indicating whether the context block to be loaded is in the logical space or the control space. When the X bit 15 is "0", the context block is in the logical space, and when the X bit 15 is "1", the context block is in the control space.

When the LDCTX instruction is executed, the address specified in the CTXBADR field 16 is loaded into the CTXBB register,
The operation target context block at the address specified by the CTXBADR16 field in the space specified by the X bit 15 and having the format specified by the leading CSW value is loaded into the corresponding register.

 The bit pattern of the STCTX instruction is shown in the schematic diagram of FIG.

X bit 17 of the STCTX instruction specifies the space in which to store the context block. X bit 1 of this STCTX instruction
If 7 is "0", it is designated to store the context block in the logical space, and if X bit 17 is "1", it is designated to store the context block in the control space. The memory address to be stored is specified by the CTXBB register.

When the STCTX instruction is executed, the contents of the register included in the context block in the format specified by the CSW register are saved at the address specified by the CTXBB register in the space specified by the X bit 17.

(4) “Configuration of Functional Block of Data Processing Device of the Present Invention” FIG. 4 is a block diagram showing a configuration example of the data processing device of the present invention.

Functionally dividing the inside of the data processing apparatus of the present invention roughly, an instruction input unit 110, an instruction fetch unit 111, an instruction decode unit 112, a first micro ROM unit 113, a second micro ROM unit 114, an operand address calculation unit 115 , PC calculation unit 116, integer operation unit 11
7, a floating point operation unit 118, an address input / output unit 119, an operand access unit 120, and a data input / output unit 121.

The address input / output unit 119 is connected to the address bus 101, the data input / output unit 121 is connected to the data bus 102, and the instruction input unit is connected.
By connecting 110 to the instruction bus 103, the system configuration shown in FIG. 6 can be obtained.

(4.1) “Instruction Input Unit” The instruction input unit 110 inputs an instruction code to the data processing device from the external instruction bus 103 every 32 bits.

The access method of the instruction cache 106 includes a standard access mode in which a 32-bit instruction code is accessed for one address, and 32 consecutive accesses for one address.
There is a quad access mode for accessing a bit instruction code. In each case, the instruction code input to the instruction input unit 110 is output to the instruction fetch unit 111.

(4.2) "Instruction Fetch Unit" The instruction fetch unit 111 includes an address conversion mechanism for instruction addresses, a built-in instruction cache, a TLB for instructions, an instruction queue, and a control unit for them.

The instruction fetch unit 111 stores the PC of the instruction to be fetched next.
The value is converted to a physical address, an instruction code is fetched from the internal instruction cache, and output to the instruction decode unit 112. If the built-in instruction cache misses, it outputs a physical address to the address input / output unit 119, requests external instruction access, and registers the instruction code input through the instruction input unit 110 in the built-in instruction cache.

The PC value of the next instruction to be fetched is calculated by a dedicated counter as the PC value of the instruction to be input to the instruction queue. When a jump occurs, the PC value of the new instruction is stored in the operand address calculation unit 115, the PC calculation unit 116, or the integer operation unit 1
Transferred from 17.

The control circuit inside the instruction fetch unit 111 also performs address conversion by pacing and updating of the instruction TLB when the instruction TLB misses.

When the data processing device of the present invention is in the bus watch mode, the entry of the internal instruction cache in which the physical address input through the address input / output unit 119 hits is invalidated.

(4.3) “Instruction Decoding Unit” The instruction decoding unit 112 basically decodes an instruction code in units of 16 bits (half word).

This block includes an FHW decoder for decoding the operation code included in the first halfword, an NFHW decoder for decoding the operation code included in the second and third halfwords, and an addressing mode decoder for decoding the addressing mode.

Furthermore, a second decoder for further calculating the entry address of the micro ROM by further decoding the outputs of the FHW decoder and the NFHW decoder, a branch prediction mechanism for predicting a branch of a conditional branch instruction, and checking for a pipeline conflict in calculating an operand address. An address calculation conflict check mechanism is also included.

The instruction decode unit 112 decodes the instruction code output from the instruction fetch unit 111 from 0 to 6 bytes per clock. Of the decoding result, information about the operation in the integer operation unit 117 is sent to the first micro ROM unit 113, and information about the operation in the floating point operation unit 118 is sent to the second micro ROM unit 114.
The information related to the operand address calculation is output to the operand address calculation unit 115, and the information related to the PC calculation is output to the PC calculation unit 116.

(4.4) "First Micro ROM Unit" The first micro ROM unit 113 includes a micro ROM, a micro sequencer, a micro instruction decoder, etc. in which various micro program routines for controlling the integer operation unit 117 are stored. .

The micro instruction is read from the micro ROM once per clock. The micro-sequencer is not only the sequence processing for micro program execution related to instruction execution, but also exceptions, interrupts, and traps (these three are collectively referred to as EIT)
And performs microprogram sequence processing corresponding to each EIT.

The first micro ROM unit 113 also receives an external interrupt that does not depend on the instruction code and a branch condition of the micro program based on the result of executing the integer operation.

The output of the microdecoder is mainly output to the integer operation unit 117, but also outputs some information to other functional blocks when a jump instruction is executed and when an exception is accepted.

(4.5) "Second Micro ROM Unit" The second micro ROM unit 114 includes a micro ROM, a micro sequencer, a micro instruction decoder, and the like in which various micro program routines for controlling the floating point arithmetic unit 118 are stored. .

The micro instruction is read from the micro ROM once per clock. The micro-sequencer also performs exception processing related to floating-point operations in addition to the sequence processing indicated by the micro-program. If an unmasked floating-point exception is detected, the micro-sequencer sends the exception processing to the first micro-ROM unit 113. Request. The micro-sequencer of the second micro-ROM unit 114 operates in parallel with the micro-sequencer of the first micro-ROM unit 113, and controls the floating-point operation unit 118 in parallel with the integer operation unit 117.

The flag information based on the result of the execution of the floating point operation is also input to the second micro ROM unit 113.

The output of the microdecoder is mainly the floating point
However, some information such as detection of an exception related to the floating-point operation is also output to other functional blocks.

(4.6) “Operand address calculation unit” The operand address calculation unit 115 includes the instruction decoding unit 112
Is hard-wired by information related to operand address calculation output from an addressing mode decoder or the like. In this block, address calculation of operands other than memory access for memory indirect addressing and calculation of a jump destination address of a jump instruction are performed.

The calculation result of the operand address is output to integer operation section 117. In the preceding jump process at the end of the operand address calculation, the calculation result of the jump destination address is output to the instruction fetch unit 111 and the PC calculation unit.

The immediate operand is output to the integer operation unit 117 and the floating point operation unit 118. The values of general-purpose registers and the program counter required for address calculation are stored in the integer operation unit 117 or PC.
Input from the calculation unit 116.

(4.7) “PC Calculation Unit” The PC calculation unit 116 is hard-wiredly controlled by information related to PC calculation output from the instruction decoding unit 112, and calculates a PC value of an instruction.

As described above, the instruction of the data processing device of the present invention is a variable length instruction, and the length of the instruction cannot be known unless the instruction is decoded. The PC calculation unit 116 calculates the PC value of the next instruction by adding the instruction length output from the instruction decoding unit 112 to the PC value of the instruction being decoded.

The PC calculation unit 116 also compares the value of the breakpoint register or trigger pointer register of the instruction address with the PC value of the executed instruction.

The calculation result of the PC calculation unit 116 is output as a PC value of each instruction together with the decoding result of the instruction.

In the preceding branch processing in the instruction decode stage, the address of the branch destination instruction is calculated by adding the branch width output from the instruction decode unit 11 to the PC value.

Further, the PC calculation unit 116 is provided with a PC stack that holds a copy of the return PC value from the subroutine that has been pushed onto the stack when the jump instruction to the subroutine is executed. For the return instruction from the subroutine, the PC calculation unit 116 also performs a process of generating the address of the pre-return destination instruction by reading the return destination PC from the PC stack.

(4.8) “Integer operation unit” The integer operation unit 117 is a micro ROM of the first micro ROM unit 113.
Is executed by using a register file and an operation unit inside the integer operation unit 117, which are controlled by a microprogram stored in the integer operation unit 117 and required to realize the function of each integer operation instruction.

The register file includes general-purpose registers and work registers. In addition, the integer operation unit 117 includes a processor status word (PSW), CS, including a flag that changes according to the result of the integer operation and a bit that determines a mask level of an external interrupt.
It also includes the W register, UATB register, CTXBB register, buffer memory control register, etc.

When the operand to be operated on by the instruction is an address or an immediate, the operand or the calculated address is input from the operand address calculating unit 115. Also,
If the operand to be operated on by the instruction is data on the memory, the address calculated by the address calculation unit 115 is output to the operand access unit 120, and the operand fetched from the data buffer or externally is transferred to the integer operation unit 117. Is entered.

If it is necessary to read the data buffer, external data caches 107 and 108 or the main memory 109 during the operation, the integer operation unit 117 outputs an address to the operand access unit 120 in accordance with the instruction of the microprogram and fetches the target data. .

Data buffer for operation results, external data cache
When it is necessary to store the data in the memory 107 or 108 or the main memory 109, the integer operation unit 117 outputs an address and data to the operand access unit 120 according to the instruction of the microprogram. At this time, the PC value of the instruction that performed the store operation is output from the P calculation unit 116 to the operand access unit 120.

When the integer operation unit 117 obtains a new instruction address by performing an external interrupt, exception processing, or the like, the integer operation unit 117 outputs this to the instruction fetch unit 111 and the PC calculation unit 116.

(4.9) “Floating-point operation unit” The floating-point operation unit 118 is controlled by a microprogram stored in the micro-ROM of the second micro-ROM unit 114, and performs operations necessary for realizing the function of each floating-point operation instruction. The execution is performed using the register file and the operation unit inside the floating point operation unit 118.

The floating-point arithmetic unit 118 includes a floating-point arithmetic mode control register FMC for setting a rounding method for floating-point arithmetic and a mode for permitting detection of a floating-point arithmetic exception, a flag for the floating-point arithmetic result, and a state of occurrence of the floating-point arithmetic exception. And a floating-point operation status word FSW comprising the status bits shown in FIG.

When the operand to be operated on by the instruction is an immediate value, the immediate value is input from the operand address calculation unit 115 to the floating point operation unit 118. If the operand to be operated on by the instruction is data on a memory, the address calculated by the address calculation unit 115 is output to the operand access unit 120, and the operand fetched from the data buffer or from the outside is converted to a floating-point operation. The data is input to the unit 118.

When the operands need to be stored in the built-in data cache, external data caches 107 and 108 or the main memory 109, the floating-point operation unit 118 outputs data to the operand access unit 120 according to the instruction of the microprogram. In the store operation, the floating-point operation unit 118 and the integer operation unit 117 operate in cooperation, and the operand access unit 1
For 20, the address of the operand is output from the integer operation unit 117, and the operand is output from the floating-point operation unit 118. At this time, the PC value of the instruction that performed the store operation is output from the PC calculation unit 116 to the operand access unit 120.

(4.10) “Operand access unit” The operand access unit 120 includes an address conversion mechanism for an operand address, a data buffer, a data TLB, a store buffer, an operand breakpoint register, and a control unit therefor.

The data buffer operates as a built-in data cache or a PC value trace memory by mode switching.

When the data buffer is operated as a built-in data cache, the operand access unit 120 converts the logical address of the data to be loaded output from the operand address calculation unit 115 or the integer operation unit 117 into a physical address during the data loading operation. , Fetches data from the data buffer and outputs the fetched data to the integer operation unit 117 or the floating point operation unit 118.

If the data buffer misses, the operand access unit 120 outputs a physical address to the address input / output unit 119, requests data access to the outside, and
The data input through 122 is registered in the data buffer.

In the data storing operation, the operand access unit 120 converts the logical address of the data to be stored output from the integer operation unit 117 into a physical address, and
7 or store the data output from the floating point arithmetic unit 118 in the data buffer, and output the physical address to the address input / output unit 119 through the store buffer,
The output from the data input / output unit 122 is output to the outside. If a mistake occurs in the store operation, the data is not updated.

In the store buffer, data to be stored, its address, and the PC value of the instruction that performed the store operation are managed as a set. The store operation in the store buffer is managed by a first-in first-out control method.

When operating the data buffer as context save memory, the data buffer has an address of H'FFFFE000
It operates as a (random access memory) RAM serving as a control space of ~ H'FFFFFFFF (H 'represents a hexadecimal number), and can be accessed by a context switching instruction or a control space operation instruction.

Address conversion by paging and updating of the data TLB when the data TLB is missed are also performed by the control circuit inside the operand access unit 120. Also, a check is made to determine whether the memory access address falls into an I / O area mapped to the memory.

When the data buffer is operated as the built-in data cache, if the data processing apparatus of the present invention is in the bus watch mode, the operand access unit 120 outputs the data to which the physical address input through the address input / output unit 119 hits. Invalidates a buffer entry.

(4.11) “Address input / output unit” The address input / output unit 119 outputs addresses output from the instruction fetch unit 111 and the operand access unit 120 to the outside of the data processing device 100 of the present invention.

The output of the address is executed according to a bus protocol defined by the data processing device 100 of the present invention.

The control of the bus protocol is performed by an external bus control circuit in the address input / output unit 119. The external bus control circuit also receives page absence exceptions, bus access exceptions, and external interrupts.

Also, an external device other than the data processing device 100 of the present invention is a bus master, and the data processing device of the present invention is
When the bus 100 is in the bus watch mode, the address input / output unit 119 takes in the address output on the address bus 101 when the external device executes the data write cycle, and fetches the instruction fetch unit 111 and the operand access unit 120.
And forward to.

(4.12) “Data Input / Output Unit” The data input / output unit 121 takes in data from the data bus 102 and transfers it to the operand access unit 120 at the time of an operand loading operation. At the time of the operand storing operation, the operand output from the operand access unit 120 is output to the data bus 102.

The access method of the data caches 107 and 108 includes a standard access mode in which 64-bit data is accessed for one address and four consecutive accesses for one address.
There is a quad access mode for accessing 64-bit data. In any case, the data input / output unit 121 inputs and outputs data exchanged between the operand access unit 120 and an external memory.

(5) “Pipeline processing” The data processing apparatus 100 of the present invention performs high-performance operations by performing pipeline processing of instructions by means of various buffer storages and efficient access of memories using the instruction bus 103 and the data bus 102. .

Here, the pipeline processing method of the data processing device 100 of the present invention will be described.

(5.1) “Pipeline Mechanism” The pipeline processing mechanism of the data processing device 100 of the present invention is configured as shown in the schematic diagram of FIG.

Instruction fetch stage (IF
Stage) 31, a decode stage (D stage) 32 for decoding an instruction, an operand address calculation stage (A stage) 33 for calculating the address of an operand, a micro ROM access (particularly referred to as an R stage 37), and a prefetch of an operand (particularly, OF stage 38), an execution stage (E stage) 35 for executing instructions, and a store stage (S stage) 36 for storing memory operands.
The pipeline processing is executed in a six-stage configuration.

 The S stage 36 has a three-stage store buffer.

Each stage operates independently of the other stages, and theoretically six stages operate completely independently.

Each stage other than S stage 36 requires one processing at least
Can be done with a clock. The S stage 36 can perform one operand store process with a minimum of two clocks. Therefore, if there is no store processing of the memory operand,
Ideally, pipeline processing proceeds one after another for each clock.

Although the data processing device of the present invention has an instruction that cannot be processed by only one basic pipeline processing such as a memory-memory operation or a memory indirect addressing,
The processing is configured so that pipeline processing as balanced as possible can be performed for these processings.

For an instruction having a plurality of memory operands, pipeline processing is performed by decomposing the instruction into a plurality of pipeline processing units (step codes) at a decoding stage based on the number of memory operands.

The information passed from the IF stage 31 to the D stage 32 is the instruction code itself.

The information passed from the D stage 32 to the A stage 33 includes a code relating to the operation specified by the instruction (referred to as D code 41), a code relating to the address calculation of the operand (referred to as A code 42), and the instruction being processed. And a program counter value (PC).

Information passed from the A stage 33 to the F stage 34 includes an R code 43 including an entry address of a microprogram routine and parameters to the microprogram, an F code 44 including an operand address and access method instruction information, and the like. And the program counter value (PC) of the middle instruction.

Information passed from the F stage 34 to the E stage 35 includes an E code 45 including operation control information and literals, and an S code (46a, 46a) including operands and operand addresses.
b) and the program counter value (PC) of the instruction being processed.

The S codes 46a and 46b include an address 46a and data 46b.

The information passed from the E stage 35 to the S stage 36 is two words: W words 47a and 47b, which are the operation results to be stored, and the program counter value (PC) of the instruction that outputs the operation result.

The W codes 47a and 47b include an address 47a and data 47b.

The EIT detected in the stage before the E stage 35 does not start the EIT process until the code reaches the E stage 35. This is because only the instruction processed in the E stage 35 is the instruction in the execution stage, and the instruction processed in the IF stage 31 to the F stage 34 has not yet reached the execution stage. Therefore, EITs detected before the E stage 35 are recorded in the step code and only transmitted to the next stage.

The EIT detected in the S stage 36 is accepted when the execution of the instruction being processed in the E stage 35 is completed or when the processing of the instruction is canceled, and returns to the E stage 35 for processing.

(5.2) “Processing of Each Pipeline Stage” As shown in FIG. 5, names are given to input / output step codes for each pipeline stage for convenience.
Also, there are two types of step codes: a sequence serving as an entry address of the micro ROM performing processing relating to the operation code and a parameter for the E stage 35, and a sequence serving as an operand to be processed by the E stage 35.

Further, between the D stage 32 and the S stage 36, the program counter value of the processing instruction is transferred.

(5.2.1) “Instruction Fetch Stage” The instruction fetch unit 111 operates in the instruction fetch stage (IF stage) 31.

The instruction fetch unit 111 fetches an instruction from a built-in instruction cache or an external device, inputs the instruction to an instruction queue, and outputs an instruction code to the D stage 32 in units of 2 to 6 bytes. The input of the instruction queue is performed in aligned 4-byte units.

When the instruction fetch unit 111 fetches an instruction from the outside in the standard access mode, a minimum of two clocks are required for the aligned four bytes.

In the quad access mode, a minimum of 5 clocks is required for 16 bytes.

Aligned 8 if internal instruction cache hits
Fetching is possible in one clock per byte.

The output unit of the instruction queue is variable every 2 bytes,
Up to 6 bytes can be output during one clock. Immediately after the jump, the instruction queue can be bypassed and the instruction basic part 2 bytes can be directly transferred to the instruction decoder.

The IF stage also converts the logical address of an instruction to a physical address, controls the internal instruction cache and TLB for instructions, manages prefetch destination instruction addresses, and controls the instruction queue.
Done at 31.

(5.2.2) "Instruction decode stage" Instruction decode stage (D stage) 32 is IF stage
Decode the instruction code input from 31.

The instruction code is decoded once per clock using the FHW decoder, NFHW decoder, and addressing mode decoder of the instruction decoding unit 112, and 0 to 6 bytes of instruction code are consumed in one decoding process ( The instruction code is not consumed in the output processing of the step code including the return address of the return subroutine instruction, etc.).

In one decoding, an A code 42 as address calculation information and a D code 41 as an intermediate decoding result of the operation code are output to the A stage 33.

In the D stage 32, control of the PC calculation unit 116 and processing of outputting an instruction code from the instruction queue are also performed.

In the D stage 32, a preceding jump process is performed for a branch instruction or a return instruction from a subroutine. The D code 41 and the A code 42 are not output for the unconditional branch instruction that performed the preceding jump, and the D stage
At 32, processing of the instruction is terminated.

(5.2.3) Operand address calculation stage The processing of the operand address calculation stage (A stage) 33 is roughly divided into two.

One is a process of performing the second-stage decoding of the operation code using the second decoder of the instruction decoding unit 112, and the other is a process of calculating the operand address in the operand address calculation unit 54.

D code is used for the decoding process after the operation code
An R code 43 including a register, memory write reservation, an entry address of a microprogram routine, parameters for the microprogram, and the like is output.

Note that the register or memory write reservation is for preventing incorrect address calculation when the contents of the register or memory referred to in the address calculation have been rewritten by the preceding instruction on the pipeline. is there.

In the operand address calculation process, the A code 42 is input, the operand address calculation unit 54 calculates the address of the operand according to the A code 42, and the calculation result is output as the F code 44.

For a jump instruction, a jump destination address is calculated and a preceding jump process is executed. On this occasion,
At the time of reading the register accompanying the address calculation, a write reservation check is also performed. If the preceding instruction indicates that there is a reservation because the preceding instruction has not completed the write processing to the register or the memory, the preceding instruction is sent to the E stage 35. It enters a standby state until the writing process is completed.

In the A stage 33, the preceding jump processing is performed for the jump instruction for which the preceding jump was not performed in the D stage 32.

For a jump to an absolute value address or a jump in register indirect addressing, a preceding jump is performed in the A stage 33. The R code 43 and the F code 44 are not output for the unconditional jump instruction that has performed the preceding jump, and the processing of the instruction is terminated in the A stage 33.

(5.2.4) "Micro ROM access stage" The processing of the operand fetch stage (F stage) 34 is largely divided into two.

One is access processing of a micro ROM, which is particularly called an R stage 37. The other is an operand prefetch process, particularly referred to as an OF stage 38.

The R stage 37 and the OF stage 38 do not always operate at the same time, and the operation timing differs depending on the miss and hit of the data cache and the miss and hit of the data TLB.

The micro ROM access processing as the processing of the R stage 37 includes a micro ROM access and a micro instruction decoding processing for creating an E code 45 which is an execution control code used for execution in the next E stage 35 with respect to the R code 43. It is.

If the processing for one R code is divided into two or more microprogram steps, the first micro ROM
The unit 113 and the second micro ROM unit 114 may be used in the E stage 35, and the next R code 43 may wait for micro ROM access.

The micro ROM access to the R code 43 is performed when the micro ROM access in the E stage 35 is not performed.

In the data processing device 100 of the present invention, since many integer operation instructions are performed in one microprogram step and many floating point operation instructions are performed in two microprogram steps, the micro ROM access to the R code 43 is actually performed one after another. And the frequency is high.

(5.2.5) “Operand fetch stage” The operand fetch stage (OF stage) 38 performs an operand prefetch process of the above two processes performed in the F stage 34.

In the operand fetch stage 38, the logical address of the F code 44 is converted into a physical address by the data TLB, the built-in data cache is accessed at the physical address to fetch the operand, and the operand and the logical address transferred as the F code 44 are transferred. The addresses are combined and output as S codes 46a and 46b.

One F code 44 may cross an 8-byte boundary, but specifies an operand fetch of 8 bytes or less.

The F code 44 also includes designation of whether or not to access the operand. When the operand address itself or the immediate value calculated in the A stage 33 is transferred to the E stage 35, the operand prefetch is not performed. code
The contents of 44 are transferred as S codes 46a and 46b.

Operands to be prefetched and E stage 35
If the operands to be written match, the operand prefetch is not performed from the built-in data cache, but is performed by bypass.

(5.2.6) "Execution Stage" The execution stage (E stage) 35 operates with the E code 45 and the S codes 46a and 46b as inputs.

This E stage 35 is a stage for executing an instruction,
All processes performed in stages before the E stage 34 are pre-processes for the E stage 35.

Jump is executed in E stage 35 or EIT
When the processing is started, all the processing in the IF stage 31 to the F stage 34 is invalidated.

The E stage 35 is controlled by a microprogram,
The instruction is executed by executing a series of microinstructions from the entry address of the microprogram routine indicated by the E code 45.

The E code 45 includes a code for controlling the integer operation unit 117 (particularly, an EI code) and a code for controlling the floating point operation unit 118 (particularly, an EF code). EI code and EF
It can be output independently of the code.
In this case, the integer operation unit 117 and the floating-point operation unit 118 operate in parallel.

For example, when the floating-point operation unit 118 executes a floating-point instruction having no memory operand, this operation is executed in parallel with the operation of the integer operation unit 117.

In both the integer operation and the floating-point operation, reading of the micro ROM and execution of the micro instruction are performed in a pipelined manner. Therefore, when a branch occurs in the microprogram, a space of one microstep is created.

In the E stage 35, the write reservation to the register or the memory made in the A stage 33 is released after the writing of the operand.

The various interrupts are directly received by the E stage 35 at the breaks of the instructions, and the necessary processing is executed by the microprogram. Other various EIT processes are also performed by a microprogram in the E stage 35.

If you need to store the result of the operation in memory,
The E stage 35 outputs the W codes 47a and 47b and the program counter value of the instruction for performing the store process to the S stage 36.

(5.2.7) "Operand Store Stage" The operand store stage (S stage) 36 converts the logical address 47a of the W code into a physical address using the data TLB, and stores the data 47b of the W code in the data buffer at that address. Operand store stage 36 at the same time
Performs a process of inputting the W codes 47a and 47b and the program counter value to the store buffer, and using the physical address output from the data TLB to store the W code data 47b in an external memory.

The operation of the operand store stage 36 is performed by the operand access unit 120, and also performs an address conversion process and a data buffer exchange process when the data TLB or the data buffer misses.

When the operand store stage 36 detects by the EIT in the operand store processing, the W code 47 is stored in the store buffer.
The EIT is notified to the E stage 35 while holding the a and 47b and the program counter value.

(5.3) “State control of each pipeline stage” Each stage of the pipeline has an input latch and an output latch, and basically operates independently of the other stages.

Each stage completes the previous processing, transfers the processing result from the output latch to the input latch of the next stage, and stores all the input signals necessary for the next processing in the input latch of its own stage. Then, the next process is started.

That is, in each stage, all the input signals for the next process output from the previous stage become valid, and the processing result at that time is transferred to the input latch of the subsequent stage, and the output latch becomes empty. Then, the next process is started.

It is necessary that all input signals be complete at the timing immediately before each stage starts operation. If the input signals are not ready, the stage enters a waiting state (input waiting).

When transferring from the output latch to the input latch of the next stage, the input latch of the next stage must be empty, and the pipeline stage waits even if the input latch of the next stage is not empty Status (waiting for output).

Further, if a cache or TLB misses or data interference occurs between instructions being processed in the pipeline, a plurality of clocks are required for processing in one stage, and the pipeline processing is delayed.

(6) “Detailed Operation of Operand Access Unit” (6.1) “Configuration of Operand Access Unit” FIG. 1 is a detailed block diagram showing a configuration example of the operand access unit 120.

The operand access unit 120 is a TLB2 that buffers a logical address and a physical address of data in pairs.
01, a data buffer 202 that operates as a built-in data cache that buffers physical addresses and data in pairs, or that operates as a memory in a control space for context saving, A logical address comparator 303 for comparing with a logical address tag; a physical address comparator 204 for comparing a physical address output from the TLB 201 with a physical address tag output from the data buffer 202; a data input / output circuit
207, an address output circuit 206, a store buffer unit 208, and an operand access unit control circuit 205 for controlling the whole according to the comparison result of the logical address comparator 203 and the physical address comparator 204.

(6.2) “Operation at the time of reading data in logical space” The entry of the TLB 201 is specified in the lower side (8 bits) of the upper 20 bits of the logical address output from the integer operation unit 117, which are to be converted.

From the designated entry of the TLB 201, a logical address tag (12 bits) and a physical address (20 bits) are output. At this time, if the upper side (12 bits) of the logical address matches the logical address tag, the TLB 201 has been hit, and the physical address output from the TLB 201 is valid.

When the data buffer 202 operates as a built-in data cache, an entry of the data buffer 202 is designated by lower bits (12 bits) indicating a page offset in a logical address and not being converted into a physical address. From the designated entry in the data buffer 202, a physical address tag (20 bits) and data are output. At this time, if the physical address output from the TLB 201 is valid and matches the physical address tag, the data buffer 202
Is hit, and the data output from the data buffer is valid.

If the TLB201 misses, the operand access control unit
Under the control of 205, the address translation table in the external memory of the data processing device 100 of the present invention is accessed, the logical address is translated into the physical address, and the entry of the TLB 201 is updated. After updating the entry of TLB201, TLB2 again
01 is accessed and TLB 201 hits.

If the TLB 201 hits but the data buffer 202 operating as a built-in data cache misses, the external memory is accessed by the physical address under the control of the operand access unit control circuit 205, and the entry in the data buffer 202 is updated.

When the TLB 201 misses, the data buffer 202 does not hit even if the physical address read from the TLB 201 matches the physical address tag of the data buffer. In this case, the hit / miss judgment of the data buffer 202 is determined by TLB20.
This is performed after the entry of 1 is updated and TLB 201 hits.

When the data buffer 202 operates as a memory of the control space, data is fetched from the outside by outputting the physical address converted by the TLB 201 to the access of the logical space to the outside of the data processing device 100 of the present invention. You.

(6.2) “Operation at the time of logical space data write” The operation of writing data to the operand access unit 120 is the same as that of the data read operation regarding the access of the TLB 201.

When the data buffer 202 operates as the built-in data cache, the access operation of the data buffer 202 is similar to the data read operation, but no data is read from the data buffer 202.

In the data write operation, when the data buffer 202 hits, data is written to the hit entry. If a miss occurs, no data is written to the data buffer 202, and no entry update operation is performed.

The data buffer 202 of the data processing device 100 of the present invention operates as a data cache of write-through control, and stores data is output to the outside regardless of whether the data buffer 202 hits or misses during a data write operation.

When the data buffer 202 operates as a memory of the control space, the data buffer is not accessed at the time of writing the operand to the logical space. In this case, the physical address converted by the TLB 201 corresponds to the data processing device 100 of the present invention.
And the store data is output to the outside.

The external data storage process requires at least two clocks, and the E stage 35 of the data processing apparatus 100 of the present invention.
Is slower than the store operation speed. For this reason, the store data is temporarily registered in the store buffer together with the PC value of the instruction that performed the store operation, the physical address of the store destination, and the logical address of the store destination, and thereafter the store buffer performs the store operation. The PC value of the instruction that has performed the store operation registered in the store buffer is the PC value of the instruction input from the PC calculation unit 116.

(6.4) “Operation at the time of access to control space” The data buffer 202 has an address of H'FFFFE000 to H'FFF.
When operating as a memory in the control space of FFFFF, access to the control space whose address is H'FFFFE000 to H'FFFFFFFF is made to the data buffer 202.

No address translation is performed for access to the control space.
B201 does not work. The data buffer 202 operates as a random access memory (RAM) having an address range of H'FFFFE000 to H'FFFFFFFF.

At the time of the read operation, the contents of the data buffer 202 are read according to the address input from the AA bus 124, and are read via the DD bus 125 to the integer operation unit 117 or the floating point operation unit 11.
Output to 8. In the line operation, data input to the data input / output circuit 207 via the DD bus 125 is transferred to the data buffer 2 according to the address input from the AA bus 124.
Written in 02.

Access to the control space in an area whose address range is other than H'FFFFE000 to H'FFFFFFFF is performed outside the data processing device 100 of the present invention.

Whether to access the control space to the data buffer 202 or to the outside is determined in the operand access unit 120 according to the upper 20 bits of the control space address. This determination is made by the logical address comparator 203 in the TLB 201
By setting all 20 bits to “1” and comparing that value with the 19 bits of the lower 20 bits of the upper 20 bits of the address input from the AA bus 124, which are set to don't care Done.

(7) “External access operation” (7.1) “Input / output signal line” FIG. 7 is a schematic diagram showing input / output signals of the data processing device 100 of the present invention.

The data processing device 100 of the present invention has a power supply Vcc and a ground GND, 64
Various control signals are input and output in addition to the data pins, the 32 address pins, the 32 command pins, and the input clock CLK.

For both instruction access and data access, a physical address is output to the address pins.

CLK is an external input clock, and is a clock having the same frequency as the operation clock of the data processing device 100 of the present invention.

The data address strobe DAS # (# represents negative logic) indicates that the data address output to the address pin is valid.

The read / write R / W # distinguishes whether the data pin bus cycle is an input or an output.

The data strobe DS # is a data processing device 100 of the present invention.
Indicates that data input preparation has been completed or that data has been output from the data processing apparatus 100 of the present invention.

DC # is a signal that notifies the data processing device 100 of the present invention that the data access cycle may be ended.

BAT (0: 2) indicates the meaning of the values of the address pin, the data pin, and the instruction pin as shown in FIG.

The instruction address strobe IAS # indicates that the instruction address output on the address pin is valid.

The instruction strobe IS # indicates that the data processing apparatus 100 of the present invention has completed preparation for inputting an instruction.

IC # is a signal notifying the data processing device 100 of the present invention that the instruction access cycle may be ended.

Hold request HREQ # is a data processing device of the present invention.
HACK # is a signal indicating that the data processing apparatus 100 of the present invention has received the old request HREQ # and passed the bus right to another device.

 IRL # (0: 2) is an external interrupt request signal.

IACK # is a signal indicating that the data processing device 100 of the present invention has received an external interrupt and is performing an interrupt vector access cycle.

The WD pin is a pin used to set, at the time of a system reset, whether the data bus of the data processor of the present invention is valid for all 64 bits or only 32 bits.

Although FIG. 6 shows an example in which the data bus is made valid for all 64 bits, the data processing device of the present invention enables the data bus to operate with only 32 bits, thereby reducing the cost. It is possible to configure the system.

(7.2) “Access to External Device” In the example of the system shown in FIG. 6 using the data processing device 100 of the present invention, the data bus connecting the data processing device 100 of the present invention and the data caches 107 and 108 to the data pins is used. 102, the address bus 101 connected to the address pins, as well as BAT (0: 2), DAS #, R / W #, DS #, DC #.

The data processor 100 of the present invention and the instruction cache 11 are connected to BAT (0: 2), IAS #, IS #, and IC # in addition to the instruction bus 103 and the address bus 101 connected to the instruction pins.

CLK is a clock supplied to the entire system and determining the basic timing of the system.

In the bus access in the standard access mode, the data access using the data bus 102 and the instruction access using the instruction bus 103 are performed once every two cycles of the external input clock CLK to a sufficiently high-speed external memory. Do it at speed.

When accessing the bus in the quad access mode, the data access using the data bus 102 and the instruction bus 1
03 to the external memory which is sufficiently high-speed in 5 cycles of the external input clock CLK.
Perform at a speed of degrees.

The address bus 101 is used for both accessing the data caches 107 and 108 and accessing the instruction cache 106.

(8) “Various control registers” (8.1) “Configuration of processor status word PSW” FIG. 36 shows an integer operation unit 117 of the data processing device 100 according to the present invention.
FIG. 3 is a schematic diagram showing a configuration of a processor status word (PSW) in FIG.

In FIG. 36, the SM bit 20 indicates whether the interrupt processing stack pointer is being used in the ring 0 or the ring 0 stack pointer is being used.

The RNG field 21 indicates the ring number where the program is being executed.

AT field 22 indicates the mode of address translation and memory protection.

The FE bit 23 indicates a start mode of the floating-point operation trap.

DB bit 24 indicates the debug environment. If DB = 1, the debug support mechanism is on, and if the debug conditions are satisfied, a self-debug trap is activated. If DB = 0, the debug support mechanism is off, and the self-debug trap is not activated even if the debug conditions are satisfied.

The IMASK field 25 indicates the mask level of the external interrupt. When an external interrupt having a higher priority than the mask level indicated in the IMASK field 25 is input to the data processing device 100 of the present invention, the interrupt processing is started.

The PRNG field 26 indicates the ring number of the ring that called the current ring.

 The FLAG field 27 indicates a flag relating to an integer operation.

RSW is cleared to all zeros at reset. The PSW can read the contents of the LDC command and the STC command and write the specified contents.

(8.2) “Buffer memory control register” FIG. 3 is a schematic diagram showing a configuration of a buffer memory control register for controlling the built-in data buffer 202 and the built-in instruction buffer of the data processing device 100 of the present invention.

In Fig. 3, DM field 3 is a built-in data buffer.
This field controls 202 and has the following meaning.

DM = 00: Data buffer is not operated.

DM = 01: Data buffer address is H'FFFFE000 to H'FFF
Operate as the memory of the control space which is FFFFF.

DM = 10: Operate the data buffer as a write-through control data cache.

DM = 11: undefined The RP field 1 is a field for controlling when the data buffer 202 operates as a data cache.
It has the following meaning.

RP = 00: Data cache is frozen.

RP = 01: Undefined RP = 10: Operate the data cache with a line size of 16 bytes.

RP = 11: Operate the data cache with a line size of 32 bytes.

The IM field 4 is a field for controlling the internal instruction buffer, and has the following meaning.

IM = 00: Do not operate the instruction buffer.

IM = 01: Operate the instruction buffer as a selective cache for selectively registering fetched instructions when the instruction queue is empty.

IM = 10: Not defined.

IM = 11: Operate the instruction buffer as an instruction cache with a line size of 16 bytes.

The LEN field 2 is a field for controlling an instruction registration condition when the instruction buffer is operated as a selective cache, and has the following meaning.

LEN = 000: The instruction cache is frozen without registering the instruction.

LEN = 001: One line is continuously replaced after the instruction queue becomes empty.

LEN = 010: Two lines are exchanged continuously after the instruction queue becomes empty.

LEN = 011 to 111: Not defined.

(8.3) "Purge designation register" FIG. 29 is a schematic diagram showing a configuration of a purge designation register for controlling a purge operation of the built-in data buffer 202 and the built-in instruction buffer of the data processing device 100 of the present invention.

In the figure, each bit of DS5, DU6, IS7, IU8 is a bit for controlling the purge operation of the built-in data buffer 202,
When "1" is written to each of these bits, the contents of the buffer memory corresponding to each bit are purged. Also,
When "0" is written to each of these bits, the contents of the buffer memory corresponding to each bit are not purged. Further, when the value of this register is read, all bits become zero.

DS = 0: Do not purge data buffer entries with negative physical addresses.

DS = 1: Purge data buffer entries with negative physical addresses.

DU = 0: Do not purge data buffer entries with positive physical addresses.

DU = 1: Purge the data buffer entry at the positive physical address.

IS = 0: Do not purge instruction cache entries with negative physical addresses.

IS = 1: Purge instruction cache entries at negative physical addresses.

IU = 0: Do not purge instruction cache entries at positive physical addresses.

IU = 1: Purge instruction cache entry at positive physical address.

(9) “Exception handling function of the data processing device of the present invention” (9.1) “Type of EIT detected by the data processing device of the present invention” The EIT generated by the data processing device 100 of the present invention depends on instructions. A non-existent EIT is a page fault exception detected when data and an instruction corresponding to the accessed logical address are not in the main memory 109 and a page fault occurs, an error occurs during the conversion of the logical address to a physical address, and memory protection. An address translation exception that occurs when a violation or an illegal access to the I / O area occurs, or a bus access exception that occurs when there is no response from the bus within a certain time during instruction or operand access and no memory access is executed There is.

Also, as an EIT generated depending on the instruction, an odd address jump trap generated when the jump destination address of the jump instruction is odd, an unassigned instruction, and an attempt to execute a bit pattern in the addressing mode are performed. Reserved instruction exception that occurs, division-by-zero trap that occurs when integer division is performed by zero, floating-point operation trap that occurs when an unmasked exception is detected when a floating-point instruction is executed, TRAPA
There are unconditional traps generated by instructions and conditional traps generated by TRAP / cc instructions.

(9.2) “Operation when Activating EIT Processing Hydra” In the data processing device 100 of the present invention, when an EIT is detected, a microprogram according to the following procedure is executed, and the EIT processing hydra is activated.

First, a vector number corresponding to the detected EIT is generated inside the data processing device 100 of the present invention.

Next, an EIT vector table which is stored in the memory space and stores a pair of the start address of the processing hydra for each EIT and the vector of the EIT is accessed.

Each entry of the EIT vector table is composed of 8 bytes, and before the processing is shifted to the EIT processing hydra, the processor status word (P
SW) to update the data.

Next, after returning from the EIT processing hydra, NEXTPC which is the PC value of the return instruction to return to the original instruction sequence, PSW before starting the EIT, and various types of the detected EIT such as the number of the detected EIT. EITINF, which is information, is saved on the stack.

If necessary, information such as the PC value of the instruction that detected the EIT is also saved on the stack.

The stack frame generated by these processes is EI
It depends on the type of T and is divided into five types.

Next, the PSW is updated based on the read EIT vector table entry. At this time, if a reserved value is set in the PSW, a system error occurs. This PS
By updating W, it becomes possible to update the ring number serving as the memory protection information, switch the presence / absence of address conversion, switch the debug environment, switch the interrupt mask level, and switch the floating point operation trap acceptance mode.

Next, the PC fetched from the entry in the EIT table
A jump to the value is performed, and the EIT processing handler starts. If multiple EITs are detected and the unprocessed EIT is not suppressed, a process for activating the EIT processing handler for the unprocessed EIT is performed before executing the first instruction of the EIT processing handler.

(9.3) “Return operation from the EIT processing handler to the original instruction sequence” After the processing corresponding to each EIT by the EIT processing handler is completed, the REIT instruction executed last by the EIT processing handler performs the following processing. The microprogram to be executed is executed to perform processing for returning to the original instruction sequence.

First, the PSW value and EI when the EIT is detected from the stack
TINF is read. Subsequently, the logical address of the return instruction is read from the stack.

Further, the presence or absence of additional information is determined based on the format information in EITINF, and if there is additional information, it is read from the stack. The additional information is different depending on the five formats as described above.

Next, all the fields of the PSW are returned to the values before the occurrence of the EIT according to the PSW value at the time when the EIT read from the stack is detected.

In some cases, the write cycle is re-executed by the store buffer that has generated the EIT during the execution of the REIT instruction.

Next, a jump to the logical address of the return instruction read from the stack is executed, and the sequence returns to the original instruction sequence.

(10) “Detailed operation of data buffer” (10.1) Configuration of data buffer FIG. 8 shows the data buffer 202 and the physical address comparator 204
FIG. 3 is a block diagram showing an example of the configuration.

The memory array section of the data buffer 202 including the tag address section and the data section includes a W block 230, an X block 231, and a Y block.
It is composed of four blocks, a block 232 and a Z block 233. Each of the blocks 230, 231, 232, and 233 has 128 entries each composed of a 20-bit tag address and 16-bit data.

Data is input / output via four data input / output registers WD234, XD235, YD236, ZD237.

The tag address is output to four address comparators WC238, XC239, YC240, and ZC241.

The IA register 242 holds an address input from the TLB 201 or the address input / output circuit 246 to the data buffer 202,
Address comparator 238, 239, 240, 241 with four high-order 20 bits
And the lower 9th bit from the 5th bit to the 13th bit is output to the memory array unit. Also, IA register 24
The lower 12th bit and the lower 5 bits of 2 are output to the multiplexer control circuit 244.

The multiplexer 243 has four data input / output registers 2
It is connected to an 8-byte IOD buffer 245 serving as an interface between the data input / output circuit 207 and the data input / output circuit 207. The multiplexer control circuit 244 controls the multiplexer 243 according to the contents of the four address comparators 238, 239, 240, 241 and the IA register 242.

(10.2) "Operation as data cache" Set DM field 3 of the buffer memory control register to "1".
If the RP field 1 is set to "10" and the RP field 1 is set to "10", the data buffer 202 operates as a 4-way set associative data cache having a capacity of 8 kB and a line size of 16. Bytes 230, 231, 232,
233 each operate as one compartment.

In this case, in the read access, the entry of each compartment is selected by the 7th bit from the 5th bit to the 11th bit of the address input to the IA register 242, and the four tag addresses are output to the four address comparators 238, 239, 240, 241 respectively. Four byte data are read to four data input / output registers 234, 235, 236, 237, respectively.

The four tag comparators 238, 239, 240, and 241 compare the four tag addresses with the upper 20-bit address of the IA register 242, respectively. According to the address of the lower 4 bits of the IA register 242 and the comparison result, necessary data is output from the output data of the matched compartment to the multiplexer.
Selected by 243 and read to IOD buffer 245.

In the write access, data is written from the IOD buffer 245 to the hit compartment through the multiplexer 243 and the data input / output registers 234, 235, 236, 267 by the same operation.

When the data cache misses, the external memory is accessed in the 4-byte × 4 quad access mode, and the corresponding one of the four compartments is rewritten. Therefore, RP field 1 = “1”
In the 16 "line size mode of 0", the data bus 102
Works well on systems that use 32-bit.

Set DM field 3 of the buffer memory control register to "1".
When the RP field 1 is set to "11" and the RP field 1 is set to "11", the data buffer 202 operates as a two-way set associative data cache having a capacity of 8 kB and a line size of 32 bytes. Block 231 combines to operate as one compartment, and Y block 232 and Z block 233 combine to operate as one compartment.

The same value is stored in the tag address part of the same entry in the W block 230 and the X block 231, and the data part of the same entry stores 16 bytes of 32-byte data. Similarly, the same value is stored in the tag address portion of the same entry in the Y block 232 and the Z block 233, and the data portion of the same entry stores 16 bytes of 32-byte data.

In this case, in the read access, the entry of each compartment is selected by the 7th bit from the 6th bit to the 12th bit of the address input to the IA register 242, and the four tag data are output to the four address comparators 238, 239, 240, 241 respectively. Four 16-byte data are read out to four data input / output registers 234, 235, 236, 237, respectively.

The four tag comparators 238, 239, 240, and 241 compare the four tag addresses with the upper 20-bit address of the IA register 242, respectively. According to the lower 5 bits of the address of the IA register 242 and the comparison result, necessary data is selected by the multiplexer 243 from the 32 bytes, which are the output data of the two blocks that form the matched compartment, and read out to the IOD buffer 245.

In a write access, the operation similar to the hit compartment is performed, and the multiplexer 243 is transferred from the IOD buffer 245.
And data are written through the data input / output registers 234,235,236,237.

When the data cache misses, the external memory is accessed in the quad access mode of 8 bytes × 4 times, and the corresponding one of the two compartments is rewritten. Therefore, in the 32-byte line size mode when RP1 = “11”, the system operates effectively in a system using the 64-bit data bus 102.

(103.4) “Operation as control space memory” Set DM field 3 of the buffer memory control register to “0”.
If "1" is set, the data buffer 202 operates as an 8 kB control space memory having addresses of H'FFFFE000 to H'FFFFFFFF regardless of the value of the RP field 1.

In this case, the tag address part of the memory array is not used, and only the data part is used.

In the data buffer, the four blocks 230, 231, 232, and 233 operate as a memory array of 256 entries x 32 bytes in total, and the entry is specified by the 6th to 13th bits of the control space address specified by the IA register 242, and the memory array is accessed. Is done.

In the read operation, necessary bytes of the read 32 bytes of data are selected by the multiplexer according to the lower 5 bits of the address of the IA register 242 and input to the IOD buffer 245.

In the write operation, necessary bytes of the 8-byte data held in the IOD buffer 245 are transferred to the corresponding data input / output registers 234, 235, 236, 237 by the multiplexer, and written in the corresponding case of the memory array.

(11) “Details of context switch operation” In the data processing apparatus 100 of the present invention, when the context block information shown in FIG. 30 is operated by the LDCTX instruction and the STCTX instruction which are context switching instructions, data is processed in units of 8 bytes. And perform context switching at high speed.

(11.1) Detailed Configuration of Integer Operation Unit FIG. 2 shows details of a configuration example of the integer operation unit 117 related to the context switching operation, including an operand address calculation unit 115, a floating point operation unit 118, and an operand access unit 12
It is a block diagram shown with 0.

The SA register 210 is a register that holds an operand address and an immediate value output from the operand address calculation unit 115 to the integer operation unit 117.

The AA register 211 is a register for outputting an address from the integer operation unit 117 to the operand access unit 120,
It has 1, 2, 4, and 8 increment / decrement functions for the held contents.

The general-purpose register file 213 and the dedicated register / work register file hold various data in the integer operation unit 117, and are connected to the operation circuit 215 and the auxiliary ALU 212 by three 4-byte buses each. Arithmetic operations such as addition and comparison on operands on registers are performed by arithmetic
Alternatively, it can be performed by the auxiliary ALU 212.

The DD register 216 is an interface register for the integer operation unit 117 and the operand access unit 120 to input and output data, and is connected to the operand access unit 120 by an 8-byte DD bus 123.

The FF register 217 has an integer operation unit 117 and a floating-point operation unit 11
8 is an interface register.

(11.2) "Context loading operation" As an example of a context loading operation, LDCTX / CS is used for a context block in which both FR bit 13 and RG bit 14 of data to be stored in the CSM register are "1".
The operation when the instruction is executed will be described. In this case, it is assumed that the context block is located in the control space whose address is H'FFFFF000. The LDCTX / CS instruction is an LDCTX instruction whose X bit 15 is “1”.

First, the start address H'FFFFF000 of the context block calculated by the operand address calculation unit 115 in accordance with the addressing mode specified in the CTXBADR field and transferred to the SA register 210 is stored in the S1 bus 221 and the AA register 2
The data is output to the AA bus through 11 and stored in the CTXBB register in the dedicated register / work register file 214 through the S1 bus 221, the arithmetic circuit 215, and the D1 bus 225.

After outputting the contents, the AA register 211 increments the value by eight.

The operand access unit 120 accesses the data buffer 202, and the first 8 bytes of the context block are
The data is transferred to the DD register via the DD bus 123.

Next, the upper 4 bytes of the 8-byte data stored in the DD register 216 are stored in the S2 bus 222, the arithmetic circuit 215, and the D1 bus 22.
5 through the CSW register in the dedicated register / work register file 214. At this time, the arithmetic circuit 215
Checks the contents of FR bit 13 and RG bit 14,
The result is transmitted to the micro ROM unit 113 and used for determination of the context block format in the micro program.

At the same time, the lower 4 bytes of the 8-byte data stored in the DD register 216 are the S1 bus 221, the auxiliary ALU 212, and the D3 bus.
SP0 in general register file 213 via bus 226
Stored in a register. In addition, the AA register
211 transfers H'FFFFF008 to the operand access unit 120 via the AA bus 122, and reads the second 8 bytes of the context block from the data buffer 202 to the DD register 216.

After outputting the value, the AA register 211 increments the content by eight.

Next, the upper 4 bytes of the 8-byte data stored in the DD register 216 are stored in the S2 bus 222, the arithmetic circuit 215, and the D1 bus 22.
5 is stored in the SP1 register in the general-purpose register file 213. At this time, the lower 4 bytes of the 8-byte data stored in the DD register 216 are stored in the S1 bus 22 at the same time.
1, General purpose register file through auxiliary ALU212, D3 bus 226
213 is stored in the SP2 register. At the same time, AA
The register 211 transfers the address H'FFFFF010 to the operand access unit 120 through the AA bus 122, and the data buffer 202
, The third 8 bytes of the context block are read into the DD register 216.

After outputting the value, the AA register 211 increments the content by eight.

A similar operation is repeated, and values are loaded into the registers CSW, SP0 to 3, UATB, and R0 to R14. At this time, SP3 and UATB, R1
R2, R3 and R4, R5 and R6, R7 and R8, R9 and R10, R11 and R12, R13 and R14
The upper 4 bytes and lower 4 bytes of DD register 216
Bytes are loaded at once. D3 bus 22 to register R0
When a value is loaded from 6, the corresponding upper 4 bytes are not loaded.

For each of the registers FR0 to FR15, the 8-byte data transferred from the operand access unit 120 to the floating point arithmetic unit 118 is stored in each floating point register by the floating point arithmetic unit 118. However, the address is AA of the integer operation unit 117.
Output from the register 211.

When the 8-byte data transferred from the operand access unit 120 is stored in the FR15 register, the AA register
No address is output from 211, and the data buffer 202 is not accessed.

When the context is loaded from an external memory instead of the data buffer 202, the operand access unit 12
Since 0 accesses the external memory, data buffer 2
Requires more clock cycles than loading context from 02.

(11.3) “Store Operation of Context” As an example of the context operation, an operation when the STCTX / CS instruction is executed when the FR bit 13 and the RG bit 14 of the CSW register are both “1” will be described. In this case, CTXB
The contents of the B register are H'FFFFF000. STCTX / CS
The instruction is an STCTX instruction whose X bit 15 is "1".

First, the top address H'FFFFF000 of the context block held in the CTXBB register is transferred to the AA register 211 through the S3 bus 213, and the contents of the CSW register are transferred to the upper 4 bytes of the DD register 216 through the S1 bus 221. , SP0 register is transferred to the lower 4 bytes of the DD register 216 via the S2 bus 222. Also at the same time CSW
The contents of the register are also input to the arithmetic circuit 215 from the S1 bus 221. The arithmetic circuit 215 checks the contents of the FR bit 13 and the RG bit 14 and transmits the result to the first micro ROM unit 113.
Used to determine the context block format in the micro program.

Next, the address H'FFFFF000 from the AA register 211 is transferred to the operand access unit 120 through the AA bus 122,
From the register 216, the CSW register value and the SP0 register value, which are the first 8-byte data of the context block, are DD
Transferred to the operand access unit 120 via the bus 123,
The data is stored in the data buffer 202.

After outputting the value, the AA register 211 increments the content by eight. At this time, the contents of the SP1 register, which is the upper 4 bytes of the second 8-byte information of the context block, are transferred from the general-purpose register file 213 to the upper position of the DD register 216 via the S1 bus 221 and the contents of the SP2 register, which is the lower 4 bytes, Is transferred from the general-purpose register file 213 to the lower part of the DD register 216 via the S2 bus 222.

Next, the address H'FFFFF008 from the AA register 211 is transferred to the operand access unit 120 through the AA bus 122,
From register 216, the second 8 of the context block
The SP1 register value and SP2 register value that are byte data
The data is transferred to the operand access unit 120 via the DD bus 123 and stored in the data buffer 202.

After outputting the value, the AA register 211 increments the content by eight. At this time, the contents of the SP3 register, which is the upper 4 bytes of the third 8-byte information of the context block, are transferred from the general-purpose register file 213 to the upper position of the DD register 216 via the S1 bus 221 and the UATB which is the lower 4 bytes
The contents of the register are transferred from the dedicated register / work register file 214 to the lower part of the DD register 216 via the S2 bus 222.

The same operation is repeated, and the values of the registers CSW, SP0 day 3, UATB, and R0 to R14 are stored in the data buffer 202. At this time, SP3 and UATB, R1 and R2, R3 and R4, R5 and R6, R7 and R8, R9 and R1
0, the values of R11 and R12, and the values of R13 and R13 are
Are transferred at a time to the upper 4 bytes and the lower 4 bytes.

When the value of the R0 register is transferred to the DD register 216, the corresponding upper byte is not transferred.

When the value of the R0 register is transferred from the DD register 216 to the operand access unit 120, zero is transferred to the corresponding upper 4 bytes.

For each of the registers FR0 to FR15, the value read from each floating-point register of the floating-point operation unit 118 is transferred to the operand access unit 120. However, the address is output from the AA register 211 of the integer operation unit 117.

When storing the context in an external memory instead of the data buffer 202, the operand access unit 120
Access the external memory, the data buffer 20
Requires more clock cycles than storing the context in 2.

(12) "Another embodiment of the present invention" In the above embodiment, an example was described in which the data buffer was operated as either a random access memory or a data cache serving as a control space for holding a context block by mode switching. In the method described above, a configuration may be adopted in which one buffer memory is operated as either a random access memory or an instruction cache serving as a control space for holding a context block by mode switching.

When the buffer memory operates as a random access memory, a configuration may be adopted in which the buffer memory operates as a part of a logical memory space instead of operating as a control space for holding a context block.

In the above embodiment, an address register for outputting an address to the operand access unit and a data register having a byte width twice as large as a general-purpose register for inputting / outputting data to / from the operand access unit are provided. In the case where an LDCTX instruction, which is an instruction for loading data from a memory into two or more registers, is executed by controlling an instruction execution control unit, Data obtained by concatenating two data to be loaded into the two registers from the operand access unit is transferred to the data register, and the upper 4 bytes and the lower 4 bytes of the data register are transferred to the two registers via two transfer paths respectively. It is configured to be transferred at the same time. For this reason, the contents of the register can be transferred to the memory at twice the transfer speed as compared with the case where data is transferred one by one.
The execution of the LDCTX instruction for loading the context is accelerated, and the time required for task switching is reduced.

When executing the STCX instruction, which is an instruction to store data from two or more registers to the memory, the contents of the two registers are transferred from the two transfer paths to the upper four bytes of the data register under the control of the instruction execution control unit. The data is simultaneously transferred to the lower 4 bytes, two data are linked by a data register, and the linked data is transferred to the operand access unit as one memory access. This makes it possible to transfer the contents of the register at twice the transfer rate as compared with the case where data is transferred one by one.
The speed of execution of the CTX instruction is increased, and the time required for task switching is reduced.

Further, when a configuration is adopted in which the data buffer is built in the same integrated circuit as the main body of the data processing device as in the above-described embodiment, the access time to the data buffer is particularly shorter than that to the memory outside the integrated circuit. Because of the short length, the above-described effect is particularly large.

[Effects of the Invention] In the data processing device of the present invention as described in detail above, the memory control information holding means, that is, the first data buffer control field contained in the buffer memory control register is used.
Memory (data buffer)
Holds and caches data that is the operand of the instruction to be executed by the instruction execution unit, and is accessed if the data cache hits because the address output to the operand access unit matches the tag address in the data cache. Output data corresponding to the address.

On the other hand, when the second value is held by the memory control information holding means, the memory is a memory accessible by an instruction, which is not only a user space, but also a control space (a space other than the user space, that is, a system program). It operates as a memory in the used memory space). In this case, if the address of the control space output to the operand access unit is within the range of the address area, the memory (data buffer) outputs the data held at that address.

For this reason, in the data processing device of the present invention, one data buffer can physically operate as a data cache or can operate as a random access memory in a specific address area. Available. Therefore, in the context switching instruction or the like, the area of the context saving data buffer can be used as a particularly high-speed memory area, and the maximum value of the task switching time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of an operand access unit of a data processing device of the present invention. FIG. 2 is a block diagram showing a partial detailed configuration of an integer operation unit of the data processing device of the present invention. Is a schematic diagram showing the configuration of a buffer memory control register of the data processing device of the present invention, FIG. 4 is a block diagram showing an example of the overall configuration of the data processing device of the present invention, and FIG. FIG. 6 is a block diagram illustrating a pipeline processing stage, FIG. 6 is a block diagram illustrating a configuration example of a data processing system using the data processing device of the present invention, and FIG. 7 is an input / output signal of the data processing device of the present invention. FIG. 8 is a schematic diagram showing pins, FIG. 8 is a block diagram showing a detailed configuration example of a data buffer of the data processing device of the present invention, and FIGS. 9 to 13 show instruction formats of the data processing device of the present invention. 14 to 27 are schematic diagrams showing a format of an addressing mode designating section in an instruction of the data processing device of the present invention, and FIG. 28 is a BAT (0: 2) of the data processing device of the present invention. FIG. 29 is a diagram showing a table representing the meaning of signals, FIG. 29 is a schematic diagram showing a configuration of a purge designation register for purging a buffer memory of the data processing device of the present invention, and FIG. 30 is a diagram of the data processing device of the present invention. FIG. 31 is a schematic diagram illustrating an example of a format of a context block, FIG. 31 is a schematic diagram illustrating a configuration of a CSW register that specifies a context block format of the data processing device of the present invention, and FIG. 32 is a context load of the data processing device of the present invention. FIG. 33 is a schematic diagram showing a bit pattern of an instruction, FIG. 33 is a schematic diagram showing a bit pattern of a context instruction of the data processing device of the present invention, and FIG. FIG. 35 is a schematic diagram showing the configuration of a CTXBB register that holds the start address of the context block currently being executed. FIG. 35 shows the configuration of a UATB register that holds the start address of the user address conversion table of the data processing device of the present invention. FIG. 36 is a schematic diagram showing the configuration of the PSW (after the processor state) of the data processing device of the present invention. 3 ... DM field, 112 ... Instruction decoding unit, 117 ...
Integer operation unit, 118... Floating-point operation unit, 120... Operand access unit, 202... Data buffer In each drawing, the same reference numerals indicate the same or corresponding parts.

Claims (4)

(57) [Claims] An instruction fetch unit for fetching an instruction, an instruction decode unit for decoding an instruction fetched by the instruction fetch unit, an instruction execution unit for executing an instruction in accordance with an output of the instruction decode unit, an address decoder, and a tag A memory comprising: a tag address memory for storing an address; and a data memory for storing data, the memory operating in a first mode or a second mode; and a first value or a second value defining an operation mode of the memory. Memory control information holding means for holding; an internal address bus and an internal data bus connected between the instruction execution unit and the memory; an address for generating an address in response to an instruction from the instruction execution unit and outputting the address to the memory A generation unit, and an address output by the address generation unit when the memory control information holding unit holds a first value. Is compared with a tag address stored in the tag address memory, and when a match is found with any of the tag addresses, means for outputting corresponding data from the data memory to the internal data bus; When the address output from the address generation unit is compared with the address allocated to the data memory as a part of the memory space accessible by the instruction when the address is within the range of the address, The address generating unit transfers the output address to the data memory via the internal address bus, outputs corresponding data from the data memory to the internal data bus, and stores the data at a storage location corresponding to the transferred address. The operation of the instruction being executed by the instruction execution unit is transferred from the instruction execution unit to the memory via the internal data bus. Means for transferring and writing lands. 2. An instruction fetch unit for fetching an instruction, an instruction decode unit for decoding an instruction fetched by the instruction fetch unit, an instruction execution unit for executing an instruction according to an output of the instruction decode unit, an address decoder, and a tag A memory including a tag address memory for storing an address and a data memory for storing data or an instruction code, and operating in a first mode or a second mode; and a first value or a second value defining an operation mode of the memory. Memory control information holding means for holding a value of the following; an internal address bus and an internal data bus connected between the instruction execution unit and the memory; an address generated in response to an instruction from the instruction execution unit; An address generation unit for outputting, and the address generation unit outputs when the memory control information holding unit holds the first value. Means for comparing the input address with a tag address stored in the tag address memory, and outputting a corresponding instruction code from the data memory to the instruction fetch unit when any of the addresses matches the tag address, and holding the memory control information. When the means holds the second value, the address output by the address generation unit is compared with an address allocated to the data memory as a part of a memory space accessible by an instruction, and the address range When the address is within, the address generation unit transfers the output address to the data memory via the internal address bus, outputs corresponding data from the data memory to the internal data bus, and At the corresponding storage location, the instruction execution unit transfers the data from the instruction execution unit to the memory via the internal data bus. Means for transferring and writing operands of an instruction being executed. 3. The data processing device according to claim 1, wherein the memory space is a memory space used by a system program. 4. The data processing apparatus according to claim 1, further comprising means for executing a plurality of data processing processes in a time-division manner, wherein said memory space is a memory space used for an instruction for saving a context related to execution of said data processing process. The data processing device according to claim 1.