JP2505479B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2505479B2 JP2505479B2 JP62206866A JP20686687A JP2505479B2 JP 2505479 B2 JP2505479 B2 JP 2505479B2 JP 62206866 A JP62206866 A JP 62206866A JP 20686687 A JP20686687 A JP 20686687A JP 2505479 B2 JP2505479 B2 JP 2505479B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- semiconductor substrate
- heat sink
- present
- warpage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、製造の容易な半導体装置に関するもので
ある。The present invention relates to a semiconductor device that can be easily manufactured.
第３図（ａ），（ｂ）は従来の半導体装置（MMIC）を
示す側面図および平面図である。FIGS. 3A and 3B are a side view and a plan view showing a conventional semiconductor device (MMIC).
また、第４図（ａ），（ｂ）はアセンブリを説明する
ための側面図である。4 (a) and 4 (b) are side views for explaining the assembly.
これらの図において、１は回路パターン、２は前記回
路パターン１が形成される半導体基板、３はヒートシン
ク、４は半導体装置を取り付けるキャリア、５はアセン
ブリ治具、６はアセンブリにより生じるクラックであ
る。In these figures, 1 is a circuit pattern, 2 is a semiconductor substrate on which the circuit pattern 1 is formed, 3 is a heat sink, 4 is a carrier for mounting a semiconductor device, 5 is an assembly jig, and 6 is a crack generated by the assembly.
次に、第３図（ａ），（ｂ）および第４図（ａ），
（ｂ）を参照してその構造およびアセンブリ方法を説明
する。Next, FIGS. 3 (a) and (b) and FIG. 4 (a),
The structure and assembly method will be described with reference to FIG.
例えば従来の半導体装置では、半導体基板２として30
μｍ厚のGaAs,ヒートシンク３として70μｍ厚のAuを使
用している。このような半導体装置を実装する場合は、
あらかじめ無酸素銅に２〜３μｍ厚のAuメッキを行った
キャリア４にAu:Sn＝80:20等の半田材を用いて取り付け
る。この際、半田材を溶かすためにキャリア４および半
導体装置を300〜320℃の雰囲気中で温めると、半導体基
板２とヒートシンク３との熱膨張係数の差により第４図
（ａ）に示すような、そりが生じて半導体装置の隅が浮
き上がる。このため、従来は第４図（ｂ）に示すよう
に、アセンブリ治具５により半導体基板２を上から押え
て半導体装置をキャリア４と密着させることが行われて
いた。For example, in a conventional semiconductor device, the semiconductor substrate 2 is 30
μm thick GaAs and 70 μm thick Au are used as the heat sink 3. When mounting such a semiconductor device,
It is attached to the carrier 4 in which oxygen-free copper is plated with Au in a thickness of 2 to 3 μm in advance by using a solder material such as Au: Sn = 80: 20. At this time, when the carrier 4 and the semiconductor device are heated in an atmosphere of 300 to 320 ° C. in order to melt the solder material, due to the difference in thermal expansion coefficient between the semiconductor substrate 2 and the heat sink 3, as shown in FIG. The warp causes the corners of the semiconductor device to rise. Therefore, conventionally, as shown in FIG. 4B, the semiconductor jig 2 is pressed from above by the assembly jig 5 to bring the semiconductor device into close contact with the carrier 4.
上記のような従来の半導体装置は、ヒートシンク３の
上面全体に半導体基板２があるため、そりが大きく、ま
た、半導体基板２に直接アセンブリ治具５があたるた
め、クラック６が生じ易いという問題点があった。In the conventional semiconductor device as described above, since the semiconductor substrate 2 is on the entire upper surface of the heat sink 3, the warpage is large, and since the assembly jig 5 directly hits the semiconductor substrate 2, the crack 6 is likely to occur. was there.
この発明は、かかる問題点を解決するためになされた
もので、そり量が小さくクラックが生じにくい半導体装
置を得ることを目的とする。The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor device having a small amount of warpage and less likely to cause cracks.
この発明に係る半導体装置は、半導体基板のヒートシ
ンク上の領域に加熱時のそり量を小さくする除去部を設
けたものである。In the semiconductor device according to the present invention, a removing portion for reducing the amount of warpage during heating is provided in a region on the heat sink of the semiconductor substrate.
この発明においては、加熱時の半導体基板のそり量が
小さくなるうえ、アセンブリ治具を用いてキャリアにヒ
ートシンクを密着させる際に、ヒートシンクを直接押え
られるためクラックが入りにくくなる。According to the present invention, the amount of warpage of the semiconductor substrate during heating is reduced, and when the heat sink is brought into close contact with the carrier using the assembly jig, the heat sink is directly pressed so that cracks are less likely to occur.
第１図（ａ），（ｂ）はこの発明の半導体装置の一実
施例を示す側面図および平面図である。1 (a) and 1 (b) are a side view and a plan view showing an embodiment of a semiconductor device of the present invention.
また、第２図（ａ），（ｂ）はこの発明の半導体装置
のアセンブリを説明するための図である。2 (a) and 2 (b) are views for explaining the assembly of the semiconductor device of the present invention.
これらの図において、第３図（ａ），（ｂ）および第
４図（ａ），（ｂ）と同一符号は同一部分を示し、2aは
この発明における半導体基板で、加熱時のそり量が小さ
くなるようにその四隅が除去されて除去部2bが形成され
ている。In these figures, the same reference numerals as those in FIGS. 3 (a) and (b) and FIGS. 4 (a) and (b) indicate the same parts, and 2a is a semiconductor substrate according to the present invention, in which the amount of warpage during heating is The four corners are removed so as to be small, and the removed portion 2b is formed.
次に、第１図（ａ），（ｂ）および第２図（ａ），
（ｂ）を参照して構造およびアセンブリ方法を説明す
る。Next, FIG. 1 (a), (b) and FIG. 2 (a),
The structure and assembly method will be described with reference to FIG.
例えば半導体基板2aとして30μｍ厚のGaAs,ヒートシ
ンク３として70μｍ厚のAuを使用しており、半導体基板
2aの四隅の回路パターン１に影響を与えない領域は除去
部2bとなっている。For example, 30 μm thick GaAs is used as the semiconductor substrate 2a and 70 μm thick Au is used as the heat sink 3.
Areas that do not affect the circuit pattern 1 at the four corners of 2a are removal portions 2b.
この発明においてもこのような半導体装置を実装する
場合は、あらかじめ無酸素銅に２〜３μｍ厚のAuメッキ
を行ったキャリア４にAu:Sn＝80:20等の半田材を用いて
取り付ける。この際、半田材を溶かすためにキャリア４
および半導体装置を300〜320℃の窒素雰囲気中で温め
る。このとき、従来の装置と同様にそりが生じるが、半
導体基板2aはヒートシンク３上の一部が除去されている
ため、そり量が小さい。また、これに加えて最後に、キ
ャリア４と半導体装置を密着させる際、アセンブリ治具
５を用いてヒートシンク３を押えることができるため、
第４図（ｂ）に示したようなクラック６は半導体基板2a
に生じない。Also in the present invention, when such a semiconductor device is mounted, it is attached to the carrier 4 in which oxygen-free copper is plated with Au in a thickness of 2 to 3 μm in advance by using a solder material such as Au: Sn = 80: 20. At this time, the carrier 4 is used to melt the solder material.
And heating the semiconductor device in a nitrogen atmosphere at 300 to 320 ° C. At this time, warpage occurs as in the conventional device, but the semiconductor substrate 2a has a small amount of warpage because a part of the heat sink 3 is removed. In addition to this, finally, when the carrier 4 and the semiconductor device are brought into close contact with each other, the heat sink 3 can be pressed by using the assembly jig 5.
The crack 6 as shown in FIG. 4 (b) is caused by the semiconductor substrate 2a.
Does not occur in
なお、上記実施例では半導体基板2aにGaAsを用いた場
合について説明したが、この発明はこれに限定されるも
のでなく、例えばSi等の半導体基板についても同様であ
る。It should be noted that although the case where GaAs is used for the semiconductor substrate 2a has been described in the above embodiment, the present invention is not limited to this, and the same applies to a semiconductor substrate such as Si.
また、上記実施例では半導体基板2aの四隅を除去した
除去部2bの場合について説明したが、この発明はこれに
限定されるものでなく、回路パターン１に影響を与えな
い範囲で、かつそり量を小さくできるならどのようなパ
ターンの除去部であってもよい。Further, in the above-described embodiment, the case of the removed portion 2b in which the four corners of the semiconductor substrate 2a are removed has been described, but the present invention is not limited to this, and the amount of warpage and the warpage amount may be within a range that does not affect the circuit pattern 1. Any pattern removal unit may be used as long as it can reduce
この発明は以上説明したとおり、半導体基板のヒート
シンク上の領域に加熱時のそり量を小さくする除去部を
設けたので、そり量が小さくなり、アセンブリが容易と
なるうえ、アセンブリ時にヒートシンクをアセンブリ治
具により押えられるので、半導体基板にクラックを生じ
にくいという効果がある。As described above, according to the present invention, since the removal portion for reducing the amount of warpage during heating is provided in the area on the heat sink of the semiconductor substrate, the amount of warpage is reduced, and the assembly is facilitated. Since it is pressed by the tool, there is an effect that the semiconductor substrate is less likely to crack.
第１図はこの発明の半導体装置の一実施例を示す図、第
２図はこの発明におけるアセンブリを説明するための
図、第３図は従来の半導体装置を示す図、第４図は従来
のアセンブリを説明するための図である。 図において、１は回路パターン、2aは半導体基板、2bは
除去部、３はヒートシンク、４はキャリア、５はアセン
ブリ治具である。 なお、各図中の同一符号は同一または相当部分を示す。1 is a diagram showing an embodiment of a semiconductor device of the present invention, FIG. 2 is a diagram for explaining an assembly in the present invention, FIG. 3 is a diagram showing a conventional semiconductor device, and FIG. 4 is a diagram showing a conventional semiconductor device. It is a figure for explaining an assembly. In the figure, 1 is a circuit pattern, 2a is a semiconductor substrate, 2b is a removal part, 3 is a heat sink, 4 is a carrier, and 5 is an assembly jig. The same reference numerals in each drawing indicate the same or corresponding parts.
Claims (1)
体基板のヒートシンクとからなり、加熱されて前記ヒー
トシンクがキャリアにろう付けされる半導体装置におい
て、前記半導体基板のヒートシンク上の領域に加熱時の
そり量を小さくする除去部を設けたことを特徴とする半
導体装置。1. A semiconductor device comprising a semiconductor substrate having a circuit formed thereon and a heat sink of the semiconductor substrate, wherein the heat sink is brazed to a carrier by heating, when heating is performed on an area on the heat sink of the semiconductor substrate. A semiconductor device comprising a removing portion for reducing a warp amount.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62206866A JP2505479B2 (en) | 1987-08-19 | 1987-08-19 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62206866A JP2505479B2 (en) | 1987-08-19 | 1987-08-19 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6449246A JPS6449246A (en) | 1989-02-23 |
| JP2505479B2 true JP2505479B2 (en) | 1996-06-12 |
Family
ID=16530336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62206866A Expired - Lifetime JP2505479B2 (en) | 1987-08-19 | 1987-08-19 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2505479B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4682571B2 (en) * | 2004-09-24 | 2011-05-11 | 凸版印刷株式会社 | Liquid chemical transpiration container |
-
1987
- 1987-08-19 JP JP62206866A patent/JP2505479B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6449246A (en) | 1989-02-23 |
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