JP2023104750A - Multilayer wiring board and manufacturing method for the same - Google Patents

Abstract

To provide a multilayer wiring board that has high insulation reliability even if an adhesion layer is formed between a conductor and an insulating resin layer.SOLUTION: The multilayer wiring board includes a first insulating resin layer, a seed layer stacked on the first insulating resin layer, a conductor layer that has a plating layer stacked on the opposite side of the first insulating resin layer of the seed layer and is configured to form a plurality of conductors, an adhesion layer formed on the surface of a conductor, a second insulating resin layer covering the conductor, the adhesion layer, and the first insulating resin layer. The adhesion layer is formed on at least the top surface of the plating layer and is not formed on the first insulating resin layer between adjacent conductors.SELECTED DRAWING: Figure 1

Description

The present invention relates to a multilayer wiring board used for mounting electronic components such as semiconductor elements (chips) and a manufacturing method thereof.

2. Description of the Related Art In recent years, there has been an increase in the degree of integration due to demands for higher functionality of electronic devices, and an increase in the frequency of electrical signals, that is, the so-called operating frequency, due to the need for high-speed signal processing in electronic devices. Multilayer wiring substrates used in these devices are required to have finer wiring due to higher densities and to cope with higher frequencies.

Generally, a multilayer wiring board is manufactured by laminating one or more conductor layers and one or more insulating resin layers. At this time, if the adhesion between the conductor forming the conductor layer and the insulating resin layer is insufficient, problems such as delamination, cracking, and deterioration of insulation reliability occur.

Therefore, conventionally, as a method for improving the adhesion between the conductor and the insulating resin layer, a method of roughening the surface of the conductor to produce an anchor effect has been used. However, it is difficult to roughen wiring (conductors) that have been miniaturized due to high density, and there is a problem that the transmission characteristics of high-frequency signals deteriorate due to the roughened surface (skin effect). .

Therefore, as a method of improving the adhesion between the conductor and the insulating resin layer without roughening the conductor surface, a method of forming an adhesion layer (film) has been proposed as in Patent Document 1.

JP-A-11-354922

FIG. 10 is an enlarged sectional view showing part of a conventional multilayer wiring board.

In the conventional method for forming the adhesion layer 114 disclosed in Patent Document 1, the adhesion layer 114 is also formed on the insulating resin 111 between the conductors 113 as shown in FIG. Further, even when forming an adhesion layer that chemically bonds only to the conductor, the material forming the adhesion layer is also applied onto the insulating resin in terms of the process. Therefore, a step of removing the coating liquid by washing with water or the like is required, but there is a risk that residuals may remain on the insulating resin between the conductors due to insufficient washing or the like.

In other words, when a material having a low dielectric strength is used for the adhesion layer, there is a possibility that the reliability of insulation between wirings may deteriorate in the conventional method for forming the adhesion layer.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a multilayer wiring board having an adhesion layer between a conductor and an insulating resin layer and having high insulation reliability.

One aspect of the present invention for solving the above problems is a first insulating resin layer, a seed layer laminated on the first insulating resin layer, and a surface of the seed layer opposite to the first insulating resin layer. A conductor layer having a plated layer laminated on a conductor, a conductor layer forming a plurality of conductors, an adhesion layer formed on a part of the surface of the conductor, the conductor, the adhesion layer, and the first insulating resin layer. 2 insulating resin layers, and the adhesion layer is formed at least on the upper surface of the plating layer and is not formed on the first insulating resin layer between adjacent conductors.

Another aspect of the present invention includes a step of forming a seed layer on a first insulating resin layer, a step of forming a resist pattern on the seed layer, and a plating layer on the seed layer on which the resist pattern is formed. and removing part of the resist pattern so that the resist pattern remains on the seed layer with a height of 10% or more and 90% or less of the total thickness of the seed layer and the plating layer; A step of forming an adhesion layer on the surface of the resist pattern and the surface of the plating layer, a step of removing the remaining resist pattern and the adhesion layer on the surface, and a seed layer exposed by removing the remaining resist pattern. and forming a second insulating resin layer covering the seed layer, the plating layer, the adhesion layer, and the first insulating resin layer.

Another aspect of the present invention includes a step of forming a seed layer on a first insulating resin layer, a step of forming a resist pattern on the seed layer, and a plating layer on the seed layer on which the resist pattern is formed. and removing the portion of the resist pattern that contacts the side surface of the plating layer until it reaches the seed layer so that the width of the resist pattern in the surface direction of the first insulating resin layer is reduced. exposing a portion; forming an adhesion layer on the surface of the plating layer, the surface of the remaining resist pattern, and the surface of the exposed seed layer; and removing the adhesion layer on the remaining resist pattern and its surface. a step of removing the seed layer exposed by removing the remaining resist pattern; and a second insulating resin covering the seed layer, the plating layer, the adhesion layer, and the first insulating resin layer. and forming a layer.

Another aspect of the present invention includes a step of forming a seed layer on a first insulating resin layer, a step of forming a resist pattern on the seed layer, and a plating layer on the seed layer on which the resist pattern is formed. A step of forming a film having a thickness substantially equal to that of the resist pattern, a step of forming an adhesion layer on the surface of the resist pattern and the surface of the plating layer, a step of removing the adhesion layer on the surface of the resist pattern and its surface, and a step of removing the resist a step of removing the seed layer exposed by removing the pattern; and a step of forming a second insulating resin layer covering the seed layer, the plating layer, the adhesion layer, and the first insulating resin layer. and a method for manufacturing a multilayer wiring board.

ADVANTAGE OF THE INVENTION According to this invention, the multilayer wiring board which has an adhesion layer between a conductor and an insulating resin layer, and has high insulation reliability can be provided.

1 is an enlarged cross-sectional view showing a part of a multilayer wiring board according to a first embodiment of the present invention; FIG. Explanatory drawing which shows an example of the manufacturing method of the core substrate of this invention. 1A and 1B are explanatory views showing a multilayer wiring board and a manufacturing method according to a first embodiment of the present invention; FIG. 1A and 1B are explanatory views showing a multilayer wiring board and a manufacturing method according to a first embodiment of the present invention; FIG. FIG. 2 is a cross-sectional view showing an example of a semiconductor device in which the semiconductor element of the present invention is mounted; FIG. 4 is an enlarged cross-sectional view showing a part of a multilayer wiring board according to a second embodiment of the present invention; FIG. 5 is an explanatory diagram showing a multilayer wiring board and a manufacturing method according to a second embodiment of the present invention; FIG. 11 is an enlarged cross-sectional view showing a part of a multilayer wiring board according to a third embodiment of the present invention; FIG. 5 is an explanatory diagram showing a multilayer wiring board and a manufacturing method according to a third embodiment of the present invention; FIG. 2 is an enlarged cross-sectional view showing a part of a conventional multilayer wiring board;

First to third embodiments will be described with reference to the drawings. The dimensional ratios in the drawings may differ from the actual ratios for convenience of explanation, and some configurations may be omitted from the drawings.

<First embodiment>
A first embodiment will be described with reference to FIGS. FIG. 1 is an enlarged cross-sectional view showing part of a multilayer wiring board according to a first embodiment of the present invention.

A multilayer wiring board 100 includes a first insulating resin layer 11 , a second insulating resin layer 12 , a conductor layer 13 and an adhesion layer 14 . The multilayer wiring board 100 may be, for example, a core board formed on a core board 1 to be described later, or may be a coreless board having no core layer. Hereinafter, the upper surface is the surface farther from the core substrate or, in the case of a coreless substrate, the surface farther from the carrier substrate.

(First insulating resin layer)
The first insulating resin layer 11 is made of a thermosetting resin, a thermoplastic resin, a photosensitive resin, or a resin mixture thereof, such as epoxy resin, acrylic resin, phenolic resin, melamine resin, silicone resin, polyimide resin. , polyphenylene ether resin, maleimide resin, liquid crystal polymer, fluororesin, or a combination of two or more thereof, and may contain an inorganic filler or an organic filler.

(conductor layer)
The conductor layer 13 has a seed layer 13a and a plating layer 13b in order from the first insulating resin layer 11 side. A plurality of conductors 13' are formed by patterning the conductor layer 13 by etching. The conductor layer 13 may include various patterns such as wiring, vias, shields, grounds, and dummies, but FIG. 1 shows wiring portions. Adjacent conductors 13 ′ are spaced apart in the planar direction of the first insulating resin layer 11 . The portion of the conductor 13' where the adhesion layer 14 is formed has a smaller surface roughness than the portion where the adhesion layer 14 is not formed. Therefore, even if the electrical signal has a high frequency, it is less likely to be affected by the skin effect, and deterioration in transmission characteristics can be suppressed.

(seed layer)
Seed layer 13 a is laminated on first insulating resin layer 11 . The material forming the seed layer 13a is not particularly limited, but when forming by electroless plating, for example, metal materials such as Cu, Pd, Al, Sn, Ni and Cr can be used. When formed by a sputtering method, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO (Indium Tin Oxide), Using IZO (Indium Zinc Oxide), AZO (Aluminum-doped Zinc Oxide), ZnO, PZT (lead zirconate titanate), TiN, Cu ₃ N ₄ , Cu alloy, or a combination of two or more of these can be done.

(Plating layer)
The plating layer 13b is laminated on the upper surface of the seed layer 13a (the surface opposite to the first insulating resin layer 11). The material forming the plated layer 13b is mainly a metal, and the type is not particularly limited. A material in which two or more kinds are combined can be used.

(Adhesion layer)
The adhesion layer 14 is formed so as to partially cover the outer surface of the conductor 13'. In the present embodiment, the adhesion layer 14 includes the entire upper surface of the conductor 13' (the upper surface of the plated layer 13b) and, of the side surfaces of the conductor 13', from the upper edge of the side surface of the conductor 13' to the thickness of 10% of the thickness of the conductor 13'. % to 90%. The material forming the adhesion layer 14 is not particularly limited, and examples thereof include silane coupling agents, azole compounds, thiol compounds, and triazinethiol compounds. The adhesion layer 14 is formed on the upper surface and part of the side surface of the conductor 13', and is not formed on the first insulating resin layer 11 between the adjacent conductors 13'. Insulation between adjacent conductors 13' is ensured, and high insulation reliability can be obtained.

(Second insulating resin layer)
The second insulating resin layer 12 is laminated on the first insulating resin layer 11 so as to cover the conductor 13 ′, the adhesion layer 14 and the first insulating resin layer 11 . The second insulating resin layer 12 can be formed using the materials exemplified for the first insulating resin layer 11 .

A method for manufacturing the multilayer wiring board 100 according to the first embodiment will be described. First, the process of manufacturing the core substrate 1 will be described with reference to FIG. FIG. 2 is an explanatory view showing an example of the method of manufacturing the core substrate of the present invention.

(Fabrication of core substrate 1)
First, through holes 3 for electrically connecting the front and back surfaces are formed in a core resin 1' having copper foils 2 attached on both sides thereof by a drill or the like (FIG. 2(a)).

Next, a conductor layer 23 is formed on the surface of the copper foil 2 and the walls of the through holes 3 by electroless plating and electrolytic plating (FIG. 2(b)). In the electroless plating of the conductor layer 23, the same material as the seed layer 13a can be used. Also, in electrolytic plating of the conductor layer 23, the same material as that of the plating layer 13b can be used.

Next, the inside of the through-hole 3 is filled with a hole-filling resin 4. - 特許庁Unnecessary filling resin 4 protruding from the through hole 3 is removed by buffing or the like (FIG. 2(c)). In addition, in the process shown in FIG. 2(b), when the through holes 3 are completely filled with plating, this process is omitted.

Next, a conductor layer 33 is formed on the entire surface by electroless plating and electrolytic plating (FIG. 2(d)). In the process shown in FIG. 2(b), this process may be omitted when the through holes 3 are completely filled with plating.

Next, a resist is applied or laminated, and a resist pattern 6 is formed by photolithography on portions of the conductor layers 23 and 33 to be left as conductors (FIG. 2(e)).

Next, portions of the conductor layers 23 and 33 where the resist pattern 6 is not formed are removed by etching to form a plurality of conductors (FIG. 2(f)).

Next, by removing the resist pattern 6, the core substrate 1 having the pad portions 43 is formed (FIG. 2(g)). Pad portion 43 is electrically connected to a wiring substrate laminated on core substrate 1 .

Although the manufacturing method of the core substrate 1 has been described above, this is an example and other methods may be used. Next, a process of laminating a plurality of wiring boards on the manufactured core substrate 1 to manufacture the multilayer wiring board 100 will be described. Note that the wiring boards are laminated on both sides of the core board 1 .

3 and 4 are explanatory diagrams showing the multilayer wiring board and manufacturing method according to the first embodiment of the present invention. Note that the core resin 1' of the core substrate 1 is omitted in the subsequent explanatory diagrams of the manufacturing method.

(Preparation of multilayer wiring board)
First, the first insulating resin layer 11 is formed on the core substrate 1 .

Next, a via opening 8 is formed by a laser such as UV or CO ₂ in the case of thermosetting resin, or by photolithography in the case of photosensitive resin, so that the pad portion 43 for electrical connection in the lower layer is exposed. (Fig. 3(a)).

Next, a seed layer 13a is formed on the top surface of the first insulating resin layer 11, the wall surface of the via opening 8, and the pad portion 43 corresponding to the bottom surface of the via opening 8 by electroless plating or sputtering (FIG. 3B). .

Next, a resist is applied or laminated on the seed layer 13a and exposed and developed to form a resist pattern 16 corresponding to the pattern of the plating layer 13b (FIG. 3(c)).

Next, a plating layer 13b is formed by electroplating on the seed layer 13a on which the resist pattern 16 is formed (FIG. 3(d)).

Next, the resist pattern 16 is formed so that the resist pattern 16 with a height of 10% or more and 90% or less of the total thickness of the seed layer 13a and the plating layer 13b (thickness of the conductor layer 13) remains on the seed layer 13a. A portion is removed (FIG. 3(e)). The lower the height of the resist pattern 16 after etching, the larger the area of the adhesion layer 14 on the side surface of the conductor 13'. As the etching method, dry etching with high etching anisotropy in the height direction, or a method of using a melt-peeling type resist and melting and stripping only the upper portion with a stripping solution is preferable.

Next, an adhesion layer 14 is formed on the surface of the remaining resist pattern 16 and the surface of the plated layer 13b (FIG. 3(f)). The adhesion layer 14 can be formed by dipping, spraying, sputtering, or the like.

Next, the remaining resist pattern 16 and the adhesion layer 14 on its surface are removed (FIG. 3(g)).

Next, the seed layer 13a exposed by removing the remaining resist pattern 16 (the seed layer 13a not covered with the plating layer 13b) is removed by etching (FIG. 3(h)). At this time, since the portion of the plating layer 13b where the adhesion layer 14 is formed is protected from the etching solution, the surface roughness is lower than that of the portion where the adhesion layer 14 is not formed (the same surface roughness as after plating). roughness is maintained).

Next, the second insulating resin layer 12 is laminated on the first insulating resin layer 11 so as to cover the conductor 13', the adhesion layer 14, and the first insulating resin layer 11 (Fig. 1). Note that this step is omitted when the circuits of the desired number of layers are formed.

The steps described above with reference to FIGS. 3(a) to 3(h) are repeated until circuits with a desired number of layers are formed (FIG. 4(i)). In the formation of the conductor layers 13 after the n-th layer (n is a natural number of 2 or more), the (n−1)-th second insulating resin layer 12 formed in FIG. 3(a) to 3(h) shall be read as the first insulating resin layer 11. FIG.

After forming a desired number of layers of circuits, a solder resist layer 17 is formed as the outermost layer by coating or lamination, and solder resist openings 18 are formed on the pads 53 by photolithography or the like (FIG. 4(j)). The solder resist layer 17 is, for example, a photosensitive epoxy resin and may contain an inorganic filler. When a non-photosensitive thermosetting resin is used, the solder resist openings 18 are formed by UV laser, _CO2 laser, photolithography, or the like.

Next, the adhesion layer 14 in the solder resist opening 18 is removed by plasma or the like (FIG. 4(k)). 4(j), when the solder resist openings 18 are formed by laser, this step can be omitted because the adhesion layer 14 in the openings is also removed at the same time by the laser beam.

Next, a surface treatment layer 19 is formed on the pad portions 53 in the solder resist openings 18 (FIG. 4(l)).

Next, a multilayer wiring board 100 can be formed by forming solder bumps 20 in the solder resist openings 18 (FIG. 4(m)). The solder bumps 20 can be formed by screen printing when solder paste is used, and when solder balls are used, flux is screen-printed, the solder balls are mounted by ball transfer, and the solder balls are melted by reflow.

The method of manufacturing the multilayer wiring board 100 by laminating the wiring board on the core board 1 has been described above. A multilayer wiring board 100 that does not have the core substrate 1 may be used.

FIG. 5 shows an example of a mounting state, and shows a state (semiconductor device) in which a semiconductor element 34 (silicon chip) is mounted on the multilayer wiring board 100 . In this semiconductor device, electrode terminals of the semiconductor element 34 are electrically connected to corresponding pads 53 on the multilayer wiring board 100 via conductive materials such as solder bumps 20 (flip chip mounting). Furthermore, the gap between the mounted semiconductor element 34 and the multilayer wiring board 100 is filled with an underfill resin 35 such as a thermosetting epoxy resin, and the semiconductor element 34 and the multilayer wiring board 100 are separated by heat curing. A mechanical connection with is ensured.

On the other hand, solder bumps 20 used as external connection terminals are joined to pad portions 53 exposed from the solder resist layer 17 on the side opposite to the mounting surface of the semiconductor element 34 . The multilayer wiring board 100 is mounted on a motherboard or the like through the solder bumps 20 .

As described above, in the multilayer wiring board 100 according to the first embodiment, the film thickness of the conductor 13' is The adhesion layer 14 is formed in the range of 10% or more and 90% or less of . Therefore, the adhesion between the conductor layer 13 and the insulating resin layer is enhanced.

Also, the adhesion layer 14 is not formed on the first insulating resin layer between the adjacent conductors 13'. Therefore, the multilayer wiring board 100 with high insulation reliability can be provided.

<Second embodiment>
A second embodiment will be described with reference to FIGS. 6 and 7. FIG. FIG. 6 is an enlarged cross-sectional view showing part of a multilayer wiring board according to a second embodiment of the present invention. Note that the second embodiment will be described with a focus on differences from the first embodiment.

In the multilayer wiring board 100 according to the second embodiment, the width of the seed layer 13a in the plane direction of the first insulating resin layer 11 is larger than the width of the plating layer 13b. Further, the adhesion layer 14 is formed on the entire upper surface of the plating layer 13b (conductor 13') and the entire side surface of the plating layer 13b, and is formed on the portion of the upper surface of the seed layer 13a where the plating layer 13b is not laminated. be done. That is, in the multilayer wiring board 100 according to the second embodiment, the adhesion layer 14 is formed on the conductor 13' other than the end surface of the seed layer 13a. The adhesion layer 14 is not formed on the first insulating resin layer 11 between the adjacent conductors 13'.

A method for manufacturing the multilayer wiring board 100 according to the second embodiment will be described. Note that the core substrate 1 can be manufactured by the same method as in the first embodiment, so the description thereof is omitted.

FIG. 7 is an explanatory view showing a multilayer wiring board and manufacturing method according to a second embodiment of the present invention.

(Preparation of multilayer wiring board)
First, the first insulating resin layer 11 is formed on the core substrate 1 .

Next, a via opening 8 is formed by a laser such as UV or CO ₂ in the case of thermosetting resin, or by photolithography in the case of photosensitive resin, so as to expose the pad portion 43 for electrical connection in the lower layer. (Fig. 7(a)).

Next, a seed layer 13a is formed on the top surface of the first insulating resin layer 11, the wall surface of the via opening 8, and the pad portion 43 corresponding to the bottom surface of the via opening 8 by electroless plating or sputtering (FIG. 7B). .

Next, a resist pattern 16 is applied or laminated on the seed layer 13a and exposed and developed to form a resist pattern 16 corresponding to the pattern of the plating layer 13b (FIG. 7(c)).

Next, a plating layer 13b is formed by electroplating on the seed layer 13a on which the resist pattern 16 is formed (FIG. 7(d)).

Next, a part of the resist pattern 16 is removed by isotropic dry etching such as _O2 ashing so that the width of the resist pattern 16 in the surface direction of the first insulating resin layer 11 is reduced ( FIG. 7(e)). Specifically, the portion of the resist pattern 16 in contact with the side surface of the plating layer 13b is removed until it reaches the seed layer 13a, thereby exposing a portion of the seed layer 13a. The width of the lower surface of the resist after etching is 50 to 90% of the plating pattern gap, that is, the distance between the lower surface of the resist after etching and the plating layer 13b is 5 to 5 of the distance between the adjacent plating layers 13b. 25% is preferred. As the distance between the adjacent conductors 13' increases, the insulation reliability improves. 10% is more preferred.

Next, an adhesion layer 14 is formed on the surface of the remaining resist pattern 16, the surface of the plated layer 13b, and the exposed surface of the seed layer 13a (FIG. 7(f)). The adhesion layer 14 can be formed by dipping, spraying, sputtering, or the like.

Next, the remaining resist pattern 16 and the adhesion layer 14 on its surface are removed (FIG. 7(g)).

Next, the seed layer 13a exposed by removing the remaining resist pattern 16 (the seed layer 13a not covered with the plating layer 13b) is removed by etching (FIG. 7(h)). At this time, since the portion of the seed layer 13a where the adhesion layer 14 is formed remains, the width of the seed layer 13a becomes wider than that of the plating layer 13b (FIG. 6). In addition, since the portion of the plating layer 13b where the adhesion layer 14 is formed is protected from the etching solution, the surface roughness is lower than that of the portion where the adhesion layer 14 is not formed (surface roughness equivalent to that after plating). degree).

Next, the second insulating resin layer 12 is laminated on the first insulating resin layer 11 so as to cover the conductor 13 ′, the adhesion layer 14 and the first insulating resin layer 11 . Note that this step is omitted when the circuits of the desired number of layers are formed.

The steps described above with reference to FIGS. 7(a) to 7(h) are repeated until circuits with a desired number of layers are formed. In the formation of the conductor layers 13 after the n-th layer (n is a natural number of 2 or more), the (n−1)-th second insulating resin layer 12 formed in FIG. 7(a) to 7(h) shall be read as the first insulating resin layer 11. FIG.

After forming a desired number of layers of circuits, the same steps as in the first embodiment can be carried out to fabricate the multilayer wiring board 100 of the second embodiment.

As described above, in the multilayer wiring board 100 according to the second embodiment, the adhesion layer 14 is formed on the conductor 13' other than the end surface of the seed layer 13a. Therefore, the area of the adhesion layer 14 can be made larger than that of the multilayer wiring board 100 of the first embodiment, and the adhesion between the conductor layer 13 and the insulating resin layer is improved.

Also, the adhesion layer 14 is not formed on the first insulating resin layer between the adjacent conductors 13'. Therefore, the multilayer wiring board 100 with high insulation reliability can be provided.

<Third Embodiment>
A third embodiment will be described with reference to FIGS. 8 and 9. FIG. FIG. 8 is an enlarged cross-sectional view showing part of a multilayer wiring board according to a third embodiment of the present invention. Note that the third embodiment will be described with a focus on differences from the first embodiment.

In the multilayer wiring board 100 according to the third embodiment, the adhesion layer 14 is formed only on the upper surface of the plating layer 13b.

A method for manufacturing the multilayer wiring board 100 according to the third embodiment will be described. Note that the core substrate 1 can be manufactured by the same method as in the first embodiment, so the description thereof is omitted.

FIG. 9 is an explanatory view showing a multilayer wiring board and manufacturing method according to a third embodiment of the present invention.

(Preparation of multilayer wiring board)
First, the first insulating resin layer 11 is formed on the core substrate 1 .

Next, a via opening 8 is formed by a laser such as UV or CO ₂ in the case of thermosetting resin, or by photolithography in the case of photosensitive resin, so that the pad portion 43 for electrical connection in the lower layer is exposed. (Fig. 9(a)).

Next, a seed layer 13a is formed by electroless plating or sputtering on the top surface of the first insulating resin layer 11, the wall surface of the via opening 8, and the pad portion 43 corresponding to the bottom surface of the via opening 8 (FIG. 9B). .

Next, a resist pattern 16 corresponding to the pattern of the plating layer 13b is formed by coating or laminating a resist pattern 16 on the seed layer 13a and then exposing and developing it (FIG. 9(c)).

Next, on the seed layer 13a on which the resist pattern 16 is formed, a plated layer 13b is formed by electroplating to have a film thickness substantially equal to that of the resist pattern 16 (FIG. 9D).

Next, an adhesion layer 14 is formed on the surface of the resist pattern 16 and the surface of the plating layer 13b (FIG. 9(e)). The adhesion layer 14 can be formed by dipping, spraying, sputtering, or the like.

Next, the resist pattern 16 and the adhesion layer 14 on its surface are removed (FIG. 9(f)).

Next, the seed layer 13a exposed by removing the resist pattern 16 (the seed layer 13a not covered with the plating layer 13b) is removed by etching (FIG. 9G). At this time, since the portion of the plating layer 13b where the adhesion layer 14 is formed is protected from the etching solution, the surface roughness is lower than that of the portion where the adhesion layer 14 is not formed (the same surface roughness as after plating). maintain roughness).

Next, the second insulating resin layer 12 is laminated on the first insulating resin layer 11 so as to cover the conductor 13 ′, the adhesion layer 14 and the first insulating resin layer 11 . Note that this step is omitted when the circuits of the desired number of layers are formed.

The steps described above with reference to FIGS. 9(a) to 9(g) are repeated until circuits with a desired number of layers are formed. In forming the conductor layers 13 after the n-th layer (n is a natural number of 2 or more), the (n−1)-th second insulating resin layer 12 formed in FIG. (a) to FIG. 9(g) shall be read as the first insulating resin layer 11 in the description.

After forming a desired number of layers of circuits, the same steps as those of the first embodiment are performed, whereby the multilayer wiring board 100 of the third embodiment can be produced.

As described above, in the multilayer wiring board 100 according to the third embodiment, the adhesion layer 14 is formed only on the upper surfaces of the conductors 13'. Therefore, it is possible to provide the multilayer wiring board 100 with high insulation reliability while ensuring the adhesion between the conductor layer 13 and the insulating resin layer.

INDUSTRIAL APPLICABILITY The present invention can be used as a multilayer wiring board used for mounting electronic components such as semiconductor elements (chips).

11 First insulating resin layer 12 Second insulating resin layer 13 Conductor layer 13' Conductor 13a Seed layer 13b Plating layer 14 Adhesion layer 16 Resist pattern 100 Multilayer wiring board

Claims (8)

a first insulating resin layer;
A conductor layer having a seed layer laminated on the first insulating resin layer and a plating layer laminated on a surface of the seed layer opposite to the first insulating resin layer, and forming a plurality of conductors. and,
an adhesion layer formed on part of the surface of the conductor;
a second insulating resin layer covering the conductor, the adhesion layer, and the first insulating resin layer;
The adhesion layer is
formed on at least the upper surface of the plating layer,
A multilayer wiring board not formed on the first insulating resin layer between the adjacent conductors. 2. The multilayer wiring board according to claim 1, wherein said adhesion layer is further formed in a range of 10% or more and 90% or less of the film thickness of said conductor from an upper edge of said side surface of said conductor. . the width of the seed layer in the surface direction of the first insulating resin layer is larger than the width of the plating layer;
2. The multilayer wiring board according to claim 1, wherein said adhesion layer is further formed on a side surface of said plating layer and a portion of an upper surface of said seed layer where said plating layer is not laminated. 2. The multilayer wiring board according to claim 1, wherein said adhesion layer is formed only on an upper surface of said plating layer. 5. The multilayer wiring according to claim 1, wherein the surface roughness of a portion of the surface of the conductor that is in contact with the adhesion layer is smaller than that of a portion of the surface of the conductor that is not in contact with the adhesion layer. substrate. forming a seed layer on the first insulating resin layer;
forming a resist pattern on the seed layer;
forming a plating layer on the seed layer on which the resist pattern is formed;
removing part of the resist pattern so that the resist pattern with a height of 10% or more and 90% or less of the total thickness of the seed layer and the plating layer remains on the seed layer;
forming an adhesion layer on the surface of the remaining resist pattern and the surface of the plating layer;
removing the remaining resist pattern and the adhesion layer on its surface;
removing the seed layer exposed by removing the remaining resist pattern;
A method of manufacturing a multilayer wiring board, comprising: forming a second insulating resin layer covering the seed layer, the plating layer, the adhesion layer, and the first insulating resin layer. forming a seed layer on the first insulating resin layer;
forming a resist pattern on the seed layer;
forming a plating layer on the seed layer on which the resist pattern is formed;
A portion of the resist pattern in contact with the side surface of the plating layer is removed to reach the seed layer so that the width of the resist pattern in the surface direction of the first insulating resin layer is reduced. exposing a portion;
forming an adhesion layer on the surface of the plating layer, the surface of the remaining resist pattern, and the exposed surface of the seed layer;
removing the remaining resist pattern and the adhesion layer on its surface;
removing the seed layer exposed by removing the remaining resist pattern;
A method of manufacturing a multilayer wiring board, comprising: forming a second insulating resin layer covering the seed layer, the plating layer, the adhesion layer, and the first insulating resin layer. forming a seed layer on the first insulating resin layer;
forming a resist pattern on the seed layer;
a step of forming a plating layer on the seed layer on which the resist pattern is formed to have a film thickness substantially equal to that of the resist pattern;
forming an adhesion layer on the surface of the resist pattern and the surface of the plating layer;
removing the resist pattern and the adhesion layer on its surface;
removing the seed layer exposed by removing the resist pattern;
A method of manufacturing a multilayer wiring board, comprising: forming a second insulating resin layer covering the seed layer, the plating layer, the adhesion layer, and the first insulating resin layer.