Nothing Special   »   [go: up one dir, main page]

JP2022089962A - Mechanism for detecting abnormal current - Google Patents

Mechanism for detecting abnormal current Download PDF

Info

Publication number
JP2022089962A
JP2022089962A JP2022069405A JP2022069405A JP2022089962A JP 2022089962 A JP2022089962 A JP 2022089962A JP 2022069405 A JP2022069405 A JP 2022069405A JP 2022069405 A JP2022069405 A JP 2022069405A JP 2022089962 A JP2022089962 A JP 2022089962A
Authority
JP
Japan
Prior art keywords
voltage
ceramic capacitor
current
monolithic ceramic
monolithic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2022069405A
Other languages
Japanese (ja)
Other versions
JP7352209B2 (en
Inventor
知之 大谷
Tomoyuki Otani
良直 西岡
Yoshinao Nishioka
裕雄 藤井
Hiroo Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP2022069405A priority Critical patent/JP7352209B2/en
Publication of JP2022089962A publication Critical patent/JP2022089962A/en
Application granted granted Critical
Publication of JP7352209B2 publication Critical patent/JP7352209B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/002Details
    • H01G4/018Dielectrics
    • H01G4/06Solid dielectrics
    • H01G4/08Inorganic dielectrics
    • H01G4/12Ceramic dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01GCAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00Fixed capacitors; Processes of their manufacture
    • H01G4/30Stacked capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a mechanism for detecting an abnormal current, which can detect new cracks that occur during the inspection of structural defects.
SOLUTION: A mechanism for measuring an element body with multiple internal electrodes includes a power supply and a circuit to apply a voltage and pass a limiting current to the element body, the voltage is higher than a rated voltage flowing through the element body, the current flowing through the element body is lower than the limiting current, and an abnormal current flowing through the element body is detected during the entire period in which the voltage is applied.
SELECTED DRAWING: Figure 5
COPYRIGHT: (C)2022,JPO&INPIT

Description

本発明は、積層セラミックコンデンサの検査方法及び積層セラミックコンデンサの製造方法に関する。 The present invention relates to a method for inspecting a monolithic ceramic capacitor and a method for manufacturing a monolithic ceramic capacitor.

従来、種々の電子装置に、積層セラミックコンデンサが用いられている。積層セラミックコンデンサは、通常、セラミック素体と、セラミック素体内に配されており、セラミック部を介して対向している第1及び第2の内部電極を有する。積層セラミックコンデンサでは、セラミック素体にデラミネーションなどの構造欠陥が存在すると、電圧印加時に絶縁不良が発生する場合がある。このため、製造された積層セラミックコンデンサに対して、出荷前に、構造欠陥の有無を検査することが行われている。特許文献1では、検査方法の一例として、第1及び第2の内部電極間に高電圧を印加することにより、絶縁不良の原因となり得る構造欠陥の有無を検査する方法が提案されている。第1及び第2の内部電極間に高電圧を印加すると、構造欠陥を有する積層セラミックコンデンサは、絶縁破壊される。このため、積層セラミックコンデンサの電気抵抗が低下し、積層セラミックコンデンサを流れる電流が増大する。よって、第1及び第2の内部電極間に高電圧を印加した後に、第1及び第2の内部電極間に流れる電流をモニタリングすることにより積層セラミックコンデンサの構造欠陥を検査し得る。 Conventionally, monolithic ceramic capacitors have been used in various electronic devices. The monolithic ceramic capacitor is usually arranged in a ceramic prime field and a ceramic prime field, and has first and second internal electrodes facing each other via a ceramic portion. In a multilayer ceramic capacitor, if structural defects such as delamination are present in the ceramic prime field, insulation defects may occur when a voltage is applied. For this reason, the manufactured monolithic ceramic capacitors are inspected for structural defects before shipment. Patent Document 1 proposes, as an example of an inspection method, a method of inspecting the presence or absence of structural defects that may cause insulation defects by applying a high voltage between the first and second internal electrodes. When a high voltage is applied between the first and second internal electrodes, the multilayer ceramic capacitor having a structural defect is dielectrically broken down. Therefore, the electric resistance of the monolithic ceramic capacitor decreases, and the current flowing through the monolithic ceramic capacitor increases. Therefore, structural defects of the monolithic ceramic capacitor can be inspected by monitoring the current flowing between the first and second internal electrodes after applying a high voltage between the first and second internal electrodes.

特開2001-35758号公報Japanese Unexamined Patent Publication No. 2001-35558

しかしながら、構造欠陥を検査する際に積層セラミックコンデンサに高電圧を印加すると、電歪と呼ばれるセラミックの歪みが顕著となる。このため、積層セラミックコンデンサに新たにクラックが生じることがある。この新たに生じたクラックは、構造欠陥の検査中に生じるものであり、クラックが生じても検査中に絶縁破壊されない場合がある。しかしながら、クラックが存在すると、積層セラミックコンデンサの使用時において、クラックが進展し、絶縁不良が生じるおそれがある。従って、検査工程において生じたクラックも検出する必要がある。 However, when a high voltage is applied to the monolithic ceramic capacitor when inspecting a structural defect, the ceramic strain called electric strain becomes remarkable. Therefore, new cracks may occur in the monolithic ceramic capacitor. These newly generated cracks occur during the inspection of structural defects, and even if cracks occur, the dielectric breakdown may not occur during the inspection. However, if cracks are present, cracks may develop and insulation defects may occur when the monolithic ceramic capacitor is used. Therefore, it is necessary to detect cracks generated in the inspection process.

しかしながら、特許文献1に記載の検査方法では、構造欠陥を検査するために高電圧を印加したときに生じたクラックを検出することはできない。 However, the inspection method described in Patent Document 1 cannot detect cracks generated when a high voltage is applied to inspect structural defects.

本発明の主な目的は、構造欠陥の検査中に生じた新たなクラックも高い確実性で検出し得る積層セラミックコンデンサの検査方法を提供することにある。 A main object of the present invention is to provide a method for inspecting a multilayer ceramic capacitor, which can detect new cracks generated during inspection of structural defects with high certainty.

本発明に係る積層セラミックコンデンサの検査方法では、積層セラミックコンデンサに電圧を印加しながら、積層セラミックコンデンサに流れる電流値を測定する測定工程を行う。測定工程において異常電流が検出された積層セラミックコンデンサを異常と判定する判定工程を行う。測定工程において、構造欠陥が存在しない場合に積層セラミックコンデンサを流れる電流が予め定められた電流値を下回るように積層セラミックコンデンサに電圧を印加する。 In the method for inspecting a monolithic ceramic capacitor according to the present invention, a measurement step of measuring the current value flowing through the monolithic ceramic capacitor is performed while applying a voltage to the monolithic ceramic capacitor. A determination step of determining a multilayer ceramic capacitor in which an abnormal current is detected in the measurement step as an abnormality is performed. In the measurement step, a voltage is applied to the monolithic ceramic capacitor so that the current flowing through the monolithic ceramic capacitor is lower than a predetermined current value when there is no structural defect.

本発明に係る積層セラミックコンデンサの検査方法のある特定の局面では、測定工程において、構造欠陥が存在しない場合に積層セラミックコンデンサを流れる電流が予め定められた電流値を下回るように、積層セラミックコンデンサに印加する電圧を、積層セラミックコンデンサの定格電圧よりも高い電圧まで漸増させる。 In a specific aspect of the method for inspecting a monolithic ceramic capacitor according to the present invention, the monolithic ceramic capacitor is provided with a current flowing through the monolithic ceramic capacitor in the measurement step so that the current flowing through the monolithic ceramic capacitor falls below a predetermined current value. The applied voltage is gradually increased to a voltage higher than the rated voltage of the monolithic ceramic capacitor.

本発明に係る積層セラミックコンデンサの検査方法の別の特定の局面では、測定工程において、構造欠陥が存在しない場合に積層セラミックコンデンサを流れる電流が予め定められた電流値を下回るように、積層セラミックコンデンサに印加する電圧を、積層セラミックコンデンサの定格電圧よりも高い電圧から定格電圧以下まで漸減させる。 In another specific aspect of the method for inspecting a monolithic ceramic capacitor according to the present invention, in the measuring step, the monolithic ceramic capacitor is such that the current flowing through the monolithic ceramic capacitor is less than a predetermined current value in the absence of structural defects. The voltage applied to the capacitor is gradually reduced from a voltage higher than the rated voltage of the monolithic ceramic capacitor to a voltage below the rated voltage.

本発明に係る積層セラミックコンデンサの検査方法の他の特定の局面では、測定工程において、積層セラミックコンデンサに印加する電圧を、積層セラミックコンデンサの定格電圧よりも高い電圧まで上昇させた後に、当該電圧で保持し、その後、積層セラミックコンデンサの定格電圧以下の電圧まで低下させる。 In another specific aspect of the method for inspecting a multilayer ceramic capacitor according to the present invention, in the measuring step, the voltage applied to the multilayer ceramic capacitor is raised to a voltage higher than the rated voltage of the multilayer ceramic capacitor, and then the voltage is used. Hold and then reduce to a voltage below the rated voltage of the monolithic ceramic capacitor.

本発明に係る積層セラミックコンデンサの検査方法のさらに他の特定の局面では、測定工程において、積層セラミックコンデンサに正電圧及び負電圧の一方を印加した後に正電圧及び負電圧の他方を印加するサイクルを少なくとも一回行う。 In yet another specific aspect of the method for inspecting a monolithic ceramic capacitor according to the present invention, in the measuring step, a cycle of applying one of positive voltage and negative voltage to the monolithic ceramic capacitor and then applying the other of positive voltage and negative voltage is performed. Do it at least once.

本発明に係る積層セラミックコンデンサの製造方法では、積層セラミックコンデンサを作製する。積層セラミックコンデンサに電圧を印加しながら、積層セラミックコンデンサに流れる電流値を測定する測定工程を行う。測定工程において異常電流が検出された積層セラミックコンデンサを異常と判定する判定工程を行う。測定工程において、構造欠陥が存在しない場合に積層セラミックコンデンサを流れる電流が予め定められた電流値を下回るように積層セラミックコンデンサに電圧を印加する。 In the method for manufacturing a monolithic ceramic capacitor according to the present invention, a monolithic ceramic capacitor is manufactured. While applying a voltage to the monolithic ceramic capacitor, a measurement step of measuring the current value flowing through the monolithic ceramic capacitor is performed. A determination step of determining a multilayer ceramic capacitor in which an abnormal current is detected in the measurement step as an abnormality is performed. In the measurement step, a voltage is applied to the monolithic ceramic capacitor so that the current flowing through the monolithic ceramic capacitor is lower than a predetermined current value when there is no structural defect.

本発明によれば、構造欠陥の検査中に、新たに生じたクラックも高い確実性で検出し得る積層セラミックコンデンサの検査方法を提供することができる。 INDUSTRIAL APPLICABILITY According to the present invention, it is possible to provide a method for inspecting a multilayer ceramic capacitor capable of detecting newly generated cracks with high certainty during inspection of structural defects.

本発明の一実施形態における積層セラミックコンデンサの略図的斜視図である。It is a schematic perspective view of the monolithic ceramic capacitor in one Embodiment of this invention. 図1の線II-IIにおける略図的断面図である。FIG. 2 is a schematic cross-sectional view taken along the line II-II of FIG. 本発明の一実施形態における測定工程において積層セラミックコンデンサに印加する電圧(一点鎖線)と、積層セラミックコンデンサが良品であった場合に測定される電流(実線)とを表すグラフである。It is a graph which shows the voltage (single point chain line) applied to a laminated ceramic capacitor in the measuring process in one Embodiment of this invention, and the current (solid line) measured when a laminated ceramic capacitor is a good product. 本発明の一実施形態における測定工程において積層セラミックコンデンサに印加する電圧(一点鎖線)と、積層セラミックコンデンサに短絡不良が発生した場合に測定される電流(実線)とを表すグラフである。It is a graph which shows the voltage (single point chain line) applied to a laminated ceramic capacitor in the measuring process in one Embodiment of this invention, and the current (solid line) measured when a short circuit failure occurs in a laminated ceramic capacitor. 本発明の一実施形態における測定工程において積層セラミックコンデンサに印加する電圧(一点鎖線)と、積層セラミックコンデンサにクラックが発生した場合に測定される電流(実線)とを表すグラフである。It is a graph which shows the voltage (single point chain line) applied to a laminated ceramic capacitor in the measuring process in one Embodiment of this invention, and the current (solid line) measured when a crack occurs in a laminated ceramic capacitor. 第1の変形例における測定工程において積層セラミックコンデンサに印加する電圧(一点鎖線)を表すグラフである。It is a graph which shows the voltage (the alternate long and short dash line) applied to the laminated ceramic capacitor in the measurement process in the 1st modification. 第2の変形例における測定工程において積層セラミックコンデンサに印加する電圧(一点鎖線)を表すグラフである。It is a graph which shows the voltage (one-dot chain line) applied to a laminated ceramic capacitor in the measurement process in the 2nd modification. 第4の変形例における測定工程において積層セラミックコンデンサに印加する電圧(一点鎖線)を表すグラフである。It is a graph which shows the voltage (one-dot chain line) applied to a laminated ceramic capacitor in the measurement process in 4th modification. 第5の変形例における測定工程において積層セラミックコンデンサに印加する電圧(一点鎖線)を表すグラフである。It is a graph which shows the voltage (the alternate long and short dash line) applied to the laminated ceramic capacitor in the measurement process in the 5th modification. 第7の変形例における測定工程において積層セラミックコンデンサに印加する電圧(一点鎖線)を表すグラフである。It is a graph which shows the voltage (one-dot chain line) applied to a laminated ceramic capacitor in the measurement process in 7th modification. 第8の変形例における測定工程において積層セラミックコンデンサに印加する電圧(一点鎖線)を表すグラフである。It is a graph which shows the voltage (one-dot chain line) applied to a laminated ceramic capacitor in the measurement process in 8th modification. 第9の変形例における測定工程において積層セラミックコンデンサに印加する電圧(一点鎖線)を表すグラフである。It is a graph which shows the voltage (one-dot chain line) applied to a laminated ceramic capacitor in the measurement process in 9th modification.

以下、本発明を実施した好ましい形態の一例について説明する。但し、下記の実施形態は、単なる例示である。本発明は、下記の実施形態に何ら限定されない。 Hereinafter, an example of a preferred embodiment of the present invention will be described. However, the following embodiments are merely examples. The present invention is not limited to the following embodiments.

また、実施形態等において参照する各図面において、実質的に同一の機能を有する部材は同一の符号で参照することとする。また、実施形態等において参照する図面は、模式的に記載されたものである。図面に描画された物体の寸法の比率などは、現実の物体の寸法の比率などとは異なる場合がある。図面相互間においても、物体の寸法比率等が異なる場合がある。具体的な物体の寸法比率等は、以下の説明を参酌して判断されるべきである。 Further, in the drawings referred to in the embodiments and the like, the members having substantially the same function are referred to by the same reference numerals. Further, the drawings referred to in the embodiments and the like are schematically described. The ratio of the dimensions of the object drawn in the drawing may differ from the ratio of the dimensions of the actual object. The dimensional ratios of objects may differ between the drawings. The specific dimensional ratio of the object should be determined in consideration of the following explanation.

図1は、本実施形態における積層セラミックコンデンサの略図的斜視図である。図2は、図1の線II-IIにおける略図的断面図である。まず、図1及び図2を参照しながら、検査対象となる積層セラミックコンデンサの一例について説明する。本発明において、積層セラミックコンデンサは、以下に説明する積層セラミックコンデンサ1に特に限定されない。本発明において、積層セラミックコンデンサは、セラミック素体を有するものである限りにおいて特に限定されない。 FIG. 1 is a schematic perspective view of a multilayer ceramic capacitor in the present embodiment. FIG. 2 is a schematic cross-sectional view taken along the line II-II of FIG. First, an example of a multilayer ceramic capacitor to be inspected will be described with reference to FIGS. 1 and 2. In the present invention, the monolithic ceramic capacitor is not particularly limited to the monolithic ceramic capacitor 1 described below. In the present invention, the monolithic ceramic capacitor is not particularly limited as long as it has a ceramic prime field.

(積層セラミックコンデンサ1の構成)
図1及び図2に示されるように、積層セラミックコンデンサ1は、セラミック素体10を備えている。セラミック素体10は、略直方体状である。セラミック素体10は、第1及び第2の主面10a,10bと、第1及び第2の側面10c,10dと、第1及び第2の端面10e,10f(図2を参照)とを有する。第1及び第2の主面10a,10bは、それぞれ、長さ方向L及び幅方向Wに沿って延びている。第1の主面10aと第2の主面10bとは、互いに平行である。第1及び第2の側面10c,10dは、それぞれ、長さ方向L及び厚み方向Tに沿って延びている。第1の側面10cと第2の側面10dとは、互いに平行である。第1及び第2の端面10e,10fは、それぞれ、幅方向W及び厚み方向Tに沿って延びている。第1の端面10eと第2の端面10fとは互いに平行である。
(Structure of Multilayer Ceramic Capacitor 1)
As shown in FIGS. 1 and 2, the monolithic ceramic capacitor 1 includes a ceramic prime field 10. The ceramic prime field 10 has a substantially rectangular parallelepiped shape. The ceramic prime field 10 has first and second main surfaces 10a and 10b, first and second side surfaces 10c and 10d, and first and second end surfaces 10e and 10f (see FIG. 2). .. The first and second main surfaces 10a and 10b extend along the length direction L and the width direction W, respectively. The first main surface 10a and the second main surface 10b are parallel to each other. The first and second side surfaces 10c and 10d extend along the length direction L and the thickness direction T, respectively. The first side surface 10c and the second side surface 10d are parallel to each other. The first and second end faces 10e and 10f extend along the width direction W and the thickness direction T, respectively. The first end face 10e and the second end face 10f are parallel to each other.

セラミック素体10は、例えば、誘電体セラミックを主成分とする材料により構成することができる。誘電体セラミックの具体例としては、例えば、BaTiO、CaTiO、SrTiO、CaZrOなどが挙げられる。セラミック素体10には、例えば、Mn化合物、Mg化合物、Si化合物、Co化合物、Ni化合物、希土類化合物などの副成分を適宜添加してもよい。 The ceramic prime field 10 can be made of, for example, a material containing a dielectric ceramic as a main component. Specific examples of the dielectric ceramic include BaTIO 3 , CaTIO 3 , SrTiO 3 , CaZrO 3 , and the like. Sub-components such as Mn compound, Mg compound, Si compound, Co compound, Ni compound, and rare earth compound may be appropriately added to the ceramic prime body 10.

なお、「略直方体」には、角部や稜線部が面取りされた直方体や、角部や稜線部が丸められた直方体が含まれるものとする。 The "substantially rectangular parallelepiped" includes a rectangular parallelepiped in which the corners and ridges are chamfered and a rectangular parallelepiped in which the corners and ridges are rounded.

図2に示されるように、セラミック素体10の内部には、複数の内部電極11,12が設けられている。複数の内部電極11,12は、厚み方向Tに沿って積層されている。各内部電極11,12は、長さ方向L及び幅方向Wに平行に設けられている。セラミック素体10の内部において、内部電極11と内部電極12とは、厚み方向Tに沿って交互に設けられている。厚み方向Tにおいて隣り合う内部電極11,12間には、セラミック部15が配されている。すなわち、厚み方向Tにおいて隣り合う内部電極11,12は、セラミック部15を介して対向している。 As shown in FIG. 2, a plurality of internal electrodes 11 and 12 are provided inside the ceramic prime field 10. The plurality of internal electrodes 11 and 12 are laminated along the thickness direction T. The internal electrodes 11 and 12 are provided in parallel with the length direction L and the width direction W. Inside the ceramic prime field 10, the internal electrodes 11 and 12 are alternately provided along the thickness direction T. A ceramic portion 15 is arranged between the adjacent internal electrodes 11 and 12 in the thickness direction T. That is, the adjacent internal electrodes 11 and 12 in the thickness direction T face each other via the ceramic portion 15.

内部電極11は、第1の端面10eに引き出されている。第1の端面10eの上には、外部電極13が設けられている。外部電極13は、内部電極11と電気的に接続されている。 The internal electrode 11 is drawn out to the first end face 10e. An external electrode 13 is provided on the first end surface 10e. The external electrode 13 is electrically connected to the internal electrode 11.

内部電極12は、第2の端面10fに引き出されている。第2の端面10fの上には、外部電極14が設けられている。外部電極14は、内部電極12と電気的に接続されている。 The internal electrode 12 is drawn out to the second end face 10f. An external electrode 14 is provided on the second end surface 10f. The external electrode 14 is electrically connected to the internal electrode 12.

内部電極11,12及び外部電極13,14は、例えば、Ni,Cu,Ag,Pd,Au,Ag-Pd合金などの適宜の導電材料により構成することができる。 The internal electrodes 11 and 12 and the external electrodes 13 and 14 can be made of an appropriate conductive material such as Ni, Cu, Ag, Pd, Au or Ag—Pd alloy.

(積層セラミックコンデンサ1の製造方法)
積層セラミックコンデンサ1の製造に際しては、まず、積層セラミックコンデンサ1を作製する。その後、下記の検査方法による検査を行う。その検査結果を踏まえ、良品と不良品とに選別する。このようにすることにより、絶縁不良品や検査中に新たに生じたクラックを有する積層セラミックコンデンサの割合が低い、複数の積層セラミックコンデンサを製造することができる。
(Manufacturing method of multilayer ceramic capacitor 1)
When manufacturing the monolithic ceramic capacitor 1, first, the monolithic ceramic capacitor 1 is manufactured. After that, the inspection is performed by the following inspection method. Based on the inspection results, we will sort out non-defective products and defective products. By doing so, it is possible to manufacture a plurality of multilayer ceramic capacitors having a low proportion of defective insulating products and multilayer ceramic capacitors having cracks newly generated during inspection.

(積層セラミックコンデンサ1の検査方法)
本実施形態における積層セラミックコンデンサ1の検査方法では、検査前に生じていた構造欠陥を有する積層セラミックコンデンサの判別だけでなく、検査中に新たに生じたクラックも高い確実性で検出することができる。
(Inspection method for multilayer ceramic capacitor 1)
In the inspection method of the monolithic ceramic capacitor 1 in the present embodiment, not only the monolithic ceramic capacitor having a structural defect that occurred before the inspection but also the crack newly generated during the inspection can be detected with high certainty. ..

具体的には、積層セラミックコンデンサ1に電圧を印加しながら、積層セラミックコンデンサ1に流れる電流値を測定する(測定工程)。測定工程において、異常電流が検出された積層セラミックコンデンサ1を異常(不良品)と判断する(判定工程)。測定工程において、積層セラミックコンデンサ1に構造欠陥が存在しない場合に積層セラミックコンデンサ1を流れる電流が予め定められた電流値(制限電流値)を下回るように積層セラミックコンデンサ1に電圧を印加する。予め定められた電流値は、例えば、10mA、30mA、50mAなどの値である。予め定められた電流値は、検査に用いられる電源や回路上に設けられた過電流を防止する機構により設定された電流の制限値であることが好ましい。 Specifically, the current value flowing through the monolithic ceramic capacitor 1 is measured while applying a voltage to the monolithic ceramic capacitor 1 (measurement step). In the measurement step, the monolithic ceramic capacitor 1 in which the abnormal current is detected is determined to be abnormal (defective product) (determination step). In the measurement step, a voltage is applied to the monolithic ceramic capacitor 1 so that the current flowing through the monolithic ceramic capacitor 1 is lower than a predetermined current value (current limit value) when there is no structural defect in the monolithic ceramic capacitor 1. The predetermined current value is, for example, a value such as 10 mA, 30 mA, or 50 mA. The predetermined current value is preferably a current limit value set by a power source used for inspection or a mechanism for preventing overcurrent provided on the circuit.

例えば、積層セラミックコンデンサに印加する電圧を一気に上昇させた場合は、積層セラミックコンデンサに大電流が流れる。このため、積層セラミックコンデンサ1に流れる電流が制限電流値に達する場合がある。一方、本実施形態では、積層セラミックコンデンサ1に印加する電圧を、積層セラミックコンデンサ1の定格電圧よりも低い電圧(例えば、0V)から、積層セラミックコンデンサ1の定格電圧よりも高い電圧(V1)まで漸増させる。また、積層セラミックコンデンサ1に印加する電圧を、積層セラミックコンデンサ1の定格電圧よりも高い電圧(V1)から積層セラミックコンデンサ1の定格電圧よりも低い電圧(例えば、0V)まで漸減させる。より具体的には、本実施形態では、積層セラミックコンデンサ1に印加する電圧を、積層セラミックコンデンサ1の定格電圧よりも低い電圧(例えば、0V)から、積層セラミックコンデンサ1の定格電圧よりも高い電圧(V1)まで漸増させる。その後、積層セラミックコンデンサ1に印加する電圧をV1で所定の時間保持し、その後、積層セラミックコンデンサ1に印加する電圧を、積層セラミックコンデンサ1の定格電圧よりも高い電圧(V1)から積層セラミックコンデンサ1の定格電圧よりも低い電圧(例えば、0V)まで漸減させる。このため、積層セラミックコンデンサ1に構造欠陥が存在しない場合に積層セラミックコンデンサ1を流れる電流が予め定められた電流値(制限電流値)を下回る。 For example, when the voltage applied to the monolithic ceramic capacitor is increased at once, a large current flows through the monolithic ceramic capacitor. Therefore, the current flowing through the monolithic ceramic capacitor 1 may reach the limit current value. On the other hand, in the present embodiment, the voltage applied to the multilayer ceramic capacitor 1 ranges from a voltage lower than the rated voltage of the multilayer ceramic capacitor 1 (for example, 0V) to a voltage higher than the rated voltage of the multilayer ceramic capacitor 1 (V1). Gradually increase. Further, the voltage applied to the multilayer ceramic capacitor 1 is gradually reduced from a voltage higher than the rated voltage of the multilayer ceramic capacitor 1 (V1) to a voltage lower than the rated voltage of the multilayer ceramic capacitor 1 (for example, 0V). More specifically, in the present embodiment, the voltage applied to the multilayer ceramic capacitor 1 is changed from a voltage lower than the rated voltage of the multilayer ceramic capacitor 1 (for example, 0V) to a voltage higher than the rated voltage of the multilayer ceramic capacitor 1. Gradually increase to (V1). After that, the voltage applied to the laminated ceramic capacitor 1 is held by V1 for a predetermined time, and then the voltage applied to the laminated ceramic capacitor 1 is changed from a voltage (V1) higher than the rated voltage of the laminated ceramic capacitor 1 to the laminated ceramic capacitor 1. The voltage is gradually reduced to a voltage lower than the rated voltage of (for example, 0V). Therefore, when the multilayer ceramic capacitor 1 does not have a structural defect, the current flowing through the multilayer ceramic capacitor 1 is lower than a predetermined current value (limit current value).

上記のような電圧の印加を行った場合、積層セラミックコンデンサ1に構造欠陥がなければ、積層セラミックコンデンサ1を流れる電流は、図3の実線で示すグラフのようになる。すなわち、まず、積層セラミックコンデンサ1に対して電圧の印加が開始されると、積層セラミックコンデンサ1への充電が開始する。このため、積層セラミックコンデンサ1を流れる電流値が増大する。図3においては、電圧を直線的に漸増させている。その後、積層セラミックコンデンサ1のDCバイアス特性に従って電流が漸減する。印加電圧が一定の状態では、積層セラミックコンデンサ1の充電がさらに進み、電流はさらに漸減する。一方、電圧が漸減すると、放電が起こるため、正逆が反対方向の電流が流れる。図3においては、電圧を直線的に漸減させている。 When the voltage as described above is applied and there is no structural defect in the multilayer ceramic capacitor 1, the current flowing through the multilayer ceramic capacitor 1 is as shown in the graph shown by the solid line in FIG. That is, first, when the application of the voltage to the monolithic ceramic capacitor 1 is started, the charge to the monolithic ceramic capacitor 1 is started. Therefore, the current value flowing through the monolithic ceramic capacitor 1 increases. In FIG. 3, the voltage is linearly and gradually increased. After that, the current gradually decreases according to the DC bias characteristic of the monolithic ceramic capacitor 1. When the applied voltage is constant, the multilayer ceramic capacitor 1 is further charged, and the current is further gradually reduced. On the other hand, when the voltage gradually decreases, discharge occurs, so current flows in the opposite direction. In FIG. 3, the voltage is linearly gradually reduced.

図4に、測定工程において積層セラミックコンデンサに印加される電圧と、積層セラミックコンデンサに短絡不良が発生した場合に測定される電流とを表すグラフを示す。例えば、測定工程の途中で積層セラミックコンデンサ1に短絡不良が発生すると、積層セラミックコンデンサ1を流れる電流値が制限電流値に達し、積層セラミックコンデンサ1への電圧印加が終了するまで、制限電流値の電流が流れる。図4に示す例では、時間t1において短絡不良が発生したため、時間t1までは、図3に示す場合と同様に電流値が変化するが、時間t1から積層セラミックコンデンサ1への電圧印加が終了する時間t2までは、積層セラミックコンデンサ1に制限電流値の電流が流れ続ける。仮に、測定工程の実施前から積層セラミックコンデンサ1に短絡不良が発生している場合は、測定工程の全期間において積層セラミックコンデンサ1に制限電流値の電流が流れ続ける。 FIG. 4 shows a graph showing the voltage applied to the monolithic ceramic capacitor in the measurement process and the current measured when a short circuit failure occurs in the monolithic ceramic capacitor. For example, if a short-circuit failure occurs in the multilayer ceramic capacitor 1 in the middle of the measurement process, the current value flowing through the multilayer ceramic capacitor 1 reaches the limiting current value, and the current limiting current value is reached until the voltage application to the multilayer ceramic capacitor 1 is completed. Current flows. In the example shown in FIG. 4, since a short-circuit failure occurred at time t1, the current value changes as in the case shown in FIG. 3 until time t1, but the voltage application to the multilayer ceramic capacitor 1 ends from time t1. Until the time t2, the current of the limiting current value continues to flow in the multilayer ceramic capacitor 1. If a short-circuit defect has occurred in the monolithic ceramic capacitor 1 even before the measurement step is performed, the current of the limiting current value continues to flow in the monolithic ceramic capacitor 1 during the entire period of the measurement step.

このため、測定工程において、測定された電流値が、制限電流値に達した場合は、測定対象である積層セラミックコンデンサ1に短絡不良があるものと判断することができる。 Therefore, when the measured current value reaches the limit current value in the measurement step, it can be determined that the multilayer ceramic capacitor 1 to be measured has a short-circuit defect.

図5に、測定工程において積層セラミックコンデンサに印加する電圧と、積層セラミックコンデンサに短絡不良は発生しなかったものの、クラックが発生した場合に測定される電流とを表すグラフを示す。図5に示される例では、時間t3において、図3に示される良品の場合とは異なり、積層セラミックコンデンサ1を流れる電流値の一時的な増大が生じている。すなわち、異常電流が検出されている。本発明者らが鋭意研究した結果、このような異常電流が検出された積層セラミックコンデンサ1には、クラックが発生していることが見いだされた。よって、積層セラミックコンデンサ1を流れる電流が制限電流値に至らないものの、図5に示されるような異常電流が発生した場合は、測定対象である積層セラミックコンデンサ1にクラックが発生したものと判断することができる。なお、このような異常電流が生じている区間において、積層セラミックコンデンサを流れる電流が制限電流値に達することはあり得る。 FIG. 5 shows a graph showing the voltage applied to the monolithic ceramic capacitor in the measurement process and the current measured when a crack occurs in the monolithic ceramic capacitor although no short circuit failure occurs. In the example shown in FIG. 5, at time t3, unlike the case of the non-defective product shown in FIG. 3, the current value flowing through the multilayer ceramic capacitor 1 temporarily increases. That is, an abnormal current is detected. As a result of diligent research by the present inventors, it was found that cracks were generated in the multilayer ceramic capacitor 1 in which such an abnormal current was detected. Therefore, if the current flowing through the monolithic ceramic capacitor 1 does not reach the current limit value, but an abnormal current as shown in FIG. 5 occurs, it is determined that a crack has occurred in the monolithic ceramic capacitor 1 to be measured. be able to. In the section where such an abnormal current is generated, the current flowing through the multilayer ceramic capacitor may reach the limit current value.

本実施形態のように、測定工程において、構造欠陥が存在しない場合に積層セラミックコンデンサ1を流れる電流が予め定められた電流値(例えば、制限電流値)を下回るように積層セラミックコンデンサ1に電圧を印加することにより、図5に示されるような異常電流を正確に検出することが可能となる。従って、絶縁不良が発生していないものの、クラックが発生した積層セラミックコンデンサ1を判別することが可能となる。よって、検査前に生じていた構造欠陥だけでなく、検査中に新たに生じたクラックも高い確実性で検出し得る。また、クラックの検出に、超音波探傷等の他の工程を必要としないため、積層セラミックコンデンサ1の測定工程に要する工数及び時間を低減することができる。 As in the present embodiment, in the measurement step, a voltage is applied to the multilayer ceramic capacitor 1 so that the current flowing through the multilayer ceramic capacitor 1 is lower than a predetermined current value (for example, a limiting current value) when there is no structural defect. By applying the current, it becomes possible to accurately detect the abnormal current as shown in FIG. Therefore, it is possible to discriminate the monolithic ceramic capacitor 1 in which cracks have occurred, although insulation defects have not occurred. Therefore, not only the structural defects that occurred before the inspection but also the cracks newly generated during the inspection can be detected with high certainty. Further, since the detection of cracks does not require another step such as ultrasonic flaw detection, the man-hours and time required for the measurement step of the multilayer ceramic capacitor 1 can be reduced.

一方、測定工程において、例えば電圧を一気に昇圧した場合は、積層セラミックコンデンサに流れる電流が制限電流値に達するため、その時点でクラックが生じたとしても、図5において観測されるような異常電流のピークは観測されない。電圧印加が開始する時間から電圧印加が終了する時間までの全区間において、積層セラミックコンデンサに流れる電流が制限電流値を下回ることが好ましい。 On the other hand, in the measurement process, for example, when the voltage is boosted at once, the current flowing through the monolithic ceramic capacitor reaches the limit current value, so even if a crack occurs at that time, the abnormal current as observed in FIG. 5 No peak is observed. It is preferable that the current flowing through the multilayer ceramic capacitor falls below the current limit value in the entire section from the time when the voltage application starts to the time when the voltage application ends.

なお、積層セラミックコンデンサ1にクラックが発生した場合に異常電流が流れる理由としては、定かではないが、クラックが発生した瞬間に積層セラミックコンデンサ1の性状が変化するためであると考えられる。 The reason why the abnormal current flows when the multilayer ceramic capacitor 1 is cracked is not clear, but it is considered that the properties of the multilayer ceramic capacitor 1 change at the moment when the crack occurs.

本発明において、「異常電流」とは、測定工程において、良品である積層セラミックコンデンサに流れる電流の変化とは異なり、一時的な増大を示す電流のことである。「異常電流」は、例えば、積層セラミックコンデンサが良品である場合には検出されない電流のピーク(正電圧の場合は極大ピーク、負電圧の場合は極小ピーク)である。通常、「異常電流」は急峻なピークとして観測され、電流の増大が観測される時間は1~300μsec程度である。この時間は、測定する積層セラミックコンデンサの静電容量などによって60μsec程度、150μsec程度、200μsec程度などと変化する。 In the present invention, the "abnormal current" is a current showing a temporary increase, unlike a change in the current flowing through a non-defective monolithic ceramic capacitor in the measurement process. The "abnormal current" is, for example, a peak of a current that is not detected when the monolithic ceramic capacitor is a good product (a maximum peak in the case of a positive voltage and a minimum peak in the case of a negative voltage). Normally, the "abnormal current" is observed as a steep peak, and the time during which the increase in current is observed is about 1 to 300 μsec. This time varies from about 60 μsec to about 150 μsec to about 200 μsec depending on the capacitance of the monolithic ceramic capacitor to be measured.

本実施形態では、積層セラミックコンデンサ1に印加する電圧を漸増させた後ないし漸減させる前に、一定の電圧で保持する時間を設ける例について説明したが、図6に示されるように、電圧を漸増させた後に、直ちに電圧を漸減させてもよい。 In the present embodiment, an example of providing a time for holding at a constant voltage after gradually increasing or gradually decreasing the voltage applied to the multilayer ceramic capacitor 1 has been described, but as shown in FIG. 6, the voltage is gradually increased. After that, the voltage may be gradually reduced immediately.

本実施形態では、電圧を漸増する速度、電圧を漸減する速度が、それぞれ一定である例について説明した。但し、本発明は、この構成に限定されない。例えば、図7及び図8に示されるように、電圧を漸増する速度、電圧を漸減する速度を、それぞれ変化させてもよい。図7及び図8に示す例では、電圧を漸増する速度を、時間と共に低くしている。図7に示す例では、電圧を漸減する速度を、時間と共に高くしている。図8に示す例では、電圧を漸減する速度を、時間と共に低くしている。 In this embodiment, an example is described in which the speed at which the voltage is gradually increased and the speed at which the voltage is gradually decreased are constant. However, the present invention is not limited to this configuration. For example, as shown in FIGS. 7 and 8, the speed at which the voltage is gradually increased and the speed at which the voltage is gradually decreased may be changed, respectively. In the examples shown in FIGS. 7 and 8, the rate at which the voltage is gradually increased is decreased with time. In the example shown in FIG. 7, the rate of gradually decreasing the voltage is increased with time. In the example shown in FIG. 8, the rate of gradually decreasing the voltage is decreased with time.

本実施形態では、電圧を漸増させた後に漸減させる例について説明したが、図9に示されるように、電圧を漸増させた後に、電圧を一気に低下させてもよい。また、電圧を一気に上昇させた後に、電圧を漸減してもよい。好ましくは、電圧を漸増させた後に漸減させる。 In the present embodiment, an example in which the voltage is gradually increased and then gradually decreased has been described, but as shown in FIG. 9, the voltage may be gradually decreased after the voltage is gradually increased. Further, the voltage may be gradually decreased after the voltage is increased at once. Preferably, the voltage is gradually increased and then gradually decreased.

図10に示されるように、定格電圧以下の電圧まで一気に昇圧した後に、電圧を漸増させ、その後、定格電圧以下の電圧まで漸減した後に、一気に電圧を低下させてもよい。このようにすることにより、クラックが発生する可能性の低い低電圧領域にかかる時間を縮め、測定工程の実施に要する時間を短縮することができる。 As shown in FIG. 10, the voltage may be boosted to a voltage below the rated voltage at once, then gradually increased, then gradually reduced to a voltage below the rated voltage, and then lowered at once. By doing so, it is possible to shorten the time required for the low voltage region where cracks are unlikely to occur, and shorten the time required to carry out the measurement step.

図11や図12に示されるように、測定工程において、積層セラミックコンデンサ1に正電圧及び負電圧の一方を印加した後に、正電圧及び負電圧の他方を印加するサイクルを少なくとも一回行ってもよい。例えば、正弦波状の電圧を積層セラミックコンデンサ1に印加してもよい。そうすることにより、積層セラミックコンデンサ1の検査中に新たに生じたクラックをさらに確実に検出することが可能となる。 As shown in FIGS. 11 and 12, in the measurement step, even if one of the positive voltage and the negative voltage is applied to the multilayer ceramic capacitor 1, the cycle of applying the other of the positive voltage and the negative voltage is performed at least once. good. For example, a sinusoidal voltage may be applied to the monolithic ceramic capacitor 1. By doing so, it becomes possible to more reliably detect cracks newly generated during the inspection of the monolithic ceramic capacitor 1.

なお、積層セラミックコンデンサ1に流れる電流を測定する電流測定部と、異常電流を検出する異常電流検出部との間に、DCカットフィルタ(ハイパスフィルタ)を配してもよい。そうすることにより、周波数の低い電流変化をカットすることができるため、異常電流の検出が容易となる。 A DC cut filter (high-pass filter) may be arranged between the current measuring unit for measuring the current flowing through the multilayer ceramic capacitor 1 and the abnormal current detecting unit for detecting the abnormal current. By doing so, it is possible to cut a low-frequency current change, so that it becomes easy to detect an abnormal current.

1…積層セラミックコンデンサ
10…セラミック素体
10a…第1の主面
10b…第2の主面
10c…第1の側面
10d…第2の側面
10e…第1の端面
10f…第2の端面
11,12…内部電極
13,14…外部電極
15…セラミック部
1 ... Multilayer ceramic capacitor 10 ... Ceramic element 10a ... First main surface 10b ... Second main surface 10c ... First side surface 10d ... Second side surface 10e ... First end surface 10f ... Second end surface 11, 12 ... Internal electrodes 13, 14 ... External electrodes 15 ... Ceramic part

Claims (5)

複数の内部電極を備えた素体を測定する機構であって、
電圧を印加し、前記素体に制限電流を流す電源および回路を備え、
前記電圧は、前記素体に流す定格電圧より高く、前記素体に流す電流は、前記制限電流より低く、
前記電圧を印加する全期間において、前記素体に流れる異常電流を検出する機構。
A mechanism for measuring prime fields with multiple internal electrodes.
It is equipped with a power supply and a circuit that applies a voltage and allows a current limiting current to flow through the prime field.
The voltage is higher than the rated voltage flowing through the prime field, and the current flowing through the prime field is lower than the limiting current.
A mechanism for detecting an abnormal current flowing through the prime field during the entire period in which the voltage is applied.
前記電流が予め定められた電流値を下回るように、前記素体に印加する電圧を、前記素体の定格電圧よりも高い電圧まで漸増させる、請求項1に記載の異常電流を検出する機構。 The mechanism for detecting an abnormal current according to claim 1, wherein the voltage applied to the prime field is gradually increased to a voltage higher than the rated voltage of the prime field so that the current falls below a predetermined current value. 前記電流が予め定められた電流値を下回るように、前記素体に印加する電圧を、前記素体の定格電圧よりも高い電圧から定格電圧以下の電圧まで漸減させる、請求項1または2に記載の異常電流を検出する機構。 The invention according to claim 1 or 2, wherein the voltage applied to the element body is gradually reduced from a voltage higher than the rated voltage of the element body to a voltage lower than the rated voltage so that the current falls below a predetermined current value. Mechanism to detect abnormal current. 前記素体に印加する電圧を、前記定格電圧よりも高い電圧まで上昇させた後に、当該電圧で保持し、その後、前記定格電圧以下の電圧まで低下させる、請求項1~3のいずれか一項に記載の異常電流を検出する機構。 One of claims 1 to 3, wherein the voltage applied to the element is increased to a voltage higher than the rated voltage, held at the voltage, and then decreased to a voltage equal to or lower than the rated voltage. A mechanism for detecting an abnormal current as described in. 前記電圧として、正電圧及び負電圧の一方を印加した後に正電圧及び負電圧の他方を印加するサイクルを少なくとも一回行う、請求項1~4のいずれか一項に記載の異常電流を検出する機構。 The abnormal current according to any one of claims 1 to 4, wherein the cycle of applying one of the positive voltage and the negative voltage and then applying the other of the positive voltage and the negative voltage is performed at least once as the voltage. mechanism.
JP2022069405A 2018-10-17 2022-04-20 Mechanism to detect abnormal current Active JP7352209B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2022069405A JP7352209B2 (en) 2018-10-17 2022-04-20 Mechanism to detect abnormal current

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018195842A JP7110902B2 (en) 2018-10-17 2018-10-17 Multilayer Ceramic Capacitor Inspection Method and Multilayer Ceramic Capacitor Manufacturing Method
JP2022069405A JP7352209B2 (en) 2018-10-17 2022-04-20 Mechanism to detect abnormal current

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2018195842A Division JP7110902B2 (en) 2018-10-17 2018-10-17 Multilayer Ceramic Capacitor Inspection Method and Multilayer Ceramic Capacitor Manufacturing Method

Publications (2)

Publication Number Publication Date
JP2022089962A true JP2022089962A (en) 2022-06-16
JP7352209B2 JP7352209B2 (en) 2023-09-28

Family

ID=70388418

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2018195842A Active JP7110902B2 (en) 2018-10-17 2018-10-17 Multilayer Ceramic Capacitor Inspection Method and Multilayer Ceramic Capacitor Manufacturing Method
JP2022069405A Active JP7352209B2 (en) 2018-10-17 2022-04-20 Mechanism to detect abnormal current

Family Applications Before (1)

Application Number Title Priority Date Filing Date
JP2018195842A Active JP7110902B2 (en) 2018-10-17 2018-10-17 Multilayer Ceramic Capacitor Inspection Method and Multilayer Ceramic Capacitor Manufacturing Method

Country Status (2)

Country Link
JP (2) JP7110902B2 (en)
KR (1) KR102253401B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023234349A1 (en) 2022-06-01 2023-12-07 富士フイルム株式会社 All-solid-state lithium-ion secondary battery and method for manufacturing all-solid-state lithium-ion secondary battery

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7415322B2 (en) * 2019-01-28 2024-01-17 ニデックアドバンステクノロジー株式会社 Capacitor inspection device and capacitor inspection method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09152455A (en) * 1995-12-01 1997-06-10 Matsushita Electric Ind Co Ltd Internal defect detector and method thereof for laminated ceramic capacitor
JP2000228338A (en) * 1999-02-04 2000-08-15 Matsushita Electric Ind Co Ltd Screening method for multilayer ceramic capacitor
JP2005223253A (en) * 2004-02-09 2005-08-18 Murata Mfg Co Ltd Method for screening laminated ceramic capacitors
JP2008180546A (en) * 2007-01-23 2008-08-07 Showa Denki Kk Withstand voltage test method for three-terminal capacitor, and withstand voltage tester thereof
WO2016125679A1 (en) * 2015-02-03 2016-08-11 株式会社ジェイ・イー・ティ Electricity storage device production method, structure body inspection device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227826A (en) * 1995-02-20 1996-09-03 Matsushita Electric Ind Co Ltd Method for screening laminated ceramic capacitor
JP2000124088A (en) * 1998-10-13 2000-04-28 Matsushita Electric Ind Co Ltd Method for sorting stacked ceramic capacitor
JP2001035758A (en) 1999-07-15 2001-02-09 Murata Mfg Co Ltd Method and apparatus for screening laminated ceramic electronic component
JP3925136B2 (en) 2001-10-01 2007-06-06 株式会社村田製作所 Capacitor pass / fail judgment method
JP2009295606A (en) 2008-06-02 2009-12-17 Panasonic Corp Method for testing multilayer ceramic capacitor and method for manufacturing the multilayer ceramic capacitor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09152455A (en) * 1995-12-01 1997-06-10 Matsushita Electric Ind Co Ltd Internal defect detector and method thereof for laminated ceramic capacitor
JP2000228338A (en) * 1999-02-04 2000-08-15 Matsushita Electric Ind Co Ltd Screening method for multilayer ceramic capacitor
JP2005223253A (en) * 2004-02-09 2005-08-18 Murata Mfg Co Ltd Method for screening laminated ceramic capacitors
JP2008180546A (en) * 2007-01-23 2008-08-07 Showa Denki Kk Withstand voltage test method for three-terminal capacitor, and withstand voltage tester thereof
WO2016125679A1 (en) * 2015-02-03 2016-08-11 株式会社ジェイ・イー・ティ Electricity storage device production method, structure body inspection device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023234349A1 (en) 2022-06-01 2023-12-07 富士フイルム株式会社 All-solid-state lithium-ion secondary battery and method for manufacturing all-solid-state lithium-ion secondary battery

Also Published As

Publication number Publication date
JP7352209B2 (en) 2023-09-28
KR20200043279A (en) 2020-04-27
JP2020064975A (en) 2020-04-23
KR102253401B1 (en) 2021-05-18
JP7110902B2 (en) 2022-08-02

Similar Documents

Publication Publication Date Title
JP2022089962A (en) Mechanism for detecting abnormal current
JP5711696B2 (en) Multilayer ceramic electronic components
JP5567647B2 (en) Ceramic electronic components
TW202028758A (en) Capacitor inspection device and capacitor inspection method that includes a variable voltage source, a current detection section, and an inspection section
CN1228148C (en) Method of screening laminated ceramic capacitor
US8885323B2 (en) Multilayered ceramic electronic component and fabricating method thereof
JP2009295606A (en) Method for testing multilayer ceramic capacitor and method for manufacturing the multilayer ceramic capacitor
JPH10293107A (en) Internal defect inspection method for multilayer ceramic capacitor
JP4779976B2 (en) Manufacturing method of electronic parts
JP7127369B2 (en) Determination method for quality of multilayer ceramic capacitors
JP2017040563A (en) Particulate matter detection sensor and method for manufacturing particulate matter detection sensor
JP4655504B2 (en) Inspection method for multilayer piezoelectric element
US6509741B2 (en) Method for screening multi-layer ceramic electronic component
JP4466106B2 (en) Screening method for multilayer ceramic capacitors
JPH08227826A (en) Method for screening laminated ceramic capacitor
JP2008124276A (en) Manufacturing method for electronic component
JP2994911B2 (en) Screening method for ceramic electronic components
JP2003059784A (en) Method for sorting multilayer ceramic capacitor
JP2003347175A (en) Method for discriminating capacitor
CN210467600U (en) Multilayer ceramic capacitor
JPH07161570A (en) Method of detecting internal crack of multilayer ceramic capacitor
CN110534343A (en) A kind of multilayer ceramic capacitor
WO2012108123A1 (en) Capacitor array screening method
JP2005064245A (en) Laminated ceramic capacitor and short-circuiting detection method thereof
JP4131776B2 (en) Screening method for multilayer capacitors

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20220420

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20230530

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230725

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20230816

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20230829

R150 Certificate of patent or registration of utility model

Ref document number: 7352209

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150