JP2022046334A - リードフレーム、半導体装置及びリードフレームの製造方法 - Google Patents
リードフレーム、半導体装置及びリードフレームの製造方法 Download PDFInfo
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- JP2022046334A JP2022046334A JP2020152327A JP2020152327A JP2022046334A JP 2022046334 A JP2022046334 A JP 2022046334A JP 2020152327 A JP2020152327 A JP 2020152327A JP 2020152327 A JP2020152327 A JP 2020152327A JP 2022046334 A JP2022046334 A JP 2022046334A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 238000000034 method Methods 0.000 claims abstract description 24
- 230000000994 depressogenic effect Effects 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 229920005989 resin Polymers 0.000 claims description 21
- 239000011347 resin Substances 0.000 claims description 21
- 238000007747 plating Methods 0.000 claims description 19
- 238000007789 sealing Methods 0.000 claims description 19
- 239000000463 material Substances 0.000 abstract description 31
- 238000010586 diagram Methods 0.000 description 20
- 230000002093 peripheral effect Effects 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 150000001412 amines Chemical class 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical compound OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- JRKICGRDRMAZLK-UHFFFAOYSA-L peroxydisulfate Chemical compound [O-]S(=O)(=O)OOS([O-])(=O)=O JRKICGRDRMAZLK-UHFFFAOYSA-L 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- NNFCIKHAZHQZJG-UHFFFAOYSA-N potassium cyanide Chemical compound [K+].N#[C-] NNFCIKHAZHQZJG-UHFFFAOYSA-N 0.000 description 1
- LFAGQMCIGQNPJG-UHFFFAOYSA-N silver cyanide Chemical compound [Ag+].N#[C-] LFAGQMCIGQNPJG-UHFFFAOYSA-N 0.000 description 1
- 229940098221 silver cyanide Drugs 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4828—Etching
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
- H01L23/49582—Metallic layers on lead frames
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
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- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
111 めっき層
120 ダイパッド
121 凹部
121a 底面
122 突起部
123 陥没部
124 鍔部
130 連結部
200 金属板
210 DFR
220 レジスト
230 接合材
240 半導体素子
250 ワイヤ
260 封止樹脂
Claims (10)
- 半導体素子の搭載面を有するダイパッドと、
前記搭載面に設けられた凹部と、
前記ダイパッドの周囲に配置されるリードとを有し、
前記凹部は、
前記凹部の開口面から前記ダイパッドの厚さ未満の深さに位置する底面と、
前記底面から突起する複数の突起部と、
前記底面から陥没する陥没部とを有する
ことを特徴とするリードフレーム。 - 前記複数の突起部は、
前記底面の一部に第1の密度で形成され、前記底面の他の一部に前記第1の密度よりも低い第2の密度で形成され、
前記陥没部は、
前記底面の他の一部に形成される
ことを特徴とする請求項1記載のリードフレーム。 - 前記複数の突起部は、
前記凹部の開口面からの深さが前記底面よりも浅い位置に先端を有する
ことを特徴とする請求項1記載のリードフレーム。 - 前記陥没部は、
前記凹部の開口面からの深さが前記底面よりも深い位置まで陥没する
ことを特徴とする請求項1記載のリードフレーム。 - 前記ダイパッドは、
前記凹部の外周に形成され、前記リードの方向へ迫り出す鍔部
を有することを特徴とする請求項1記載のリードフレーム。 - 前記リードは、
前記搭載面と同じ側の面に形成されるめっき層
を有することを特徴とする請求項1記載のリードフレーム。 - リードフレームと、
前記リードフレームに搭載される半導体素子と、
前記半導体素子を封止する封止樹脂とを有し、
前記リードフレームは、
前記半導体素子の搭載面を有するダイパッドと、
前記搭載面に設けられた凹部と、
前記ダイパッドの周囲に配置されるリードとを有し、
前記凹部は、
前記凹部の開口面から前記ダイパッドの厚さ未満の深さに位置する底面と、
前記底面から突起する複数の突起部と、
前記底面から陥没する陥没部とを有する
ことを特徴とする半導体装置。 - 金属板に、両面がレジストに被覆されない第1の領域と、一方の面がレジストに被覆されるとともに他方の面が点在する複数のレジストに被覆される第2の領域とを形成し、
前記第1の領域及び前記第2の領域を有する金属板をエッチングすることにより、前記第1の領域においてリードとダイパッドを分離し、前記第2の領域において底面に複数の突起部を有する凹部を前記ダイパッドに形成する
工程を有することを特徴とするリードフレームの製造方法。 - 前記第1の領域と前記第2の領域とを形成する工程は、
前記他方の面の一部が第1の密度で点在するレジストに被覆され、前記他方の面の他の一部が第1の密度よりも低い第2の密度で点在するレジストに被覆される第2の領域を形成し、
前記エッチングする工程は、
前記第2の領域の前記他の一部において前記底面よりも深く陥没する陥没部を有する凹部を前記ダイパッドに形成する
ことを特徴とする請求項8記載のリードフレームの製造方法。 - 前記第1の領域と前記第2の領域とを形成する工程は、
前記他方の面のみがレジストに被覆される第3の領域をさらに形成し、
前記エッチングする工程は、
前記第3の領域において前記凹部の外周から前記リードの方向へ迫り出す鍔部を前記ダイパッドに形成する
ことを特徴とする請求項8記載のリードフレームの製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2020152327A JP7506564B2 (ja) | 2020-09-10 | 2020-09-10 | リードフレーム、半導体装置及びリードフレームの製造方法 |
CN202111037742.8A CN114171486A (zh) | 2020-09-10 | 2021-09-06 | 引线框架、半导体装置以及引线框架的制造方法 |
US17/469,129 US11756866B2 (en) | 2020-09-10 | 2021-09-08 | Lead frame and semiconductor device |
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Application Number | Priority Date | Filing Date | Title |
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JP2020152327A JP7506564B2 (ja) | 2020-09-10 | 2020-09-10 | リードフレーム、半導体装置及びリードフレームの製造方法 |
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Publication Number | Publication Date |
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JP2022046334A true JP2022046334A (ja) | 2022-03-23 |
JP7506564B2 JP7506564B2 (ja) | 2024-06-26 |
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Country Status (3)
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US (1) | US11756866B2 (ja) |
JP (1) | JP7506564B2 (ja) |
CN (1) | CN114171486A (ja) |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
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US7741158B2 (en) * | 2006-06-08 | 2010-06-22 | Unisem (Mauritius) Holdings Limited | Method of making thermally enhanced substrate-base package |
JP2009147094A (ja) | 2007-12-14 | 2009-07-02 | Panasonic Corp | 半導体装置 |
JP5834647B2 (ja) | 2011-09-07 | 2015-12-24 | 大日本印刷株式会社 | リードフレームおよびその製造方法 |
JP2014203861A (ja) | 2013-04-02 | 2014-10-27 | 三菱電機株式会社 | 半導体装置および半導体モジュール |
JP6603538B2 (ja) | 2015-10-23 | 2019-11-06 | 新光電気工業株式会社 | リードフレーム及びその製造方法 |
JP6961337B2 (ja) * | 2016-11-25 | 2021-11-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10109563B2 (en) | 2017-01-05 | 2018-10-23 | Stmicroelectronics, Inc. | Modified leadframe design with adhesive overflow recesses |
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2020
- 2020-09-10 JP JP2020152327A patent/JP7506564B2/ja active Active
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2021
- 2021-09-06 CN CN202111037742.8A patent/CN114171486A/zh active Pending
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JP7506564B2 (ja) | 2024-06-26 |
US11756866B2 (en) | 2023-09-12 |
CN114171486A (zh) | 2022-03-11 |
US20220077028A1 (en) | 2022-03-10 |
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