JP2017152523A - Power semiconductor element and power semiconductor module using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor element having a SiC-SBD structure, in which surge current tolerance can be improved without causing energization degradation or recovery loss.SOLUTION: A power semiconductor element includes a Schottky barrier diode composed of silicon carbide and has, in an active region where a forward current flows, a Schottky electrode 15, an n-type impurity region 11 constituting a Schottky region 12 between the Schottky electrode and the impurity region, a p-type impurity region 2p+type semiconductor region 18 connected electrically with the Schottky electrode, and constituting a PN junction between it and the n-type impurity region, and a cathode electrode 3 connected electrically with the n-type impurity region. The PN junction starts conduction when a forward current in a range of 2-3 times of the rated current flows.SELECTED DRAWING: Figure 9

Description

  The present invention relates to a power semiconductor element using silicon carbide as a semiconductor material and a power semiconductor module using the same.

  Among power conversion devices represented by inverters, power semiconductor elements are used as main components having a rectifying function and a switching function. Silicon is currently the mainstream semiconductor material for power semiconductor elements, but silicon carbide (SiC), which has excellent physical properties, has begun to be used.

  SiC has a dielectric breakdown field strength that is an order of magnitude higher than that of silicon, and is suitable for high voltage applications. Furthermore, since the thickness of the semiconductor layer can be reduced with respect to a desired device withstand voltage, the resistance of the device can be lowered. In addition, SiC has a thermal conductivity three times that of silicon and hardly loses the properties of a semiconductor even at high temperatures, so that it is resistant to temperature rise in principle. Accordingly, SiC is suitable as a semiconductor material for power semiconductor elements.

  In an inverter or the like, a power semiconductor module on which a power semiconductor element is mounted is applied. FIG. 2 is a set diagram schematically showing a configuration of a general power semiconductor module. An insulating circuit board 22 on which the switching element 26 and the rectifying element 27 are mounted is stored in the resin case 25. The insulated circuit boards are electrically connected to each other by a wiring electrode having an external terminal. Among the switching element 26 and the rectifying element 27, development of a SiC hybrid module in which a free-wheeling diode, which is a rectifying element, is replaced with a SiC diode from a silicon diode has been advanced. The reason is that the rectifying element has a simple structure and operation compared to the switching element, facilitates the development of the element, and clearly shows the merit of greatly reducing the switching loss.

  As such a SiC hybrid module, in a power semiconductor module with a high breakdown voltage rating of 3.3 kV, a silicon (Si) IGBT (Insulated Gate Bipolar Transistor) which is a high breakdown voltage switching element and a SiC diode which is a freewheeling diode. An arm circuit to which an SBD (Schottky Barrier Diode) is connected in antiparallel is stored in a resin case.

  Unlike the PN diode that is a bipolar element, the SBD that is a unipolar element does not accumulate minority carriers in the element. For this reason, since a recovery current hardly flows during the switching operation of the arm circuit, the switching loss generated in the power semiconductor module can be greatly reduced. However, in SBD, when the thickness of the drift layer is increased in order to increase the withstand voltage, the element resistance increases and the power loss increases. In particular, a general Si SBD has an excessive increase in power loss and is difficult to apply to the high voltage field. On the other hand, since the SBD of SiC can make the drift layer much thinner than the SBD of Si, it can be applied up to a high voltage region of 600 V to 3.3 kV even though it is a unipolar element.

  In SBD, the leakage current in the off state tends to be larger than that of the PN diode. This is because the barrier height of the Schottky junction is lower than the barrier height of the PN junction. In order to reduce the leakage current of SBD, for example, a JBS (Junction Barrier Controlled Schottky) structure as described in Patent Document 1 and an MPS (Merged PiN Schottky) structure described in Patent Document 2 and Patent Document 3 are used. Are known.

  FIG. 4 shows a cross section of a SiC SBD having a simple structure as a conventional example, and FIG. 5 shows a cross section of a SiC SBD having a JBS structure as a conventional example. 4 and 5, 5 is an n + type SiC substrate, and 10 is an n − type SiC epitaxial layer (drift layer) made of SiC. In the SBD having the JBS structure shown in FIG. 5, p-type impurity region 2 is formed in n-type impurity region 1 on the surface of n − -type SiC epitaxial layer 10. In the off state, the cathode electrode 3 in FIG. 5 is at a positive potential, so that the pn junction 4 is reverse-biased, and the depletion layer extending from the junction interface of the pn junction 4 relaxes the electric field on the surface of the Schottky junction 9, thereby reducing leakage current. Is done.

  The junction structure in the MPS structure is the same as the junction structure shown in FIG. 5, and the leakage current is reduced as in the JBS structure. However, in the MPS structure, the impurity concentration of the p-type impurity region 2 is increased, and thereby the connection between the p-type impurity region 2 and the anode electrode 6 is brought into ohmic contact or close to ohmic contact. For this reason, at the time of forward bias, minority carriers are injected from the p-type impurity region 2 into the n − -type SiC epitaxial layer 10, and the resistance decreases due to conductivity modulation. For this reason, the conduction loss at high temperature can be reduced, and the surge current resistance can be improved.

  In the technique described in Patent Document 2, the p + type impurity region has a pattern width of 15 μm or more in order to improve surge resistance, thereby reducing the voltage that causes conductivity modulation by injecting minority carriers. .

In the technique described in Patent Document 3, in the JBS structure and the MPS structure, the p-type impurity element has a p-type impurity region having a concentration of 1 × 10 ¹⁷ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. And an n-type impurity element whose concentration ratio to the p-type impurity element is greater than 0.33 and smaller than 1.0. Thereby, the contact resistance between the anode electrode and the p-type impurity region is reduced, and the surge current resistance is improved.

  FIG. 6 shows a planar pattern of a SiC SBD having a JBS structure as a conventional example. As shown in FIG. 6, a plurality of linear n-type impurity regions (active regions) 1 in which Schottky junctions are formed are arranged in parallel with each other at equal intervals along the longitudinal direction. That is, the planar pattern of the conventional example is a so-called line and space pattern. N-type impurity region 1 is a part of n − type SiC epitaxial layer 10 in FIG. As shown in FIG. 6, the n-type impurity region (1) is surrounded by the p-type impurity region 2. As described above, since p-type impurity region 2 is a non-conducting region, the effective area of the conductive region in the active region including n-type impurity region 1 and p-type impurity region 2 is larger than the area of the active region. It decreases by the area of the type impurity region 2. For this reason, resistance increases compared with SBD of the simple structure of FIG.

  A technique for suppressing such an increase in resistance is disclosed in Patent Document 1. FIG. 7 shows a cross section of a SiC SBD having a JBS structure, which is a conventional example to which the present technology is applied. As shown in FIG. 7, in the vicinity of the p-type impurity region 2, the carrier concentration of the n-type impurity region 11 is increased by ion implantation. By such an n-type impurity region 11, that is, a current diffusion layer, the resistance of the narrowed current path 12 is reduced, and the current path can be expanded to a position immediately below the p-type impurity region 2. Therefore, the conduction loss can be reduced to almost the same level as the SBD having the simple structure shown in FIG.

International Publication No. 2011/151901 JP 2011-151208 A JP 2014-187115 A

  As described above, the SBD made of SiC (hereinafter referred to as “SiC-SBD”) makes it possible to apply the SBD of a unipolar element excellent in recovery characteristics up to a high voltage region, and further, the leakage current is reduced by applying the JBS structure. The practicality of SiC-SBD is improved. However, SiC-SBD has a problem that the surge current withstand capability is lower than that of a silicon PN diode (hereinafter referred to as “Si-PND”).

  The surge current withstand capability is the limit of the energizing current (under non-repetitive conditions) that does not break even when the forward current of the diode significantly exceeds the maximum value (rated value) allowed under normal operating conditions. The Si-PND generally allows about 10 times the rated current. On the other hand, the surge current resistance of the SiC-SBD having a simple structure (FIG. 4) is less than half that of the Si-PND. The surge current withstand capability is further reduced in a SiC-SBD having a JBS structure as shown in FIGS.

Further, in the SiC-SBD having the MPS structure, since minority carriers are injected from the p-type impurity region 2 at the time of forward bias, an increase in on-voltage (V _F ) at a high temperature can be suppressed, and a decrease in surge current resistance can be suppressed. However, when the MPS structure is introduced with SiC, there are problems such as deterioration of energization in which crystal defects such as basal plane dislocation (BPD) expand due to minority carrier injection and recovery loss during switching due to minority carrier injection. Newly occurs. In addition, the technique described in Patent Document 3 as described above, that is, the technique for reducing the contact resistance between the anode electrode and the p-type impurity region and improving the surge current withstand capability, is the same problem as the MPS structure. There is.

  Further, when a plurality of MPS-structured SiC diode chips are connected in parallel to constitute a power semiconductor module, the following problem arises.

  FIG. 8 shows an example of forward current voltage (IV) characteristics of an SiC-SBD having an MPS structure in which the conductivity type of the semiconductor substrate is n-type. When the forward voltage exceeds the built-in voltage of the Schottky barrier, current starts to flow and the slope of the IV characteristic is almost linear (arrow 37 in FIG. 8). At this time, the forward characteristic of the SBD appears and the PN junction is not conductive. That is, minority carrier (hole) injection into the n-type region does not substantially occur. Further, when the voltage rises and a voltage exceeding the built-in potential is applied to the PN junction, holes are injected from the PN junction, and the current value suddenly increases (arrow 38 in FIG. 8). Since SBD and PND are connected in parallel in terms of circuit, PND having a low element resistance starts to conduct, so that the resistance of the entire diode is lowered and a voltage drop (arrow 44 in FIG. 8) may appear. is there.

  At this time, if a plurality of diode chips are connected in parallel, the current concentrates on the diode chip in which the PN junction is first conducted, and this diode chip is likely to be destroyed. Therefore, even if the SiC-SBD having the MPS structure is used, the surge withstand capability is not necessarily improved as a power semiconductor module.

  Therefore, the present invention provides a power semiconductor element having a SiC-SBD structure and capable of improving surge current resistance without energization deterioration and generation of recovery loss.

  Furthermore, the present invention provides a power semiconductor module in which power semiconductor elements having a SiC-SBD structure are connected in parallel and surge resistance can be improved.

  In order to solve the above-described problem, a power semiconductor device according to the present invention includes a Schottky barrier diode made of silicon carbide, and includes an active region in which a forward current flows, and includes a first electrode and a first electrode. A first conductivity type first semiconductor region that forms a Schottky junction therebetween, and a second conductivity type second semiconductor that is electrically connected to the first electrode and forms a PN junction between the first semiconductor region Two semiconductor regions and a second electrode electrically connected to the first semiconductor region, and when a forward current in a range greater than twice the rated current and less than three times flows, the PN junction becomes conductive To start.

  In order to solve the above problems, a power semiconductor module according to the present invention includes a plurality of power semiconductor elements each including a Schottky barrier diode made of silicon carbide, and the plurality of power semiconductor elements are connected in parallel. In the active region where forward current flows, the power semiconductor element includes a first conductivity type first semiconductor region that forms a Schottky junction between the first electrode and the first electrode, and a first electrode. A second conductive type second semiconductor region that is electrically connected and forms a PN junction with the first semiconductor region; and a second electrode that is electrically connected to the first semiconductor region. Each of the plurality of power semiconductor elements is used when the PN junction is conducted such that the current flowing when the PN junction is conducted independently is smaller than the surge withstand capability of the power semiconductor element alone. Current is limited by the element resistance of the power semiconductor device.

  According to the present invention, when a forward current in a range greater than twice the rated current and less than or equal to three times flows, the PN junction starts to conduct, so that the surge current withstand capability without energization deterioration or occurrence of recovery loss. Can be improved.

  In addition, according to the present invention, the current that flows when the PN junction is conducted is reduced so that the current that flows when the PN junction is conducted alone is smaller than the surge resistance of the power semiconductor device alone. Therefore, the surge withstand capability of the power semiconductor module is improved.

  Problems, configurations, and effects other than those described above will become apparent from the following description of embodiments.

The plane pattern of the power semiconductor element which is Example 1 of this invention is shown. It is an assembly figure showing typically composition of a general power semiconductor module. 12 shows a circuit configuration example constituted by the semiconductor power module of FIG. The cross section of SiC-SBD which has a simple structure which is a prior art example is shown. The cross section of SiC-SBD which has a JBS structure which is a prior art example is shown. The plane pattern of SiC-SBD which has a JBS structure which is a prior art example is shown. The cross section of SiC-SBD to which the technique of patent document 1 is applied is shown. The example of the forward direction current voltage characteristic of SiC-SBD of a MPS structure is shown. The longitudinal direction cross section of the power semiconductor element of Example 1 is shown. The layout structure of the insulated circuit board in the power semiconductor module in which SiC-SBD of Example 1 is used is shown. It is a set figure which shows the structure of a semiconductor module provided with the insulated circuit board of FIG. The example of the forward direction current voltage characteristic of SiC-SBD of the present Example 1 is shown. The carrier flow in the energized state is schematically shown. A carrier flow at the time of a current voltage characteristic change is shown typically. The current-voltage characteristics of the SiC-SBD of the first embodiment, the current-voltage characteristics of the Schottky diode section, and the current-voltage characteristics of the PN diode section are shown. The relationship between the line width of the p-type impurity region and _IPN in Example 1 is shown. The relationship between the donor density | concentration of the n-type impurity area | region in the power semiconductor element which is Example 2 of this invention, and the electric current which starts injection | pouring of a hole is shown. It is sectional drawing which shows typically the electrical resistance of an n-type impurity region. It is a typical equivalent circuit diagram which shows SiC-SBD connected in parallel. It is a top view of SiC-SBD to which parasitic resistance was added.

  A power semiconductor device according to an embodiment of the present invention includes a Schottky barrier diode made of SiC, and in an active region in which a forward current flows, is shot between the first electrode and the first electrode. The second conductivity type second semiconductor region which is electrically connected to the first electrode and which forms the PN junction between the first conductivity type first semiconductor region constituting the key junction and the first electrode. And a second electrode electrically connected to the first semiconductor region. The Schottky barrier diode in this embodiment has an MPS structure. Preferably, the second conductivity type second semiconductor region includes a first region and a second region located in the first region and having a higher impurity concentration than the first region. The first region functions as a JBS structure, and the second region contributes to minority carrier injection.

  The first electrode, the first conductivity type first semiconductor region, the second conductivity type second semiconductor region, and the second electrode are the anode electrode 6 including the Schottky electrode 15 and the n + type SiC, respectively, in the examples described later. An n-type semiconductor region including substrate 5, n − -type SiC epitaxial layer 10 and n-type impurity region 11, p-type impurity region 2 (first region), and p-type impurity region 18 (second region). The semiconductor region corresponds to the cathode electrode 3.

  Embodiments of the present invention will be described below with reference to the drawings.

  In each figure, the same reference numerals indicate the same constituent elements or constituent elements having similar functions. In the following description, n−, n, and n + indicate that the conductivity type of the semiconductor is n-type, and the impurity concentration and the carrier concentration are relatively high in this order. Further, p−, p, and p + indicate that the conductivity type of the semiconductor is p-type, and the impurity concentration and the carrier concentration are relatively high in this order.

  FIG. 1 shows a planar pattern of a power semiconductor element that is Embodiment 1 of the present invention. The power semiconductor element of Example 1 is an n-type SiC-SBD having an MPS structure, and FIG. 1 shows a planar pattern on the anode side.

  As shown in FIG. 1, the SiC-SBD of the present embodiment surrounds the active region 1 through which current flows and the active region 1, and relaxes the electric field at the outer periphery of the chip in a voltage blocking state to ensure a desired breakdown voltage. Region 13. A p-type impurity region constituting a so-called JTE structure (Junction Termination Extension) is provided at the boundary portion 7 with the active region 1 in the peripheral region 13. Of the two broken lines shown in FIG. 1, the area within the inner broken line is the active area 1, and the area between the two broken lines is the peripheral area 13.

  In the active region 1, a plurality of linear Schottky regions 12 are arranged in parallel with each other at equal intervals along the longitudinal direction. That is, on the main surface on the anode side of the SiC-SBD, the plurality of linear Schottky regions 12 form a so-called line and space pattern. A p-type impurity region 2 is provided around each of the plurality of Schottky regions 12 so as to be in contact with the Schottky region 12. In the p-type impurity region 2, a plurality of linear p + -type impurity regions 18 having an impurity concentration higher than that of the p-type impurity region 2 are provided. The plurality of linear p + type impurity regions 18 are arranged in parallel with each other at equal intervals along the longitudinal direction. Accordingly, the plurality of linear p + -type impurity regions 18 form a line and space pattern as with the Schottky region 12. Further, each p + -type impurity region 18 is located between adjacent Schottky regions 12, and the linear pattern of p + -type impurity region 18 and the linear pattern of Schottky region 12 are alternately arranged in parallel with each other.

  FIG. 9 shows a longitudinal section of the power semiconductor element of Example 1 shown in FIG.

  As shown in FIG. 9, an n− type SiC epitaxial layer 10 having an impurity concentration lower than that of the n + type SiC substrate 5 is in contact with the n + type SiC substrate 5 in the vertical direction. The thickness of the n− type SiC epitaxial layer 10 is about 30 μm when the rated breakdown voltage is 3.3 kV. In the active region including the plurality of Schottky regions 12, the n − type SiC epitaxial layer 10 is in contact with the n type impurity region 11 having a higher impurity concentration than the n − type SiC epitaxial layer 10 in the vertical direction. P type impurity region 2 is located in n type impurity region 11, and p + type impurity region 18 is located in p + type impurity region 2. Since p-type impurity region 2 and n-type impurity region 11 are in contact with each other, p-type impurity region 2 and n-type impurity region 11 form a pn junction. The depth of the n-type impurity region 11 from the anode side surface, that is, the depth of the junction between the n − -type SiC epitaxial layer 10 and the n-type impurity region 11 is determined by the pn junction between the p-type impurity region 2 and the n-type impurity region 11. Deeper than the depth of the part. N-type impurity region 11 corresponds to the current diffusion layer in the above-described conventional example (FIG. 7). Accordingly, as in the conventional example, the resistance of the narrow current path in the Schottky region 12 is reduced, and the current flowing region is expanded in the lateral direction to reduce the resistance, so that the conduction loss can be reduced.

  On the anode-side main surface, Schottky electrode 15 is in contact with n-type impurity region 11, p-type impurity region 2 and p + -type impurity region 18 p + -type impurity region 18. As a result, a Schottky junction is formed between the n-type impurity region 11 and the Schottky electrode 15. Further, an anode electrode 16 is provided on the Schottky electrode 15 so as to cover the surface of the Schottky electrode 15. Further, on the cathode-side main surface, the cathode electrode 3 contacts the n + -type SiC substrate 5 from the active region to the peripheral region. The anode electrode 6 serves as a wiring connection terminal in a power semiconductor module or the like to be described later. When a forward voltage is applied between the anode electrode 6 and the cathode electrode 3, the Schottky junction is forward biased, the n-type impurity region 11 becomes a conduction region, and the SiC-SBD enters a forward current conduction state. Here, in this embodiment, since the barrier height of the Schottky junction is lower than the barrier height of the pn junction constituted by the p-type impurity region 2 and the n-type impurity region 11, when a forward voltage is applied, When a current flows through the Schottky region 12 and a forward voltage exceeds a certain threshold voltage and a voltage exceeding the barrier height is applied to the pn junction, a current also flows through the pn junction.

  Further, when a reverse voltage is applied between the anode electrode 6 and the cathode electrode 3, the Schottky junction is reverse-biased, and the SiC-SBD enters a blocking state. At this time, since the depletion layer extending from the pn junction between the p-type impurity region 2 and the n-type impurity region 11 covers the Schottky junction, the electric field at the Schottky junction is relaxed. Thereby, the leakage current is reduced and a high voltage can be prevented.

  In the peripheral region outside the active region, a JTE (Junction Termination Extension) structure is formed by the p-type impurity region 13 on the anode side surface of the n − -type SiC epitaxial layer 10. The p-type impurity region 13 is in contact with the n-type impurity region 11 on the outer periphery of the active region (corresponding to the region denoted by reference numeral 7 in FIG. 1). Since the electric field at the end of the SiC-SBD chip is relaxed by the JTE structure, a desired high breakdown voltage can be ensured. In the peripheral region, a channel stopper 14 made of an n + type impurity region provided on the anode side surface of the n− type SiC epitaxial layer 10 is provided on the outer periphery of the chip outside the JTE structure. The JTE structure and the channel stopper 14 have an annular pattern on the anode side main surface.

  FIG. 10 shows a layout configuration of an insulating circuit board in a power semiconductor module in which the SiC-SBD of this embodiment is used.

  The insulated circuit board 22 has a symmetrical circuit pattern composed of a ceramic insulated substrate and a conductor layer bonded on the surface thereof. On the circuit pattern, 4 chips of IGBT (Insulated Gate Bipolar Transistor) 23 made of silicon (Si) and 10 chips of SiC-SBD 24 are mounted and arranged symmetrically. A collector electrode provided on the chip back surface side of each IGBT 23 and a cathode electrode provided on the chip back surface side of each SiC-SBD 24 are electrically joined to the circuit pattern. The emitter electrode provided on the chip surface side of each IGBT 23 and the anode electrode provided on the chip surface side of each SiC-SBD 24 are electrically connected to the circuit pattern via the metal wire 53. A wiring electrode is joined to the main terminal contact 52 in the circuit pattern.

  In FIG. 10, the metal wire 53 is not shown in the right half of the insulated circuit board.

  FIG. 11 is a set diagram illustrating a configuration of a semiconductor module including the insulated circuit board of FIG. This power semiconductor module is a SiC hybrid module in which silicon IGBT and SiC-SBD, which are switching elements, are mounted as power semiconductor elements.

  As shown in FIG. 11, in the power semiconductor module, a plurality of, that is, four, insulating circuit boards 22 are stored in a resin case 25. The insulated circuit board 22 may be bonded onto a heat dissipation metal substrate that is bonded to the bottom of the resin case. A wiring electrode 21 having external terminals is connected to the plurality of insulated circuit boards. Therefore, the wiring electrode 21 is also accommodated in the resin case. The resin case 25 is filled with a gel resin (not shown) for protecting and insulating each member in the resin case, and a lid is attached. The external terminal of the wiring electrode 21 is taken out of the resin case 25 through the lid. The numbers of IGBTs, SiC-SBDs, and insulating substrates are set according to desired current characteristics and voltage characteristics as the power semiconductor module.

  FIG. 3 shows an example of a circuit configuration constituted by the semiconductor power module of FIG. As shown in FIG. 3, two sets of anti-parallel circuits of IGBT and SiC-SBD are configured. Note that one insulating circuit board shown in FIG. 10 constitutes one antiparallel circuit, and a plurality of (for example, two) such insulating circuit boards are used to form a set of semiconductor power modules. A circuit is constructed. Here, anti-parallel circuits configured on a plurality of insulated circuit boards are connected in parallel in the resin case 25 by the wiring electrodes 21 and external terminals (G: gate terminals, E: for connecting external wirings). Emitter terminal, C: collector terminal) is taken out.

  Hereinafter, the operation of the SiC-SBD of the present embodiment will be described with reference to FIGS.

  FIG. 12 shows an example of forward current voltage (IV) characteristics of the SiC-SBD of this example.

  When the forward voltage is increased from 0V, a forward current substantially flows out from a voltage value exceeding the Schottky barrier built-in voltage (see reference numeral 30 in FIG. 12), and thereafter, the differential resistance becomes a voltage with a substantially constant slope. The current increases proportionally. Such characteristics are caused by the fact that SiC-SBD is a unipolar element, and in this embodiment, only electrons become current carriers. That is, at this time, only the Schottky junction is substantially conductive among the Schottky junction and the PN junction. When the current increases, the element resistance increases due to the temperature rise due to self-heating, so the slope of the current-voltage characteristic deviates from the linear slope and becomes a convex curve, and the current increases slowly with respect to the voltage. (See arrow 31 in FIG. 12). In the case of the present embodiment, as in a general unipolar element, the element resistance in the energized state (arrows 30 to 31 in FIG. 12) increases in proportion to the absolute temperature of 2.5 to the third power. The descent increases.

  FIG. 13 schematically shows the carrier flow in the energized state. As shown in FIG. 13, the electron flow 33 from the Schottky junction constitutes a current.

  When the voltage further increases, as shown in FIG. 12 (see arrow 32 in FIG. 12), the current-voltage characteristic changes greatly, and the current suddenly increases. The state in the element at this time is shown in FIG.

FIG. 14 schematically shows the flow of carriers when the current-voltage characteristic changes. In addition to the electron flow 33 from the Schottky region, the hole flow 34 injected from the p + -type impurity region also forms a current. Here, the current and voltage at which hole injection is started are I _PN and V _PN , respectively. When a voltage equal to or higher than V _PN is applied to the SiC-SBD, the PN junction becomes conductive at the center of the pattern where the potential is highest at the PN junction, and hole injection is started.

  When the element resistance after the start of hole injection is significantly lower than the energized state in which current flows only in the Schottky region, as shown in FIG. 12 (arrow 32), a voltage drop (snap) that temporarily decreases the forward voltage. Back) is seen. In the subsequent current-voltage characteristics, the characteristics as a PN diode having a relatively low resistance in a large current region dominate. Therefore, the current-voltage characteristics as a PN diode whose differential resistance changes continuously (arrow 35 in FIG. 12) Transition to Reference).

FIG. 15 shows the current-voltage characteristics (solid line 36) of the SiC-SBD of this example, the current-voltage characteristics of the Schottky diode part (broken line 37), and the current-voltage characteristics (dotted line 38) of the PN diode part in this SiC-SBD. Show. If there is no measurement error due to self-heating, subtracting the linear Schottky diode current-voltage characteristics from the SiC-SBD current-voltage characteristics, the current-voltage characteristics of the PN diode section, that is, the PN junction conduction state As can be seen, the current and voltage (I _PN , V _PN ) at which hole injection is started can be set in consideration of the conduction state of the PN junction. As will be described later, since (I _PN , V _PN ) depends on the local potential of the PN junction and the potential of the Schottky region, the pattern size of the p-type semiconductor region 2 and the n-type impurity region 11 Can be controlled by the electrical resistance of the substrate, that is, the impurity concentration.

Hereinafter, the setting of (I _PN , V _PN ) will be described.

By setting the values of (I _PN , V _PN ) within a certain range, surge resistance can be improved by operating the PN diode portion while preventing the deterioration of energization due to hole injection. According to the study of the present inventors, the value of the current value _{IPN at which} the PN junction starts to conduct is set in a range larger than twice the rated current and not larger than three times.

The rated current of the power semiconductor module is defined as the maximum current value that allows continuous energization, but normally, if the repeated pulse energization has a pulse width of 1 ms or less, a current value up to twice the rated current is allowed. An allowable value of a current value exceeding twice the rated current is set for a non-repetitive surge current. Therefore, if I _PN is set to a value exceeding twice the rated current, the PN diode section does not substantially operate under normal repetitive operating conditions, so that a current deterioration phenomenon can be prevented. Further, if I _{PN is set} to a very high current value, the Schottky diode part having a surge resistance lower than that of the PN diode part is damaged. According to the study by the present inventors, the surge resistance of the Schottky diode part can be secured up to three times the rating. Therefore, by setting the I _PN to the current value of 3 times or less than twice the rated current, without energization degradation, thereby improving the surge resistance. According to the inventor's study, a surge withstand capability of at least 6 to 10 times the rated current can be obtained. In a normal energized state, the PN diode portion does not operate, so that recovery loss during switching can be reduced.

Here, the rated current value of the element is a junction temperature having a relationship of P × R _th = T _j −T _amb where P is a power loss, R _{th is} a thermal resistance, T _{j is} a junction temperature, and T _amb is an environmental temperature. The upper limit T _{jmax of} T _j is set so as not to exceed the maximum allowable temperature (usually 125 ° C. to 150 ° C.) in a predetermined package. For example, in the case of a power semiconductor module using a 3.3 kV SiC-SBD, the rated current value is normalized by the current density, although it depends on the loss characteristics of the element, the thermal resistance of the package, and the ambient temperature used. It becomes approximately 100A / cm ² or more 175A / cm ² or less. At this time, the surge withstand capability of the SiC-SBD is limited when the temperature determined by the balance between the heat generated by the energization loss of the element and the transient exhaust heat amount reaches the limit temperature at which thermal runaway occurs. For this reason, the surge resistance is affected by the element current density, the transient thermal resistance, and the environmental temperature, and becomes a current value in the range of 3 times to 6 times the rated current.

As described above, according to the study of the present inventors, by setting the I _PN to large and 3 times or less of the current value than twice the nominal, and preventing energization degradation in SiC-SBD having the MPS structure Both surge resistance can be improved.

_Next, detailed setting means _{I PN.}

Figure 16 is a line width of the p-type impurity region 2 in the present embodiment (Line width) and shows the I _PN relationship. Here, the line width corresponds to the width dimension 39 of the p-type impurity region 2 in the cross-sectional view of FIG. Note that the impurity concentration of the n-type impurity region 11 is 3 × 10 ¹⁵ atoms / cm ³ (solid line) and 2 × 10 ¹⁶ atoms / cm ³ (broken line), which are preferable for the current diffusion layer. According to the study of the present inventor, these impurity concentration values are particularly suitable for a SiC-SBD having a breakdown voltage of 3.3 kV. Further, in FIG. 16, the vertical axis represents the value normalized by the rated current _{I 0} to _{I PN.}

As shown in FIG. 16, when the line width of the p-type impurity region is increased, the potential drop amount of the n-type impurity region 11 in the path from the Schottky electrode 15 to the center in the width direction of the p-type impurity region 2 is increased. In addition, the voltage applied to the PN junction formed by the p-type impurity region 2 and the n-type impurity region 11 increases. For this reason, when the line width of the p-type impurity region 2 is widened, the PN junction becomes easy to conduct. Therefore, based on the relationship as shown in FIG. 16, the _IPN can be set to a desired range, that is, a current value greater than twice the rated current and less than three times depending on the line width of the p-type impurity region 2. Based on the relationship of FIG. 16, in this embodiment, the line width is in the range 40 of 1.5 μm to 10 μm, and the impurity concentration of the n-type impurity region 11 is 3 × 10 ¹⁵ atoms / cm ^{3 to} 2 × 10 ^16. be appropriately set in atoms / cm ³ or less of the _range, can be set _{I PN} to 3 times the current value greater than twice the rated current. According to the study by the present inventor, in the case of a breakdown voltage of 3.3 kV class, considering the balance with other characteristics (breakdown voltage, ON voltage, etc.), as an example, the line width of the p-type impurity region 2 is set to 7 μm. The impurity concentration of the n-type impurity region 11 is preferably optimized to about 2 × 10 ¹⁶ atoms / cm ³ .

The shape of the p-type impurity region 2 is not limited to a line & space pattern, and may be a geometric shape such as a regular polygon. Also in this case, _IPN depends on the amount of potential drop in the n-type impurity region 11 in the path from the Schottky electrode to the center of the p-type impurity region. Therefore, as in the present embodiment, the _IPN can be set to a desired value with a predetermined pattern dimension. In the case of the line & space pattern, since a uniform pattern can be easily manufactured, the _IPN can be set with high accuracy.

FIG. 17 shows the relationship between the donor concentration N _D of the n-type impurity region 11 and the current I _PN at which hole injection is started in the power semiconductor element that is Embodiment 2 of the present invention. Here, the line width of the p-type impurity region 2 is used as a parameter. In FIG. 17, the vertical axis indicates a value (I _PN / I ₀ ) obtained by normalizing I _PN with the rated current I ₀ . Note that the power semiconductor element of Example 2 is an n-type SiC-SBD having an MPS structure, and its junction structure (vertical structure) and planar pattern are the same as those of Example 1. No p-type counter doping or the like is performed on the n-type semiconductor region. If p-type impurities are present in the n-type semiconductor region by counter-doped, the vertical axis N _D in FIG. 17, a donor concentration of the acceptor concentration N _A and the n-type impurity region of the p-type impurity N _D of the difference N _D - it may be replaced with N _A.

As described for Example 1, I _PN depends from the upper electrode (Schottky electrode) to the potential drop amount of n-type impurity region 11 in route to the PN junction central portion. Therefore, _IPN depends on the electric resistance of the n-type impurity region 11 in the same path.

FIG. 18 is a cross-sectional view schematically showing the electrical resistance of the n-type impurity region. As shown in FIG. 18, the vertical resistance in the path from the contact portion of the anode electrode 6 and the n-type impurity region (current diffusion layer), that is, the Schottky electrode (not shown) to the bottom of the p-type impurity region, The series resistance 45 with the lateral resistance in the path up to the center of the p-type impurity region following the path affects the magnitude of _IPN . Note that changing the width of the p-type impurity region to set _IPN as in Example 1 corresponds to changing the lateral resistance in FIG.

When the impurity concentration of the n-type semiconductor region is high, current carriers increase and the resistance value of the resistor 45 in FIG. 18 decreases, so that the potential of the PN junction does not increase and the PN junction becomes difficult to conduct. Therefore, based on the relationship as shown in FIG. 17, the _IPN can be set to a desired range, that is, a current value larger than twice the rated current and not larger than three times depending on the impurity concentration of the n-type semiconductor region. Based on the relationship shown in FIG. 17, in Example 2, the impurity concentration of the n-type semiconductor region is set to 41 within a range of 2 × 10 ¹⁵ atoms / cm ³ or more and 3 × 10 ¹⁶ atoms / cm ³ or less. by appropriately setting the line width of the area in a range of 10μm or 1.5 [mu] m, can be set I _PN to 3 times the current value greater than twice the rated current. According to the inventor's study, in the case of a breakdown voltage of 3.3 kV class, considering the balance with other characteristics (breakdown voltage, on-voltage, etc.), as an example, the impurity concentration of the n-type impurity region is 2 × 10 ¹⁶ atoms. It is preferable to optimize the line width of the p-type semiconductor region to about 7 μm as / cm ³ .

Note that without providing the n-type impurity region, by setting based on the n-type impurity concentration of the n- type SiC epitaxial layer 10 in relation of Figure 17, it may be set I _PN.

  Next, a power semiconductor module on which SiC-SBD is mounted will be described as a third embodiment of the present invention. The power semiconductor module of Example 3 has an insulating circuit board as shown in FIG. 10 and an overall configuration as shown in FIG.

  In the third embodiment, a plurality (10 in FIG. 10) of SiC-SBD chips having an MPS structure are connected in parallel on the insulating circuit board. Furthermore, the power semiconductor module of the third embodiment has a plurality of such insulated circuit boards (four in FIG. 11) mounted thereon, and the plurality of insulated circuit boards are electrically connected in parallel in the power semiconductor module. Is done. Therefore, in the power semiconductor module, a large number of SiC-SBD chips such as 40 to 60 (40 in FIG. 11) are connected in parallel.

  If there is variation in element characteristics among a plurality of SiC-SBDs connected in parallel, when a surge current flows through the power semiconductor module, the surge current concentrates on the SiC-SBD in which the PN junction portion is first conducted. In this case, the desired surge withstand according to the number of parallel SiC-SBDs cannot be obtained. In particular, as shown in FIG. 12 and FIG. 15, when the current-voltage characteristic shows a kind of negative resistance characteristic called a snapback characteristic, the current tends to be excessively concentrated.

  Therefore, in the third embodiment, the SiC-SBD in which the PN junction portion conducts in advance is prevented from being destroyed by the surge current until the PN junction portion of another SiC-SBD is conducted. The means will be described below.

  In the third embodiment, each of the plurality of SiC-SBDs connected in parallel has a PN junction so that the current flowing when the PN junction alone is conducted is smaller than the surge withstand capability of the power semiconductor element alone. The current that flows when conducting is limited by the element resistance.

FIG. 19 is a schematic equivalent circuit diagram showing SiC-SBDs connected in parallel. The element resistance before the SiC-SBD1~m the PN junction begins to conduct, respectively to _R 1 to R _m. The element resistance in this case corresponds to the element resistance when only the Schottky junction is conducted and the unipolar operation is performed. For simplicity, R ₁ = R ₂ =... = R _m is set. Here, PN junction of SiC-SBD 1 starts energizing ahead, the element resistance decreases from _{R 1} to _R 1 / n. Note that a state immediately before the PN junction starts to conduct is denoted as state A, and a state after the PN junction is rendered conductive is denoted as state B. Accordingly, in the following, the suffixes A and B indicating the electrical quantity such as voltage indicate whether the electrical quantity is in the state A or the state B.

In an inverter or the like which is a main application of a power semiconductor module, it may be considered that the current is constant. Therefore, in the states A and B, when the voltages applied to the parallel connection of m SiC-SBDm are V _A and V _B , the current I Is expressed as in equation (1).

I = V _A / R _allA = V _B / R _allB (1)
Here, the resistors R _allA and R _allB are parallel connection resistors, and are represented by the equations (2) and (3), respectively.

R _allA = R ₁ / m (2)
R _allB = 1 / {(R ₁ / n) ⁻¹ + (m−1) R ₁ ⁻¹ } = R ₁ / (n + m−1) (3)
Relationship from equation (1) to (3), before and after the conduction of the PN junction, the voltage _{V A} and _{V B} of the whole SiC-SBD is connected in parallel of the formula (4).

V _B = mV _A / (n + m−1) (4)
Therefore, the current values I _1A and I _1B before and after the PN junction conduction of SiC-SBD ₁ have a relationship represented by Expression (5).

I _1B = mnI _1A / (n + m−1) (5)
Here, the surge withstand capability of SiC-SBD 1 in which the PN junction conducts in advance is assumed to be S _PN × I ₀ where the rated current is I ₀ . That is, when the current flowing through the SiC-SBD 1 exceeds the _SPN times the rated current, the SiC-SBD 1 is subjected to surge breakdown alone. Further, it is assumed that the current value at which the PN junction starts to conduct is S _SBD times the rated current I ₀ . Furthermore, the ratio of _SPN and S _SBD is defined as r, as shown in equation (6).

_SPN / S _SBD = r (6)
For SiC-SBD 1 does not surge breakdown alone, the current value _{I 1B} after PN junction conduction SiC-SBD 1 satisfies the condition represented by the formula (7).

I _1B < _SP N × I ₀ (7)
Further, I _1A is represented by the formula (8).

I _1A = S _SBD × I ₀ (8)
From Expressions (5) to (8), Expression (9) is obtained for the condition of n.

n <r × (m−1) / (m−r) (where m> r) (9)
In the equation (9), when the parallel number m is infinite, the equation (10) is obtained.

n <r (10)
In other words, the current of SiC-SBD1 in which the PN junction is conducted first is within the range of the single surge withstand capability as long as equation (10) is satisfied at any parallel number. do not do. Moreover, if Formula (9) is satisfy | filled with respect to the parallel number m, SiC-SBD1 will not destroy.

In the third embodiment, if the SiC-SBD of the first and second embodiments is applied, r = _3/10 (S _PN = 10, S _SBD = 3), and the parallel number m is 40. From 9), n <3.54. That is, if the element resistance after PN junction conduction of SiC-SBD1 is larger than R / 3.54 with respect to the element resistance R before conduction, the single surge of SiC-SBD1 when the PN junction conducts in advance. Destruction can be prevented.

In the power semiconductor module of the third embodiment, a plurality (m) of SiC-SBDs are electrically connected in parallel, and the lower limit value (R _min ) of the element resistance after the PN junction conduction of each SiC-SBD is , Larger than R / r (R _min > R / r) or larger than R × (m−r) / {r × (m−1)} with respect to the element resistance R before conduction. (R _min > R × (m−r) / {r × (m−1)}). Thereby, since the single surge destruction of SiC-SBD which conducts in advance is prevented, the surge current withstand capability of the power semiconductor module is improved.

  In addition, by applying the SiC-SBD of Embodiments 1 and 2, a power semiconductor module having a high surge resistance and a small recovery loss can be obtained.

  The element resistance of SiC-SBD after PN junction conduction can be increased by the following means.

  As one increase means, the area of the p + type impurity region constituting the PN diode portion is limited with respect to the entire active region. For example, the area of the p + type semiconductor region 18 shown in FIG. 9 is limited to 1/10 or less of the area of the n type semiconductor region 11 constituting the Schottky junction. Since the element resistance of a pure PN diode can be 1/5 or less in a state where a large current such as a surge current flows with respect to the element resistance R of the Schottky diode portion before PN junction conduction, the PN as described above Considering the restriction of element resistance after junction conduction, by limiting the area of the p + type semiconductor region 18 to 1/10 or less with respect to the Schottky region 12 (FIG. 9), single surge breakdown during parallel connection can be prevented. Is done. Since holes injected from the p + type impurity region spatially expand in the plane direction of the SiC-SBD chip and flow, preferably the area of the p + type semiconductor region 18 is larger than that of the Schottky region 12 (FIG. 9). 1/15 or less.

  As another element resistance increasing means, a parasitic resistance is added to the PN diode portion. Such increasing means will be described with reference to FIG.

  FIG. 20 is a plan view of a SiC-SBD to which parasitic resistance is added.

  As shown in FIG. 20, a plurality of p + type impurity regions 18 are intermittently provided along the longitudinal direction of the p type impurity region 2 in the p type impurity region 2 having a line pattern. In such a SiC-SBD, the forward current spreads from the p + type semiconductor region 18 in ohmic contact with the upper electrode into the surrounding p type semiconductor region 2 (see arrow 42 in FIG. 20). It flows through the PN junction to the lower n-type semiconductor region 11. Here, since the electric resistance of the p-type impurity region 2 is larger than that of the metal electrode, the p-type impurity region 2 becomes a parasitic resistance to the PN diode portion.

  In terms of an equivalent circuit, a parasitic resistance due to the p-type impurity region 2 is connected in series to the element resistance of the PN diode portion. The magnitude of the parasitic resistance is set by the distance 43 between the p + type impurity regions 18 adjacent in the longitudinal direction of the p type impurity region 2. For example, according to the study of the present inventor, when the distance 43 is 5 μm or more, a parasitic resistance effective for increasing the element resistance can be obtained.

  For SiC-SBDs having other geometric patterns as well as line & space patterns, a plurality of devices can be connected in parallel by increasing the element resistance of the PN diode part under the above-mentioned constraints. In this case, it is possible to prevent single surge destruction.

  In addition, this invention is not limited to the Example mentioned above, Various modifications are included. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and are not necessarily limited to those having all the configurations described. Further, it is possible to add, delete, and replace other configurations for a part of the configuration of each embodiment.

  For example, SiC-SBD is not limited to n-type but may be p-type. In this case, the conductivity type of each semiconductor region in the above embodiment is reversed.

1 active region 2 p-type impurity region 3 cathode electrode 4 PN junction 5 n + type SiC substrate 6 anode electrode 9 Schottky junction 10 n− type SiC epitaxial layer 11 n-type impurity region 12 Schottky region 13 peripheral region 14 channel stopper 15 Schottky electrode 18 p + type semiconductor region 21 wiring electrode 22 insulating circuit board 23 IGBT
24 SiC-SBD
25 Resin case 26 Switching element 27 Rectifier element 50 Emitter sense terminal circuit pattern 51 Gate terminal circuit pattern 52 Main terminal contact 53 Wire bonding

Claims (10)

In a power semiconductor element including a Schottky barrier diode made of silicon carbide,
In the active region where the forward current flows, the power semiconductor element,
A first electrode;
A first semiconductor region of a first conductivity type constituting a Schottky junction with the first electrode;
A second semiconductor region of a second conductivity type electrically connected to the first electrode and forming a PN junction with the first semiconductor region;
A second electrode electrically connected to the first semiconductor region;
Have
The power semiconductor device according to claim 1, wherein the PN junction starts to conduct when the forward current in a range greater than twice and less than or equal to three times the rated current flows. The power semiconductor device according to claim 1,
A power semiconductor element, wherein a planar pattern of the Schottky junction and the second semiconductor region is a line and space pattern. The power semiconductor device according to claim 2,
A power semiconductor element having a line width of 1.5 μm or more and 10 μm or less in the planar pattern of the second semiconductor region. The power semiconductor device according to claim 2,
The power semiconductor element, wherein an impurity concentration of the first semiconductor region is 2 × 10 ¹⁵ atoms / cm ³ or more and 3 × 10 ¹⁶ atoms / cm ³ or less. The power semiconductor element according to claim 4,
A power semiconductor element having a line width of 1.5 μm or more and 10 μm or less in the planar pattern of the second semiconductor region. In a power semiconductor module having a plurality of power semiconductor elements comprising a Schottky barrier diode made of silicon carbide, wherein the plurality of power semiconductor elements are connected in parallel,
In the active region where the forward current flows, the power semiconductor element,
A first electrode;
A first semiconductor region of a first conductivity type constituting a Schottky junction with the first electrode;
A second semiconductor region of a second conductivity type electrically connected to the first electrode and forming a PN junction with the first semiconductor region;
A second electrode electrically connected to the first semiconductor region;
Have
Each of the plurality of power semiconductor elements has a current flowing when the PN junction is conducted so that a current flowing when the PN junction is conducted alone is smaller than a surge resistance of the power semiconductor element alone, The power semiconductor module is limited by an element resistance of the power semiconductor element. In the power semiconductor module according to claim 6,
The parallel number of the power semiconductor elements is m,
_{S PN} multiple of the power semiconductor element rated current _{I 0} is the surge resistance of the sole, and current is the rated current _{S SBD} when the PN junction begins to _conduct, the ratio of _{S PN} and _{S SBD} r _{(= S PN} / S _SBD )
Between the lower limit value R _{min of the} element resistance when the PN junction portion conducts and the value R of the element resistance when the PN junction portion starts conduction, R _min > R × (m−r) / {R × (m−1)} relationship, a power semiconductor module characterized by In the power semiconductor module according to claim 6,
_{S PN} multiple of the power semiconductor element rated current _{I 0} is the surge resistance of the sole, and current is the rated current _{S SBD} when the PN junction begins to _conduct, the ratio of _{S PN} and _{S SBD} r _{(= S PN} / S _SBD )
There is a relationship of R _min > R / r between the lower limit value R _{min of the} element resistance when the PN junction portion conducts and the value R of the element resistance when the PN junction portion starts conduction. A power semiconductor module. The power semiconductor module according to claim 6, wherein
The second semiconductor region is
A first region;
A second region located within the first region and having a higher impurity concentration than the first region;
Have
The power semiconductor module, wherein an area of the second region is one tenth or less of an area of the first semiconductor region. The power semiconductor module according to claim 6, wherein
The second semiconductor region is
A first region;
A plurality of second regions located in the first region and having a higher impurity concentration than the first region;
Have
A power semiconductor module, wherein a distance between adjacent second regions is 5 μm or more.

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