JP2017017303A - Package substrate and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a coreless package structure and a manufacturing method thereof.SOLUTION: A first copper layer and a first plating copper layer formed thereon, a first dielectric layer, a second copper layer and a second plating copper layer formed thereon, a second dielectric layer, and a third copper layer and a third plating copper layer formed thereon are provided and laminated so that the first and second dielectric layers encapsulate edges of the second copper layer and the second plating copper layer to form a temporary carrier. Two circuit structures are formed on two opposite surfaces of the temporary carrier. The temporary carrier and the circuit structures are cut to expose the edges of the second copper layer and the second plating copper layer, and separated along the exposed edges of the second copper layer and the second plating copper layer to form two package substrates independent from each other.SELECTED DRAWING: Figure 1(b)

Description

  The present invention relates to a package substrate and a manufacturing method thereof, and more particularly to a coreless package substrate and a manufacturing method thereof.

  In the semiconductor manufacturing process, the chip mounting substrate is one of the basic components of the mounted component. The chip mounting board may be, for example, a single-layer circuit board, a two-layer circuit board, or a multilayer circuit board configured by alternately stacking a plurality of circuit layers and a plurality of dielectric layers. Generally, circuit layers and dielectric layers in a multilayer circuit board are made on a core substrate having a constant thickness. As thin electronic components have evolved, the thickness of the core substrate has also decreased. However, if the thickness of the core substrate is reduced, the rigidity of the thin core substrate becomes insufficient, and the handling difficulty and the failure rate of the substrate manufacturing process and mounting process are likely to increase.

  Therefore, by using a coreless process in the manufacture of a multilayer circuit board, problems arising in the board and the mounting process can be solved. In the coreless process, the core substrate is not used. A carrier panel is used as a temporary support, a build-up circuit layer is formed thereon, and separated from the carrier after the multilayer circuit board is completed. The conventional coreless process combines a part of the edge of the carrier and a part of the edge of the multilayer circuit board into one. After the manufacturing process (eg, etching, circuit stacking or laser drilling) is completed, the edges of the carrier combined with the multilayer circuit board are cut away, leaving the multilayer circuit layer without the edge region and used in subsequent processes. . However, in the conventional core process, since the carrier and the multilayer circuit layer are combined only at a specific portion, when the thickness of the package substrate is reduced, relative movement is likely to occur during the manufacturing process, or the carrier and the multilayer circuit layer are Deformation occurs in the parts where the cores are not joined, and the failure rate of the coreless manufacturing process further increases. Thus, how to provide a stable temporary carrier and increase the yield of the manufacturing process and the subsequent separation process is a problem that must be solved.

  The present invention provides a package substrate having the advantages of effectively improving the strength and expansion / shrinkage uniformity of a temporary carrier, making it easy to separate plates, and increasing the yield of the manufacturing process and plate separation, and a method for manufacturing the same. .

  The manufacturing method of the package structure of the present invention includes the following steps. First copper layer and first plated copper layer formed thereon, first dielectric layer, second copper layer and second plated copper layer formed thereon, second dielectric layer, third copper layer And a third plated copper layer formed thereon. The first dielectric layer is disposed between the first copper layer and the second copper layer, and the second dielectric layer is disposed between the second plated copper layer and the third copper layer. The edge of the second copper layer is recessed a predetermined distance from the edge of the first copper layer and the edge of the third copper layer. The first dielectric layer and the second dielectric layer completely cover the edge of the second copper layer and the edge of the second plated copper layer thereon, and the edge of the first dielectric layer and the second dielectric layer A first copper layer, a first dielectric layer, a second copper layer, a second copper layer, a second copper layer, a second copper layer, a second copper layer, and a second copper layer; The dielectric layer and the third copper layer are stacked to form a temporary carrier. Two circuit structures are formed on two opposing surfaces of the temporary carrier. Each circuit structure includes at least two patterned circuit layers, an insulating layer disposed between the patterned circuit layers, and a plurality of conductive throughs that penetrate the insulating layer and are electrically connected to the patterned circuit layer. Including a hole structure. The temporary carrier and the circuit structure are cut to expose the edge of the second copper layer and the edge of the second plated copper layer. The temporary carrier and circuit structure are separated along the exposed edge of the second copper layer and the exposed edge of the second plated copper layer to form two independent package substrates.

  In one embodiment of the present invention, the thickness of the first copper layer, the thickness of the second copper layer, and the thickness of the third copper layer are the thickness of the first plated copper layer and the thickness of the second plated copper layer, respectively. It is thicker than the thickness and the thickness of the third plated copper layer.

  In one embodiment of the present invention, the thickness of the first copper layer, the thickness of the second copper layer, and the thickness of the third copper layer are 10 μm to 35 μm.

  In one embodiment of the present invention, the thickness of the first plated copper layer, the thickness of the second plated copper layer, and the thickness of the third plated copper layer are 1 μm to 7 μm.

  In one embodiment of the present invention, the method of stacking the first copper layer, the first dielectric layer, the second copper layer, the second dielectric layer, and the third copper layer is performed by thermo-compression bonding. is there.

  In one embodiment of the present invention, forming two circuit structures on two opposing surfaces of the temporary carrier includes forming patterned circuit layers on the two opposing surfaces of the temporary carrier, respectively. The patterned circuit layer exposes a part of the first plated copper layer and a part of the third plated copper layer, respectively. An insulating layer and a circuit layer thereon are stacked on the patterned circuit layer. The insulating layer and a portion of the circuit layer are removed to form a plurality of blind holes that expose the patterned circuit layer. A plurality of conductive through-hole structures are formed in the blind hole. The conductive through hole structure fills the blind hole and is connected to the circuit layer. The circuit layer is patterned to form two other patterned circuit layers. The patterned circuit layer is electrically connected to the other two patterned circuit layers through a conductive through-hole structure.

  In one embodiment of the invention, the step of separating the temporary carrier and the circuit structure along the exposed edge of the second conductive layer and the edge of the second plated copper layer comprises performing a first separation process, Separating the second copper layer and the second plated copper layer and performing a second separation process to separate the first copper layer and the third copper layer from the first plated copper layer and the third plated copper layer, respectively. And performing a third separation process to separate the first plated copper layer and the third plated copper layer from the patterned circuit layer, respectively, to form independent package substrates.

  The circuit board of the present invention includes a first copper layer, a second copper layer, a third copper layer, a first plated copper layer, a second plated copper layer, a third plated copper layer, and a first dielectric. A layer and a second dielectric layer. The second copper layer is disposed between the first copper layer and the third copper layer, and the edge of the second copper layer is recessed by a predetermined distance from the edge of the first copper layer and the edge of the third copper layer. . The first plated copper layer is disposed on the first copper layer and directly covers the first copper layer. The second plated copper layer is disposed on the second copper layer and directly covers the second copper layer. The third plated copper layer is disposed on the third copper layer and directly covers the third copper layer. The first dielectric layer is disposed between the first copper layer and the second copper layer. The second dielectric layer is disposed between the second plated copper layer and the third copper layer. The first dielectric layer and the second dielectric layer completely cover the edge of the second copper layer and the edge of the second plated copper layer.

  In one embodiment of the present invention, the thickness of the first copper layer, the thickness of the second copper layer, and the thickness of the third copper layer are the thickness of the first plated copper layer and the thickness of the second plated copper layer, respectively. It is thicker than the thickness and the thickness of the third plated copper layer.

  In one embodiment of the present invention, the thickness of the first copper layer, the thickness of the second copper layer, and the thickness of the third copper layer are 10 μm to 35 μm.

  In one embodiment of the present invention, the thickness of the first plated copper layer, the thickness of the second plated copper layer, and the thickness of the third plated copper layer are 1 μm to 7 μm.

  In one embodiment of the present invention, the first plated copper layer and the third plated copper layer are disposed outside the first copper layer and the third copper layer, respectively.

  In one embodiment of the present invention, the edges of the first dielectric layer and the second dielectric layer are substantially aligned with the edges of the first copper layer and the third copper layer.

  As described above, according to the present invention, the edge of the second copper layer and the second plating in which the first dielectric layer and the second dielectric layer are recessed by a predetermined distance from the edges of the first copper layer and the third copper layer are provided. Completely covering the edges of the copper layer, and the edges of the first dielectric layer and the second dielectric layer are substantially aligned with the edges of the first copper layer and the third copper layer The temporary carrier of the present invention has a strong sealing boundary because the dielectric layer completely seals the second copper layer and the second plated copper layer to form a complete sealed border. be able to. In addition, since the first dielectric layer and the second dielectric layer completely cover the edge of the second copper layer and the edge of the second plated copper layer, the strength of the temporary carrier and the expansion / shrinkage uniformity are effective. Can be improved. In addition, the temporary carrier and the circuit structure are separated along the edge of the second copper layer and the edge of the second plated copper layer exposed by cutting the temporary carrier and the circuit structure to form two independent package substrates. There is an advantage that the plate is easily separated.

  In order to make the above and other objects, features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described below.

These are the cross-sectional schematic diagrams which show the manufacturing method of the package structure which concerns on one Embodiment of this invention. These are the cross-sectional schematic diagrams which show the manufacturing method of the package structure which concerns on one Embodiment of this invention. These are the cross-sectional schematic diagrams which show the manufacturing method of the package structure which concerns on one Embodiment of this invention. These are the cross-sectional schematic diagrams which show the manufacturing method of the package structure which concerns on one Embodiment of this invention. These are the cross-sectional schematic diagrams which show the manufacturing method of the package structure which concerns on one Embodiment of this invention. These are the cross-sectional schematic diagrams which show the manufacturing method of the package structure which concerns on one Embodiment of this invention. These are the cross-sectional schematic diagrams which show the manufacturing method of the package structure which concerns on one Embodiment of this invention. These are the cross-sectional schematic diagrams which show the manufacturing method of the package structure which concerns on one Embodiment of this invention. These are the cross-sectional schematic diagrams which show the manufacturing method of the package structure which concerns on one Embodiment of this invention. These are the cross-sectional schematic diagrams which show the manufacturing method of the package structure which concerns on one Embodiment of this invention. These are the cross-sectional schematic diagrams which show the manufacturing method of the package structure which concerns on one Embodiment of this invention. It is the schematic which showed the upper side figure of the temporary carrier of FIG.1 (b).

  FIG. 1A to FIG. 1K are schematic cross-sectional views illustrating a method for manufacturing a package structure according to one embodiment of the present invention. Referring to FIG. 1A, in the method for manufacturing a package structure according to this embodiment, a first copper layer 110 and a first plated copper layer 112, a first dielectric layer 120, and a second copper formed thereon. A layer 130 and a second plated copper layer 132 formed thereon, a second dielectric layer 140, a third copper layer 150, and a third plated copper layer 152 formed thereon are provided. More specifically, the first dielectric layer 120 is disposed between the first copper layer 110 and the second copper layer 130. The second dielectric layer 140 is disposed between the second plated copper layer 132 and the third copper layer 150. Specifically, the edge of the second copper layer 130 of the present embodiment is retracted by a distance D from the edge of the first copper layer 110 and the edge of the third copper layer 150, as shown in FIG. . That is, the width / length of the second copper layer 130 of this embodiment and the second plated copper layer 132 formed thereon are the width / length of the first copper layer 110 and the width / length of the third copper layer 150. Less than length. In another embodiment, the width of the second copper layer 130 and the second plated copper layer 132 formed thereon may only be smaller than the width of the first copper layer 110 and the third copper layer 150. In another embodiment, the length of the second copper layer 130 and the second plated copper layer 132 formed thereon may only be smaller than the length of the first copper layer 110 and the length of the third copper layer 150. .

  As shown to Fig.1 (a), in this embodiment, the 1st copper layer 110, the 2nd copper layer 130, and the 3rd copper layer 150 are copper foil or an electroless-plated copper layer, for example. The first plated copper layer 112, the second plated copper layer 132, and the third plated copper layer 152 are directly formed on the first copper layer 110, the second copper layer 130, and the third copper layer 150, respectively, by electroplating. . That is, the edges of the first plated copper layer 112, the edges of the second plated copper layer 132, and the edges of the third plated copper layer 152 are the edges of the first copper layer 110 and the edges of the second copper layer 130, respectively. In addition, it may be substantially aligned with the edge of the third copper layer 150. Here, the thickness of the first copper layer 110, the thickness of the second copper layer 130, and the thickness of the third copper layer 150 are the thickness of the first plated copper layer 112 and the thickness of the second plated copper layer 132, respectively. And thicker than the thickness of the third plated copper layer 152. Preferably, the thickness of the 1st copper layer 110, the thickness of the 2nd copper layer 130, and the thickness of the 3rd copper layer 150 are 10 micrometers-35 micrometers. The thickness of the 1st plating copper layer 112, the thickness of the 2nd plating copper layer 132, and the thickness of the 3rd plating copper layer 152 are 1 micrometer-7 micrometers.

  Referring to FIG. 1B, the first dielectric layer 120 and the second dielectric layer 140 completely cover the edge of the second copper layer 130 and the edge of the second plated copper layer 132 formed thereon. Covering and substantially aligning the edge of the first dielectric layer 120 and the edge of the second dielectric layer 140 with the edge of the first copper layer 110 and the edge of the third copper layer 150; The first copper layer 110, the first dielectric layer 120, the second copper layer 130, the second dielectric layer 140, and the third copper layer 150 are stacked to form a temporary carrier. Here, the method of stacking the first copper layer 110, the first dielectric layer 120, the second copper layer 130, the second dielectric layer 140, and the third copper layer 150 may be hot-pressure bonding.

  The first dielectric layer 120 and the second dielectric layer 140 of the present embodiment are slightly dissolved depending on the temperature during the hot press bonding. The slightly dissolved first dielectric layer 120 and second dielectric layer 140 are stretched to cover the edge of the second copper layer 130 and the edge of the second plated copper layer 132 formed thereon, Form a complete sealing boundary. In this way, the temporary carrier 100 of this embodiment can have a strong sealing boundary. Here, the edge of the second copper layer 130 is retracted by a distance D from the edge of the first copper layer 110 and the edge of the third copper layer 150. The distance D is the retracted distance D from the long and short sides of the structure, as shown in FIG. In another embodiment not shown, only the long side of the structure may be retracted a predetermined distance, or only the short side of the structure may be retracted a predetermined distance, and the present invention is not limited thereto. In addition, the first dielectric layer 120 and the second dielectric layer 140 completely cover the edge of the second copper layer 130 and the edge of the second plated copper layer 132, so that the strength and expansion / contraction of the temporary carrier 100 are increased. Uniformity can be effectively improved. In other words, the second copper layer 130 and the second plated copper layer 132 covered by the first dielectric layer 120 and the second dielectric layer 140 may change greatly due to heating or cooling during manufacturing (for example, excessive warping (warp ) Or bend), the temporary carrier 100 can have better structural strength and expansion and contraction uniformity.

  Next, referring to FIG. 1 (g), two circuit structures CS 1 and CS 2 are formed on the two opposing surfaces 101 and 102 of the temporary carrier 100. Each circuit structure CS1 (or CS2) has at least two patterned circuit layers 160, 170, an insulating layer 190 disposed between the patterned circuit layers 160, 170, and penetrates the insulating layer 190 and is patterned. A plurality of conductive through hole structures 180 electrically connected to the circuit layers 160 and 170 are included. More specifically, with reference to FIG. 1C, the step of forming the two circuit structures CS1 and CS2 on the two opposing surfaces 101 and 102 of the temporary carrier 100 will be described. A patterned circuit layer 160 is formed on each 102. The patterned circuit layer 160 exposes a part of the first plated copper layer and a part of the third plated copper layer, respectively. Next, referring to FIG. 1D, an insulating layer 190 and a circuit layer C formed thereon are formed on the patterned circuit layer 160, respectively. The method of stacking the insulating layer 190 and the circuit layer C formed thereon on the patterned circuit layer 160 may be, for example, hot-pressure bonding.

  Next, referring to FIG. 1E, a part of the insulating layer 190 and the circuit layer C are removed to form a plurality of blind holes B that expose the patterned circuit layer 160. Here, a method for removing a part of the insulating layer 190 and the circuit layer C is, for example, laser ablation or mechanical drilling, but the present invention is not limited thereto. Next, referring to FIG. 1 (f), a plurality of conductive through-hole structures 180 are formed in the blind hole B. The conductive through-hole structure 180 fills the blind hole B and is connected to the circuit layer C. Here, the method for forming the conductive through-hole structure 180 is, for example, a via filling plating process. Next, referring to FIG. 1G, the circuit layer C is patterned to form two other patterned circuit layers 170. The patterned circuit layer 160 is electrically connected to the patterned circuit layer 170 through the conductive through-hole structure 180. Thus far, the circuit structures CS <b> 1 and CS <b> 2 are formed on the temporary carrier 100.

  Next, referring to FIG. 1H, the temporary carrier 100 and the circuit structures CS1 and CS2 are cut to expose the edge of the second copper layer 130 and the edge of the second plated copper layer 132. Here, the method of cutting the temporary carrier 100 and the circuit structures CS1 and CS2 is, for example, laser cutting or mechanical cutting.

  Next, referring to FIG. 1 (i) and FIG. 1 (k), the temporary carrier 100 and the circuit structures CS1 and CS2 are exposed to the exposed edge of the second copper layer 130 and the exposed edge of the second plated copper layer 132. The two package substrates 10 and 20 separated from each other and independent of each other are formed. More specifically, the step of separating the temporary carrier 100 and the circuit structures CS1 and CS2 along the exposed edge of the second copper layer 130 and the exposed edge of the second plated copper layer 132 will be described with reference to FIG. Referring to i), a first separation process is performed to separate the second copper layer 130 and the second plated copper layer 132. Since the second copper layer 130 and the second plated copper layer 132 are only adhered to the surface, the second copper layer 130 and the second plated copper layer 132 can be easily peeled off using a mechanical force. Next, referring to FIG. 1J, a second separation process is performed to separate the first copper layer 110 and the third copper layer 150 from the first plated copper layer 112 and the third plated copper layer 152, respectively. For example, the first copper layer 110 and the first plated copper layer 112 are peeled off using a mechanical force, and the third copper layer 150 and the third plated copper layer 152 are peeled off using a mechanical force. Finally, referring to FIG. 1 (j) and FIG. 1 (k), a third separation process is performed to form the first plated copper layer 112 and the third plated copper layer 152 in the circuit structures CS1 and CS2, respectively. The package substrates 10 and 20 separated from the layer 160 and independent of each other are formed. Thus, the manufacturing of the package substrates 10 and 20 is completed. The third separation process may be peeled off using a mechanical force, for example, or a micro-etching process may be performed.

  In the present embodiment, the temporary carrier 100 and the circuit structures CS1 and CS2 are arranged along the edge of the second copper layer 130 and the edge of the second plated copper layer 132 exposed by cutting the temporary carrier 100 and the circuit structures CS1 and CS2. Since the independent package substrates 10 and 20 are formed, there is an advantage that the plates can be easily separated.

  As described above, according to the present invention, the edge of the second copper layer and the second plating in which the first dielectric layer and the second dielectric layer are recessed by a predetermined distance from the edges of the first copper layer and the third copper layer are provided. Completely covering the edges of the copper layer, and the edges of the first dielectric layer and the second dielectric layer are substantially aligned with the edges of the first copper layer and the third copper layer That is, since the first dielectric layer and the second dielectric layer completely seal the second copper layer and the second plated copper layer to form a perfect sealing boundary, the temporary carrier of the present invention is strong. It can have a sealing boundary. In addition, since the first dielectric layer and the second dielectric layer completely cover the edge of the second copper layer and the edge of the second plated copper layer, the strength of the temporary carrier and the expansion / shrinkage uniformity are effective. Can be improved. In addition, the temporary carrier and the circuit structure are separated along the edge of the second copper layer and the edge of the second plated copper layer exposed by cutting the temporary carrier and the circuit structure to form two independent package substrates. The advantages of being easy to separate the plates and increasing the yield of the manufacturing process and plate cutting.

  As described above, the present invention has been disclosed by the embodiments. However, the present invention is not intended to limit the present invention, and is within the scope of the technical idea of the present invention so that those skilled in the art can easily understand. Therefore, the scope of patent protection should be defined based on the scope of claims and the equivalent area.

  The present invention relates to a package substrate having an advantage of easily separating plates and a method for manufacturing the same.

10, 20 Package substrate 100 Temporary carrier 101, 102 Surface 110 First copper layer 112 First plated copper layer 120 First dielectric layer 130 Second copper layer 132 Second plated copper layer 140 Second dielectric layer 150 Third copper Layer 152 Third plated copper layer 160, 170 Patterned circuit layer 180 Conductive through hole structure 190 Insulating layer B Blind hole C Circuit layer CS1, CS2 Circuit structure D Distance

Claims (13)

First copper layer and first plated copper layer formed thereon, first dielectric layer, second copper layer and second plated copper layer formed thereon, second dielectric layer, third copper layer And providing a third plated copper layer formed thereon, wherein the first dielectric layer is disposed between the first copper layer and the second copper layer, and the second dielectric layer is provided. A layer is disposed between the second plated copper layer and the third copper layer, and the edge of the second copper layer is more than the edge of the first copper layer and the edge of the third copper layer. Retracting a predetermined distance;
The first dielectric layer and the second dielectric layer completely cover the edge of the second copper layer and the edge of the second plated copper layer thereon, and the edge of the first dielectric layer The first copper layer, the first dielectric layer, such that an edge and an edge of the second dielectric layer are substantially aligned with an edge of the first copper layer and an edge of the third copper layer; Stacking the second copper layer, the second dielectric layer, and the third copper layer to form a temporary carrier;
Forming two circuit structures on two opposing surfaces of the temporary carrier, each circuit structure comprising at least two patterned circuit layers, an insulating layer disposed between the patterned circuit layers, and Including a plurality of conductive through-hole structures penetrating the insulating layer and electrically connected to the patterned circuit layer;
Cutting the temporary carrier and the circuit structure to expose an edge of the second copper layer and an edge of the second plated copper layer;
Separating the temporary carrier and the circuit structure along the exposed edge of the second copper layer and the exposed edge of the second plated copper layer to form two independent package substrates; ,
A method for manufacturing a package structure including:   The thickness of the first copper layer, the thickness of the second copper layer, and the thickness of the third copper layer are the thickness of the first plated copper layer, the thickness of the second plated copper layer, and the thickness of the second copper layer, respectively. The manufacturing method of the package structure of Claim 1 thicker than the thickness of a 3rd plating copper layer.   3. The method for manufacturing a package structure according to claim 2, wherein the thickness of the first copper layer, the thickness of the second copper layer, and the thickness of the third copper layer are 10 μm to 35 μm.   3. The method for manufacturing a package structure according to claim 2, wherein the thickness of the first plated copper layer, the thickness of the second plated copper layer, and the thickness of the third plated copper layer are 1 μm to 7 μm. .   2. The package structure according to claim 1, wherein the method of stacking the first copper layer, the first dielectric layer, the second copper layer, the second dielectric layer, and the third copper layer is hot-pressure bonding. Production method. Forming the two circuit structures on the two opposing surfaces of the temporary carrier;
Forming a patterned circuit layer on each of the two opposing surfaces of the temporary carrier, wherein the patterned circuit layer comprises a part of the first plated copper layer and a part of the third plated copper layer, respectively. Exposing the step,
Stacking an insulating layer and a circuit layer thereon on the patterned circuit layer,
Removing a portion of the insulating layer and the circuit layer to form a plurality of blind holes exposing the patterned circuit layer;
Forming the conductive through-hole structure in the blind hole, the conductive through-hole structure filling the blind hole and connected to the circuit layer;
Patterning the circuit layer to form another two patterned circuit layers, wherein the patterned circuit layer is electrically connected to the other two patterned circuit layers through the conductive through-hole structure. Connected steps;
The manufacturing method of the package structure of Claim 1 containing this. Separating the temporary carrier and the circuit structure along the exposed edge of the second conductive layer and the edge of the second plated copper layer;
Performing a first separation process to separate the second copper layer and the second plated copper layer;
Performing a second separation process to separate the first copper layer and the third copper layer from the first plated copper layer and the third plated copper layer, respectively;
Performing a third separation process to separate the first plated copper layer and the third plated copper layer from the patterned circuit layer, respectively, and forming the package substrates independent of each other;
The manufacturing method of the package structure of Claim 1 containing this. A first copper layer;
A second copper layer;
A third copper layer;
A first plated copper layer disposed on the first copper layer and directly covering the first copper layer;
A second plated copper layer disposed on the second copper layer and directly covering the second copper layer;
A third plated copper layer disposed on the third copper layer and directly covering the third copper layer;
A first dielectric layer disposed between the first copper layer and the second copper layer;
A second dielectric layer disposed between the second plated copper layer and the third copper layer;
The second copper layer is disposed between the first copper layer and the third copper layer, and the edge of the second copper layer is the edge of the first copper layer and the third copper Retract a certain distance from the edge of the layer,
A package structure in which the first dielectric layer and the second dielectric layer completely cover an edge of the second copper layer and an edge of the second plated copper layer.   The thickness of the first copper layer, the thickness of the second copper layer, and the thickness of the third copper layer are the thickness of the first plated copper layer, the thickness of the second plated copper layer, and the thickness of the second copper layer, respectively. The package structure according to claim 8, wherein the package structure is thicker than the third plated copper layer.   The package structure according to claim 9, wherein the thickness of the first copper layer, the thickness of the second copper layer, and the thickness of the third copper layer are 10 μm to 35 μm.   The package structure according to claim 9, wherein the thickness of the first plated copper layer, the thickness of the second plated copper layer, and the thickness of the third plated copper layer are 1 μm to 7 μm.   The package structure according to claim 8, wherein the first plated copper layer and the third plated copper layer are installed outside the first copper layer and the third copper layer, respectively.   The edge of the first dielectric layer and the edge of the second dielectric layer are substantially aligned with the edge of the first copper layer and the edge of the third copper layer. Package structure.

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