JP2017085006A - Compound semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor device capable of reducing the ohmic resistance, and to provide a method of manufacturing the same.SOLUTION: A compound semiconductor device 100 includes a GaN-based carrier transit layer 103, a carrier supply layer 105 of InAlGaN(0<x<1, 0<y<1, 0<x+y≤1) above the carrier transit layer 103, producing two-dimensional electron gas in the carrier transit layer 103, and ohmic electrodes 112, 113 above the carrier supply layer 105. Pits 132, 133 are formed in a region overlapping the ohmic electrodes 112, 113, in the plan view of the carrier supply layer 105, and a part of the ohmic electrodes 112, 113 is entering into the pits 132, 133.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  A high electron mobility transistor (HEMT) using InAlN as a carrier supply layer and GaN as a carrier transit layer is known. In this HEMT, a higher carrier electron density can be expected as compared with a HEMT using AlGaN as a carrier supply layer. This is because the conduction band discontinuity (ΔEc) between InAlN and GaN is larger than that between AlGaN and GaN, and the amount of charge due to natural polarization of InAlN is larger than that of AlGaN. . In a HEMT using InAlN as a carrier supply layer and GaN as a carrier travel layer (hereinafter sometimes referred to as “InAlN / GaN-HEMT”), even if the thickness of the carrier supply layer is as thin as 10 nm or less, A high carrier electron density can be obtained. Therefore, it is not necessary to form a gate recess in order to shorten the distance between the gate and the channel. Therefore, according to InAlN / GaN-HEMT, good gate characteristics such as high mutual conductance (gm) can be obtained, and InAlN / GaN-HEMT is expected as a next-generation device.

  However, InAlN / GaN-HEMT has a property of high ohmic resistance. Such a problem also occurs when InAlGaN is used for the carrier supply layer.

Japanese Patent Laid-Open No. 10-215034 JP 2014-57012 A JP 2003-332562 A

  An object of the present invention is to provide a compound semiconductor device capable of reducing ohmic resistance and a manufacturing method thereof.

In one embodiment of a compound semiconductor device, and the carrier transit layer GaN-based, the the carrier transfer layer causes a two-dimensional electron gas, the carrier transit layer above _{In x Al y Ga 1-xy} N (0 <x <1, 0 <y <1, 0 <x + y ≦ 1) and an ohmic electrode above the carrier supply layer. A pit is formed in a region overlapping the ohmic electrode in plan view of the carrier supply layer, and a part of the ohmic electrode enters the pit.

In one embodiment of the production method of a compound semiconductor device, the carrier transit layer above the GaN-based, causing the two-dimensional electron gas in the carrier transit layer in _{In x Al y Ga 1-xy} N (0 <x <1,0 <Y <1, 0 <x + y ≦ 1), a carrier supply layer is formed, pits are formed in the carrier supply layer, and a plane and a region where the pits of the carrier supply layer are formed above the carrier supply layer The ohmic electrodes that overlap with each other are formed so that part of them enter the pits.

  According to the above compound semiconductor device or the like, the ohmic resistance can be reduced because the ohmic electrode enters the pit of the carrier supply layer.

It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 1st Embodiment. It is sectional drawing which shows the example of the manufacturing method of the compound semiconductor device which concerns on 1st Embodiment to process order. It is sectional drawing which shows the example of the manufacturing method of a compound semiconductor device in order of a process following FIG. 2A. It is sectional drawing to which a part in FIG. 2A was expanded. It is sectional drawing which shows the other example of the manufacturing method of the compound semiconductor device which concerns on 1st Embodiment in process order. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 2nd Embodiment. It is sectional drawing which shows the structure of the compound semiconductor device which concerns on 3rd Embodiment. It is a figure which shows the measurement result of ohmic resistance. It is a figure which shows the discrete package which concerns on 4th Embodiment. It is a connection diagram which shows the PFC circuit which concerns on 5th Embodiment. It is a connection diagram which shows the power supply device which concerns on 6th Embodiment. It is a connection diagram which shows the amplifier which concerns on 7th Embodiment.

  Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

(First embodiment)
First, the first embodiment will be described. The first embodiment relates to a compound semiconductor device including a HEMT. FIG. 1A is a cross-sectional view showing the configuration of the compound semiconductor device according to the first embodiment. FIG.1 (b) is sectional drawing which expanded a part in Fig.1 (a).

As shown in FIG. 1A, the compound semiconductor device 100 according to the first embodiment includes a substrate 101, a buffer layer 102 above the substrate 101, a GaN-based carrier running layer 103 above the buffer layer 102, and carrier running. A spacer layer 104 above the layer 103 and a carrier supply layer 105 above the spacer layer 104 are included. The substrate 101 is, for example, a SiC substrate, a Si substrate, a GaN substrate, or a sapphire substrate. The buffer layer 102 is an AlN layer, for example. The carrier traveling layer 103 is a GaN layer that is not intentionally doped with impurities, for example. The spacer layer 104 is, for example, an AlN layer having a thickness (about 1 nm to 2 nm) through which electrons can tunnel. Carrier supply layer 105 is made of a material which in the carrier transit layer 103 generates a two-dimensional electron gas, for _{example, In x Al y Ga 1-} xy N (0 , such InAlN layer <x <1,0 <y <1 , 0 <x + y ≦ 1) layer. The thickness of the carrier supply layer 105 is, for example, about 5 nm to 15 nm.

  The compound semiconductor device 100 includes a source electrode 112 and a drain electrode 113 above the carrier supply layer 105. An insulating film 121 covering the source electrode 112 and the drain electrode 113 is formed on the carrier supply layer 105. In the insulating film 121, an opening 122 positioned between the source electrode 112 and the drain electrode 113 is formed, and a gate electrode 111 in contact with the carrier supply layer 105 is formed through the opening 122. The material of the insulating film 121 is not particularly limited, and for example, a silicon nitride film is used. The source electrode 112 and the drain electrode 113 are examples of ohmic electrodes.

  Pits 132 are formed in a region of the carrier supply layer 105 that overlaps the source electrode 112 in a plan view, and pits 133 are formed in a region that overlaps the drain electrode 113 in a plan view. As shown in FIG. 1B, the pit 133 penetrates the carrier supply layer 105 and reaches the spacer layer 104, and a part of the drain electrode 113 enters the pit 133 and contacts the spacer layer 104 through the pit 133. ing. Similarly, the pit 132 passes through the carrier supply layer 105 and reaches the spacer layer 104, and a part of the source electrode 112 enters the pit 132 and communicates with the spacer layer 104 through the pit 132.

In the first embodiment, a part of the source electrode 112 is in contact with the spacer layer 104 through the pit 132, a part of the drain electrode 113 is in contact with the spacer layer 104 through the pit 133, and the thickness of the spacer layer 104 is That is the degree to which electrons can tunnel. Therefore, a current path including a portion in the pit 132 of the source electrode 112 and a current path including a portion in the pit 133 of the drain electrode 113 exist, and the contact resistance can be reduced. Further, a portion pits 132 or pits 133 of the carrier supply layer 105 is not formed, although through a thin spacer layer 104, an _{In x Al y Ga 1-xy} N carrier supply layer 105 and the carrier transit layer 103 There is a laminated structure. For this reason, a large amount of two-dimensional electron gas (2DEG) is generated due to spontaneous polarization, and sheet resistance is kept low.

The pits 132 and 133 are preferably formed at a density of 5.0 × 10 ⁸ pieces / cm ² or more in a region overlapping the source electrode 112 and the drain electrode 113 in plan view, respectively. This is because if the density is less than 5.0 × 10 ⁸ pieces / cm ² , excessive current concentration may occur. Furthermore, it is preferable that the difference in density between any two square regions each having a side length of 1 μm in this region is 20 pieces / μm ² or less. This is because if the density difference is more than 20 / μm ² , excessive current concentration may occur in a portion where the density is relatively low.

  The spacer layer 104 may not be included. When the spacer layer 104 is not included, a part of the source electrode 112 and a part of the drain electrode 113 are in direct contact with the carrier traveling layer 103. Therefore, the contact resistance can be further reduced.

  Next, an example of a method for manufacturing the compound semiconductor device according to the first embodiment will be described. 2A to 2B are cross-sectional views illustrating an example of the method of manufacturing the compound semiconductor device according to the first embodiment in the order of steps. 3 is an enlarged cross-sectional view of a part of FIG. 2A.

In this example, first, as shown in FIG. 2A (a), a buffer layer 102, a carrier traveling layer 103, a spacer layer 104, and a carrier supply layer 105 are formed on a substrate 101. The buffer layer 102, the carrier traveling layer 103, the spacer layer 104, and the carrier supply layer 105 are formed by crystal growth such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). It can be formed by the method. Examples of the source gas include trimethylaluminum (TMA) gas that is an Al source, trimethylgallium (TMG) gas that is a Ga source, trimethylindium (TMI) that is an In source, and ammonia (NH ₃ ) gas that is an N source. Use gas. At this time, whether or not trimethylaluminum gas, trimethylgallium gas and trimethylindium gas are supplied and the flow rate are appropriately set according to the composition of the nitride semiconductor layer to be grown. The flow rate of ammonia gas, which is a common material for each nitride semiconductor layer, is, for example, about 100 sccm to 10000 sccm. For example, the growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 800 ° C. to 1200 ° C.

  Next, element isolation regions that define element regions are formed in the carrier traveling layer 103, the spacer layer 104, and the carrier supply layer 105. In the formation of the element isolation region, for example, a photoresist pattern exposing the region where the element isolation region is to be formed is formed on the carrier supply layer 105, and argon (Ar) ion implantation is performed using this pattern as a mask. Dry etching using a chlorine-based gas may be performed using this pattern as an etching mask.

  Thereafter, in the element region, as shown in FIGS. 2A (b) and 3 (a), the region where the source electrode 112 is to be formed and the region where the drain electrode 113 is to be formed are exposed, and other regions are exposed. A covering photoresist mask 130 is formed on the carrier supply layer 105. Subsequently, pits 132 are formed in a region where the source electrode 112 is to be formed in a portion exposed from the mask 130 of the carrier supply layer 105 by, for example, plasma treatment with a chlorine (Cl) gas, and the drain electrode Pits 133 are formed in a region where 113 is to be formed. In forming the pits 132 and 133, for example, an inductive coupled plasma (ICP) etching apparatus is used. According to the study by the present inventors, when the bias power is 3 W or less, the etching of the carrier supply layer 105 hardly progresses due to low energy, but the pits originated from dislocations and defects contained in the carrier supply layer 105. Is formed. And this pit spreads with progress of processing time. Although an ICP etching apparatus is preferable in terms of easy control of the bias power, other etching apparatuses such as a reactive ion etching (RIE) etching apparatus may be used. The mask 130 is removed after the plasma treatment.

  Subsequently, as shown in FIG. 2A (c), the source electrode 112 and the drain electrode 113 are formed on the carrier supply layer 105. The source electrode 112 and the drain electrode 113 can be formed by a lift-off method, for example. That is, a region where the source electrode 112 is to be formed and a region where the drain electrode 113 is to be formed are exposed, and a photoresist pattern covering the other region is formed, and a metal film is formed by vapor deposition using this pattern as a growth mask. Then, the pattern is removed together with the metal film thereon. In the formation of the metal film, for example, a Ti film having a thickness of about 20 nm is formed, and an Al film having a thickness of about 200 nm is formed thereon. Next, for example, heat treatment (for example, rapid thermal annealing (RTA)) is performed at 400 ° C. to 1000 ° C. (for example, about 550 ° C.) in a nitrogen atmosphere to obtain ohmic contact. As shown in FIG. 3B, a part of the drain electrode 113 enters the pit 133 and contacts the spacer layer 104 through the pit 133. Similarly, a part of the source electrode 112 enters the pit 132 and contacts the spacer layer 104 through the pit 132.

  Subsequently, as illustrated in FIG. 2B (d), an insulating film 121 covering the source electrode 112 and the drain electrode 113 is formed on the carrier supply layer 105. As the insulating film 121, a silicon nitride film is formed by, for example, a plasma CVD chemical vapor deposition (CVD) method. The insulating film 121 can also be formed by, for example, atomic layer deposition (ALD) method or sputtering method. The thickness of the insulating film 121 is about 100 nm, for example.

Next, as shown in FIG. 2B (e), an opening 122 for the gate electrode 111 is formed in the insulating film 121 so that a part of the carrier supply layer 105 is exposed from the opening 122. In forming the opening 122, for example, a photoresist pattern that exposes a region where the opening 122 is to be formed and covers the other region is formed on the carrier supply layer 105, and this pattern is used as an etching mask. 121 is dry-etched. In this dry etching, a fluorine-based gas such as SF ₆ is used. The opening 122 may be formed by wet etching or ion milling.

  Thereafter, as shown in FIG. 2B (f), a gate electrode 111 including a portion in the opening 122 is formed. The lower surface of the gate electrode 111 is in contact with the upper surface of the carrier supply layer 105 in the opening 122. The gate electrode 111 can be formed by, for example, a lift-off method. That is, a photoresist pattern exposing a region where the gate electrode 111 is to be formed is formed, a metal film is formed by vapor deposition using this pattern as a growth mask, and this pattern is removed together with the metal film thereon. In the formation of the metal film, for example, a Ni film having a thickness of about 10 nm is formed, and an Au film having a thickness of about 300 nm is formed thereon.

  And a protective film, wiring, etc. are formed as needed and a compound semiconductor device is completed.

According to this method, pits 132 and pits 133 having a diameter of about 10 nm to 100 nm can be formed at a density of 5.0 × 10 ⁸ pieces / cm ² or more while suppressing variation in density.

  Next, another example of the method for manufacturing the compound semiconductor device according to the first embodiment will be described. FIG. 4 is a cross-sectional view showing another example of the manufacturing method of the compound semiconductor device according to the first embodiment in the order of steps.

  In this example, first, as shown in FIG. 4A, processing up to the formation of the carrier supply layer 105 is performed in the same manner as in the above example. Next, a photoresist mask 230 is formed on the carrier supply layer 105 so as to expose a region where the source electrode 112 is to be formed and a region where the drain electrode 113 is to be formed. Thereafter, pits 132 are formed in a region where the source electrode 112 is to be formed in a portion exposed from the mask 230 of the carrier supply layer 105 by, for example, wet treatment using tetramethylammonium hydroxide (TMAH). And pits 133 are formed in the region where the drain electrode 113 is to be formed. According to the study by the present inventors, pits starting from dislocations and defects included in the carrier supply layer 105 are formed by TMAH. The wet treatment is preferably performed in a dark room so that the mask 230 is not exposed. Etchants other than TMAH such as a mixed solution of sulfuric acid and hydrogen peroxide solution, hydrofluoric acid, hydrochloric acid, and potassium hydroxide may be used for the wet treatment. Two or more of these may be used. In the wet treatment, for example, the carrier supply layer 105 is immersed in an etchant. The mask 230 is removed after the plasma treatment.

  Subsequently, as shown in FIG. 4B, the processes after the formation of the source electrode 112 and the drain electrode 113 are performed in the same manner as in the above example.

  And a protective film, wiring, etc. are formed as needed and a compound semiconductor device is completed.

According to this method, the density of pits 132 and 133 having a diameter of about 10 nm to 100 nm is suppressed to 5.0 × 10 ⁸ pieces / cm ² or more, for example, 1.5 × 10 ¹⁰ pieces / cm ² while suppressing variation in density. It can be formed with a density of about cm ² .

(Second Embodiment)
Next, a second embodiment will be described. The second embodiment relates to a compound semiconductor device including a HEMT. FIG. 5A is a cross-sectional view showing the configuration of the compound semiconductor device according to the second embodiment. FIG. 5B is an enlarged cross-sectional view of a part of FIG.

  In the compound semiconductor device 200 according to the second embodiment, as shown in FIGS. 5A and 5B, a part of the plurality of pits 132 penetrates the carrier supply layer 105 and reaches the spacer layer 104. A part of the pit 132 is stopped in the thickness direction of the carrier supply layer 105. Similarly, some of the plurality of pits 133 penetrate the carrier supply layer 105 and reach the spacer layer 104, and some of the plurality of pits 133 are stopped in the thickness direction of the carrier supply layer 105. The distance between the lower end of the pit 132 and the 2DEG and the distance between the lower end of the pit 133 and the 2DEG are equal to or less than a distance that allows electron tunneling. Other configurations are the same as those of the first embodiment.

  In the second embodiment, a part of the source electrode 112 is in contact with the spacer layer 104 through the pit 132, and a part of the drain electrode 113 is in contact with the spacer layer 104 through the pit 133. That is the degree to which electrons can tunnel. Although some pits 132 and some pits 133 are not in contact with the spacer layer 104, the distances between the lower ends of these pits 132 and pits 133 and 2DEG are short, and electron tunneling is possible. Therefore, the contact resistance can be reduced.

  As in the first embodiment, the spacer layer 104 may not be included. When the spacer layer 104 is not included, the contact resistance can be further reduced.

  The compound semiconductor device 200 according to the second embodiment can be manufactured in the same manner as in the first embodiment, except for changing the conditions of plasma processing or wet etching.

(Third embodiment)
Next, a third embodiment will be described. The third embodiment relates to a compound semiconductor device including a HEMT. FIG. 6A is a cross-sectional view showing the configuration of the compound semiconductor device according to the third embodiment. FIG. 6B is an enlarged cross-sectional view of a part of FIG.

  In the compound semiconductor device 300 according to the third embodiment, as shown in FIGS. 6A and 6B, a plurality of pits 133 are stopped in the thickness direction of the carrier supply layer 105. Similarly, a plurality of pits 132 are stopped in the thickness direction of the carrier supply layer 105. The distance between the lower end of the pit 132 and the 2DEG and the distance between the lower end of the pit 133 and the 2DEG are equal to or less than a distance that allows electron tunneling. Other configurations are the same as those of the first embodiment.

  In the third embodiment, the pits 132 and 133 are not in contact with the spacer layer 104, but the distance between the lower ends of these pits 132 and pits 133 and 2DEG is short, and electron tunneling is possible. Therefore, the contact resistance can be reduced.

  As in the first embodiment, the spacer layer 104 may not be included. When the spacer layer 104 is not included, the contact resistance can be further reduced.

  The compound semiconductor device 300 according to the third embodiment can be manufactured in the same manner as in the first embodiment except for changing the conditions of plasma processing or wet etching.

  Next, the test conducted by the present inventors and the result thereof will be described. In this test, the compound semiconductor device 100 according to the first embodiment was manufactured, and a compound semiconductor device of a reference example was manufactured for comparison. In the reference example, the formation of the pits 132 and 133 is omitted. And the ohmic resistance of the source electrode and drain electrode in these was measured. The result is shown in FIG.

As shown in FIG. 7, the ohmic resistance of the reference example was 1.0 × 10 ⁻⁵ Ω · cm ² , whereas the ohmic resistance of the first embodiment was 3.0 × 10 ⁻⁶ Ω · cm ^2. cm ² . That is, according to the first embodiment, the ohmic resistance can be reduced to less than 1/3 that of the reference example.

(Fourth embodiment)
Next, a fourth embodiment will be described. The fourth embodiment relates to a HEMT discrete package. FIG. 8 is a diagram illustrating a discrete package according to the fourth embodiment.

  In the fourth embodiment, as shown in FIG. 8, the back surface of the HEMT chip 1210 of the HEMT of the first, second, or third embodiment is formed on a land (die pad) 1233 using a die attach agent 1234 such as solder. It is fixed. A wire 1235d such as an Al wire is connected to the drain pad 1226d to which the drain electrode 113 is connected, and the other end of the wire 1235d is connected to a drain lead 1232d integrated with the land 1233. A wire 1235 s such as an Al wire is connected to the source pad 1226 s connected to the source electrode 112, and the other end of the wire 1235 s is connected to a source lead 1232 s independent of the land 1233. A wire 1235g such as an Al wire is connected to the gate pad 1226g connected to the gate electrode 111, and the other end of the wire 1235g is connected to a gate lead 1232g independent of the land 1233. The land 1233, the HEMT chip 1210, and the like are packaged with the mold resin 1231 so that a part of the gate lead 1232g, a part of the drain lead 1232d, and a part of the source lead 1232s protrude.

  Such a discrete package can be manufactured as follows, for example. First, the HEMT chip 1210 is fixed to the land 1233 of the lead frame using a die attach agent 1234 such as solder. Next, by bonding using wires 1235g, 1235d, and 1235s, the gate pad 1226g is connected to the gate lead 1232g of the lead frame, the drain pad 1226d is connected to the drain lead 1232d of the lead frame, and the source pad 1226s is connected to the source of the lead frame. Connect to lead 1232s. Thereafter, sealing using a mold resin 1231 is performed by a transfer molding method. Subsequently, the lead frame is separated.

(Fifth embodiment)
Next, a fifth embodiment will be described. The fifth embodiment relates to a PFC (Power Factor Correction) circuit including a HEMT. FIG. 9 is a connection diagram illustrating a PFC circuit according to the fifth embodiment.

  The PFC circuit 1250 is provided with a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an AC power supply (AC) 1257. The drain electrode of the switch element 1251 is connected to the anode terminal of the diode 1252 and one terminal of the choke coil 1253. A source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 and the other terminal of the choke coil 1253 are connected. The other terminal of the capacitor 1255 and the cathode terminal of the diode 1252 are connected. A gate driver is connected to the gate electrode of the switch element 1251. An AC 1257 is connected between both terminals of the capacitor 1254 via a diode bridge 1256. A direct current power supply (DC) is connected between both terminals of the capacitor 1255. In this embodiment, the HEMT of the first, second, or third embodiment is used for the switch element 1251.

  In manufacturing the PFC circuit 1250, the switch element 1251 is connected to the diode 1252, the choke coil 1253, and the like using, for example, solder.

(Sixth embodiment)
Next, a sixth embodiment will be described. The sixth embodiment relates to a power supply device including a HEMT. FIG. 10 is a connection diagram illustrating the power supply device according to the sixth embodiment.

  The power supply device is provided with a high-voltage primary circuit 1261 and a low-voltage secondary circuit 1262, and a transformer 1263 disposed between the primary circuit 1261 and the secondary circuit 1262.

  The primary circuit 1261 is provided with an inverter circuit connected between both terminals of the PFC circuit 1250 according to the fifth embodiment and the capacitor 1255 of the PFC circuit 1250, for example, a full bridge inverter circuit 1260. The full bridge inverter circuit 1260 is provided with a plurality (here, four) of switch elements 1264a, 1264b, 1264c, and 1264d.

  The secondary side circuit 1262 is provided with a plurality (three in this case) of switch elements 1265a, 1265b, and 1265c.

  In the present embodiment, the switch element 1251 of the PFC circuit 1250 and the switch elements 1264a, 1264b, 1264c, and 1264d of the full bridge inverter circuit 1260 constituting the primary side circuit 1261 are the same as those of the first, second, or third embodiment. HEMT is used. On the other hand, normal MIS type FETs (field effect transistors) using silicon are used for the switch elements 1265a, 1265b, and 1265c of the secondary side circuit 1262.

(Seventh embodiment)
Next, a seventh embodiment will be described. The seventh embodiment relates to an amplifier including a HEMT. FIG. 11 is a connection diagram illustrating an amplifier according to the seventh embodiment.

  The amplifier is provided with a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

  The digital predistortion circuit 1271 compensates for nonlinear distortion of the input signal. The mixer 1272a mixes the input signal compensated for nonlinear distortion and the AC signal. The power amplifier 1273 includes the HEMT according to the first, second, or third embodiment, and amplifies the input signal mixed with the AC signal. In the present embodiment, for example, by switching the switch, the signal on the output side can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271. This amplifier can be used as a high-frequency amplifier or a high-power amplifier. The high-frequency amplifier can be used in, for example, a mobile phone base station transceiver device, a radar device, and a microwave generator.

  Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.

(Appendix 1)
A GaN-based carrier traveling layer;
Producing a two-dimensional electron gas in the carrier transit layer, the carrier of the carrier transit layer above _{In x Al y Ga 1-xy} N (0 <x <1,0 <y <1,0 <x + y ≦ 1) A supply layer,
An ohmic electrode above the carrier supply layer;
Have
Pits are formed in a region overlapping the ohmic electrode in plan view of the carrier supply layer,
A compound semiconductor device, wherein a part of the ohmic electrode enters the pit.

(Appendix 2)
The compound semiconductor device according to appendix 1, wherein a distance between a lower end of the pit and the two-dimensional electron gas is equal to or shorter than a distance at which electrons can tunnel.

(Appendix 3)
3. The compound semiconductor device according to appendix 1 or 2, wherein the pit penetrates the carrier supply layer.

(Appendix 4)
4. The compound semiconductor device according to claim 1, wherein the pits are formed in the region at a density of 5.0 × 10 ⁸ pieces / cm ² or more.

(Appendix 5)
Any one of Supplementary notes 1 to 4, wherein a difference in density of the pits between any two square regions each having a side length of 1 μm in the region is 20 pieces / μm ² or less. The compound semiconductor device according to item.

(Appendix 6)
The compound semiconductor device according to any one of appendices 1 to 5, wherein the composition of the carrier supply layer is represented by InAlN.

(Appendix 7)
A power supply device comprising the compound semiconductor device according to any one of appendices 1 to 6.

(Appendix 8)
An amplifier comprising the compound semiconductor device according to any one of appendices 1 to 6.

(Appendix 9)
The carrier transit layer above the GaN-based, causing the two-dimensional electron gas in the carrier transit layer in _{In x Al y Ga 1-xy} N (0 <x <1,0 <y <1,0 <x + y ≦ 1) Forming a carrier supply layer of
Forming pits in the carrier supply layer;
Forming a ohmic electrode that overlaps the carrier supply layer in a plan view with a region where the pits are formed in the carrier supply layer so as to partially enter the pits;
A method for producing a compound semiconductor device, comprising:

(Appendix 10)
10. The method of manufacturing a compound semiconductor device according to appendix 9, wherein the step of forming the pit includes a step of performing a plasma treatment of a chlorine-based gas on the carrier supply layer.

(Appendix 11)
In the step of forming the pits, wet treatment using a mixed solution of tramethylammonium hydroxide, sulfuric acid and hydrogen peroxide water, hydrofluoric acid, hydrochloric acid, potassium hydroxide, or any combination thereof is performed on the carrier supply layer. The method for manufacturing a compound semiconductor device according to appendix 9, wherein the method includes a step.

100, 200, 300: Compound semiconductor device 103: Carrier traveling layer 104: Spacer layer 105: Carrier supply layer 112: Source electrode 113: Drain electrode

Claims (8)

A GaN-based carrier traveling layer;
Producing a two-dimensional electron gas in the carrier transit layer, the carrier of the carrier transit layer above _{In x Al y Ga 1-xy} N (0 <x <1,0 <y <1,0 <x + y ≦ 1) A supply layer,
An ohmic electrode above the carrier supply layer;
Have
Pits are formed in a region overlapping the ohmic electrode in plan view of the carrier supply layer,
A compound semiconductor device, wherein a part of the ohmic electrode enters the pit.   The compound semiconductor device according to claim 1, wherein a distance between a lower end of the pit and the two-dimensional electron gas is equal to or shorter than a distance at which electrons can tunnel.   The compound semiconductor device according to claim 1, wherein the pit penetrates the carrier supply layer.   A power supply device comprising the compound semiconductor device according to claim 1.   An amplifier comprising the compound semiconductor device according to claim 1. The carrier transit layer above the GaN-based, causing the two-dimensional electron gas in the carrier transit layer in _{In x Al y Ga 1-xy} N (0 <x <1,0 <y <1,0 <x + y ≦ 1) Forming a carrier supply layer of
Forming pits in the carrier supply layer;
Forming a ohmic electrode that overlaps the carrier supply layer in a plan view with a region where the pits are formed in the carrier supply layer so as to partially enter the pits;
A method for producing a compound semiconductor device, comprising:   The method of manufacturing a compound semiconductor device according to claim 6, wherein the step of forming the pit includes a step of performing a plasma treatment of a chlorine-based gas on the carrier supply layer.   In the step of forming the pits, wet treatment using a mixed solution of tramethylammonium hydroxide, sulfuric acid and hydrogen peroxide water, hydrofluoric acid, hydrochloric acid, potassium hydroxide, or any combination thereof is performed on the carrier supply layer. The method of manufacturing a compound semiconductor device according to claim 6, further comprising a step.

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