JP2016213318A - ウエーハの加工方法 - Google Patents
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- 238000003672 processing method Methods 0.000 title claims abstract description 20
- 239000002390 adhesive tape Substances 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 41
- 238000010438 heat treatment Methods 0.000 claims abstract description 20
- 239000004820 Pressure-sensitive adhesive Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 abstract description 57
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 230000001678 irradiating effect Effects 0.000 abstract description 5
- 230000035699 permeability Effects 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 126
- 230000003287 optical effect Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000011218 segmentation Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000004800 polyvinyl chloride Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
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Abstract
【解決手段】ウエーハ2の表面に粘着テープ3を貼着する粘着テープ貼着工程と、ウエーハに対して透過性を有する波長のパルスレーザー光線の集光点をウエーハの裏面側から内部に位置付けて分割予定ラインに沿って照射し、ウエーハの内部に分割予定ラインに沿って改質層210を形成する改質層形成工程と、改質層形成工程が実施されたウエーハの表面に貼着している粘着テープを加熱することにより、改質層からウエーハの表面に向けてクラック211を伸長させる粘着テープ加熱工程と、粘着テープ加熱工程が実施されたウエーハに外力を付与し、ウエーハを改質層及び表面に向けて伸長するクラックが形成された分割予定ラインに沿って個々のデバイスに分割する分割工程とを含む。
【選択図】図5
Description
ウエーハの表面に粘着テープを貼着する粘着テープ貼着工程と、
ウエーハに対して透過性を有する波長のパルスレーザー光線の集光点をウエーハの裏面側から内部に位置付けて分割予定ラインに沿って照射し、ウエーハの内部に分割予定ラインに沿って改質層を形成する改質層形成工程と、
該改質層形成工程が実施されたウエーハの表面に貼着されている粘着テープを加熱することにより、改質層からウエーハの表面に向けてクラックを伸長させる粘着テープ加熱工程と、
該粘着テープ加熱工程が実施されたウエーハに外力を付与し、ウエーハを改質層および表面に向けて伸長するクラックが形成された分割予定ラインに沿って個々のデバイスに分割する分割工程と、を含む、
ことを特徴とするウエーハの加工方法が提供される。
この改質層形成工程は、先ず上述した図3に示すレーザー加工装置4のチャックテーブル41上に上記粘着テープ貼着工程が実施された半導体ウエーハ2の粘着テープ3側を載置する。そして、図示しない吸引手段によってチャックテーブル41上に半導体ウエーハ2を粘着テープ3を介して吸引保持する(ウエーハ保持工程)。従って、チャックテーブル41上に保持された半導体ウエーハ2は、裏面2bが上側となる。このようにして、半導体ウエーハ2を吸引保持したチャックテーブル41は、図示しない加工送り手段によって撮像手段43の直下に位置付けられる。
波長 ;1064nmのパルスレーザー
繰り返し周波数 :100kHz
平均出力 :1W
集光スポット径 ;φ1μm
加工送り速度 ;100mm/秒
この実施形態においては、先ず上記粘着テープ加熱工程が実施された半導体ウエーハ2の裏面2bにダイシングテープを貼着し該ダイシングテープの外周部を環状のフレームによって支持するウエーハ支持工程を実施する。即ち、図7に示すように、環状のフレームFの内側開口部を覆うように外周部が装着されたダイシングテープTの表面に上述した粘着テープ加熱工程が実施された半導体ウエーハ2の裏面2bを貼着する。そして、半導体ウエーハ2の表面2aに貼着されている粘着テープ3を剥離する。従って、ダイシングテープTの表面に貼着された半導体ウエーハ2は、表面2aが上側となる。
21:分割予定ライン
22:デバイス
3:粘着テープ
4:レーザー加工装置
41:レーザー加工装置のチャックテーブル
42:レーザー光線照射手段
422:集光器
5:ホットプレート
6:研削装置
61:研削装置のチャックテーブル
62:研削手段
66:研削ホイール
7:テープ拡張装置
71:フレーム保持手段
72:テープ拡張手段
73:ピックアップコレット
F:環状のフレーム
T:ダイシングテープ
Claims (2)
- 表面に複数の分割予定ラインが格子状に形成されているとともに該複数の分割予定ラインによって区画された複数の領域にデバイスが形成されたウエーハを、分割予定ラインに沿って個々のデバイスに分割するウエーハの加工方法であって、
ウエーハの表面に粘着テープを貼着する粘着テープ貼着工程と、
ウエーハに対して透過性を有する波長のパルスレーザー光線の集光点をウエーハの裏面側から内部に位置付けて分割予定ラインに沿って照射し、ウエーハの内部に分割予定ラインに沿って改質層を形成する改質層形成工程と、
該改質層形成工程が実施されたウエーハの表面に貼着されている粘着テープを加熱することにより、改質層からウエーハの表面に向けてクラックを伸長させる粘着テープ加熱工程と、
該粘着テープ加熱工程が実施されたウエーハに外力を付与し、ウエーハを改質層および表面に向けて伸長するクラックが形成された分割予定ラインに沿って個々のデバイスに分割する分割工程と、を含む、
ことを特徴とするウエーハの加工方法。 - 該分割工程は、ウエーハの表面に貼着された粘着テープ側をチャックテーブルに保持し、ウエーハの裏面を研削砥石で研削して所定の厚みに形成するとともに、ウエーハを改質層および表面に向けて伸長するクラックが形成された分割予定ラインに沿って個々のデバイスに分割する、請求項1記載のウエーハの加工方法。
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JP2015095680A JP6456766B2 (ja) | 2015-05-08 | 2015-05-08 | ウエーハの加工方法 |
TW105110762A TWI665720B (zh) | 2015-05-08 | 2016-04-06 | 晶圓的加工方法 |
KR1020160052128A KR102437901B1 (ko) | 2015-05-08 | 2016-04-28 | 웨이퍼의 가공 방법 |
CN201610289115.6A CN106129003B (zh) | 2015-05-08 | 2016-05-04 | 晶片的加工方法 |
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JP2016213318A true JP2016213318A (ja) | 2016-12-15 |
JP6456766B2 JP6456766B2 (ja) | 2019-01-23 |
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CN (1) | CN106129003B (ja) |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2018182078A (ja) * | 2017-04-13 | 2018-11-15 | 株式会社ディスコ | 分割方法 |
CN108987341A (zh) * | 2017-06-05 | 2018-12-11 | 株式会社迪思科 | 芯片的制造方法 |
CN110098148A (zh) * | 2018-01-30 | 2019-08-06 | 株式会社迪思科 | 晶片的加工方法 |
KR20190103942A (ko) * | 2018-02-28 | 2019-09-05 | 가부시기가이샤 디스코 | 피가공물의 가공 방법 |
KR20200024708A (ko) | 2018-08-28 | 2020-03-09 | 가부시기가이샤 디스코 | 테이블 |
KR20200039559A (ko) | 2018-10-05 | 2020-04-16 | 가부시기가이샤 디스코 | 웨이퍼의 가공 방법 |
CN111162042A (zh) * | 2018-11-08 | 2020-05-15 | 株式会社迪思科 | 晶片的加工方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP6879832B2 (ja) * | 2017-06-14 | 2021-06-02 | 株式会社ディスコ | ウェーハの加工方法 |
JP7088768B2 (ja) * | 2018-07-24 | 2022-06-21 | 株式会社ディスコ | ウェーハの分割方法 |
JP7154860B2 (ja) * | 2018-07-31 | 2022-10-18 | 株式会社ディスコ | ウエーハの加工方法 |
TWI727860B (zh) * | 2020-07-22 | 2021-05-11 | 環球晶圓股份有限公司 | 晶圓橫向撞擊測試裝置及晶圓強度測試方法 |
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- 2016-04-06 TW TW105110762A patent/TWI665720B/zh active
- 2016-04-28 KR KR1020160052128A patent/KR102437901B1/ko active IP Right Grant
- 2016-05-04 CN CN201610289115.6A patent/CN106129003B/zh active Active
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Cited By (14)
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JP2018182078A (ja) * | 2017-04-13 | 2018-11-15 | 株式会社ディスコ | 分割方法 |
JP7217585B2 (ja) | 2017-04-13 | 2023-02-03 | 株式会社ディスコ | 分割方法 |
CN108987341A (zh) * | 2017-06-05 | 2018-12-11 | 株式会社迪思科 | 芯片的制造方法 |
CN108987341B (zh) * | 2017-06-05 | 2024-03-01 | 株式会社迪思科 | 芯片的制造方法 |
CN110098148A (zh) * | 2018-01-30 | 2019-08-06 | 株式会社迪思科 | 晶片的加工方法 |
KR20190103942A (ko) * | 2018-02-28 | 2019-09-05 | 가부시기가이샤 디스코 | 피가공물의 가공 방법 |
KR102586315B1 (ko) | 2018-02-28 | 2023-10-06 | 가부시기가이샤 디스코 | 피가공물의 가공 방법 |
US11460354B2 (en) | 2018-08-28 | 2022-10-04 | Disco Corporation | Table |
KR20200024708A (ko) | 2018-08-28 | 2020-03-09 | 가부시기가이샤 디스코 | 테이블 |
JP2020061398A (ja) * | 2018-10-05 | 2020-04-16 | 株式会社ディスコ | ウエーハの加工方法 |
US11322404B2 (en) * | 2018-10-05 | 2022-05-03 | Disco Corporation | Wafer processing method |
KR20200039559A (ko) | 2018-10-05 | 2020-04-16 | 가부시기가이샤 디스코 | 웨이퍼의 가공 방법 |
KR20200053427A (ko) | 2018-11-08 | 2020-05-18 | 가부시기가이샤 디스코 | 웨이퍼의 가공 방법 |
CN111162042A (zh) * | 2018-11-08 | 2020-05-15 | 株式会社迪思科 | 晶片的加工方法 |
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JP6456766B2 (ja) | 2019-01-23 |
TWI665720B (zh) | 2019-07-11 |
CN106129003A (zh) | 2016-11-16 |
CN106129003B (zh) | 2019-05-31 |
KR102437901B1 (ko) | 2022-08-29 |
KR20160131905A (ko) | 2016-11-16 |
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