JP2016111255A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device manufacturing method which can prevent a solder scattered at the time of reflow from adhering to a top face of a semiconductor element thereby to improve productivity.SOLUTION: A semiconductor device manufacturing method comprises the steps of: mounting on a base plate 3a, a positioning jig 12 which has an opening 13 and a protrusion 14 provided on an internal surface of the opening 13; placing a solder 4 on the base plate 3a in the opening 13; mounting on the solder 4a in the opening 13, a transistor element 1a which has an upper surface electrode 11a and a lower surface electrode 11c on an upper surface and a lower surface, respectively; and performing reflow in a state where the protrusion 14 is arranged on the side of the transistor element 1a to bond the lower surface electrode 11c of the transistor element 1a to the base plate 3a by the solder 4a, thereby blocking the solder 4a scattered at the time of reflow by the protrusion 14.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a method of manufacturing a semiconductor device applied to an inverter for controlling a motor of an automobile, a train or the like, a power generation, a regeneration converter, or the like.

  When the soldering is performed by reduced pressure reflow, a positioning jig is placed on the base plate, and solder and a semiconductor element are placed on the base plate in order within the opening of the positioning jig. At the time of reflow, the voids in the solder come off and the solder scatters. Note that scattered solder does not adhere to the portion of the base plate covered with the jig (see, for example, Patent Document 1 (paragraph 0036, FIG. 4)).

JP 2010-272650 A

  Since the inner surface of the opening of the conventional jig is a vertical plane, the solder scattered during reflow rebounds on the inner surface of the opening of the jig and reaches the upper surface of the semiconductor element. As a result, there are many cases where solder adheres to the upper surface electrode of the semiconductor element or adheres to a position where it interferes with the tool of the wire bonder, and the wire cannot be bonded to the upper surface electrode, resulting in a failure. As a result, there is a problem that productivity is lowered.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to improve productivity by preventing solder scattered during reflow from adhering to the upper surface of a semiconductor element. A manufacturing method is obtained.

  The method of manufacturing a semiconductor device according to the present invention includes a step of placing a positioning jig having an opening and a protrusion provided on an inner surface of the opening on the base plate, and placing solder on the base plate in the opening. Reflow in a state where a semiconductor element having an upper surface electrode and a lower surface electrode on the upper surface and the lower surface, respectively, is placed on the solder in the opening, and the protrusion is disposed on the side of the semiconductor element. A step of joining the lower surface electrode of the semiconductor element to the base plate with the solder and damaging the solder scattered during the reflow with the protrusion.

  In the present invention, the solder scattered at the time of reflow is blocked by the protrusion provided on the inner side surface of the opening of the positioning jig. As a result, it is possible to improve the productivity by preventing the solder scattered during the reflow from adhering to the upper surface of the semiconductor element.

1 is a circuit diagram showing a semiconductor device according to a first embodiment of the present invention. 1 is a perspective top view showing the inside of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing along I-II of FIG. It is sectional drawing to which a part of FIG. 3 was expanded. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 1 of this invention. 2 is a flowchart of a method for manufacturing a semiconductor device according to the first embodiment of the present invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is a top view which shows the manufacturing method of the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 3 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 4 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 5 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 6 of this invention. It is a flowchart of the manufacturing method of the semiconductor device which concerns on Embodiment 6 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 7 of this invention. It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Embodiment 8 of this invention.

  A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a semiconductor device according to the first embodiment of the present invention. Six pairs of transistor elements 1a to 1f and diodes 2a to 2f form a three-phase half-bridge circuit. Power from the power supply is supplied to the load via the U, V, and W terminals. The transistor elements 1a to 1f are insulated gate bipolar transistors (IGBTs) that conduct current supplied from a power source for a necessary time. The diodes 2a to 2f are free wheel diodes that circulate current when the transistor elements 1a to 1f change from the conductive state to the cut off state.

  FIG. 2 is a transparent top view showing the inside of the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line I-II in FIG.

  The base plate 3a and the base plates 3b to 3d are spaced apart from each other on the left and right. The base plates 3b to 3d are separated from each other. Transistor elements 1a to 1c and diodes 2a to 2c are mounted on a base plate 3a, and their lower surfaces are joined to the base plate 3a with solder 4a. Transistor elements 1d to 1f and diodes 2d to 2f are mounted on base plates 3b to 3d, respectively, and their lower surfaces are individually joined to base plates 3b to 3d with solder 4b.

  The wiring members 5a to 5c separated from each other are individually joined to the upper surfaces of the transistor elements 1a to 1c and the diodes 2a to 2c by solder 4c. A wiring member 5d is commonly bonded to the upper surfaces of the transistor elements 1d to 1f and the diodes 2d to 2f with solder 4d. The wiring members 5a to 5c are joined to the peripheral portions of the upper surfaces of the base plates 3b to 3d, respectively. The wiring member 5e is joined to the peripheral edge of the upper surface of the base plate 3a.

  The signal wirings 6a to 6f are connected to the control terminals of the transistor elements 1a to 1f by wires 7, respectively. The insulating substrate integrated fins 8 are provided on the lower surfaces of the base plates 3a to 3d. A case 9 is arranged so as to surround the transistor elements 1a to 1c and the diodes 2a to 2c. In the case 9, the base plates 3a to 3d, the transistor elements 1a to 1f, the diodes 2a to 2f, a part of the wiring members 5a to 5e, a part of the signal wirings 6a to 6f, and the upper surface of the insulating substrate integrated fin 8 are Covered with potting resin 10.

  FIG. 4 is an enlarged cross-sectional view of a part of FIG. As the insulating substrate integrated fin 8, an Al heat radiation fin 8a, an AlN layer 8b, an Al layer 8c, and an AlN layer 8d are sequentially laminated. The base plate 3a made of Al is provided on the AlN layer 8d, and is insulated from other base plates and the heat radiation fins 8a by the insulating AlN layer 8d. The thickness of the fin portion of the radiation fin 8a is 8 mm, the thickness of the flat plate portion of the radiation fin 8a is 0.9 mm, the thickness of the AlN layer 8b is 0.635 mm, the thickness of the Al layer 8c is 1.13 mm, and the thickness of the AlN layer 8d is The thickness of 0.635 mm and the base plate 3 a is 0.6 mm.

  A gate electrode 11a (control terminal) and an emitter electrode 11b are formed on the upper surface of the transistor element 1a, and a collector electrode 11c is formed on the lower surface. The gate electrode 11a, emitter electrode 11b, and collector electrode 11c are formed on a silicon substrate by plating and sputtering.

  The collector electrode 11c is joined to the base plate 3a by solder 4a. The emitter electrode 11b is joined to the wiring member 5a by solder 4c. The solders 4a and 4c are tin-lead solder, lead-free solder, etc., and may contain flux or may be fluxless solder. A wire 7 is bonded to the gate electrode 11a. Although the configuration of the transistor element 1a has been described here, the configuration of other transistor elements is the same.

  FIG. 5 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention. FIG. 6 is a flowchart of the semiconductor device manufacturing method according to the first embodiment of the present invention.

  First, the positioning jig 12 is placed on the base plate 3a (step S1). The positioning jig 12 is provided with an opening 13 penetrating from the upper surface to the lower surface. A protrusion 14 is provided on the inner side surface of the opening 13. The material of the positioning jig 12 and the protrusion 14 is carbon, aluminum, or the like. The cross section of the protrusion 14 is rectangular. In order to improve the wettability with the solder, a plating layer such as nickel may be formed on the solder joint portion of the base plate 3a. However, when the material of the base plate 3a is a substance having high wettability with solder, a plating layer is not necessary.

  Next, the solder 4a is placed on the base plate 3a in the opening 13 (step S2). The solder 4a is a plate solder. The transistor element 1a is placed on the solder 4a (step S3). In order to reduce the stress on the solder 4a due to the thinning of the transistor element 1a, the thickness of the solder 4a is set to 100 μm or more. However, the thicker the solder 4a, the more easily the solder 4a is scattered.

  Next, decompression reflow is performed in a state where the protrusions 14 are arranged on the side of the transistor element 1a, and the collector electrode 11c of the transistor element 1a is joined to the base plate 3a by the solder 4a (step S4). The temperature of the reduced pressure reflow is, for example, 260 ° C., and the atmospheric pressure is 50 Pa. The solder 4a scattered at the time of reflow bounces off the lower surface of the protrusion 14 or adheres to the lower surface of the protrusion 14 and stops, and does not reach the upper surface of the transistor element 1a. After reflow, the wire 7 is bonded to the gate electrode 11a. Thereafter, a general manufacturing process such as resin sealing is performed.

  As described above, in the present embodiment, the solder 14a scattered at the time of reflow is blocked by the protrusions 14 provided on the inner surface of the opening 13 of the positioning jig 12. Thereby, it is possible to prevent the solder 4a scattered during the reflow from adhering to the upper surface of the transistor element 1a. Therefore, since the wire 7 can be satisfactorily bonded to the gate electrode 11a after the reflow, productivity can be improved.

  Further, since the positioning jig 12 having the protrusions 14 only needs to be placed on the base plate 3a, a jig or manufacturing tool separate from the positioning jig 12 may be used to prevent the solder 4a from adhering to the upper surface of the transistor element 1a. There is no need to add a process. Therefore, there is no increase in manufacturing cost or manufacturing process delay.

  Here, when the lower surface of the protrusion 14 is higher than the upper surface of the transistor element 1a, the solder 4a bounced off the lower surface of the protrusion 14 adheres to the upper surface of the transistor element 1a. If the lower surface of the protrusion 14 is lower than the upper surface of the solder 4a, the solder 4a cannot be blocked by the protrusion 14. Furthermore, the space below the protrusion 14 that holds the scattered solder 4a is reduced. Therefore, the lower surface of the protrusion 14 is disposed at a height between the upper surface of the transistor element 1a and the upper surface of the solder 4a during reflow.

  Further, if the protrusion 14 and the transistor element 1a are too far apart, the solder 4a scattered during reflow cannot be blocked by the protrusion 14. Therefore, the distance d1 between the protrusion 14 and the side surface of the transistor element 1a is set to 0.25 mm or less. For example, the distance d1 is set to 0.1 mm to 0.25 mm. The protrusion 14 and the side surface of the transistor element 1a may partially contact each other.

  Although the method for mounting the transistor element 1a on the base plate 3a has been described, the method for mounting other transistor elements on the base plate is the same. In practice, the transistor elements 1a to 1f and the diodes 2a to 2f are simultaneously mounted on the base plates 3a to 3d using the positioning jig 12 having a plurality of openings.

Embodiment 2. FIG.
FIG. 7 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 8 is a top view showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention. A hole 15 is provided on the inner side surface of the opening 13 below the protrusion 14. The hole 15 is a through hole that penetrates the wall of the positioning jig 12. The scattered solder 4a is discharged to the outside of the positioning jig 12 through the hole 15. However, the hole 15 is not limited to the through hole, and may be provided up to the middle of the wall of the positioning jig 12. In any case, it is possible to more reliably prevent the solder 4a from adhering to the upper surface of the transistor element 1a by allowing the solder 4a scattered during the reflow to escape to the hole 15. When the hole 15 is a through hole, the hole 15 is not provided in the wall between two adjacent openings 13 of the positioning jig 12 as shown in FIG. Other configurations and effects are the same as those of the first embodiment.

Embodiment 3 FIG.
FIG. 9 is a cross-sectional view showing a method of manufacturing a semiconductor device according to the third embodiment of the present invention. The opening 13 has a first opening diameter w <b> 1 above the protrusion 14 and a second opening diameter w <b> 2 below the protrusion 14. By making the second opening diameter w2 larger than the first opening diameter w1, the space below the protrusion 14 is increased, and the scattered solder 4a is likely to stay on the base plate 3a. For this reason, it can prevent more reliably that the solder 4a adheres to the upper surface of the transistor element 1a. Other configurations and effects are the same as those of the first embodiment.

  If the first opening diameter w1 is too large, the positioning accuracy by the positioning jig 12 is lowered. On the other hand, if the first opening diameter w1 is too small, it is difficult to dispose the transistor element 1a in the opening 13. Further, as the second opening diameter w2 is larger, the space below the protrusion 14 is increased, but the wall of the positioning jig 12 is thinned and the strength is lowered. Considering these, the first and second opening diameters w1 and w2 are set within an appropriate range.

Embodiment 4 FIG.
FIG. 10 is a cross-sectional view showing a method of manufacturing a semiconductor device according to Embodiment 4 of the present invention. The protrusion 14 includes a first member 14 a joined to the inner side surface of the opening 13 and a second member 14 b disposed closer to the center of the opening 13 than the first member 14 a. The lower surface of the first member 14a is higher than the lower surface of the second member 14b. For this reason, the cross section of the protrusion 14 has a bowl shape, and a space 16 exists between the second member 14 b and the inner side surface of the opening 13. By disposing the lower surface of the second member 14b at the height between the upper surface of the transistor element 1a and the solder 4a at the time of reflow, the scattered solder 4a can be blocked. Note that the lower surface of the first member 14a may be higher than the upper surface of the transistor element 1a.

  Further, by letting the solder 4a scattered at the time of reflow escape to the space 16, it is possible to more reliably prevent the solder 4a from adhering to the upper surface of the transistor element 1a. Other configurations and effects are the same as those of the first embodiment. Note that the shape of the protrusion 14 of the present embodiment may be combined with the positioning jig 12 according to the second or third embodiment.

Embodiment 5 FIG.
FIG. 11 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the fifth embodiment of the present invention. The upper part of the protrusion 14 is tapered, and the opening diameter of the opening 13 increases as it goes upward. For this reason, it becomes easy to arrange the transistor element 1 a and the solder 4 a in the opening 13. Other configurations and effects are the same as those of the first embodiment. The tapered shape of the present embodiment may be combined with the positioning jig 12 according to the second to fourth embodiments.

Embodiment 6 FIG.
FIG. 12 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the sixth embodiment of the present invention. FIG. 13 is a flowchart of the semiconductor device manufacturing method according to the sixth embodiment of the present invention. Note that the overall configuration of the semiconductor device is the same as that of the first embodiment.

  First, the positioning jig 12 having the opening 13 is placed on the base plate 3a (step S11). Unlike the first embodiment, no protrusion 14 is provided on the inner surface of the opening 13 of the positioning jig 12, and the inner surface is a vertical plane.

  Next, the solder 4a is placed on the base plate 3a in the opening 13 (step S12). Next, the transistor element 1a is placed on the solder 4a in the opening 13 (step S13). The planar shape of the transistor element 1a is a quadrangle with sides of 10 mm to 15 mm.

  Next, the cover jig 17 is placed on the positioning jig 12 and the transistor element 1a (step S14). Here, the cover jig 17 has a protrusion 18 on the lower surface, and the protrusion 18 is disposed in the opening 13. The material of the cover jig 17 and the protrusion 18 is carbon, aluminum, or the like. The protrusion 18 has a thickness of 1 mm to 2 mm and a rectangular cross section.

  Next, reflow is performed with the lower surface of the protrusion 18 facing the upper surface of the transistor element 1a, and the collector electrode 11c of the transistor element 1a is joined to the base plate 3a by the solder 4a (step S15). The solder 4a scattered at the time of reflow rebounds on the side surface of the protrusion 18 or adheres to the side surface of the protrusion 18 and stops, and does not reach the upper surface of the transistor element 1a. After reflow, the wire 7 is bonded to the gate electrode 11a. Thereafter, a general manufacturing process such as resin sealing is performed.

  As described above, in the present embodiment, the protrusions 18 provided on the lower surface of the cover jig 17 prevent the solder 4a scattered during reflow. Thereby, it is possible to prevent the solder 4a scattered during the reflow from adhering to the upper surface of the transistor element 1a. Therefore, since the wire 7 can be satisfactorily bonded to the gate electrode 11a after the reflow, productivity can be improved.

  Further, at the time of reflow, the upper surface of the transistor element 1a (not the upper surface of the substrate of the transistor element 1a, but the upper surfaces of the gate electrode 11a and the emitter electrode 11b) and the protrusion 18 are separated. Thereby, it can prevent that the protrusion 18 contacts and the transistor element 1a is destroyed.

  Here, a method of covering only the upper surface of the transistor element 1a with the cover is also conceivable. However, in that case, the cover must be brought into contact with the upper surface of the transistor element 1a. On the other hand, in this embodiment, the cover jig 17 is supported by the positioning jig 12 so that the protrusion 18 provided on the lower surface of the cover jig 17 is held in a state of being separated from the upper surface of the transistor element 1a. be able to.

  However, if the protrusion 18 and the transistor element 1a are too far apart, the solder 4a scattered during reflow cannot be blocked by the protrusion 18. Therefore, the distance d2 between the protrusion 18 and the upper surface of the transistor element 1a is set to 0.25 mm or less. For example, the interval d2 is set to about 70 μm.

  If the planar size of the protrusion 18 is smaller than that of the transistor element 1a, it is impossible to prevent the solder 4a scattered during reflow from adhering to the upper surface of the transistor element 1a. On the other hand, when the planar size of the protrusion 18 is approximately the same as that of the opening 13, it is difficult to align the cover jig 17 in order to arrange the protrusion 18 in the opening 13. Therefore, it is preferable that the planar size of the protrusion 18 is approximately the same as that of the transistor element 1a.

  Further, the mounting method of the transistor element 1a on the base plate 3a has been described, but the mounting method of other transistor elements on the base plate is the same. In practice, the transistor elements 1a to 1f and the diodes 2a to 2f are simultaneously mounted on the base plates 3a to 3d using the positioning jig 12 having a plurality of openings.

Embodiment 7 FIG.
FIG. 14 is a cross-sectional view showing a method for manufacturing a semiconductor device according to Embodiment 7 of the present invention. A recess 19 is provided on the lower surface of the protrusion 18. Thereby, even when the transistor element 1a is warped upward, it is possible to prevent the transistor element 1a from being broken due to the contact of the protrusions 18. Other configurations and effects are the same as those of the sixth embodiment.

Embodiment 8 FIG.
FIG. 15 is a cross-sectional view showing a method for manufacturing a semiconductor device according to the eighth embodiment of the present invention. The protrusion 18 is provided only at a position facing the outer peripheral portion of the upper surface of the transistor element 1a. Even the protrusion 18 having such a configuration can prevent the solder 4a scattered during the flow from adhering to the upper surface of the transistor element 1a. Since there is no protrusion 18 at the center of the upper surface of the transistor element 1a, it is possible to prevent the transistor element 1a from being damaged due to the contact of the protrusion 18 even when the transistor element 1a warps upward. Further, since the gate electrode 11a and the like are not provided on the outer peripheral portion of the upper surface of the transistor element 1a, the protrusion 18 is difficult to contact the upper surface of the transistor element 1a. Other configurations and effects are the same as those of the sixth and seventh embodiments.

  The transistor elements 1a to 1f and the diodes 2a to 2f are not limited to those formed of silicon, but may be formed of a wide band gap semiconductor having a larger band gap than silicon. The wide band gap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. An element formed of such a wide bandgap semiconductor can be miniaturized because it has high withstand voltage and allowable current density. By using this miniaturized element, a semiconductor device incorporating this element can also be miniaturized. Further, since the heat resistance of the element is high, the radiating fins 8a of the insulating substrate integrated fins 8 can be reduced in size, and the water cooling part can be cooled in the air, so that the semiconductor device can be further reduced in size. In addition, since the power loss of the element is low and the efficiency is high, the semiconductor device can be highly efficient. Note that it is desirable that both the transistor elements 1a to 1f and the diodes 2a to 2f are formed of a wide band gap semiconductor. However, any one of the elements may be formed of a wide band gap semiconductor. The effect described in the form can be obtained.

1a to 1f transistor element (semiconductor element), 3a to 3d base plate, 4a and 4b solder, 7 wires, 11a gate electrode (upper surface electrode), 11c collector electrode (lower surface electrode), 12 positioning jig, 13 opening, 14, 18 projection, 14a first member, 14b second member, 15 holes, 16 spaces, 17 cover jig, 19 recess

Claims (13)

Placing a positioning jig on the base plate having an opening and a protrusion provided on the inner surface of the opening;
Placing solder on the base plate in the opening;
In the opening, placing a semiconductor element having an upper surface electrode and a lower surface electrode on the upper surface and the lower surface, respectively, on the solder;
Reflowing in a state where the protrusion is arranged on the side of the semiconductor element, joining the lower surface electrode of the semiconductor element to the base plate with the solder, and ceasing the solder scattered during the reflow with the protrusion. A method for manufacturing a semiconductor device, comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the lower surface of the protrusion is disposed at a height between the upper surface of the semiconductor element and the upper surface of the solder during the reflow.   3. The method of manufacturing a semiconductor device according to claim 1, wherein an interval between the protrusion and a side surface of the semiconductor element is set to 0.25 mm or less during the reflow.   The method for manufacturing a semiconductor device according to claim 1, wherein a hole is provided in the inner side surface of the opening below the protrusion.   The opening has a first opening diameter above the protrusion, a second opening diameter below the protrusion, and the second opening diameter is larger than the first opening diameter. The method for manufacturing a semiconductor device according to claim 1, wherein: The protrusion has a first member joined to the inner surface of the opening, and a second member disposed closer to the center of the opening than the first member,
The method for manufacturing a semiconductor device according to claim 1, wherein the lower surface of the first member has a height higher than that of the lower surface of the second member.   The method of manufacturing a semiconductor device according to claim 1, wherein an upper portion of the protrusion has a tapered shape. Placing a positioning jig having an opening on the base plate;
Placing the solder on the base plate in the opening;
In the opening, placing a semiconductor element having an upper surface electrode and a lower surface electrode on the upper surface and the lower surface, respectively, on the solder;
Covering the positioning jig and the semiconductor element with a cover jig having a protrusion on the lower surface, and disposing the protrusion in the opening;
Reflow is performed with the upper surface of the semiconductor element facing the lower surface of the protrusion, the lower surface electrode of the semiconductor element is bonded to the base plate with the solder, and the solder scattered during the reflow is applied to the protrusion. A method of manufacturing a semiconductor device, comprising the step of:   9. The method of manufacturing a semiconductor device according to claim 8, wherein the upper surface of the semiconductor element and the protrusion are separated from each other during the reflow.   The method for manufacturing a semiconductor device according to claim 9, wherein an interval between the protrusion and the upper surface of the semiconductor element is set to 0.25 mm or less during the reflow.   The method for manufacturing a semiconductor device according to claim 8, wherein a recess is provided on a lower surface of the protrusion.   The method of manufacturing a semiconductor device according to claim 8, wherein the protrusion is provided only at a position facing an outer peripheral portion of the upper surface of the semiconductor element.   The method for manufacturing a semiconductor device according to claim 1, further comprising a step of bonding a wire to the upper surface electrode after the reflow.

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