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JP2015123485A - Bonding method and power semiconductor device - Google Patents

Bonding method and power semiconductor device Download PDF

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Publication number
JP2015123485A
JP2015123485A JP2013271028A JP2013271028A JP2015123485A JP 2015123485 A JP2015123485 A JP 2015123485A JP 2013271028 A JP2013271028 A JP 2013271028A JP 2013271028 A JP2013271028 A JP 2013271028A JP 2015123485 A JP2015123485 A JP 2015123485A
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bonding
joining
metal
power semiconductor
mixed layer
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成人 太田
Naruto Ota
成人 太田
真之介 曽田
Shinnosuke Soda
真之介 曽田
吉典 横山
Yoshinori Yokoyama
吉典 横山
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Die Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a bonding method and a power semiconductor device capable of obtaining bonding which responds to high temperature and is excellent in heat conductivity.SOLUTION: A method of performing bonding by producing a metallic compound (CuSn) between bonding objects M1, M2 opposite to each other includes a process of forming a mixed layer of a first metal (Cu) and a second metal (Sn), a process of overlapping the bonding objects M1, M2 so as to put the mixing layer between the bonding objects and a process of heating the mixed layer to a temperature in the middle of a melting point of the first metal and a melting point of the second metal to produce the metallic compound (CuSn) between the bonding objects M1, M2. Therein, in the process of forming the mixed layer, the mixed layer is formed by deposition on the bonding surface of at least one side bonding object (M1).

Description

本発明は、金属間化合物を生成して接合対象間を接合する方法に関し、とくに電力用半導体装置の製造に適した接合方法に関する。   The present invention relates to a method for producing an intermetallic compound and joining objects to be joined, and particularly to a joining method suitable for manufacturing a power semiconductor device.

従来、電力用半導体装置をはじめとする電子機器等の接合を行うための方法として、はんだ接合が極めて有用であり多用されてきた。しかし、はんだに含まれる鉛(Pb)は人体に対して影響があることから、Pbを含まないPbフリーはんだの開発が行われてきた。電力用半導体装置の接合材としては、融点約183℃程度の低温系はんだと、融点約300℃程度の高温系はんだが工程に応じて使われている。また、電力用半導体装置のように発熱を伴う電子部品では、放熱フィンやヒートシンクと隙間を無くすように接合することで、発生した熱を効率よくヒートシンクに伝達するための放熱部材が使用されている。   Conventionally, solder bonding has been extremely useful and widely used as a method for bonding electronic devices such as power semiconductor devices. However, since lead (Pb) contained in solder has an influence on the human body, development of Pb-free solder not containing Pb has been performed. As a bonding material for a power semiconductor device, a low-temperature solder having a melting point of about 183 ° C. and a high-temperature solder having a melting point of about 300 ° C. are used depending on the process. Also, in electronic components that generate heat, such as power semiconductor devices, heat dissipation members are used to efficiently transmit generated heat to the heat sink by joining with heat dissipation fins and heat sinks so as to eliminate gaps. .

一方、近年の技術進歩に伴い、電力用半導体装置の出力向上・小型化のため、炭化ケイ素(SiC)のようなワイドバンドギャップ半導体と称される電力用半導体素子を採用することで、高電流密度化および高運転温度化の傾向にある。そのため、高温に耐える接合層・放熱層の形成が必要になっている。そこで、2種類の金属を反応させて金属間化合物を生成し、接合時の温度よりも耐熱温度が高くなる接合層を形成する技術が開発されている。具体的には、それぞれの種類の金属粒子を混合した金属箔を予め形成しておき、接合対象間に挿入して熱処理する方法(例えば、特許文献1参照。)や、一方の種類の金属層を接合対象のそれぞれの表面に形成し、他方の種類の金属層をその間に介在させた状態で熱処理する方法(例えば、特許文献2参照。)等が提案されている。   On the other hand, with the recent technological advancement, in order to improve the output and miniaturization of power semiconductor devices, by adopting power semiconductor elements called wide band gap semiconductors such as silicon carbide (SiC), high current There is a tendency of higher density and higher operating temperature. Therefore, it is necessary to form a bonding layer and a heat dissipation layer that can withstand high temperatures. Therefore, a technique has been developed in which two kinds of metals are reacted to form an intermetallic compound, and a bonding layer having a heat resistant temperature higher than the temperature at the time of bonding is formed. Specifically, a metal foil in which each type of metal particle is mixed is formed in advance, and is inserted between objects to be bonded and heat-treated (for example, see Patent Document 1), or one type of metal layer. Has been proposed (see, for example, Patent Document 2) and the like in which the other type of metal layer is interposed therebetween.

特開2002−301588号公報(段落0018〜0021、図1〜図2、段落0042、図3)JP 2002-301588 A (paragraphs 0018 to 0021, FIG. 1 to FIG. 2, paragraph 0042, FIG. 3) 特開2009−290007号公報(段落0018、図1、段落0025〜0027、図2〜図3)JP 2009-290007 A (paragraph 0018, FIG. 1, paragraphs 0025 to 0027, FIGS. 2 to 3)

しかしながら、接合対象間に挿入した金属箔を反応させて金属間化合物を生成する場合には、接合対象と金属間化合物との境界部分(接合界面)にボイドが残留することがあり、境界部分の伝熱経路が寸断されて伝熱性が損なわれる可能性があった。また、金属層間で反応させる場合は、厚み方向によって接合状態が変化するため、厚み方向における伝熱経路が阻害され、伝熱性が損なわれる可能性があった。そのため、発生した熱を効率よく放熱することが困難となり、高出力で信頼性の高い電力用半導体装置を得ることが困難であった。   However, when the intermetallic compound is produced by reacting the metal foil inserted between the objects to be joined, voids may remain at the boundary part (joining interface) between the object to be joined and the intermetallic compound. There is a possibility that the heat transfer path is broken and the heat transfer performance is impaired. Moreover, when making it react between metal layers, since a joining state changes with thickness directions, the heat-transfer path | route in the thickness direction may be obstructed and heat conductivity may be impaired. Therefore, it is difficult to efficiently dissipate the generated heat, and it is difficult to obtain a power semiconductor device with high output and high reliability.

この発明は、上記のような問題点を解決するためになされたものであり、高温に対応し、熱伝導性にすぐれた接合を得ることを目的とする。   The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a joint that can cope with a high temperature and has excellent thermal conductivity.

本発明にかかる接合方法は、相対向する接合対象の間に金属間化合物を生成して接合する方法であって、第一金属と第二金属との混合層を形成する工程と、前記混合層を間に挟むように、前記接合対象を重ねあわせる工程と、前記第一金属の融点と前記第二金属の融点の中間の温度に加熱し、前記接合対象の間に前記金属間化合物を生成する工程と、を含み、前記混合層を形成する工程では、少なくとも一方の接合対象の接合面上に、析出によって前記混合層を形成することを特徴とする。   The joining method according to the present invention is a method for producing an intermetallic compound between joining objects to be opposed to each other, forming a mixed layer of a first metal and a second metal, and the mixed layer. And the step of superimposing the joining objects so as to sandwich them, and heating to a temperature intermediate between the melting point of the first metal and the melting point of the second metal to produce the intermetallic compound between the joining objects. And the step of forming the mixed layer includes forming the mixed layer by precipitation on at least one of the bonding surfaces to be bonded.

この発明によれば、厚み方向での接合状態を変化させることなく、接合界面でのボイドを抑制し、発生した熱を効率よく放熱する接合が得られる。また、この接合方法を適用することにより、高出力で信頼性の高い電力用半導体装置を得ることができる。   According to the present invention, it is possible to obtain a joint that suppresses voids at the joint interface and efficiently radiates the generated heat without changing the joining state in the thickness direction. Further, by applying this bonding method, a power semiconductor device with high output and high reliability can be obtained.

本発明の実施の形態1にかかる接合方法を説明するための、工程ごとの接合部分の断面模式図である。It is a cross-sectional schematic diagram of the junction part for every process for demonstrating the joining method concerning Embodiment 1 of this invention. 本発明の実施の形態1にかかる電力用半導体装置の構成を説明するための断面模式図である。It is a cross-sectional schematic diagram for demonstrating the structure of the power semiconductor device concerning Embodiment 1 of this invention. 本発明の実施の形態1の変形例にかかる接合方法におけるある工程での接合部分の断面模式図である。It is a cross-sectional schematic diagram of the junction part in a process in the joining method concerning the modification of Embodiment 1 of this invention. 本発明の実施の形態2にかかる接合方法による接合部分の断面模式図である。It is a cross-sectional schematic diagram of the junction part by the joining method concerning Embodiment 2 of this invention. 本発明の実施の形態3にかかる接合方法を説明するための、工程ごとの接合部分の断面模式図である。It is a cross-sectional schematic diagram of the junction part for every process for demonstrating the joining method concerning Embodiment 3 of this invention. 本発明の実施の形態4にかかる接合方法による接合部分の断面模式図である。It is a cross-sectional schematic diagram of the junction part by the joining method concerning Embodiment 4 of this invention. 本発明の実施の形態5にかかる接合方法を説明するための、工程ごとの接合部分の断面模式図である。It is a cross-sectional schematic diagram of the junction part for every process for demonstrating the joining method concerning Embodiment 5 of this invention.

以下に、本発明の各実施の形態にかかる接合方法およびこの接合方法(電力用半導体装置の製造方法)を用いて製造した電力用半導体装置について詳細に説明する。なお、本発明は、以下の記述に限定されるものではなく、本発明の要旨を逸脱しない範囲において適宜変更可能である。また、以下に示す図面においては、模式的な記載となっているため、各部材の縮尺が実際とは異なる場合がある。   Below, the joining method concerning each embodiment of the present invention and the power semiconductor device manufactured using this joining method (manufacturing method of a power semiconductor device) are explained in detail. In addition, this invention is not limited to the following description, In the range which does not deviate from the summary of this invention, it can change suitably. Moreover, in the drawings shown below, since it is a schematic description, the scale of each member may differ from the actual scale.

実施の形態1.
図1〜図3は、本発明の実施の形態1にかかる接合方法、およびその接合方法を用いて製造した電力用半導体装置について説明するための図である。図1は金属間化合物を用いて相対向する接合対象を接合する方法を説明するためのもので、図1(a)〜(e)は各工程における接合部分の状態を示す模式断面図である。そして、図2は本実施の形態1にかかる接合方法を用いて製造した電力用半導体装置の構成を示す断面模式図である。また、図3は変形例にかかる接合方法における、ある工程での接合部分の断面模式図で、図1(d)の工程に対応する。
Embodiment 1 FIG.
1 to 3 are diagrams for explaining a bonding method according to a first embodiment of the present invention and a power semiconductor device manufactured by using the bonding method. FIG. 1 is a view for explaining a method of joining opposing objects to be joined using an intermetallic compound, and FIGS. 1A to 1E are schematic cross-sectional views showing states of joined portions in respective steps. . FIG. 2 is a schematic cross-sectional view showing the configuration of the power semiconductor device manufactured by using the bonding method according to the first embodiment. FIG. 3 is a schematic cross-sectional view of a joining portion at a certain step in the joining method according to the modification, and corresponds to the step of FIG.

本発明の特徴である接合方法の説明に先立ち、はじめに電力用半導体装置の構成について図2を用いて説明する。
本実施の形態あるいは後述する各実施の形態にかかる接合方法(電力用半導体装置の製造方法)を用いて製造した電力用半導体装置10は、図2に示すように、例えば、熱伝導性に優れたセラミック基材4iの両面に銅箔層やアルミ箔層などの導体層4f、4rが形成された絶縁基板4と、絶縁基板4の一方の面(図中下側:放熱面)に、金属間化合物化による接合部3−3を介して接合されたアルミニウム(Al)もしくは銅(Cu)などの高熱伝導性の材料を主体に構成したヒートシンク5と、絶縁基板4の他方の面(図中上側:回路面)に、接合部3−2を介して、裏面電極1rが接合された電力用半導体素子1と、接合部3−1を介して、電力用半導体素子1の主面の電極1eに一端が接合されたリード端子2とを備えている。また、導体層4fには図示しないリード端子が接合されており、電力用半導体素子1と外部回路との電気接続が可能となっている。そして、電力用半導体素子1を包むように、回路面側が封止体6によって封止され、パッケージ化されている。
Prior to the description of the bonding method, which is a feature of the present invention, the configuration of the power semiconductor device will be described with reference to FIG.
The power semiconductor device 10 manufactured using the bonding method (power semiconductor device manufacturing method) according to the present embodiment or each embodiment described later has, for example, excellent thermal conductivity as shown in FIG. Insulating substrate 4 in which conductor layers 4f and 4r such as a copper foil layer and an aluminum foil layer are formed on both surfaces of ceramic substrate 4i, and metal on one surface (lower side in the figure: heat dissipation surface) of insulating substrate 4 A heat sink 5 mainly composed of a material having high thermal conductivity such as aluminum (Al) or copper (Cu) joined through a joint 3-3 by intermetallic compound, and the other surface of the insulating substrate 4 (in the drawing) The power semiconductor element 1 having the back electrode 1r joined to the upper side (circuit surface) via the junction 3-2 and the electrode 1e on the main surface of the power semiconductor element 1 via the junction 3-1. And a lead terminal 2 having one end joined thereto. In addition, a lead terminal (not shown) is joined to the conductor layer 4f, and electrical connection between the power semiconductor element 1 and an external circuit is possible. The circuit surface side is sealed with a sealing body 6 so as to enclose the power semiconductor element 1 and packaged.

電力用半導体素子1としては、シリコンや炭化珪素を主材料として構成するのが通常である。一般的に、ワイドバンドギャップ半導体材料と呼ばれる炭化珪素(SiC)のような半導体材料は、シリコン(Si)よりもバンドギャップが広く、ワイドバンドギャップ半導体材料を用いた電力用半導体素子1は、高効率(大電流)で300℃程度までの高い温度範囲で使用可能とされている。そのため、SiCチップを用いた場合、Siチップよりも耐熱性および高放熱性が要求される。   The power semiconductor element 1 is usually composed of silicon or silicon carbide as a main material. In general, a semiconductor material such as silicon carbide (SiC) called a wide band gap semiconductor material has a wider band gap than silicon (Si), and a power semiconductor device 1 using a wide band gap semiconductor material has a high band gap. It can be used in a high temperature range up to about 300 ° C. with high efficiency (large current). Therefore, when a SiC chip is used, heat resistance and high heat dissipation are required rather than a Si chip.

つぎに、上述した電力用半導体装置10の製造方法である各接合部3−1〜3−3(まとめて接合部3)を形成する接合方法について図1を用いて説明する。
なお、各接合部3における接合対象を接合対象M1と接合対象M2と称して説明する。はじめに、図1(a)に示すように、一方の接合対象M1を図示しないスパッタ装置内に設置する。そして、図1(b)に示すように、スパッタによって、接合対象M1の接合面上に、スズ(Sn)の基材3Rb中に銅(Cu)の粒子3Rpが混合された接合材層3Rを形成していく。接合面上に図1(c)に示すように、必要な厚みの接合材層3Rが形成されると、スパッタ装置から取り出して図示しない接合装置に設置し、図1(d)に示すように、間に接合材層3Rを挟むように、他方の接合対象M2を重ねる。
Next, a bonding method for forming each of the bonding parts 3-1 to 3-3 (collectively the bonding part 3), which is a method for manufacturing the power semiconductor device 10 described above, will be described with reference to FIG.
In addition, the joining object in each joining part 3 is called and referred to as the joining object M1 and the joining object M2. First, as shown in FIG. 1A, one joining object M1 is installed in a sputtering apparatus (not shown). And as shown in FIG.1 (b), the joining material layer 3R by which the particle | grains 3Rp of copper (Cu) were mixed in the base material 3Rb of tin (Sn) on the joining surface of the joining object M1 by sputtering. To form. When a bonding material layer 3R having a required thickness is formed on the bonding surface as shown in FIG. 1C, the bonding material layer 3R is taken out from the sputtering apparatus and installed in a bonding apparatus (not shown), as shown in FIG. The other joining object M2 is overlapped so as to sandwich the joining material layer 3R therebetween.

そして、Snの融点である232℃以上(Cuの融点以下、さらには電力用半導体素子1等の耐熱温度以下)で熱し続けると、融解したSnがCu粒子3Rp内に拡散(浸食)し、Cu粒子3Rpの表面層から化合物化(合金化)していく、そして、金属間化合物の層の厚みが厚くなる過程でCu粒子3Rpは内部に向けて侵食されていく。このように金属間化合物層が成長していくと、Snが枯渇していきSn中のCu濃度も高まり、金属間化合物層同士が接触した状態で凝固点上昇する。いわば凝固点上昇による液層拡散接合が達成される。接合材層3Rは、CuとSnがモル比で3:1になるように形成されており、金属間化合物(CuSn)を主体とする接合部3が図1(e)に示すように形成される。なお、図1(e)では、理解を助けるため、便宜上Cu粒子3Rpがあった部分を点線で表示しているが、最終的な接合部3中では、Cu粒子3Rpであった部分と基材3Rbであった部分は同じ組成で一体となっている。 And if it continues heating at 232 degreeC or more which is melting | fusing point of Sn (below melting | fusing point of Cu, and also below heat-resistant temperature of the power semiconductor element 1 etc.), the fuse | melted Sn will spread | diffuse in the Cu particle 3Rp (erosion), The Cu particles 3Rp are eroded inward in the process of compounding (alloying) from the surface layer of the particles 3Rp and increasing the thickness of the intermetallic compound layer. As the intermetallic compound layer grows in this way, Sn is depleted and the Cu concentration in Sn increases, and the freezing point rises while the intermetallic compound layers are in contact with each other. In other words, liquid layer diffusion bonding is achieved by raising the freezing point. The bonding material layer 3R is formed so that the molar ratio of Cu and Sn is 3: 1. As shown in FIG. 1E, the bonding portion 3 mainly composed of an intermetallic compound (Cu 3 Sn) is formed. It is formed. In FIG. 1 (e), for the purpose of facilitating understanding, the portion where the Cu particles 3Rp are present is indicated by a dotted line for the sake of convenience. The part which was 3Rb is united with the same composition.

その際、接合対象M1と接合対象M2は、接合温度(上記の例ではSnの融点)よりも凝固点が高くなった金属間化合物(CuSn)で構成された接合部3で強固に接合される。なお、接合材層3Rは、スパッタによって接合対象M1に直接析出させて形成されたものであるので、接合対象M1と接合部3との界面ではボイドがほとんど発生せず、一体物のように伝熱性が良い。そのため、接合対象M1から接合部3にかけての温度勾配は滑らかになり、極端な応力がかかることもなく、高い接合強度を維持することも可能となる。 At that time, the joining object M1 and the joining object M2 are firmly joined at the joining part 3 composed of an intermetallic compound (Cu 3 Sn) whose freezing point is higher than the joining temperature (the melting point of Sn in the above example). The Since the bonding material layer 3R is formed by being directly deposited on the bonding target M1 by sputtering, almost no voids are generated at the interface between the bonding target M1 and the bonding portion 3, and the bonding material layer 3R is transmitted like an integrated object. Good thermal properties. Therefore, the temperature gradient from the joining object M1 to the joining part 3 becomes smooth, and it becomes possible to maintain high joining strength without applying extreme stress.

なお、接合対象M2と接合部3との間については、特許文献1と同様のボイドが発生する可能性があるが、熱源に近い側、あるいは接合面積の狭い側に接合材層3Rを形成することで、影響を抑制することができる。例えば、図2に示す電力用半導体装置10において、接合部3−1および3−2であれば、電力用半導体素子1側(電極1e上および電極1r上)に接合材層3Rを形成し、接合部3−3であれば、絶縁基板4側(導電層4r上)に接合材層3Rを形成することが望ましい。あるいは、例えば、図3に示すように、接合対象M1と同様に、接合対象M2にも接合材層3Rを形成しておけば、界面でのボイドの発生を抑制し、いずれの界面においても良好な伝熱性能を発揮することができる。ここで、例えば、ある接合対象Miに対して接合対象が複数(両面に)ある場合は、それぞれの面に接合材層3Rを形成することで、同様の効果を得ることができる。なお、本実施の形態1および以降の実施の形態においては、接合部3のすべてに上述した接合方法を用いたように記載しているが、一部の接合部に用いてもよいことは言うまでもない。   Note that a void similar to that in Patent Document 1 may occur between the bonding object M2 and the bonding portion 3, but the bonding material layer 3R is formed on the side close to the heat source or on the side having a small bonding area. Thus, the influence can be suppressed. For example, in the power semiconductor device 10 illustrated in FIG. 2, the bonding material layer 3 </ b> R is formed on the power semiconductor element 1 side (on the electrode 1 e and the electrode 1 r) if the bonding portions 3-1 and 3-2 are performed. In the case of the bonding portion 3-3, it is desirable to form the bonding material layer 3R on the insulating substrate 4 side (on the conductive layer 4r). Alternatively, for example, as shown in FIG. 3, if the bonding material layer 3R is formed on the bonding target M2 as well as the bonding target M1, the generation of voids at the interface is suppressed, and good at any interface. Heat transfer performance can be demonstrated. Here, for example, when there are a plurality of bonding targets (on both surfaces) for a certain bonding target Mi, the same effect can be obtained by forming the bonding material layer 3R on each surface. In the first embodiment and the following embodiments, it is described that the joining method described above is used for all of the joint portions 3, but it goes without saying that it may be used for some of the joint portions. Yes.

なお、接合材層3Rを構成する基材3Rbと粒子3Rpについては、金属間化合物を生成するとともに、生成した金属間化合物の融点が、一方の金属の融点よりも高くなる金属種の組合せから選択すればよい。生成した金属間化合物の融点より低い融点を有する金属種としては、本実施の形態で示したSnの他、インジウム(In)等が使用できる。他方の金属種としては、本実施の形態で示したCuの他、銀(Ag)、金(Au)、ニッケル(Ni)、コバルト(Co)等の金属が使用できる。   For the base material 3Rb and the particles 3Rp constituting the bonding material layer 3R, an intermetallic compound is generated, and the selected intermetallic compound has a melting point higher than the melting point of one metal. do it. In addition to Sn shown in this embodiment, indium (In) or the like can be used as a metal species having a melting point lower than the melting point of the generated intermetallic compound. As the other metal species, metals such as silver (Ag), gold (Au), nickel (Ni), and cobalt (Co) can be used in addition to Cu shown in the present embodiment.

そして、基材3Rbには、組合せのうち、融点の低い方の金属種を用いることが好ましく、上記例ではSnあるいはInになるが、必ずしも単種類の金属に限ることはなく、粒子3Rpと金属間化合物化可能な合金であってもよい。そして、基材3Rbの融点以上で粒子3Rpの融点以下の温度で熱処理することで、金属間化合物による接合部3が形成できる。また、粒子3Rpの形状は球形や円柱形が望ましい。   And it is preferable to use the metal species having the lower melting point in the combination for the base material 3Rb. In the above example, it is Sn or In, but it is not necessarily limited to a single kind of metal, and the particle 3Rp and the metal It may be an alloy capable of forming an intermetallic compound. And the junction part 3 by an intermetallic compound can be formed by heat-processing at the temperature more than melting | fusing point of base material 3Rb and below melting | fusing point of particle | grain 3Rp. The shape of the particle 3Rp is preferably a spherical shape or a cylindrical shape.

接合対象M1、M2としては、上記金属間化合物と接合できる材料であればよく、とくに、基材3Rbとの間で金属間化合物を生成するCu、Ag、Au、Ni、Coが望ましい。一方、アルミニウム(Al)のように、Snと金属間化合物化あるいは接合しない材料に対しては、接合可能な材料で表面を覆うようにすればよい。例えば、接合対象M1あるいはM2がAl製のヒートシンク5やリード端子2の場合には、Niストライク等の被膜を表面に形成すればよい。また、接合対象M1あるいはM2が、電力用半導体素子1のAl製の電極1rや1eの場合、電極表面にAu被膜を設けるなどすればよい。   The bonding targets M1 and M2 may be any material that can be bonded to the intermetallic compound, and Cu, Ag, Au, Ni, and Co that generate an intermetallic compound with the base material 3Rb are particularly desirable. On the other hand, for materials such as aluminum (Al) that are not intermetallic compounded with Sn or bonded, the surface may be covered with a bondable material. For example, when the joining object M1 or M2 is the heat sink 5 or the lead terminal 2 made of Al, a coating such as Ni strike may be formed on the surface. Further, when the bonding target M1 or M2 is the Al electrode 1r or 1e of the power semiconductor element 1, an Au coating may be provided on the electrode surface.

なお、基材3Rb中に粒子3Rpが混入する接合材層3Rの形成方法の例としてスパッタを例に示したが、これに限ることなく、蒸着やメッキ等、接合面上に析出させることで形成する方法であれば、接合界面でのボイド発生を抑制することが可能となる。また、基材3Rb中に粒子3Rpが混入する接合材層3Rを用いたので、例えば、2種の金属を層状に形成する場合と比較して、短時間で金属間化合物化が可能となり、高強度の接合部3を簡単に形成することが可能となる。   In addition, although sputter | spatter was shown as an example of the formation method of the joining material layer 3R in which particle | grain 3Rp mixes in base material 3Rb, it does not restrict to this, It forms by depositing on a joining surface, such as vapor deposition and plating. If it is the method to do, it becomes possible to suppress generation | occurrence | production of the void in a joining interface. Moreover, since the bonding material layer 3R in which the particles 3Rp are mixed in the base material 3Rb is used, for example, compared to the case where two kinds of metals are formed in layers, an intermetallic compound can be formed in a short time. It is possible to easily form the strong joint 3.

つまり、上述した接合方法によって、図2で示した電力用半導体装置10における各接合部3が形成されているので、高温運転に適用できるとともに、伝熱性に優れ、信頼性の高い電力用半導体装置10を得ることができる。   That is, since each junction part 3 in the power semiconductor device 10 shown in FIG. 2 is formed by the joining method described above, the power semiconductor device can be applied to a high temperature operation and has excellent heat conductivity and high reliability. 10 can be obtained.

以上のように、本実施の形態1にかかる接合方法によれば、相対向する接合対象M1、M2の間に金属間化合物(例えば、CuSn)を生成して接合する方法であって、(金属間化合物を生成するための)第一金属(例えば、Cu)と第二金属(Sn)との混合層(接合材層3R)を形成する工程と、混合層(接合材層3R)を間に挟むように、接合対象M1とM2を重ねあわせる工程と、第一金属の融点(1084℃)と第二金属の融点(232℃)の中間(232℃に近い方)の温度に加熱し、接合対象M1、M2の間に金属間化合物(CuSn)を生成する工程と、を含み、混合層(接合材層3R)を形成する工程では、少なくとも一方の接合対象(M1)の接合面上に、(スパッタやメッキなどの)析出によって混合層(接合材層3R)を形成するように構成したので、接合界面でのボイド発生を抑制し、高温に対応し、熱伝導性にすぐれた接合を得ることができる。また、接合界面でのボイドが少ないため、界面付近での温度勾配が周囲と一様になり、応力の集中を回避して接合信頼性も高まる。 As described above, according to the bonding method according to the first embodiment, an intermetallic compound (for example, Cu 3 Sn) is generated and bonded between the bonding objects M1 and M2 facing each other. Forming a mixed layer (bonding material layer 3R) of a first metal (for example, Cu) and a second metal (Sn) (for generating an intermetallic compound), and a mixed layer (bonding material layer 3R) The process of superimposing the joining objects M1 and M2 so as to be sandwiched between them, and heating to the intermediate temperature (closer to 232 ° C) between the melting point of the first metal (1084 ° C) and the melting point of the second metal (232 ° C) A step of forming an intermetallic compound (Cu 3 Sn) between the bonding targets M1 and M2, and forming a mixed layer (bonding material layer 3R), wherein at least one of the bonding targets (M1) is bonded On the surface, a mixed layer (bonding) by precipitation (such as sputtering or plating) Since the material layer 3R) is formed, it is possible to suppress the generation of voids at the bonding interface, to cope with a high temperature, and to obtain a bond with excellent thermal conductivity. Further, since there are few voids at the bonding interface, the temperature gradient near the interface becomes uniform with the surroundings, and stress concentration is avoided and bonding reliability is improved.

第一金属は、Cu、Ag、Au、Ni、およびCoのうちのいずれかであり、第二金属は、SnまたはInにすれば、電力用半導体装置10の部材に影響を与える温度以下で接合ができ、かつ高温に対応し、熱伝導性にすぐれた接合を得ることができる。   The first metal is any one of Cu, Ag, Au, Ni, and Co. If the second metal is Sn or In, the first metal is bonded at a temperature lower than the temperature that affects the members of the power semiconductor device 10. In addition, it is possible to obtain a joint that is compatible with high temperatures and excellent in thermal conductivity.

混合層(接合材層3R)は、第一金属(Cuおよび上述した金属種)より融点の低い第二金属(SnおよびIn)の基材3Rb中に、第一金属の粒子3Rpが混入したものであるので、接合時間が短縮でき、また、良好な接合部3が形成される。   The mixed layer (bonding material layer 3R) is obtained by mixing particles 3Rp of the first metal in the base material 3Rb of the second metal (Sn and In) having a melting point lower than that of the first metal (Cu and the above-described metal species). Therefore, the bonding time can be shortened, and a good bonding portion 3 is formed.

また、混合層(接合材層3R)が、他方の接合対象M2の接合面にも析出によって形成されているようにすれば、両接合界面でのボイド発生を抑制し、より伝熱性に優れた接合が得られる。そのため接合信頼性も向上する。   In addition, if the mixed layer (bonding material layer 3R) is formed on the bonding surface of the other bonding target M2 by precipitation, the generation of voids at both bonding interfaces is suppressed, and the heat transfer is more excellent. Bonding is obtained. Therefore, the joining reliability is also improved.

実施の形態2.
本実施の形態2にかかる接合方法では、実施の形態1に対して基材と粒子の含有比率を粒子が多くなるように変更したものである。図4は、本実施の形態2にかかる接合方法によって形成された接合部の構成を示すもので、実施の形態1における図1(e)に対応するものである。図中、実施の形態1と同様の部分については同様の符号を付し、詳細な説明は省略する。また、実施の形態1における図1(e)以外の部分については、実施の形態2においても流用する。
Embodiment 2. FIG.
In the joining method according to the second embodiment, the content ratio of the base material and the particles is changed with respect to the first embodiment so that the number of particles increases. FIG. 4 shows the structure of the joint formed by the joining method according to the second embodiment, and corresponds to FIG. 1 (e) in the first embodiment. In the figure, the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the portions other than FIG. 1E in the first embodiment are also used in the second embodiment.

本実施の形態2においては、接合材層3R中における基材3Rbを構成するSnと粒子3Rpを構成するCuの構成比率が、実施の形態1と比較してCuのモル比が1:3よりも高くなるようにしたものである。つまり金属間化合物(CuSn)を形成する量論比よりも粒子3Rpを構成するCuの比率を高くしたものである。これにより、接合後の接合部3には、図4に示すように、金属間化合物部分の中に、粒子3Rpから金属間化合物化されずに、Cuの単金属部分が残った核3cが含まれることになる。その他の構成および工程、あるいは変形例等の適用については、実施の形態1と同様である。 In the second embodiment, the constituent ratio of Sn constituting the base material 3Rb and Cu constituting the particles 3Rp in the bonding material layer 3R is higher than the molar ratio of Cu from 1: 3 as compared with the first embodiment. It is intended to be higher. That is, the ratio of Cu constituting the particles 3Rp is set higher than the stoichiometric ratio for forming the intermetallic compound (Cu 3 Sn). As a result, as shown in FIG. 4, the bonded portion 3 after bonding includes a nucleus 3c in which the single metal portion of Cu is left in the intermetallic compound portion without being converted into an intermetallic compound from the particles 3Rp. Will be. Other configurations and processes, or application of modification examples are the same as those in the first embodiment.

このように、接合材層3R中の金属の配合比を組成比よりもCu(粒子3Rp)の比率が大きくなるように調整することにより、金属間化合物相の中に、単金属の核3cが残る接合部3を形成することが出来る。この構成を用いることにより、導電性の高いCuの核3cが伝熱パスとなり、放熱性能を向上させることができる。さらに、接合部3内に残留する核3cの線膨張係数(銅の場合:約16.6ppm/K)が金属間化合物相の線膨張
係数(CuSnの場合:約18.0ppm/K)と異なるため、応力緩和に対する効果がある。
Thus, by adjusting the compounding ratio of the metal in the bonding material layer 3R so that the ratio of Cu (particle 3Rp) is larger than the composition ratio, the single metal nucleus 3c is included in the intermetallic compound phase. The remaining joint 3 can be formed. By using this configuration, the highly conductive Cu core 3c becomes a heat transfer path, and heat dissipation performance can be improved. Further, the linear expansion coefficient of the core 3c remaining in the joint 3 (in the case of copper: about 16.6 ppm / K) is the linear expansion coefficient of the intermetallic compound phase (in the case of Cu 3 Sn: about 18.0 ppm / K). Therefore, there is an effect on stress relaxation.

なお、本実施の形態2においては、SnとCuの金属間化合物に対して粒子側の比率を想定される金属間化合物を形成するための量論比よりも高くなる形態について説明したが、他の金属種の組合せについても適用できることは言うまでもない。また、本実施の形態2を含め、以降の各実施の形態にかかる接合方法は、実施の形態1における電力用半導体装置10の各接合部3のどれに適用してもよく、さらには異なる接合方法を組み合わせてもよい。   In the second embodiment, a mode has been described in which the ratio becomes higher than the stoichiometric ratio for forming an intermetallic compound that is assumed to have a particle-side ratio with respect to the intermetallic compound of Sn and Cu. Needless to say, the present invention can also be applied to combinations of these metal species. In addition, the bonding method according to each of the following embodiments including the second embodiment may be applied to any of the respective bonding portions 3 of the power semiconductor device 10 according to the first embodiment, and further different bonding. You may combine methods.

以上のように、本実施の形態2にかかる接合方法によれば、混合層(接合材層3R)での第一金属(Cu)の第二金属(Sn)に対する割合が、金属間化合物(CuSn)を生成するための量論比(モル比で3:1)よりも大きくなるようにしているので、導電性の高いCuの核3cが伝熱パスとなり、放熱性能を向上させることができる。さらに、応力緩和に対する効果がある。 As described above, according to the bonding method according to the second embodiment, the ratio of the first metal (Cu) to the second metal (Sn) in the mixed layer (bonding material layer 3R) is such that the intermetallic compound (Cu 3 Sn) stoichiometric ratio for generating (in a molar ratio of 3: since to be larger than 1), nuclear 3c of high conductivity Cu becomes heat transfer path, it is possible to improve the heat dissipation performance it can. Furthermore, there is an effect on stress relaxation.

実施の形態3
本実施の形態3にかかる接合方法では、実施の形態1に対して接合材層中に含有する粒子のなかに、厚み調整に用いる粒径を有するものを使用したものである。図5は、本実施の形態3にかかる接合方法における工程ごとの接合部の構成を示すもので、図5(a)と(b)はそれぞれ、実施の形態1における図1(d)と(e)に対応するものである。図中、実施の形態1と同様の部分については同様の符号を付し、詳細な説明は省略する。また、実施の形態1における図1(d)、(e)以外の部分については、実施の形態3においても流用する。
Embodiment 3
In the bonding method according to the third embodiment, among the particles contained in the bonding material layer as compared with the first embodiment, a particle having a particle size used for thickness adjustment is used. FIG. 5 shows the structure of the joining part for each step in the joining method according to the third embodiment. FIGS. 5 (a) and 5 (b) are the same as FIGS. This corresponds to e). In the figure, the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, portions other than those in FIGS. 1D and 1E in the first embodiment are also used in the third embodiment.

本実施の形態3にかかる接合方法では、図5に示すように、接合材層3R中に、接合部3の厚さt3を規定するために、粒子3Rpの中に、厚さt3に対応する粒径を有する粒子3Rpsを用いた。その他の構成については、実施の形態1と同様である。これにより、基材3Rbを融解させる工程において、面内に分散した粒子3Rpsが支えることによってスペーサSpとして機能し、接合対象M1とM2との間隔は、接合圧力を高くしても、その粒径分に保たれる。つまり、接合強度を高めるために接合圧力を高くしても接合部3の厚みが保たれるので、任意の接合強度を得ることが可能となり、積載スペースに合致した高さに形成することができる。   In the joining method according to the third embodiment, as shown in FIG. 5, in order to define the thickness t3 of the joint 3 in the joining material layer 3R, the particle 3Rp corresponds to the thickness t3. Particles having a particle size of 3 Rps were used. Other configurations are the same as those in the first embodiment. Thus, in the step of melting the base material 3Rb, the particles 3Rps dispersed in the surface support the spacer Sp, and the interval between the joining objects M1 and M2 is the particle size even when the joining pressure is increased. Kept in minutes. That is, even if the bonding pressure is increased in order to increase the bonding strength, the thickness of the bonding portion 3 is maintained, so that an arbitrary bonding strength can be obtained and the height can be formed to match the loading space. .

例えば、チップ下接合層(接合部3−2)として用いる場合は、電力用半導体素子1で発熱した熱を早く拡散させるために、粒子3Rpsのサイズを他の接合部よりも小さくして、接合部3−2の厚みを薄くなるように形成するといった対応が可能となる。また、基板下接合層(接合部3−3)として用いる場合は、絶縁基板4の下に形成されているヒートシンク5等を有効に活用するために、粒子3Rpsのサイズを他の接合部よりも大きくして、接合部3−3の厚みを他の接合部よりも厚くし、外部へ放出する熱をヒートシンク5に合わせて拡げて拡散させることが可能となる。   For example, when used as an under-chip bonding layer (bonding portion 3-2), in order to quickly diffuse the heat generated in the power semiconductor element 1, the size of the particles 3Rps is made smaller than that of other bonding portions, and bonding is performed. It is possible to cope with the formation such that the thickness of the portion 3-2 is reduced. Moreover, when using as a board | substrate lower joining layer (joining part 3-3), in order to utilize effectively the heat sink 5 etc. which are formed under the insulated substrate 4, the size of particle | grain 3Rps is set rather than another joining part. By increasing the thickness, the thickness of the joint portion 3-3 is made thicker than other joint portions, and the heat released to the outside can be spread and diffused according to the heat sink 5.

このように、接合部3の適用箇所に合わせて、粒子3Rpsのサイズを選択することで、目的にあった接合部3を形成することが可能となる。なお、粒子3Rpsは、接合面内に適宜分散する程度配合されていれば、厚さt3を規定できる。そのため、例えば、基材3Rbとの配合比率を調整するためには、3Rpsよりも小さな粒径の粒子3Rpを混入してもよい。   As described above, the size of the particle 3 Rps is selected in accordance with the application portion of the bonding portion 3, whereby the bonding portion 3 that meets the purpose can be formed. In addition, if the particles 3Rps are blended to such an extent that they are appropriately dispersed in the joint surface, the thickness t3 can be defined. Therefore, for example, in order to adjust the blending ratio with the base material 3Rb, particles 3Rp having a particle diameter smaller than 3Rps may be mixed.

以上のように、本実施の形態3にかかる接合方法によれば、混合層(接合材層3R)は、第一金属の粒子3Rpのうち、最大径となるあらかじめ定めた径を有する複数の粒子3Rpsが、接合面内に分散しているので、接合部3の厚みを容易に規定することができる。そのため、接合圧力を上げて、接合強度を高めることもできる。   As described above, according to the bonding method according to the third embodiment, the mixed layer (bonding material layer 3R) has a plurality of particles having a predetermined diameter that is the maximum diameter among the first metal particles 3Rp. Since 3 Rps is dispersed in the joint surface, the thickness of the joint portion 3 can be easily defined. Therefore, the bonding pressure can be increased by increasing the bonding pressure.

実施の形態4.
本実施の形態4にかかる接合方法では、実施の形態3に対して基材と粒子の含有比率を粒子が多くなるように変更したものである。図6は、本実施の形態4にかかる接合方法によって形成された接合部の構成を示すもので、実施の形態3における図5(b)に対応するものである。図中、実施の形態3と同様の部分については同様の符号を付し、詳細な説明は省略する。また、実施の形態1における図1(e)以外の部分、および実施の形態3における図5(a)については、本実施の形態4においても流用する。
Embodiment 4 FIG.
In the bonding method according to the fourth embodiment, the content ratio of the base material and the particles is changed so as to increase the number of particles as compared with the third embodiment. FIG. 6 shows the structure of the joint formed by the joining method according to the fourth embodiment, and corresponds to FIG. 5B in the third embodiment. In the figure, the same parts as those in the third embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, the portions other than FIG. 1E in the first embodiment and FIG. 5A in the third embodiment are also used in the fourth embodiment.

本実施の形態4においては、厚み3tを規定するための粒子3Rpsを用いるとともに、接合材層3R中におけるSnとCuの構成比率が、CuSnを形成する量論比よりも高くなるようにしたものである。これにより、接合後の接合部3には、図6に示すように、CuSn金属間化合物部分の中に、粒子3Rpから金属間化合物化されずに、Cuの単金属部分が残った核3cが含まれることになる。なかでもあらかじめ定めた最大径を有する粒子3Rpsについては、他の粒子に比べて単金属部分の核3cとして残りやすいので、よりサイズ規定が容易にできる。つまり、接合部3の厚さ3tを規定できるとともに、放熱性の向上・応力緩和も達成できる。 In the fourth embodiment, the particles 3Rps for defining the thickness 3t are used, and the composition ratio of Sn and Cu in the bonding material layer 3R is higher than the stoichiometric ratio for forming Cu 3 Sn. It is a thing. As a result, as shown in FIG. 6, in the bonded portion 3 after bonding, a nucleus in which a single metal portion of Cu remains in the Cu 3 Sn intermetallic compound portion without being converted into an intermetallic compound from the particles 3Rp. 3c will be included. In particular, the particle 3Rps having a predetermined maximum diameter is likely to remain as the nucleus 3c of the single metal portion as compared with other particles, so that the size can be easily defined. That is, the thickness 3t of the joint portion 3 can be defined, and improvement in heat dissipation and stress relaxation can be achieved.

以上のように、本実施の形態4にかかる接合方法によれば、混合層(接合材層3R)での第一金属(Cu)の第二金属(Sn)に対する割合が、金属間化合物(CuSn)を生成するための量論比(モル比で3:1)よりも大きくなるようにしているので、導電性の高いCuの核3cが伝熱パスとなり、放熱性能を向上させることができる。さらに、応力緩和に対する効果がある。とくに、スペーサとして機能するあらかじめ定めた最大径の粒子3Rpsが核3cとなって残り、厚み規定がより容易になる。 As described above, according to the bonding method according to the fourth embodiment, the ratio of the first metal (Cu) to the second metal (Sn) in the mixed layer (bonding material layer 3R) is such that the intermetallic compound (Cu 3 Sn) stoichiometric ratio for generating (in a molar ratio of 3: since to be larger than 1), nuclear 3c of high conductivity Cu becomes heat transfer path, it is possible to improve the heat dissipation performance it can. Furthermore, there is an effect on stress relaxation. In particular, particles 3Rps having a predetermined maximum diameter functioning as a spacer remain as nuclei 3c, and the thickness can be easily defined.

実施の形態5.
本実施の形態5にかかる接合方法では、上記各実施の形態1〜4で説明した接合部に対して、厚み方向に中間部分に緩衝板を挿入するようにしたものである。図7は、本実施の形態5にかかる接合方法における工程ごとの接合部の構成を示すもので、図7(a)と(b)はそれぞれ、実施の形態1における図1(d)と(e)に対応するものである。図中、実施の形態1と同様の部分については同様の符号を付し、詳細な説明は省略する。また、実施の形態1における図1(d)、(e)以外の部分については、実施の形態5においても流用する。
Embodiment 5 FIG.
In the joining method according to the fifth embodiment, a buffer plate is inserted into the intermediate portion in the thickness direction with respect to the joint described in the first to fourth embodiments. FIG. 7 shows the structure of the joining portion for each step in the joining method according to the fifth embodiment, and FIGS. 7 (a) and 7 (b) are the same as FIGS. This corresponds to e). In the figure, the same parts as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted. Further, portions other than those in FIGS. 1D and 1E in the first embodiment are also used in the fifth embodiment.

本実施の形態5においては、図7(a)に示すように、金属製の緩衝板9(厚さ1μm〜90μmの両面に、上記各実施の形態で説明した接合材層3Rを設けた複合接合材層30Rを形成する。そして、複合接合材層30Rの両側から接合対象M1、M2を押し当て、実施の形態1で説明したようにSnの融点以上かつCuの融点以下の温度で熱処理し、図7(b)に示すように複合接合部30によって、接合対象M1、M2を接合する。   In the fifth embodiment, as shown in FIG. 7 (a), a metal buffer plate 9 (a composite material in which the bonding material layer 3R described in each of the above embodiments is provided on both sides of a thickness of 1 μm to 90 μm). The bonding material layer 30R is formed, and the bonding objects M1 and M2 are pressed from both sides of the composite bonding material layer 30R, and heat-treated at a temperature not lower than the melting point of Sn and not higher than the melting point of Cu as described in the first embodiment. 7B, the objects to be joined M1 and M2 are joined by the composite joining portion 30. As shown in FIG.

緩衝板9は接合対象M1、M2と比較して厚みの薄い金属で、接合部3と接合される材料としては特に限定されるものではなく、例えば、Cu、Al、Ag、Au、Ni、Co等の金属が適用できる。緩衝板9の両面に形成する接合材層3Rは、同じ仕様であってもよいが、異なる仕様(異なる実施の形態で示す接合材層3R)の組合せであってもよい。また、上記各実施の形態と同様、接合対象M1、M2側にも接合材層3Rを形成してもよく、その場合も、異なる仕様を組み合わせてもよい。   The buffer plate 9 is a metal that is thinner than the objects to be joined M1 and M2, and is not particularly limited as a material to be joined to the joint portion 3. For example, Cu, Al, Ag, Au, Ni, Co Metals such as can be applied. The bonding material layers 3R formed on both surfaces of the buffer plate 9 may have the same specifications, but may have a combination of different specifications (bonding material layers 3R shown in different embodiments). Further, similarly to the above-described embodiments, the bonding material layer 3R may be formed on the bonding objects M1 and M2 side, and in that case, different specifications may be combined.

このように、接合対象M1、M2間に挟み込んだ緩衝板9が接合対象M1と接合対象M2に発生するうねりを吸収することで、接合が容易に出来るようになり、緩衝板9があることで複合接合部30にかかる応力を吸収し、接合信頼性を向上させることができる。また、実施の形態3あるいは4のように、粒子3Rp中にサイズを規定する粒子3Rpsを配合すれば、複合接合部30の厚みを選択出来ることより、より高い応力緩和性と高い放熱性を得ることが可能である。そのため、複合接合部30は、特に接合部3−3に好適である。   As described above, the buffer plate 9 sandwiched between the bonding targets M1 and M2 absorbs the swell generated in the bonding target M1 and the bonding target M2, so that the bonding can be easily performed, and the buffer plate 9 is provided. The stress applied to the composite joint 30 can be absorbed, and the joining reliability can be improved. Moreover, if the particle 3Rps that defines the size is mixed in the particle 3Rp as in the third or fourth embodiment, the thickness of the composite joint 30 can be selected, so that higher stress relaxation and higher heat dissipation are obtained. It is possible. Therefore, the composite joint portion 30 is particularly suitable for the joint portion 3-3.

以上のように、本実施の形態5にかかる接合方法によれば、混合層(接合材層30R)の厚み方向の中間部分には、接合対象M1、M2よりも厚みが薄い緩衝板9が挿入されているので、より高い応力緩和性と高い放熱性を得ることが可能である。   As described above, according to the joining method according to the fifth embodiment, the buffer plate 9 having a thickness smaller than that of the joining objects M1 and M2 is inserted in the middle portion in the thickness direction of the mixed layer (joining material layer 30R). Therefore, it is possible to obtain higher stress relaxation and higher heat dissipation.

つまり、上記各実施の形態にかかる接合方法で電力用半導体装置10を製造(接合部3を形成)すれば、高出力で信頼性の高い電力用半導体装置10を得ることができる。   That is, if the power semiconductor device 10 is manufactured (forms the junction 3) by the bonding method according to each of the above embodiments, the power semiconductor device 10 with high output and high reliability can be obtained.

なお、上記各実施の形態1〜5を適用する電力用半導体装置10においては、スイッチング素子(トランジスタ)や整流素子(ダイオード)として機能する電力用半導体素子1には、炭化ケイ素によって形成されたものを示した。しかし、これに限られることはなく、一般的に用いられているシリコンで形成されたものであってもよい。しかし、シリコンよりもバンドギャップが大きい、いわゆるワイドギャップ半導体を形成できる炭化ケイ素や、窒化ガリウム系材料又はダイヤモンドを用いた時の方が、運転温度が高く、扱う電流が大きいため発熱量も大きくなるので、本発明による効果をより一層発揮することができる。   In the power semiconductor device 10 to which each of the first to fifth embodiments is applied, the power semiconductor element 1 functioning as a switching element (transistor) or a rectifier element (diode) is formed of silicon carbide. showed that. However, the present invention is not limited to this, and it may be formed of generally used silicon. However, when using silicon carbide, which can form a so-called wide gap semiconductor, or a gallium nitride-based material or diamond, which has a larger band gap than silicon, the operating temperature is high and the current handled is large, so the amount of heat generated is also large. Therefore, the effect by this invention can be exhibited further.

なお、スイッチング素子及び整流素子の両方がワイドバンドギャップ半導体によって形成されていても、いずれか一方の素子がワイドバンドギャップ半導体によって形成されていてもよいことは言うまでもない。   Needless to say, both the switching element and the rectifying element may be formed of a wide band gap semiconductor, or one of the elements may be formed of a wide band gap semiconductor.

1:電力用半導体素子、 2:リード端子(配線部材)、 3:接合部、 3R:接合材層(混合層)、 3Rb:基材、 3Rp:粒子、 3Rps:厚みを規定する粒子、
4:絶縁基板、 4f,4r:導電層、 4i:セラミック基材、 5:ヒートシンク、 6:封止体、 9:緩衝板、 30:複合接合材層(混合層)、
M1,M2:接合対象。
1: power semiconductor element, 2: lead terminal (wiring member), 3: joint, 3R: bonding material layer (mixed layer), 3Rb: base material, 3Rp: particles, 3Rps: particles defining the thickness,
4: Insulating substrate, 4f, 4r: Conductive layer, 4i: Ceramic base material, 5: Heat sink, 6: Sealing body, 9: Buffer plate, 30: Composite bonding material layer (mixed layer),
M1, M2: Joining targets.

Claims (10)

相対向する接合対象の間に金属間化合物を生成して接合する方法であって、
第一金属と第二金属との混合層を形成する工程と、
前記混合層を間に挟むように、前記接合対象を重ねあわせる工程と、
前記第一金属の融点と前記第二金属の融点の中間の温度に加熱し、前記接合対象の間に前記金属間化合物を生成する工程と、を含み、
前記混合層を形成する工程では、少なくとも一方の接合対象の接合面上に、析出によって前記混合層を形成することを特徴とする接合方法。
A method for producing and joining an intermetallic compound between opposing joining objects,
Forming a mixed layer of a first metal and a second metal;
A step of superimposing the joining objects so as to sandwich the mixed layer;
Heating to a temperature intermediate between the melting point of the first metal and the melting point of the second metal, and generating the intermetallic compound between the objects to be joined,
In the step of forming the mixed layer, the mixed layer is formed by precipitation on at least one of the bonding surfaces to be bonded.
前記第一金属は、Cu、Ag、Au、Ni、およびCoのうちのいずれかであり、
前記第二金属は、SnまたはInであることを特徴とする請求項1に記載の接合方法。
The first metal is any one of Cu, Ag, Au, Ni, and Co;
The bonding method according to claim 1, wherein the second metal is Sn or In.
前記混合層は、前記第一金属より融点の低い前記第二金属の基材中に、前記第一金属の粒子が混入したものであることを特徴とする請求項1または2に記載の接合方法。   3. The joining method according to claim 1, wherein the mixed layer is obtained by mixing particles of the first metal in a base material of the second metal having a melting point lower than that of the first metal. . 前記混合層は、前記第一金属の粒子のうち、最大径となるあらかじめ定めた径を有する複数の粒子が、前記接合面内に分散していることを特徴とする請求項3に記載の接合方法。   4. The bonding according to claim 3, wherein among the particles of the first metal, the mixed layer has a plurality of particles having a predetermined diameter that is a maximum diameter dispersed in the bonding surface. Method. 前記混合層での前記第一金属の前記第二金属に対する割合が、前記金属間化合物を生成するための量論比よりも大きいことを特徴とする請求項3または4に記載の接合方法。   The bonding method according to claim 3 or 4, wherein a ratio of the first metal to the second metal in the mixed layer is larger than a stoichiometric ratio for generating the intermetallic compound. 前記混合層が、他方の接合対象の接合面にも、析出によって形成されていることを特徴とする請求項1から5のいずれか1項に記載の接合方法。   The joining method according to claim 1, wherein the mixed layer is also formed by precipitation on the joining surface of the other joining target. 前記混合層の厚み方向の中間部分には、前記接合対象よりも厚みが薄い緩衝板が挿入されていることを特徴とする請求項1から6のいずれか1項に記載の接合方法。   The joining method according to any one of claims 1 to 6, wherein a buffer plate having a thickness smaller than that of the joining target is inserted in an intermediate portion in the thickness direction of the mixed layer. 回路基板の一方の面に、裏面電極が接合された電力用半導体素子と、
前記電力用半導体素子の表面電極に接合された配線部材と、
前記回路基板の他方の面に接合された冷却部材と、を備え、
前記電力用半導体素子と前記回路基板との接合、前記電力用半導体素子と前記配線部材との接合、および前記回路基板と前記冷却部材との接合のうちの少なくともいずれかが、請求項1から7のいずれか1項に記載の接合方法によってなされていることを特徴とする電力用半導体装置。
A power semiconductor element having a back electrode bonded to one surface of a circuit board;
A wiring member bonded to the surface electrode of the power semiconductor element;
A cooling member joined to the other surface of the circuit board,
8. At least one of joining of the power semiconductor element and the circuit board, joining of the power semiconductor element and the wiring member, and joining of the circuit board and the cooling member is performed. A power semiconductor device comprising the bonding method according to any one of the above.
前記電力用半導体素子は、ワイドバンドギャップ半導体材料で形成されていることを特徴とする請求項8に記載の電力用半導体装置。   The power semiconductor device according to claim 8, wherein the power semiconductor element is formed of a wide band gap semiconductor material. 前記ワイドバンドギャップ半導体材料は、炭化ケイ素、窒化ガリウム系材料、およびダイヤモンドのうちのいずれかであることを特徴とする請求項9に記載の電力用半導体装置。   10. The power semiconductor device according to claim 9, wherein the wide band gap semiconductor material is any one of silicon carbide, gallium nitride-based material, and diamond.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019122967A (en) * 2018-01-12 2019-07-25 メテック株式会社 Method for manufacturing copper tin alloy
WO2021192239A1 (en) * 2020-03-27 2021-09-30 三菱電機株式会社 Metal joint, semiconductor device, wave guide tube, and method for joining members designated for joining

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002314241A (en) * 2001-04-18 2002-10-25 Hitachi Ltd Electronic device
JP2007019360A (en) * 2005-07-11 2007-01-25 Fuji Electric Holdings Co Ltd Mounting method of electric component
JP2009060101A (en) * 2000-12-21 2009-03-19 Hitachi Ltd Electronic device
US20120112201A1 (en) * 2010-11-09 2012-05-10 Board of Trustees of the Univ. of Arkansas, acting for&on behalf of the Univ. of Arkansas,Fayetevill High melting point soldering layer and fabrication method for the same, and semiconductor device
JP2013013933A (en) * 2011-06-30 2013-01-24 Rohm Co Ltd Laminated high melting point soldering layer and fabrication method for the same, and semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009060101A (en) * 2000-12-21 2009-03-19 Hitachi Ltd Electronic device
JP2002314241A (en) * 2001-04-18 2002-10-25 Hitachi Ltd Electronic device
JP2007019360A (en) * 2005-07-11 2007-01-25 Fuji Electric Holdings Co Ltd Mounting method of electric component
US20120112201A1 (en) * 2010-11-09 2012-05-10 Board of Trustees of the Univ. of Arkansas, acting for&on behalf of the Univ. of Arkansas,Fayetevill High melting point soldering layer and fabrication method for the same, and semiconductor device
JP2013013933A (en) * 2011-06-30 2013-01-24 Rohm Co Ltd Laminated high melting point soldering layer and fabrication method for the same, and semiconductor device

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