JP2014072742A - Synchronization system and receiving device including the same, communication system including the receiving device and synchronization method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a synchronization system capable of precisely establishing synchronization with a small size circuit even under multipath fading circumstances.SOLUTION: A synchronization system 32 performs sampling and quantizing a baseband signal at plural sampling timings per symbol and detects the signal. The synchronization system 32 calculates a correlation value between a sample value sequence at plural sampling timings and a unique word at sampling timing without converting the quantized value into a binary value with respect to the detected sample value sequence and sets the symbol synchronization timing and the frame synchronization timing based on the correlation value. Unlike conventional manners, since the correlation value is calculated without performing binarization on a sample value, even when the waveform of the received baseband signal is distorted due to multipath fading, little rounding error is generated in the correlation value, which is caused by a binarization; thus the synchronization is accurately established. Also, compared to OFDM method etc., since a simpler processing is necessary for increasing the accuracy, the circuit size can be reduced.

Description

  The present invention relates to a synchronization system that establishes synchronization of baseband signals in communication, a receiving apparatus including the same, a communication system including the apparatus, and a synchronization method.

  General wireless communication is asynchronous communication because the transmitter and the receiver operate with different clocks. Therefore, the receiver can detect symbols by performing oversampling that performs a plurality of samplings on one symbol of the received baseband signal so as to be able to cope with any timing when the signal from the transmitter is received. It is necessary to extract the optimal timing. Such extraction processing is called symbol synchronization processing. The basic unit of a signal used for communication is a frame, and it is necessary to identify the beginning of a header or data in the frame. Such identification processing is called frame synchronization processing. A general wireless communication receiver has at least a synchronization system that establishes the symbol synchronization and frame synchronization.

  As a conventional technique for establishing symbol synchronization, a zero cross detection method is widely known. In this zero-cross detection method, a signal that repeats 1 and 0 alternately (a signal following 101010...) Is arranged at the head of the baseband signal. In the receiving apparatus, the baseband signal is oversampled, and the sign inversion timing of the signal repeating 1 and 0, that is, the zero cross timing is read. Then, based on the read zero-cross timing, a sampling timing capable of accurately detecting the symbol is obtained, and the sampling timing is set as the symbol synchronization timing. For example, the sampling timing closest to the middle between the zero cross and the next zero cross is set as the symbol synchronization timing.

  Next, FIG. 30 shows a conventional technique for establishing frame synchronization for a baseband signal with symbol synchronization. Originally, in the symbol synchronization establishment process, the value obtained by oversampling the baseband signal, that is, the sample value of the baseband signal is quantized. In the conventional method of establishing frame synchronization, the value quantized as described above is discriminated based on the binarization threshold value and replaced with the binary value for the sample value sequence at the sampling timing set at the symbol synchronization timing. (S101). Then, a correlation value between the sample value sequence and a known bit synchronization bit sequence that is also binary is calculated (S102). If the calculated correlation value is equal to or greater than a preset correlation threshold value (Yes in S103), it is determined that the sample value sequence matches the frame synchronization bit sequence, and the timing at which they match is determined by frame synchronization. Set to timing. In this way, frame synchronization is established (S104).

  Incidentally, in a wireless communication system, distortion of a received signal waveform caused by multipath fading is one of the problems. This phenomenon of waveform distortion is due to the fact that the transmitted signal arrives at the receiving antenna through different paths (multipaths) with different delay times, and these are added together by the receiving antenna. In a multipath environment, direct waves coming directly from the transmitting antenna and indirect waves reflected by obstacles or the ground surface are input to the receiving antenna, or only indirect waves that have passed through multiple paths without direct waves are received by the receiving antenna. It is transmitted to.

  When such a phenomenon occurs, the received signal waveform may be distorted. The received signal waveform tends to be more easily distorted as the signal transmission speed is higher. The reason will be described with reference to FIG. As shown in the figure, when the signal transmission rate is high, the symbol length of the signal is shortened, so that the relative ratio of the delay time to the symbol length is high. Therefore, for example, when there are two signals that have passed through different paths, the other signal is delayed due to multipath with respect to one signal, and the symbol length of the signal is close to the delay time, the first symbol of one signal And the overlapping portion of the other signal with the 0th symbol becomes longer. As a result, the distortion of the received signal waveform with respect to the symbol length becomes relatively large. In the figure, only two signals are taken up. However, in practice, a large number of multi-pulse signals having different delay amounts are added, so that the distortion can be further increased. When the distortion becomes large in this way, in the above symbol synchronization establishment process, the original zero cross timing cannot be detected, and thus there is a problem that stable symbol synchronization cannot be obtained. As a result, the above frame synchronization establishment process The synchronization accuracy may also be affected.

  Even if the symbol synchronization can be established accurately in a state where the distortion of the received signal waveform is large, the synchronization accuracy of the frame synchronization establishment process may be affected. The reason will be described with reference to FIGS. 32A to 32C respectively show an ideal signal waveform of a frame synchronization bit string, a received signal waveform after detection and before binarization, and a frame synchronization bit string after binarization. The signal waveform is illustrated. As shown in the figure, when the signal waveform is distorted due to the distortion of the received signal waveform, even if the ideal value of one bit in the frame string for frame synchronization is 1, for example, the signal value S1 that should be the value is 2 It may be less than the threshold value St, and may be rounded to 0 by mistake during binarization. As a result, the bit string for frame synchronization after binarization may be a bit string different from that at the time of transmission. As a result, the correlation value of the frame synchronization bit string becomes different from the original value, and the difference between the correlation value of the frame synchronization bit string and the correlation value of the other bit strings decreases, resulting in false synchronization. There is a risk that it will be vulnerable to noise.

  Thus, as a typical measure for eliminating the influence of multipath fading, there is a multicarrier transmission technique such as OFDM (Orthogonal Frequency Division Multiplexing) (see, for example, Patent Document 1). It is possible to reduce the influence of multipath fading while maintaining the communication speed by dividing the information to be transmitted and transmitting in parallel on multiple carriers (subcarriers) and reducing the transmission speed of each carrier. Technology. In this technique, the symbol length is lengthened by slowing the transmission rate of each carrier, and as shown in FIG. 33, the delay per symbol due to multipath is relatively sufficiently shorter than the symbol length. Therefore, even if affected by multipath fading, the distortion of the received signal waveform with respect to the symbol length becomes relatively small. Therefore, symbol synchronization can be easily established, and frame synchronization can be established stably. it can.

JP 2010-103900 A

  However, multi-carrier transmission requires a complicated configuration for processing by transforming the frequency axis and the time axis by inverse Fourier transform and Fourier transform, which increases the circuit scale and makes it difficult to reduce the size of the circuit. There is a drawback of being.

  The present invention has been made to solve this problem. The present invention provides a synchronization system capable of establishing synchronization with high accuracy in a small-scale circuit without reducing the transmission speed even in a multipath fading environment when provided in a receiving apparatus, and a receiving apparatus and the apparatus including the same. It is an object of the present invention to provide a communication system and a synchronization method.

  In order to achieve the above object, the synchronization system of the present invention samples and detects a baseband signal at a plurality of sampling timings per symbol and detects a sample value sequence of the baseband signal as it is and a predetermined value. A correlation value with the synchronization bit string is calculated at each sampling timing, and symbol synchronization and frame synchronization are established based on the calculated correlation value.

  In the present invention, an oversampling unit that samples a baseband signal at a plurality of sampling timings per symbol and quantizes with M (M: integer of 2 or more) bits, and a sample value quantized by the oversampling unit A detection unit for detecting a sequence, and a sample value sequence detected by the detection unit, the quantized sample values are used as they are without being replaced with binary values, and sample value sequences of the plurality of sampling timings are used. And a synchronization establishing unit that establishes symbol synchronization and frame synchronization based on the calculated correlation value for each sampling timing.

  In the present invention, if the calculated correlation value is equal to or greater than the correlation threshold, the synchronization establishing unit sets the sampling timing of the correlation value as the symbol synchronization timing, and sets the timing when the correlation value is equal to or greater than the correlation threshold. It is preferable to set the frame synchronization timing.

  In this invention, it is preferable that the synchronization establishing unit calculates the correlation value for sample value sequences of all sampling timings among the plurality of sampling timings.

  In this invention, the synchronization establishment unit includes: a correlation value extraction unit that extracts a correlation value that is equal to or greater than the correlation threshold; and a maximum correlation value extraction unit that extracts a maximum correlation value from the extracted correlation values. Preferably, the sampling timing of the extracted maximum correlation value is set as the symbol synchronization timing, and the timing when the correlation value becomes the maximum correlation value is preferably set as the frame synchronization timing.

  In the present invention, it is preferable to further include a normalization unit that normalizes the level of an input signal input to the synchronization system.

  In this invention, the synchronization establishment unit has an average value calculation unit that calculates a moving average value of an input signal input to the synchronization system, and sets the correlation threshold based on the calculated moving average value. It is preferable.

  The receiving device of the present invention includes the synchronization system.

  The communication system of the present invention includes the receiving device and a transmitting device that transmits an RF signal obtained by up-converting a baseband signal to the receiving device, and the receiving device includes: The apparatus further includes a receiving unit that receives the transmitted RF signal, and a down-converting unit that obtains a baseband signal by down-converting the RF signal received by the receiving unit.

  In the present invention, the transmitting device periodically transmits a unique word that is the synchronization bit string, and the synchronization establishing unit counts an elapsed time from when the last symbol of the unique word is detected. The counter of the symbol synchronization and the frame synchronization are within a known period from when the last symbol of the unique word is detected to when the next unique word is input. It is preferable to stop the establishing operation.

  In the present invention, the synchronization establishment unit counts an elapsed time from when the last symbol of the unique word is detected, and the maximum count time is set longer than the sum of the known period and the length of the unique word. It is preferable that the synchronization establishment stop function is forcibly turned off when the count time by the second counter reaches the maximum count time.

  In this invention, the transmission device continuously transmits the unique word, which is the synchronization bit string, by m (m: integer) times the number of sampling timings, and the synchronization system calculates the correlation value. It is preferable to further include a timing setting unit that switches the sampling timing every m times the length of one unique word.

  In the synchronization method of the present invention, a baseband signal is sampled and detected at a plurality of sampling timings per symbol, and a sample value sequence of the baseband signal having the detected value and a predetermined synchronization bit sequence are detected. The correlation value is calculated for each sampling timing, and symbol synchronization and frame synchronization are established based on the calculated correlation value.

  The present invention comprises a sampling step of oversampling a baseband signal at a plurality of sampling timings per symbol and quantizing with M bits, and a detection step of detecting a sample value sequence quantized by the sampling step. The sample value sequence detected by the detection step is used as it is without replacing the quantized sample value with a binary value, and the sample value sequence of the plurality of sampling timings and a predetermined synchronization bit sequence It is preferable to include a synchronization establishing step of calculating the correlation value of each at each sampling timing and establishing symbol synchronization and frame synchronization based on the calculated correlation value.

  According to the present invention, for the sample value sequence of the baseband signal after detection, the sample value is used as it is, and the correlation value is calculated. Therefore, when provided in the receiving apparatus, even if the received baseband signal waveform is distorted due to the influence of multipath fading, it is binarized compared to the case where the correlation value is calculated after binarizing the sample value as in the prior art. The error of the correlation value due to rounding of time is eliminated. Therefore, the accuracy of synchronization establishment based on the correlation value can be improved. Further, the processing necessary for improving the accuracy of establishment of synchronization is simpler than multi-carrier techniques such as OFDM, and therefore the circuit scale can be reduced.

1 is a block diagram of a communication system according to an embodiment of the present invention. The figure which shows the structure of the communication signal in the said communication system. The figure which shows the sampling timing by the synchronous system provided in the receiver of the said communication system. The flowchart of the synchronous process by the said synchronous system. (A) thru | or (d) is a figure for demonstrating the correlation value calculation method of this embodiment. (A) thru | or (d) is a figure for demonstrating the correlation value calculation method of this embodiment. The block diagram of the synchronization establishment circuit of the synchronous system which concerns on a 1st modification. The flowchart of the synchronous process by the said synchronous system. The block diagram of the synchronization establishment circuit of the synchronous system which concerns on a 2nd modification. The flowchart of the synchronous process by the said synchronous system. The block diagram of the synchronization establishment circuit of the synchronous system which concerns on a 3rd modification. The flowchart of the synchronous process by the said synchronous system. The block diagram of the receiver which concerns on a 4th modification. The flowchart of the synchronous process by the synchronous system of the said receiver. The block diagram of the synchronization establishment circuit of the synchronous system which concerns on a 5th modification. The flowchart of the synchronous process by the said synchronous system. The block diagram of the synchronization establishment circuit of the synchronous system which concerns on a 6th modification. The figure which shows the structure of the transmission signal by the transmitter of the communication system which concerns on the said modification. The flowchart of the synchronous process by the said synchronous system. The figure which shows the synchronous detection prohibition period and synchronous detection permission period in the said synchronous system. The figure for demonstrating the subject of the said modification. The block diagram of the synchronization establishment circuit of the synchronous system which concerns on a 7th modification. The flowchart of the synchronous process by the said synchronous system. The figure which shows the synchronous detection prohibition period and synchronous detection permission period in the said synchronous system. The block diagram of the communication system which concerns on an 8th modification. The figure which shows the structure of the transmission signal by the transmitter of the said communication system. The flowchart of the synchronous process by the synchronous system of the said communication system. The figure for demonstrating the structure of the transmission signal by the transmitter which concerns on a 9th modification, and the synchronous process by the synchronous system of a receiver. The figure for demonstrating the effect | action of the said modification. 10 is a flowchart of conventional frame synchronization processing. The figure which shows a received signal when a transmission signal with a high transmission rate is delayed due to multipath. (A) is an ideal signal waveform diagram of a frame synchronization bit string, (b) is a signal waveform diagram of a frame synchronization bit string after detection, and (c) a signal waveform diagram decoded from the frame synchronization bit string. The figure which shows a received signal when a signal with a slow transmission rate is delayed due to multipath.

  FIG. 1 shows a configuration of a communication system according to an embodiment of the present invention. The communication system 1 includes a transmission device 2 and a reception device 3 that communicate with each other in a wireless manner. The transmission apparatus 2 wirelessly transmits an RF signal obtained by up-converting the baseband signal. The baseband signal is a symbol string formed by modulating communication data, and is transmitted in units of frames having a predetermined data length. The data length of the frame may be a plurality of patterns. The receiving device 3 receives the RF signal transmitted from the transmitting device 2, and down-converts the received RF signal to obtain a baseband signal.

  In the wireless communication system 1, initially, the receiving device 3 is in an asynchronous state because it does not know the timing of transmission from the transmitting device 2. Therefore, in order to read communication data from the baseband signal, it is necessary not only to detect the baseband signal but also to establish symbol synchronization and frame synchronization between the transmission device 2 and the reception device 3. Therefore, as shown in FIG. 2, a unique word 22 for establishing symbol synchronization and frame synchronization is added to the head of the frame 21, and communication data 23 is included after that. The unique word 22 is a predetermined synchronization bit string, and symbol synchronization and frame synchronization are established using this synchronization bit string. In the present embodiment, the baseband signal is oversampled, and from among a plurality of sampling timings (see FIG. 3), a sampling timing at which a symbol value can be accurately captured is detected and set as a symbol synchronization timing. Synchronization is established.

  The receiving device 3 receives a RF signal via the receiving antenna 30 and down-converts it between a receiving circuit 31 (receiving unit and down-converting unit) and a baseband signal obtained by down-converting the RF signal. And a synchronization system 32 for establishing synchronization. In addition, the reception device 3 includes an error correction circuit 36 that performs error correction of a baseband signal whose synchronization is established by the synchronization system 32. The error correction circuit 36 is not necessarily provided in the receiving device 3.

  The synchronization system 32 includes an AD converter circuit 33, a filter circuit 34, and a synchronization establishment circuit 35. The AD converter circuit 33 (oversampling unit) AD-converts the baseband signal output from the receiving circuit 31 and performs oversampling at a sampling frequency equal to or higher than the symbol frequency. The symbol frequency is the number of symbols transmitted per second. In addition, the AD converter circuit 33 quantizes the sample value of the baseband signal obtained by the sampling processing with M (M: integer of 2 or more) bits. The filter circuit 34 passes only the baseband signal component out of the signal output from the AD converter circuit 33 and removes the noise component. The synchronization establishment circuit 35 (synchronization establishment unit) detects the baseband signal that has passed through the filter circuit 34, and establishes symbol synchronization and frame synchronization. Hereinafter, when simply referred to as synchronization, symbol synchronization and frame synchronization are collectively indicated.

  As shown in FIG. 3, the AD converter circuit 33 samples (oversamples) the baseband signal at a plurality of sampling timings per symbol Sb. The AD converter circuit 33 samples the signal value of the baseband signal, for example, at four sampling timings (0) to (3) per symbol Sb (four times sampling). The sampling timings (0) to (3) are shifted at equal intervals in time, and in the case of quadruple sampling, the interval is 1/4 of the symbol period, that is, at a frequency four times the symbol frequency. Sampling is performed. The number of sampling timings is not limited to the above four, and may be plural.

  The synchronization establishment circuit 35 includes a detection circuit 35a, a bit string extraction circuit (hereinafter referred to as an extraction circuit) 35b, a synchronization bit string storage circuit (hereinafter referred to as a storage circuit) 35c, a correlation value calculation circuit (hereinafter referred to as a calculation circuit) 35d, a threshold value A setting circuit 35e and a comparison circuit 35f are included. The detection circuit 35a (detection unit) detects (decodes) the sample value sequence of the baseband signal, which has been quantized by the AD converter circuit 33 and passed through the filter circuit 34, by delay detection or the like. The extraction circuit 35b extracts the sample value sequence at each sampling timing (0) to (3) from the sample value sequence detected by the detection circuit 35a at each sampling timing. The number of sample values in the extracted sample value sequence corresponds to the number of bits of the unique word 22 (see FIG. 2) stored in the storage circuit 35c. The storage circuit 35c stores a known unique word 22 in advance. The calculation circuit 35d calculates a correlation value between the sample value sequence extracted by the extraction circuit 35b and the unique word 22 stored in advance in the storage circuit 35c at each sampling timing. At this time, the calculation circuit 35d uses the sample value sequence extracted by the extraction circuit 35b as it is without replacing the M-bit quantized sample value with the binary value of 0 or 1, and uses the correlation value as it is. Is calculated. In this calculation process, since the quantized sample value is used as it is, the result of soft-decision of the detected baseband signal, that is, the certainty as to which of the above binary values is used as it is. It is done. The correlation value increases as the sample value string approaches the bit string of the unique word 22. The threshold setting circuit 35e sets in advance a correlation threshold that is a criterion for establishing synchronization. The comparison circuit 35f compares the set correlation threshold value with the calculated correlation values at a plurality of sampling timings for each sampling timing, and determines whether or not the calculated correlation value is equal to or greater than the correlation threshold value. To do.

  The value of each bit of the unique word 22 stored in the storage circuit 35c is an ideal value composed of binary values of 0 or 1. The binary values 0 and 1 are converted so as to be treated in the same manner as binary values having the same absolute value but different signs, for example, -1 and +1, in predetermined signal processing in the calculation circuit 35d. The The value subjected to the conversion processing is used as a bit value for the correlation value calculation processing by the calculation circuit 35d.

  The calculation circuit 35d multiplies the sample value string extracted by the extraction circuit 35b and the unique word 22 stored in the storage circuit 35c by the sample value and the bit value in the same order in time series order, The sum of the multiplication results is calculated as a correlation value. At this time, in actual calculation, signal processing corresponding to multiplication of the sample value sequence and the unique word 22 is executed.

  The threshold setting circuit 35e presets a correlation threshold based on an input from an operation unit or an interface unit (not shown). The correlation threshold is controlled by signal processing so as to be a value obtained by multiplying the absolute value of the maximum possible correlation value (ideal correlation value) by a coefficient of 1 or less, for example, 0.7. The reason why the correlation threshold is set to such a value is that, even if the waveform of the received signal is distorted and the correlation value becomes small, the correlation threshold can be distinguished from the correlation value of the unique word 22 and the noise correlation value in the received signal. This is because it is not necessary to completely match the ideal correlation value if possible.

  The synchronization establishment circuit 35 further includes a synchronization detection circuit 35g and a synchronization setting circuit 35h. If the comparison circuit 35f determines that the correlation value of each sampling timing calculated by the calculation circuit 35d is equal to or greater than the correlation threshold, the synchronization detection circuit 35g converts the sampling timing of the correlation value to the symbol synchronization timing. Detect as. Further, the synchronization detection circuit 35g detects the timing at which the correlation value is determined to be equal to or greater than the correlation threshold as the frame synchronization timing. The synchronization setting circuit 35h sets the sampling timing detected as the symbol synchronization timing by the synchronization detection circuit 35g to the symbol synchronization timing of the baseband signal detected by the detection circuit 35a. The synchronization setting circuit 35h sets the timing detected as the frame synchronization timing by the synchronization detection circuit 35g to the frame synchronization timing of the baseband signal detected by the detection circuit 35a. In this way, the synchronization setting circuit 35h sets the symbol synchronization timing and the frame synchronization timing based on the correlation value of each sampling timing calculated by the calculation circuit 35d, and establishes synchronization.

  The synchronization setting circuit 35h uses the sampling timing sample values (for example, 0.5, -0.7, 0.9) set as the symbol synchronization timing after the synchronization is established, and the symbol values of the detected baseband signals. (Example: 1, -1, 1) is extracted and output. For example, when the sampling timing (1) among the sampling timings (0) to (3) is set to the symbol synchronization timing, the synchronization setting circuit 35h sets the sample value sampled at the sampling timing (1) to each symbol. Output as a value. Therefore, the signal output from the synchronization setting circuit 35h is a sample value sequence obtained by sampling the baseband signal after detection at a frequency that is one time the symbol frequency (a sample value sequence obtained by sampling the baseband signal by one time). The synchronization setting circuit 35h does not output the sample value sequence at other sampling timings, that is, the sample value sequence at the sampling timings (0), (2), and (3) in the above example.

  Next, the procedure of synchronization processing by cooperation of each circuit of the synchronization system 32 will be described with reference to FIG. 4 in addition to FIG. 1 and FIG. Here, the number of bits of the unique word 22 is N.

  When an RF signal is input, the receiving circuit 31 down-converts the RF signal and converts it into a baseband signal (S1). The AD converter circuit 33 samples the baseband signal at sampling timings (0) to (3) (S2; oversampling step) and quantizes the baseband signal. After the sampled and quantized baseband signal has passed through the filter circuit 34, the detection circuit 35a detects the baseband signal (S3; detection step).

  The extraction circuit 35b sequentially extracts an N-bit sample value sequence for each sampling timing (0) to (3) from the detected baseband signal B1 (S4). The calculation circuit 35d calculates a correlation value between the sample value string extracted by the extraction circuit 35b and the unique word 22 stored in the storage circuit 35c (S5). The correlation value is calculated at every sampling timing.

  The comparison circuit 35f compares the correlation value calculated in S5 with the correlation threshold set in advance by the threshold setting circuit 35e (S6), and samples whether or not the calculated correlation value is greater than or equal to the correlation threshold. Judge at each timing.

  When it is determined that the correlation value calculated in S5 is equal to or greater than the correlation threshold (Yes in S7), the synchronization detection circuit 35g detects the sampling timing of the correlation value as the symbol synchronization timing. At the same time, the synchronization detection circuit 35g detects the timing at which the correlation value is determined to be greater than or equal to the correlation threshold as the frame synchronization timing (S8). The synchronization setting circuit 35h sets the synchronization timing detected in S8 for the baseband signal B1 detected by the detection circuit 35a (S9; synchronization establishment step). When it is determined that the correlation value calculated in S5 is less than the correlation threshold (No in S7), the process returns to S1.

  A calculation method of the calculation circuit 35d in the present embodiment will be described. In this calculation technique, the extracted sample value sequence is used as it is without replacing the sample value quantized with M bits with the binary value, and the correlation value between the sample value sequence and the unique word 22 is calculated. Is done.

  Here, as an object to be compared with the above calculation method, two examples of correlation values calculated after replacing a sample value with a binary threshold value of 0 or 1 or -1 as in the past are shown in FIG. a) Shown in (b). In these examples, the unique word 22 has three bits of 1, -1, and 1. The value and the number of bits of each bit of the unique word 22 are not limited to this. Hereinafter, a method of calculating a correlation value by replacing a sample value with a binary value is referred to as a binarization calculation method.

  FIG. 5A shows a case where the extracted sample value sequence is a sample value sequence of the received signal indicating the unique word 22 and is, for example, 0.8, −0.3, and −0.1. In this case, the sample value −0.1 has an ideal value of 1 and the sign is inverted as compared with the ideal value, but the difference from the binarization threshold is only 0.1. However, the sample value -0.1 is rounded to -1 by binarization to -1 or 1 with 0 being the binarization threshold, and the difference from the binarization threshold is considered to be 1. As a result, the correlation value of the extracted sample value sequence is 1.0.

  On the other hand, FIG. 5B is a sample value of a received signal indicating another bit string whose extracted sample value string is not the unique word 22, for example, 0.8, −0.3, −0.7. Indicates the case where there was. The correlation value in this case is also 1.0.

  As shown in these results, in the binarization calculation method, the difference between the correlation value when the signal indicating the unique word 22 is received and the correlation value when the signal indicating another bit string is received is small. Sometimes, as the above example shows, it is sometimes zero. Therefore, it may be difficult to distinguish the unique word 22 from other bit strings in the received signal, and there is a possibility that erroneous synchronization will occur.

  On the other hand, in the calculation method of the present embodiment, even if the conditions are the same as those in FIGS. 5A and 5B, the correlation values are 1 as shown in FIGS. 0.0 and 0.4, and the difference between the correlation values in each case is 0.6. As shown in this result, in the calculation method of the present embodiment, the difference between the correlation value when the signal indicating the unique word 22 is received and the correlation value when the signal indicating another bit string is received is large. Become. For this reason, the unique word 22 and other bit strings can be easily identified in the received signal, and the synchronization accuracy is increased.

  By the way, in the binarization calculation method, as shown in FIGS. 6A and 6B, even if the sample value is 0.8, −0.3, 0.1, or 0.9, Even if −0.9 and 0.9, the correlation value is 3.0, which is the same. For example, when the correlation threshold value is 2.0, the correlation value is equal to or greater than the correlation threshold value at the sampling timings in FIGS. 6A and 6B, and therefore it cannot be determined which sampling timing is good. Since the sample value sequence at the latter sampling timing is closer to the unique word 22, it is more appropriate to set the timing at which the sample value sequence is extracted as the synchronization timing. However, it is difficult because the correlation values of both sample value sequences are equal.

  On the other hand, in the calculation method of the present embodiment, as shown in FIGS. 6C and 6D, the correlation values in the above two examples are 1.2 and 2.7, respectively. Can be determined. As described above, in the calculation method according to the present embodiment, since the correlation value is calculated in detail according to the sample value string, it is possible to set a more appropriate timing as the synchronization timing based on the correlation value. Is even higher.

  Note that in FIGS. 6A and 6C, the sample value of −0.1 in FIGS. 5A and 5C is 0.1 instead of 0.1, which is closer to the ideal value 1. Shows the case. As shown in FIG. 6A, in the case of the binarization calculation method, the correlation value is 2.0 (= 3.0 even though the sample value is only 0.2 close to the ideal value. -1.0) also increases. On the other hand, as shown in FIG. 6C, in the case of the calculation method of the present embodiment, the correlation value is 1.2, and the increase in the correlation value is 0.2 (= 1.2-1. Stay 0).

  As can be seen from the comparison between the two examples, in the binarization calculation method, the correlation value may increase significantly even if the sample value changes slightly in the vicinity of the binarization threshold. The timing may be set, and the synchronization accuracy may be reduced. On the other hand, in the calculation method of the present embodiment, since the correlation value is appropriately calculated according to the sample value, a more appropriate timing can be set as the synchronization timing, and the synchronization accuracy is further improved.

  In the present embodiment, for the sample value sequence of the baseband signal after detection, the sample value quantized with M bits is used as it is without being binarized, and the correlation value is calculated. Therefore, even if the received baseband signal waveform is distorted due to multipath fading, it is binarized compared to the case where the correlation value is calculated after converting the quantized sample value to binary as in the prior art. The error of the correlation value due to rounding of time is eliminated. Therefore, it is possible to improve the accuracy of establishing synchronization based on the correlation value. Further, the processing necessary for improving the accuracy of establishing synchronization is simpler than multi-carrier techniques such as OFDM, and therefore the circuit scale can be reduced and the cost of the circuit can be reduced. .

  Further, in order to establish symbol synchronization, it is not necessary to detect a zero cross by arranging a signal that repeats 1 and 0 alternately at the head of the baseband signal. Therefore, a signal that repeats 1 and 0 alternately becomes unnecessary and a zero-cross detection circuit is not required.

  Also, if the correlation value at any of the sampling timings (0) to (3) is equal to or greater than the correlation threshold, the sampling timing is set as the symbol synchronization timing. Also, the timing at which the correlation value is equal to or greater than the correlation threshold is set as the frame synchronization timing. Therefore, both symbol synchronization and frame synchronization can be established at the same time, the time required for establishing these synchronizations can be shortened, and the processing speed can be increased.

Next, various modifications of the above embodiment will be described with reference to the drawings. Only the configuration and processing different from the above embodiment will be described, and the others will be omitted.
(First modification)
FIG. 7 shows the configuration of the synchronization establishment circuit of the first modification. The calculation circuit 35d constituting the synchronization establishment circuit 35 includes an all sampling timing selection circuit (hereinafter referred to as a selection circuit) 35i. Among them, sample values at all sampling timings are selected.

  FIG. 8 shows a procedure of synchronization processing by the synchronization system of the present modification. In the synchronization process shown in FIG. 4, the process of S5 is changed to the processes of S21 and S22, and the other processes are the same. In the synchronization process, the selection circuit 35i selects all sampling timings (0) to (3) (S21). Thereafter, the calculation circuit 35d calculates a correlation value between the sample values of all the selected sampling timings (0) to (3) and the ideal value sequence of the unique word 22 for each sampling timing (S22).

  In this modification, correlation values are calculated for all sampling timings (0) to (3). Therefore, compared to the case where the correlation value is calculated only for a part of the sampling timings (0) to (3), the sampling timing that can detect the symbol value more accurately is detected based on the calculated correlation value. It becomes possible. Therefore, the symbol synchronization accuracy can be further improved, and the frame synchronization accuracy depending on the symbol synchronization accuracy can be further increased.

(Second modification)
FIG. 9 shows the configuration of the synchronization establishment circuit of the second modification. The synchronization establishment circuit 35 includes four timing-specific correlation value calculation circuits (hereinafter referred to as calculation circuits) 35j respectively associated with the sampling timings (0) to (3) (see FIG. 3). The calculation circuits 35j are arranged in parallel with each other, and each calculation circuit 35j includes an extraction circuit 35b, a storage circuit 35c, and a calculation circuit 35d. The extraction circuit 35b extracts only the sample value string of the sampling timing associated with the calculation circuit 35j from the sampling timings (0) to (3). The calculation circuit 35j calculates a correlation value between the extracted sample value sequence and the ideal value sequence of the unique word 22. This ideal value sequence is a bit sequence obtained by performing predetermined signal processing on the unique word 22 stored in the storage circuit 35c. As shown in the figure, the storage circuit 35c may be provided in each calculation circuit 35j, or one storage circuit 35c may be shared by the calculation circuits 35j.

  FIG. 10 shows a procedure of synchronization processing by the synchronization system of this modification. In the synchronization process shown in FIG. 4, the processes of S4 and S5 are changed to the processes of S31 and S32, and the other processes are the same. In the synchronization process, the four extraction circuits 35b sequentially extract N-bit sample value strings in parallel with respect to the sampling timings (0) to (3) (S31). Then, the four calculation circuits 35d calculate the correlation value between the sample value at each sampling timing and the ideal value sequence of the unique word 22 in parallel for each sampling timing (S32).

  In this modification, the correlation value calculation process is performed independently for each sampling timing, so that the processing algorithm can be simplified and development is facilitated. Further, since the correlation value calculation process is performed in parallel at each sampling timing, the time required for calculating the correlation value at all sampling timings can be shortened, and the entire process can be speeded up.

(Third Modification)
FIG. 11 shows the configuration of the receiving apparatus of the third modification. The synchronization establishment circuit 35 of the receiving device 3 is a circuit in which a correlation value extraction circuit 35k and a maximum correlation value extraction circuit 351 are added to the configuration of the second modification shown in FIG. The correlation value extraction circuit 35k (correlation value extraction unit) determines from the correlation values of the sampling timings (0) to (3) (see FIG. 3) calculated by the calculation circuit 35j that the correlation circuit 35f is greater than or equal to the correlation threshold value. Extracted correlation values. The maximum correlation value extraction circuit 35l (maximum correlation value extraction unit) extracts the maximum correlation value from the correlation values extracted by the correlation value extraction circuit 35k. In this extraction process, the maximum correlation value is extracted within a predetermined period from when the correlation value is determined to be equal to or greater than the correlation threshold.

  FIG. 12 shows a procedure of synchronization processing by the synchronization system of the present modification. The synchronization process is the same as the process of the second modification shown in FIG. 10 except that the processes of S41 and S42 are added between the processes of S7 and S8. In the synchronization process, the correlation value extraction circuit 35k extracts the correlation value determined to be equal to or higher than the correlation threshold value in the process of S7 from the correlation values at the sampling timings (0) to (3), and temporarily stores it in the memory. Store (S41). Then, the maximum correlation value extraction circuit 351 extracts the maximum correlation value from the extracted correlation values (S42). Thereafter, in the process of S8, the synchronization detection circuit 35g detects the sampling timing of the extracted maximum correlation value as the symbol synchronization timing, and detects the timing when the correlation value becomes the maximum correlation value as the frame synchronization timing.

  In the present modification, when the correlation value is equal to or higher than the correlation threshold at a plurality of sampling timings among the sampling timings (0) to (3), the sampling timing with the highest symbol value detection accuracy is set as the symbol synchronization timing. The As a result, the synchronization establishment accuracy can be improved.

(Fourth modification)
FIG. 13 shows the configuration of the synchronization system of the fourth modification. The synchronization system 32 further includes a normalization circuit 37 (normalization unit) that normalizes an input signal input to the system. The normalization circuit 37 is a so-called normalizer, and is inserted between the filter circuit 34 and the synchronization establishment circuit 35, but may be provided at other locations. The normalization circuit 37 adjusts and normalizes the reception level of the input signal, specifically, the baseband signal that has been input to the synchronization system 32 as an RF signal and passed through the filter circuit 34, and sends it to the synchronization establishment circuit 35. That is, the normalization circuit 37 makes the level of the input signal of the synchronization establishment circuit 35 constant and stabilizes it.

  FIG. 14 shows a procedure of synchronization processing by the synchronization system 32 of the present modification. The synchronization process is the same as the process of the third modification shown in FIG. 12 except that the process of S51 is added between the processes of S2 and S3. In the synchronization process, the normalization circuit 37 normalizes the burst band signal sampled in the process of S2 (S51).

  In this modification, even when the level of the input signal fluctuates significantly due to changes in the communication environment, etc., the signal is normalized before the synchronization is established and the signal level fluctuation is suppressed. And synchronization can be established.

(Fifth modification)
FIG. 15 shows the configuration of the synchronization establishment circuit of the fifth modification. The synchronization establishment circuit 35 has an average value calculation circuit for calculating a moving average value of an input signal input to the synchronization establishment circuit 35 (which constitutes a synchronization system) in the configuration of the third modification shown in FIG. 35m (average value calculation unit) is added. The threshold setting circuit 35e of the present modification sets the correlation threshold based on the calculated moving average value. In the synchronization establishment circuit 35 of this modification, an average value calculation circuit 35m, a threshold setting circuit 35e, and a comparison circuit 35f are provided in each of the four calculation circuits 35j. The four average value calculation circuits 35m calculate moving average values for the same input signal, and the calculation results are the same. The four threshold setting circuits 35e also obtain correlation thresholds with the same algorithm based on the same calculated moving average value.

  The average value calculation circuit 35m calculates a moving average value of the input signal, specifically, a signal input to the synchronization establishment circuit 35 as a baseband signal and detected by the detection circuit 35a. The average value calculation circuit 35m is provided in each calculation circuit 35j. The average value calculation circuit 35m may be shared by the four calculation circuits 35j.

  For example, the threshold setting circuit 35e decreases the correlation threshold continuously or stepwise when the calculated moving average value decreases, and increases the correlation threshold continuously or stepwise when the moving average value increases. When the moving average value becomes lower than the predetermined value, the threshold value setting circuit 35e may maintain the correlation threshold value at a specific value without lowering the correlation threshold value in order to make erroneous synchronization less likely to occur.

  FIG. 16 shows a procedure of synchronization processing by the synchronization system of this modification. The synchronization process is the same as the process of the third modification shown in FIG. 12, except that the process of S61 is added between the processes of S3 and S31, and the process of S6 is changed to the processes of S62 and S63. The other processes are the same. In the synchronization process, the average value calculation circuit 35m calculates the moving average value of the baseband signal detected in the process of S3 (S61). Then, the threshold setting circuit 35e sets a correlation threshold based on the calculated moving average value (S62). Thereafter, in the four calculation circuits 35j, the comparison circuit 35f compares the set correlation threshold value with the correlation value calculated by the calculation circuit 35d, whereby the correlation threshold value and each sampling timing (0) to (3). The correlation values (see FIG. 3) are compared in parallel (S63).

  In this modification, even if the level of the input signal fluctuates significantly due to a change in the communication environment or the like, the correlation threshold calculated based on the moving average value of the input signal is linked to the fluctuation. Therefore, the symbol synchronization establishment based on the comparison result between the correlation value and the correlation threshold corresponds to the communication environment change or the like. Therefore, it is possible to establish stable symbol synchronization, and thus stable frame synchronization. In addition, the circuit necessary for dealing with the level fluctuation of the input signal is not a circuit having a complicated configuration like the normalization circuit 37 of the fourth modified example, but calculates a moving average value of the detected baseband signal. Since only the average calculation circuit is required, the scale can be reduced as compared with the fourth modification.

(Sixth Modification)
FIG. 17 shows a configuration of a communication system according to a sixth modification. The synchronization establishment circuit 35 of the communication system 1 is obtained by adding a first counter 35n to the configuration of the third modification shown in FIG.

  The transmission apparatus 2 transmits a signal having the configuration shown in FIG. The transmission device 2 periodically transmits the frame 21. Each frame 21 includes a unique word 22. The frame length of the frame 21 is set in advance.

  The synchronization detection circuit 35g causes the first counter 35n to count the elapsed time from when the last symbol of the unique word 22 is detected. When detecting the symbol synchronization timing and the frame synchronization timing, the synchronization detection circuit 35g considers that the last symbol of the unique word 22 has been detected. The synchronization detection circuit 35g prevents erroneous synchronization while the count time by the first counter 35n is within a known period from when the last symbol of the unique word 22 is detected to when the next unique word 22 is input. The synchronization detection operation is stopped. This synchronization detection operation is an operation for detecting symbol synchronization timing and frame synchronization timing. By stopping the synchronization detection operation, the synchronization establishment operation of the synchronization setting circuit 35h is stopped. The synchronization detection circuit 35g detects the time when the last symbol of the first unique word 22 is detected after power-on based on the detection of the symbol synchronization timing and the frame synchronization timing, and using the detection as a trigger, the first counter 35n The above operation is started. Hereinafter, the known period is referred to as a synchronization detection prohibition period, and the input period (length) of the unique word 22 in which synchronization detection is possible is referred to as a synchronization detection permission period.

  FIG. 19 shows the procedure of the synchronization processing by the synchronization system of this modification, and FIG. 20 shows the synchronization detection prohibition period and the synchronization detection permission period in the synchronization system. As shown in FIG. 20, the synchronization detection prohibition period is a known period from when the unique word 22 is received until the beginning of the next unique word 22 is received. Here, the count value when the time is counted by the first counter 35n is A. A time count value of a period obtained by adding the input period of the unique word 22 to the known period is assumed to be B (B> A). This period is a period obtained by adding the synchronization detection prohibition period and the synchronization detection permission period. In this period, for example, a transmission period of several bits may be added as a margin.

  The synchronization process of this modification (see FIG. 19) is the same as the process of the fifth modification shown in FIG. 16 except that the processes of S71 to S76 are added after the process of S10. Is. The illustration of the processes before S10 is omitted. In the synchronous processing, when the processing up to S10 is executed for the first time based on the first unique word 22 after power-on, the first counter 35n once resets the count value as a trigger (S71), Counting is started (S72). While the count value is not less than A and not more than B (Yes in S73; synchronization detection permission period in FIG. 20), the synchronization detection circuit 35g executes synchronization detection processing. It is assumed that symbol synchronization timing and frame synchronization timing are detected in the synchronization detection process (Yes in S74). That is, assume that the last symbol of the unique word 22 is detected. At this time, the synchronization setting circuit 35h sets the detected symbol synchronization timing and frame synchronization timing to the symbol synchronization timing and frame synchronization timing of the baseband signal detected by the detection circuit 35a (S75), and the process goes to S71. Return. If the symbol synchronization timing and the frame synchronization timing are not detected while the count value is not less than A and not more than B (No in S74), the process returns to S73.

  While the count value is less than A (No in S73, No in S76; synchronization detection prohibition period in FIG. 20), the synchronization detection circuit 35g stops the synchronization detection process, the process returns to S73, and the count is continued. . If the count value is greater than B (No in S73, Yes in S76), the process returns to S71.

  In this modification, synchronization is not established based on received signals other than the unique word 22. Therefore, even if a signal that coincides with or approximates to the unique word 22 is accidentally generated between the reception of the unique word 22 and the reception of the next unique word 22, synchronization is not established based on the signal. Therefore, erroneous synchronization can be prevented and occurrence of synchronization errors can be suppressed.

(Seventh Modification)
The communication system according to the seventh modification is configured to solve the problems of the sixth modification. First, the problem will be described with reference to FIG. FIG. 21 shows a synchronization detection prohibition period and a synchronization detection permission period that deviate from the regular timing in the synchronization system of the sixth modified example. As shown in the figure, for example, when the first unique word 22 after power-on does not establish synchronization and the synchronization is erroneously established by data or noise before receiving the next unique word 22, as shown in FIG. Etc. In the sixth modification, the synchronization detection prohibition period and the synchronization detection permission are triggered by the establishment of synchronization in the first unique word 22 after power-on, regardless of whether synchronization is established at regular timing or not. The period is repeated at regular intervals. Therefore, if synchronization is not first established at regular timing as described above, the synchronization detection prohibition period and the synchronization detection permission period are repeated at incorrect timing. For example, the unique word 22 is received during the synchronization detection prohibition period and the communication data 23 is received during the synchronization detection permission period, and synchronization cannot be established indefinitely.

  Therefore, FIG. 22 shows a configuration of a communication system according to a seventh modification that can solve this problem. The configuration of the synchronization establishing circuit 35 of the communication system 1 is obtained by adding a second counter 35o to the configuration of the sixth modified example. As in the sixth modification example, the transmission device 2 of this modification example periodically transmits the frame 21 (see FIG. 20), and the synchronization detection circuit 35g detects the last symbol of the unique word 22. The second counter 35o is made to count the elapsed time from the time when it was performed. The maximum count time, that is, the maximum countable period is set longer than the sum of the synchronization detection prohibition period (known period) and the synchronization detection permission period (unique word 22 input period). For example, the maximum count time is an integral multiple of the total period. When the count time of the second counter 35o reaches the maximum count time, the synchronization detection circuit 35g fixes the count value of the first counter 35n to A, forcibly turns off the synchronization establishment stop function, and thereafter The period is a synchronization detection permission period.

  FIG. 23 shows the procedure of the synchronization processing by the synchronization system of this modification, and FIG. 24 shows the synchronization detection prohibition period and the synchronization detection permission period in the synchronization system. In the synchronization process of this modification, the processes of S81 to S85 are added after the process of S10 in the process of the fifth modification shown in FIG. 16, and the other processes are the same. The illustration of the processes before S10 is omitted.

  In the synchronous process, when the process up to S10 is executed for the first time based on the unique word after the power is turned on, the second counter 35o starts the operation and counts the time (S81). While the count value by the second counter 35o is less than the maximum count time C (C> B) (Yes in S82) and the synchronization timing is not detected (No in S83), the process of S81 is continued and the count continues. On the other hand, when the synchronization timing is detected while the count value is less than the maximum count time C (Yes in S83), the synchronization detection circuit 35g resets the count value of the second counter (S84), and the process is S81. Return to.

  When the count value by the second counter 35o exceeds the maximum count time C (No in S82), the synchronization detection circuit 35g fixes the count value of the first counter to A (S85). Accordingly, the synchronization detection circuit 35g sets the subsequent time as the synchronization detection permission period.

  In this modification, even if synchronization is first established at an incorrect timing after the power is turned on in the sixth modification, the subsequent synchronization detection prohibition period is eliminated. For this reason, the synchronization detection prohibition period deviated from the regular timing does not overlap with the timing of receiving the unique word 22 that should originally establish synchronization. Therefore, it is possible to recover to a state in which synchronization can be established, and to improve reliability. Moreover, recovery can be facilitated.

(Eighth modification)
FIG. 25 shows a configuration of a communication system according to an eighth modification. The synchronization establishment circuit 35 of the communication system 1 has a configuration in which a timing setting circuit (hereinafter referred to as a setting circuit) 35p (timing setting unit) is added to the configuration of the embodiment shown in FIG. The setting circuit 35p operates in relation to a signal transmitted from the transmission device 2 of the present modification.

  The transmission apparatus 2 transmits a signal having the configuration shown in FIG. The transmission device 2 inserts unique words 22 into the frame 21 by the number of sampling timings (0) to (3) (see FIG. 3) per frame 21, and transmits these unique words 22 continuously. If the number of sampling timings per symbol Sb is n (n: an integer of 2 or more), n unique words 22 are inserted into one frame 21.

  The setting circuit 35p sequentially switches the sampling timing for extracting the sample value by the extraction circuit 35b among the sampling timings (0) to (3) for each unique word 22 length. This length is a period required for transmission of one unique word 22. The setting circuit 35p switches the sampling timing for calculating the correlation value by the calculation circuit 35d for each of the lengths.

  FIG. 27 shows a procedure of synchronization processing by the synchronization system of the present modification. The synchronization process is the same as the process of the above embodiment shown in FIG. 4 except that the process of S91 is added before the process of S1, the processes of S4 to S7 are changed to the processes of S92 to S95, respectively, and S9 The processes of S96 and S97 are added after the above process.

  The setting circuit 35p sets the sampling timing as a variable i and sets i = 0 (S91). The extraction circuit 35b sequentially extracts an N-bit sample value sequence at the sampling timing (i) (S92). The calculation circuit 35d calculates a correlation value between the sample value sequence extracted at the sampling timing (i) and the ideal unique word 22 (S93). The comparison circuit 35f compares the correlation value at the sampling timing (i) with the correlation threshold value (S94), and if the correlation value is equal to or greater than the correlation threshold value (Yes in S95), the process proceeds to S9. On the other hand, if the correlation value is less than the correlation threshold (No in S95) and the variable i is 2 or less (Yes in S96), the setting circuit 35p increments the variable i (S97), and the process proceeds to S1. Return. If the variable i becomes 3, the process returns to S91 and the variable i is cleared to zero. When the number of sampling timings is n, when the variable i is (n−2) or less, the process of S97 is executed. Thereafter, the process returns to S1, and when the variable i becomes (n−1), the process is Return to S91.

  In this modification, sample value sequences having different sampling timings (0) to (3) can be extracted from the unique words 22 received in the same number as the sampling timings (0) to (3), respectively. Accordingly, it is not necessary to provide as many calculation circuits 35d as the number of sampling timings to calculate the correlation value necessary for establishing synchronization from the extracted sample value sequence. Therefore, the circuit scale can be reduced and the manufacturing cost can be reduced.

(Ninth Modification)
The communication system according to the ninth modification has the same components as those of the eighth modification shown in FIG. 26, and the configuration of the communication system according to this modification will be described with reference to FIG.

  FIG. 28 shows a configuration of a signal transmitted from the transmission apparatus 2 of the present modification. The transmission device 2 inserts the unique word 22 per frame 21 into the frame 21 by m (m: integer, for example, 2) times the number of sampling timings (0) to (3) (see FIG. 3). The unique word 22 is transmitted continuously.

  The setting circuit 35p of the present modification sequentially switches the sampling timing at which the sample value is extracted by the extraction circuit 35b among the sampling timings (0) to (3) every m times the length of one unique word 22. The setting circuit 35p switches the sampling timing for calculating the correlation value by the calculation circuit 35d for each of the lengths.

  In the present modification, as in the eighth modification, an effect of reducing the circuit scale and reducing the manufacturing cost can be obtained. Furthermore, as shown in FIG. 29, even if the reception timing of the unique word 22 is shifted, at least one unique word 22 can be reliably detected at each sampling timing. Therefore, the accuracy of establishment of synchronization can be improved.

  In addition, this invention is not limited to the structure of the said embodiment and various modifications, A various deformation | transformation is possible according to the intended purpose. For example, any characteristic configuration of the above-described various modifications may be combined with any other configuration.

DESCRIPTION OF SYMBOLS 1 Communication system 2 Transmission apparatus 23 Frame 3 Reception apparatus 31 Reception circuit (reception part, down-conversion part)
32 Synchronization system (synchronization unit)
33 AD converter circuit (oversampling unit)
35 Synchronization establishment circuit (synchronization establishment unit)
35a Detection circuit (detection unit)
35k correlation value extraction circuit (correlation value extraction unit)
35l Maximum correlation value extraction circuit (maximum correlation value extraction unit)
35m average value calculation circuit (average value calculation unit)
35n First counter 35o Second counter 35p Timing setting circuit (timing setting unit)
37 Normalization circuit (normalization part)

Claims (14)

  A baseband signal is sampled and detected at a plurality of sampling timings per symbol, and a correlation value between a sample value sequence of the baseband signal and a predetermined bit sequence for synchronization is detected at each sampling timing. A synchronization system that calculates and establishes symbol synchronization and frame synchronization based on the calculated correlation value.   The baseband signal is sampled at a plurality of sampling timings per symbol and is quantized with M (M: integer of 2 or more) bits, and the sample value sequence quantized by the oversampling unit is detected. The detection unit and the sample value sequence detected by the detection unit are used as they are without replacing the quantized sample value with a binary value, and the sample value sequence of the plurality of sampling timings and a predetermined synchronization are used. The synchronization establishment part which calculates a correlation value with a bit sequence for every time of sampling timing, and establishes symbol synchronization and frame synchronization based on the calculated correlation value is provided. Synchronous system.   If the calculated correlation value is equal to or greater than the correlation threshold, the synchronization establishing unit sets the sampling timing of the correlation value as the symbol synchronization timing, and sets the timing when the correlation value is equal to or greater than the correlation threshold as the frame synchronization timing. The synchronization system according to claim 2, wherein the synchronization system is set.   4. The synchronization system according to claim 2, wherein the synchronization establishment unit calculates the correlation value for sample value sequences of all sampling timings among the plurality of sampling timings. 5.   The synchronization establishment unit includes a correlation value extraction unit that extracts a correlation value that is equal to or greater than the correlation threshold, and a maximum correlation value extraction unit that extracts a maximum correlation value from the extracted correlation values. 4. The synchronization system according to claim 3, wherein the sampling timing of the extracted maximum correlation value is set as symbol synchronization timing, and the timing when the correlation value becomes the maximum correlation value is set as frame synchronization timing.   The synchronization system according to claim 2, further comprising a normalization unit that normalizes a level of an input signal input to the synchronization system.   The synchronization establishment unit includes an average value calculation unit that calculates a moving average value of an input signal input to the synchronization system, and sets the correlation threshold based on the calculated moving average value. The synchronization system according to claim 3 or 5.   A receiving device comprising the synchronization system according to any one of claims 2 to 7. A receiving device according to claim 8;
A transmitter for transmitting an RF signal obtained by up-converting a baseband signal to the receiver;
The receiving device further includes a receiving unit that receives an RF signal transmitted from the transmitting device, and a down-converting unit that obtains a baseband signal by down-converting the RF signal received by the receiving unit. A featured communication system. The transmitter periodically transmits a unique word that is the synchronization bit string,
The synchronization establishing unit has a first counter that counts an elapsed time from when the last symbol of the unique word is detected, and the count time by the first counter is detected by the last symbol of the unique word 10. The communication system according to claim 9, wherein the symbol synchronization and frame synchronization establishment operation is stopped during a known period from the time when the next unique word is input until the next unique word is input.   The synchronization establishment unit counts an elapsed time from when the last symbol of the unique word is detected, and sets a maximum count time longer than a sum of the known period and the length of the unique word. The communication system according to claim 10, further comprising a counter, wherein the synchronization establishment stop function is forcibly turned off when a count time by the second counter reaches the maximum count time. The transmitter continuously transmits a unique word that is the synchronization bit string by m (m: integer) times the number of the sampling timings,
The communication system according to claim 9, wherein the synchronization system further includes a timing setting unit that switches a sampling timing for calculating the correlation value every m times the length of one unique word.   A baseband signal is sampled and detected at a plurality of sampling timings per symbol, and a correlation value between a sample value sequence of the baseband signal and a predetermined bit sequence for synchronization is detected at each sampling timing. A synchronization method characterized by calculating and establishing symbol synchronization and frame synchronization based on the calculated correlation value. An oversampling step of oversampling the baseband signal at a plurality of sampling timings per symbol and quantizing with M (M: an integer of 2 or more) bits;
A detection step of detecting the sample value sequence quantized by the oversampling step;
For the sample value sequence detected by the detection step, the quantized sample value is used as it is without replacing it with a binary value, and the sample value sequence of the plurality of sampling timings and a predetermined synchronization bit sequence are used. The synchronization method according to claim 13, further comprising: a synchronization establishing step of calculating a correlation value at each sampling timing and establishing symbol synchronization and frame synchronization based on the calculated correlation value.

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