JP2014067866A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve a problem that when a main tungsten film is formed after forming a tungsten nucleus on a barrier film containing titanium nitride and being subjected to a soak treatment by diborane, delamination defect occurs at a contact interface between the titanium nitride and a base thereof or a contact interface between the titanium nitride and the tungsten film thereby to deteriorate manufacturing yield.SOLUTION: In a semiconductor device manufacturing method, a titanium nitride-containing barrier film is subjected to a plasma treatment in an atmosphere including argon, hydrogen and ammonia before forming a tungsten nucleus thereby to improve a barrier property by desorption of an impurity in the barrier film; and inhibit deterioration in adhesion of the barrier film to the base to improve adhesion between the barrier film and the tungsten film.

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of forming tungsten on a titanium nitride barrier film by a CVD method.

  In a semiconductor device such as a DRAM, the active region of a memory cell is formed in a line pattern along with miniaturization, and a trench extending in a direction crossing the active region is formed in a substrate, and a word line ( A transistor array with a buried word line structure in which a gate is buried is employed. In F63 and F45 generation DRAMs, the trench widths are about 65 nm and 45 nm, respectively.

  The buried word line is formed by forming a silicon nitride (SiN) film serving as a hard mask on the surface of a semiconductor (silicon) substrate, patterning, and then forming a trench structure by dry etching. An exposed semiconductor (silicon) substrate surface in the trench is thermally oxidized by an in-situ steam generation (ISSG) method to form a silicon oxide film that becomes a gate insulating film, and then a barrier film is formed using titanium nitride (TiN) or the like. Then, tungsten (W) to be a main conductor is formed. For the deposition of TiN and W, a CVD method with good step coverage is adopted. The formed TiN film and W film are etched back so that the surface thereof is lower than the substrate surface, preferably lower than the diffusion layer formed on the substrate surface. Thereafter, a silicon oxide film or the like is formed on the surfaces of the receded TiN film and W film, and planarized by CMP or the like to form a cap insulating film, thereby completing a buried word line. Such a buried word line structure is shown in Patent Document 1, for example.

JP 2012-19035 A

As shown in the background art, W-CVD is used to bury tungsten (W) in a bulk structure in a stepped structure such as a trench for a buried word line. This W-CVD includes a nucleation step and a main film formation step, and SiH ₄ or B ₂ H ₆ is used as a nucleation gas. In particular, after F38, the trench width has been reduced to 32 nm, and the demand for reducing the W bulk resistance has become more severe. In this respect, B ₂ H ₆ is expected because it can reduce the bulk resistance by nearly 50%.

  However, according to the study by the present inventors, when the W-CVD condition for reducing the bulk resistance is applied to the TiN film as the barrier film, the adhesion with the underlying gate insulating film is lowered, and the TiN film It was confirmed that the interface between the gate insulating film and the gate insulating film peeled off to form a defective portion.

  This problem is not limited to the formation of the buried word line, and when a TiN film is formed as a barrier film and W is formed thereon under the above CVD conditions, the adhesion between the TiN film and the base film is reduced. ing.

According to one embodiment of the present invention,
Forming a barrier film containing titanium nitride;
Forming a tungsten nucleus on the titanium nitride by a CVD method using silane or diborane gas and a tungsten compound;
Forming a tungsten film by a CVD method using the tungsten nucleus;
A method for manufacturing a semiconductor device comprising:
Before the step of forming the tungsten nucleus, the barrier film containing titanium nitride is subjected to plasma treatment in an atmosphere containing argon, hydrogen, and ammonia,
Is provided.

  According to one embodiment of the present invention, the barrier property including titanium nitride is plasma-treated before the tungsten nuclei are formed, whereby impurities in the barrier film are removed and the density is increased, thereby improving the barrier property. Further, it is possible to reduce damage due to the source gas used during the growth of the tungsten film and suppress deterioration of adhesion. Furthermore, since the stress of the titanium nitride film is relieved by the addition of plasma treatment, it contributes to improving the adhesion between the barrier film and the tungsten film. In addition, the specific resistance of the barrier film is reduced by removing impurities in the film by the plasma treatment.

1A and 1B are diagrams illustrating a semiconductor device according to an embodiment of the present invention, where FIG. 1A is a plan view and FIG. 1B is a cross-sectional view taken along line A-A ′ in FIG. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view and (b) shows a sectional view in the A-A 'line of (a). It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view, (b) is a sectional view in an AA 'line of (a), (c) is. Sectional drawing in the BB 'line | wire of (a) is shown. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view and (b) shows a sectional view in the A-A 'line of (a). It is a figure explaining the subject of the formation process of the embedded gate electrode used as a prior art example, (a) is a process flow figure, (b) is an expanded sectional view of the broken-line part P1 of FIG.4 (b). It is a figure explaining the formation process of the embedded gate electrode by this invention, (a) is a process flowchart, (b) is an expanded sectional view of the broken-line part P1 of FIG.4 (b). It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view, (b) is a sectional view in an AA 'line of (a), (c) is. Sectional drawing in the BB 'line | wire of (a) is shown. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view and (b) shows a sectional view in the A-A 'line of (a). It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view and (b) shows a sectional view in the A-A 'line of (a). It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view and (b) shows a sectional view in the A-A 'line of (a). It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view and (b) shows a sectional view in the A-A 'line of (a). It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view and (b) shows a sectional view in the A-A 'line of (a). It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view, (b) is a sectional view in an AA 'line of (a), (c) is. The enlarged view of the broken-line part P2 of (b) is shown. It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view and (b) shows a sectional view in the A-A 'line of (a). It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view and (b) shows a sectional view in the A-A 'line of (a). It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view and (b) shows a sectional view in the A-A 'line of (a). It is a figure explaining the manufacturing process of the semiconductor device concerning one example of an embodiment of the present invention, (a) is a top view and (b) shows a sectional view in the A-A 'line of (a).

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to these embodiments.

(Example 1)
First, with reference to the plan view of FIG. 1A, the arrangement of the main part of the semiconductor device of this embodiment will be described. In FIG. 1A, the structure of the capacity portion is omitted. A peripheral circuit area PFA exists on the semiconductor substrate 1 and around the memory cell area MCA. In FIG. 1A, the memory cell area MCA and the peripheral circuit area PFA are adjacent to each other in the X direction.

  In the memory cell region MCA, an element isolation region 2 extending in a straight line in the X ′ direction having an inclination in the X direction, and an active region 1 a extending in a straight line in the X ′ direction adjacent to the element isolation region 2 are provided. It is repeatedly arranged in the Y direction at equal pitch intervals. The active region 1a is electrically isolated in the Y direction by the element isolation region 2. A buried word line (hereinafter referred to as word line) 3 and a buried dummy word line (hereinafter referred to as dummy word line) 3 ′ extending in a straight line in the Y direction are arranged across the plurality of element isolation regions 2 and the plurality of active regions 1a. Has been. Although a part of the configuration is omitted in the figure, two word lines 3 are arranged at equal intervals between two adjacent dummy word lines 3 '. That is, the dummy word lines 3 ′ and the word lines 3 are arranged with the same width and interval. The dummy word line 3 ′ is formed in the same configuration as the word line 3, but each word line 3 functions as a gate electrode of a corresponding transistor, whereas the dummy word line 3 ′ is a dummy word line 3 ′. Have an element isolation function for electrically isolating adjacent transistors on both sides. As a result, the active region 1a is insulated and isolated by the element isolation region 2 in the Y direction, and is isolated by the dummy word line 3 'in the extending X' direction to form an independent island-like active region. Here, for ease of explanation, the adjacent dummy word lines 3 are 3′-1, 3′-2 in the X direction, and the word lines 3 are 3-1, 3-2 in the X direction. Call it. One island-like active region extending in the X ′ direction is sandwiched between the dummy word line 3′-1 and the dummy word line 3′-2, and is further connected to the dummy word line 3′-1 and the word line 3-1. Adjacent capacitor contact connection region 1b, bit line contact connection region 1c adjacent to word line 3-1 and word line 3-2, and the other capacitor adjacent to word line 3-2 and dummy word line 3′-2. And a contact connection region 1b. One capacitor contact connection region 1b, one word line 3, and bit line contact connection region 1c constitute one transistor Tr1A. The bit line contact connection region 1c, the other word line 3, and the other capacitor contact connection region 1b constitute another transistor Tr1B. Therefore, the bit line contact connection region 1c is configured to be shared by the two transistors Tr1A and Tr1B. A bit line contact 5c is provided on each bit line contact connection region 1c, and a bit line gate 5 (hereinafter referred to as BLG 5) extending in the X direction is connected to each bit line contact 5c. A capacitor contact 7 is provided on each capacitor contact connection region 1b, and a capacitor (not shown) is provided on each capacitor contact 7. On the other hand, in the peripheral circuit region PFA, an element isolation region 2 is arranged so as to divide the active region 1a into a plurality of island-like regions that are long in the X direction. The longitudinal direction and number of the active regions 1a are not limited to this. BLG 5 is disposed almost directly above the center of active region 1a via a gate insulating film. In FIG. 1a, the BLG 5 extends in the Y direction through the center of a plurality of active regions 1a arranged in the Y direction, but this is not necessarily required.

  Of the active region 1a, a region that is not covered with BLG5, that is, a region divided into two by BLG5 becomes peripheral contact connection region 1d. A peripheral contact 8 is provided on the peripheral contact connection region 1d, and a peripheral wiring is provided on each peripheral contact 7 '.

  Next, reference is made to the cross-sectional view of FIG. Metal word lines 3d are respectively buried in a plurality of word trenches 3b formed on the surface of the semiconductor substrate 1 with the same width and interval through an In-Situ Steam Generation oxide film 3c (hereinafter, ISSG 3c). A cap insulating film 3e is embedded so as to cover the upper surface of the metal word line 3d. The structure formed in each word trench 3b becomes a word line 3 and a dummy word line 3 '. A first interlayer insulating film 4 is provided so as to cover the cap insulating film 3e. On the upper surface of the bit line contact connection region 1c formed of the active region 1a located between two adjacent word lines 3-1 and 3-2, a bit line contact plug 5d-1 penetrating the first interlayer insulating film 4 and A BLG upper layer film 5e-1 connected to the upper surface and extending in the X direction is laminated and formed in the shape of a wiring. A side wall insulating film 5f made of a silicon nitride film is provided on the upper surface and side wall of the BLG upper layer film 5e-1, and the bit line contact plug 5d-1, the BLG upper layer film 5e-2, and the side wall insulating film 5f serve as a memory cell region. MCR BLG5-1 is formed.

  On the other hand, in the peripheral circuit region PFA, a gate insulating film 5a and a metal gate 5b made of an oxide film, a high dielectric constant film (Hi-K film) or a laminated film of Hi-K films are directly above the central portion of the active region 1a. And a BLG lower layer film 5d-2 and a BLG upper layer film 5e-2 are sequentially stacked to form a wiring shape, and a sidewall insulating film 5f made of a silicon nitride film is provided on the upper surface and side walls thereof, and the peripheral circuit region PFA BLG5-2.

  A second interlayer insulating film 6 made of a silicon oxide film is provided on the entire surface so as to cover BLG5-1 in the memory cell region MCR and BLG5-2 in the peripheral circuit region PFA. A capacitor contact plug 7 is connected to the upper surface of the active region 1 a serving as the capacitor contact connection region 1 b through the second interlayer insulating film 6 and the first interlayer insulating film 4. A wiring contact plug 8 is connected to the upper surface of the active region 1a to be the peripheral contact connection region 1d through the second interlayer insulating film 6 and the first interlayer insulating film 4. A peripheral circuit wiring 9 is connected to the upper surface of the wiring contact plug 8. A stopper film 10 made of a silicon nitride film and a third interlayer insulating film 11 made of a silicon oxide film are provided on the entire surface including the upper surfaces of the capacitor contact plug 7 and the peripheral circuit wiring 9.

  A cylinder hole 12a penetrating the third interlayer insulating film 11 and the stopper film 10 is opened so as to reach the upper surface of the capacitor contact plug 7, and a lower electrode 12b is provided so as to cover the inside and bottom of the cylinder hole. As a result, the lower electrode 12b is connected to the upper surface of the capacitor contact plug 7. A capacitor insulating film 12c and an upper electrode 12d are provided so as to cover the lower electrode surface 12b, and the capacitor 12 is constituted by the lower electrode 12b, the capacitor insulating film 12c, and the upper electrode 12d. A fourth interlayer insulating film 13 is provided so as to cover the capacitor 12. A wiring contact 14 penetrating the fourth interlayer insulating film 13 is provided, and a wiring layer 15 is connected to the upper surface of the wiring contact 14. A protective insulating film 16 is provided on the entire surface so as to cover the wiring 15.

Next, the manufacturing method of this invention is demonstrated with reference to drawings.
First, as shown in FIG. 2, the active region 1 a is partitioned by forming STI 2 on the semiconductor substrate 1. 2 (a) is a plan view corresponding to FIG. 1 (a), and FIG. 2 (b) shows an AA ′ cross section of FIG. 2 (a).

  Next, as shown in FIG. 3, a hard mask 3a is formed on the semiconductor substrate 1 and etched to form a word trench 3b and a dummy word trench 3b '. The semiconductor substrate 1 exposed in the word trench 3b and the dummy word trench 3b 'is oxidized by ISSG to form a gate insulating film 3c. The gate insulating film 3c is preferably about 5 nm. 3A is a plan view corresponding to FIG. 1A, FIG. 3B is a cross-sectional view taken along the line AA ′ of FIG. 3A, and FIG. 3C is a cross-sectional view taken along line BB of FIG. 'Show cross section. Here, the saddle portion 1b is formed as shown in FIG. 3C by forming the semiconductor substrate 1 so as to be smaller than the etching amount of the STI 2.

  Subsequently, as shown in FIG. 4, a conductive film is formed in the word trench 3b and the dummy word trench 3b '. The conductive film 3d sequentially forms a barrier film 3d-1, which is TiN, a tungsten seed layer 3d-2, and a tungsten layer 3d-3. 4A is a plan view corresponding to FIG. 1A, and FIG. 4B is a cross-sectional view taken along the line A-A ′ of FIG.

Here, problems of the background art will be described with reference to FIG. FIG. 5A shows a conventional flow sheet for forming a conductive film 3d. After the ISSG treatment shown in FIG. 3, a barrier film 3d-1, which is TiN, a tungsten seed layer 3d-2, and a tungsten layer 3d-3 are formed in this order. Here, the tungsten seed layer 3d-2 and the tungsten layer 3d-3 are realized as each film forming step in one process. Specifically, the barrier film 3d-1 is TiN, at a thermal CVD method, 650 ° C., at 267 Pa (2 Torr), and the step of forming at TiCl ₄ and NH ₃ by 1 nm, Cl withdrawal in NH ₃ The step of performing is repeated to form a film of 5 nm. The tungsten seed layer 3d-2 reduces the WF ₆ gas with SiH ₄ or B ₂ H ₆ to form tungsten (W) nuclei, and grows the tungsten layer 3d-3 based on the W nuclei. . Here, a 4 nm seed layer 3d-2 is formed, and then a 56 nm W layer 3d-3 is grown (the total thickness of W is 60 nm).

Here, when gas infiltration (soak) is performed with B ₂ H ₆ after forming the W nucleus, the bulk resistance can be reduced. Specifically, the soaking changes the film quality of the nucleation film (underlying) and changes the orientation of the main W layer 3d-3, thereby increasing the grain size of the W layer 3d-3 and increasing the resistance. To reduce. However, after the formation of the W layer 3d-3, a peeling defect D may occur between the gate insulating film 3c and the barrier film 3d-1 due to film stress (see FIG. 5B). The exfoliation defect D appears more markedly in the B ₂ H ₆ reduction than in the SiH ₄ reduction. Further, boron (B) leakage may occur in the B ₂ H ₆ reduction. Here, boron leakage means that boron remaining in the W film passes through the gate insulating film 3c and the barrier film 3d-1, diffuses into the Si substrate, and affects the characteristics of the transistor.

If the soak treatment is omitted so that the peeling defect D does not occur, for example, the specific resistance of 60 nm tungsten is 30.6 μΩcm in SiH ₄ reduction (Comparative Example 1) and 18 in B ₂ H ₆ reduction (Comparative Example 2). It was 5 μΩcm.

Next, the solution means by this invention is demonstrated. FIG. 6A shows a flow sheet for forming a conductive film 3d according to the present invention. After the ISSG treatment shown in FIG. 3, a barrier film 3d-1 that is TiN is formed, and the adhesion between the gate insulating film 3c and the barrier film 3d-1 is improved by plasma treatment (Ar / H ₂ / NH ₃ ). Let Specifically, plasma processing is performed under the following processing conditions using a parallel plate type plasma processing apparatus.

Ar = 1200-1900 sccm
H ₂ = 1600~2200sccm
NH ₃ = 1200~1900sccm
RF power = 300 ~ 800W
(RF power is adjusted by the influence of plasma damage)
The processing device may be a remote type. Next, the nucleation W3d-2 and the main W3d-3, which are W, are formed in this order.

During this nucleation is reduced with SiH _4, B 2 _{H 6} was reduced when performing soak in Example _1, B 2 _{H 6,} it is referred to as Example 2 when performing B 2 _{H 6} soak.

By adding the plasma treatment (Ar / H ₂ / NH ₃ ) in this way, peeling between the ISSG 3c and the barrier film 3d-1 can be reduced. Further, in Example 1, the nucleation W3d-2 (SiH ₄ W nucleation layer) prevents B penetration, and B leakage hardly occurs. In the case of Example 2, the specific resistance of the 60 nm tungsten layer was 14.6 μΩcm, which was confirmed to be lower than that of Comparative Example 2.

  Next, as shown in FIGS. 7A and 7B, the barrier film 3d-1, the seed layer 3d-2, and the W layer 3d-3 are etched to about ½ from the bottom of the word trench 3b. The word line 3 and the dummy word line 3 ′ are formed.

  Next, as shown in FIGS. 8A and 8B, a cap insulating film 3e that is an oxide film is formed on the entire surface of the semiconductor substrate 1 by CVD, and the mask nitride film 3a is used as a stop film by CMP. Flatten. Thereafter, the mask nitride film 3a may be removed here.

  Next, as shown in FIGS. 9A and 9B, a first interlayer insulating film 4 that is an oxide film is formed on the entire surface of the semiconductor substrate 1 by CVD and planarized by CMP. The first interlayer insulating film 4 and the mask nitride film 3a in the peripheral circuit region PFA are removed by lithography and dry etching.

  Next, as shown in FIGS. 10A and 10B, after the gate insulating film 5a and the metal gate 5b are formed on the entire surface of the semiconductor substrate 1, the gate insulation of the peripheral circuit region PFA is performed by lithography and dry etching. Only the film 5a and the metal gate 5b are left.

  Next, as shown in FIGS. 11A and 11B, a bit contact hole 5c is opened by lithography and dry etching. Next, as shown in FIGS. 12A and 12B, a BLG underlayer film / bit contact plug 5d made of P-doped polysilicon is formed on the entire surface of the semiconductor substrate 1 including the inside of the bit contact hole 5c. And planarized by CMP.

Next, as shown in FIG. 13A, FIG. 13B, and FIG. 13C, a barrier film 5e-1 that is TiN is formed, and plasma treatment (Ar / H ₂ / NH ₃ ) is performed. The adhesion between the BLG underlayer film / bit contact plug 5d and the barrier film 5e-1 is improved.

Next, the nucleation W5e-2 and the main W5e-3 which are W are formed in this order to form the BLG upper layer film 5e. Further, a cap insulating film 5f is formed. FIG.13 (c) shows the enlarged view of P2 part of FIG.13 (b). This during nucleation, a and Example 4 When performing reduced _B 2 _{H 6} soak in Example _3, B 2 _{H 6} the case of a reduced _B 2 _{H 6} soak in SiH _4. By adding the plasma treatment (Ar / H ₂ / NH ₃ ) in this way, peeling between the BLG underlayer film / bit contact plug 5d and the barrier film 5e-1 can be reduced.

  Next, as shown in FIGS. 14A and 14B, the cap insulating film 5f, the BLG upper layer film 5e, the BLG lower layer film / bit contact plug 5d, the metal gate 5b, and the gate insulating film are formed by lithography and dry etching. 5a is etched into the pattern of the bit line gate 5A and the bit line 5B, and then, as shown in FIGS. 15A and 15B, the whole is covered with a sidewall insulating film 6a made of a nitride film or an oxide film. . Here, the sidewall insulating film 6a may be etched back so as to expose the cap insulating film 5f on the BLG upper layer film 5e so as to cover only the side surfaces of the bit line gate 5A and the bit line 5B. Next, the second interlayer insulating film 6b is formed thick on the entire surface of the semiconductor substrate 1 so as to bury the bit line gate 5A and the bit line 5B, and is flattened by CMP. The second interlayer insulating film 6b is preferably an oxide film by CVD, but may be an SOD film. In the case of the SOD film, after applying the SOD, a heat treatment is applied to modify it to form a solid SOD film.

  Next, as shown in FIGS. 17A and 17B, the capacitor contact connection region and the peripheral contact are located at positions corresponding to the capacitor contact connection region and the peripheral contact connection region of the second interlayer insulating film 6 by lithography and dry etching. An opening reaching the connection region is formed and buried with a conductive material to form the capacitor contact 7 and the peripheral contact 8.

  Next, as shown in FIG. 1, a wiring film is formed on the entire surface of the semiconductor substrate 1, and peripheral circuit wiring 9 is formed by lithography and dry etching. Next, a stopper film 10 made of a silicon nitride film and a third interlayer insulating film 11 made of a silicon oxide film are formed on the entire surface of the semiconductor substrate 1 by CVD, and a cylinder hole 12a is opened by lithography and dry etching. Next, TiN is thinly formed on the entire surface of the semiconductor substrate 1 including the bottom and inside of the cylinder hole 12a, and the lower electrode 12b is formed by etching, leaving only the bottom and inside of the cylinder hole 12a. Next, a capacitive insulating film 12c and an upper electrode film 12d are formed in this order on the entire surface of the semiconductor substrate 1 including the inside of the lower electrode 12b, and the capacitive insulating film 12c and the upper electrode film 12d on the memory cell region MCA are formed by lithography and dry etching. Etch so that only remains. Thereby, the capacitor 12 composed of the lower electrode 12b, the capacitive insulating film 12c, and the upper electrode film 12d is formed. Next, a fourth interlayer insulating film 13 is formed by CVD on the entire surface of the semiconductor substrate 1 including the gap portion of the capacitor 12, and the fourth interlayer insulating film 13, the third interlayer insulating film 11, and the stopper film 10 are formed by lithography and dry etching. The wiring contact 14 connected to the peripheral circuit wiring 9 is formed by burying the conductive film and the wiring 15 is formed on the wiring contact 14 so as to be connected to the wiring contact 14. The entire surface is covered with a protective insulating film 16. In this embodiment, the description has been given using the capacitor that uses the inside of the lower electrode as a capacitor. However, other types of capacitors such as a crown type capacitor may be used.

1. Semiconductor substrate 1a. Active region 1b. Capacitance contact connection region 1c. Bit contact connection region 1d. Peripheral contact connection region Element isolation region (STI)
3. Embedded word line (3-1, 3-2)
3a. Mask nitride film 3b. Word trench 3c. In-Situ Steam Generation oxide film (ISSG)
3d. Metal word line 3d-1. Barrier film 3d-2. Nucleation W
3d-3. Main W
3e. Cap insulating film 3 '. Embedded dummy word line (3'-1, 3'-2)
4). First interlayer insulating film (oxide film / nitride film)
5A. Bit line gate (BLG)
5B. Bit line 5a. Gate insulating film 5b. Metal gate 5c. Bit contact hole 5d. BLG underlayer / bit contact plug 5e. BLG upper layer film 5e-1. Barrier film (TiN)
5e-2. Nucleation W
5e-3. Main W
5f. 5. Side wall insulating film Second interlayer insulating film 7. Capacitive contact 8. Peripheral contact 9. Peripheral circuit wiring 10. Stopper film 11. Third interlayer insulating film 12. Capacitor 12a. Cylinder hole 12b. Lower electrode 12c. Capacitance insulating film 12d. Upper electrode 13. Fourth interlayer insulating film 14. Wiring contact 15. Wiring 16. Protective insulating film D. Peeling defect MCA. Memory cell area PFA. Peripheral circuit region Tr1. Cell transistor Tr2. Peripheral transistor

Claims (10)

Forming a barrier film containing titanium nitride;
Forming a tungsten nucleus on the titanium nitride by a CVD method using silane or diborane gas and a tungsten compound;
Forming a tungsten film by a CVD method using the tungsten nucleus;
A method for manufacturing a semiconductor device comprising:
Before the step of forming the tungsten nucleus, the barrier film containing titanium nitride is subjected to plasma treatment in an atmosphere containing argon, hydrogen, and ammonia.   The method of manufacturing a semiconductor device according to claim 1, wherein after the step of forming the tungsten nucleus, a soak process using diborane is performed, and then a tungsten film is formed by a CVD method.   The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming the tungsten film is performed by reducing a tungsten compound in the presence of a reducing agent.   The method for manufacturing a semiconductor device according to claim 3, wherein the reducing agent is silane or diborane gas.   The method for manufacturing a semiconductor device according to claim 1, wherein the tungsten compound contains a fluorine atom.   The method for manufacturing a semiconductor device according to claim 5, wherein the tungsten compound is tungsten hexafluoride.   The method for manufacturing a semiconductor device according to claim 1, wherein the barrier film containing titanium nitride is formed in contact with a silicon oxide film.   8. The method of manufacturing a semiconductor device according to claim 7, wherein the silicon oxide film is a gate silicon oxide film, and the tungsten film is formed as a gate electrode.   The method of manufacturing a semiconductor device according to claim 8, wherein the gate electrode is a buried gate electrode embedded in a semiconductor substrate.   The method for manufacturing a semiconductor device according to claim 1, wherein the barrier film containing titanium nitride is formed in contact with a polysilicon film.