JP2013229723A - Load control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a load control device that prevents generation of radiation/conduction noise and suppresses a variation in duty ratio even if a supply voltage varies across a predetermined value.SOLUTION: A first comparator 7 outputs a normally L level DC signal when a supply voltage VI is not more than a first predetermined value, and if the first predetermined value is exceeded, outputs a first pulse signal with a duty ratio increasing with increasing supply voltage VI. A second pulse signal output circuit 8 outputs a second pulse signal with a constant duty ratio if the supply voltage VI is not less than the first predetermined value, and stops outputting the second pulse signal when the supply voltage VI falls below a second predetermined value lower than the first predetermined value while the second pulse signal is output. An OR gate 9 selects one which has the longer H level period if the firs pulse signal and the second pulse signal are input and selects the second pulse signal if the DC signal and the second pulse signal are input, and uses the selected pulse signal for controlling on/off a FET.

Description

  The present invention relates to a load control device, and more particularly to a load control device that controls a load based on a duty.

  When an abnormality occurs due to a failure of an automobile power generation device or the like, the power supply voltage of a battery generally in the range of 12V to 14.5V may rise to 16V or more. At this time, since the power supply voltage supplied to the load also rises, there is a problem that the effective voltage with respect to the load rises and power is supplied to the load more than necessary. For example, when the effective voltage supplied to the lamp as a load increases, the life of the lamp is shortened, or when the lamp is irradiated with an illuminance that is more than necessary, the irradiated person feels very dazzling.

  Therefore, when the power supply voltage of the battery exceeds a predetermined value, the control of the switch for turning on / off the power supply to the load is switched from the DC signal to the pulse signal, and the duty ratio of the ON period of the switch is lowered as the power supply voltage increases. A load control device that outputs a pulse signal has been considered (Patent Document 1).

  As the load control device described above, for example, a power supply device as shown in FIG. 6 has been proposed. As shown in the figure, a power supply device 1 includes a lamp 2 as a load, a battery 3 as a power source for supplying power to the lamp 2, and a switch provided between the lamp 2 and the battery 3. A field effect transistor (hereinafter abbreviated as “FET”) 4, and a load control device 5 that controls the supply of power supply voltage from the battery 3 to the lamp 2 by controlling on / off of the FET 4.

  The load control device 5 compares a triangular wave generator 6 (periodic signal generator) for generating a triangular wave, a triangular wave VT generated by the triangular wave generator 6 and a voltage Vk1 corresponding to the power supply voltage VI of the power supply 3. 1 comparator 7 and an FET drive circuit 10 that shifts the output V1 of the first comparator 7 to a level at which the FET 4 can be turned on and off.

  According to the configuration described above, when the FET 4 is turned on / off using the output V1 of the first comparator 7, for example, as shown in FIG. 7, the FET 4 is always turned on when the power supply voltage VI is 12V or less (duty ratio 100). %). When the power supply voltage VI exceeds 12V, the FET 4 is intermittently turned on, and thereafter, the duty ratio of the ON period of the FET 4 gradually decreases as the power supply voltage VI rises. As a result, the effective voltage with respect to the lamp 2 can be suppressed even if the power supply voltage VI increases.

  As described above, since the on / off control of the FET 4 is performed using the output V1 from the first comparator 7, when the power supply voltage VI rises above a predetermined value, the duty ratio continuously decreases as the power supply voltage VI rises. For this reason, when the power supply voltage VI is slightly higher than the predetermined voltage, the FET 4 is turned on / off with a high duty ratio of 99% and 98%. While the FET 4 is turned on / off at this high duty ratio, the off period of the FET 4 is very short, and as shown in FIG. 8B, the power supply voltage VI supplied to the lamp 2 is reduced by turning off the FET 4. There is a case where the ON period is reached before it becomes 0 completely, and the FET 4 is not completely turned off. When such a state occurs, there is a problem that radiation / conduction noise increases rapidly, and malfunction of other devices is a concern. When the power supply voltage VI increases to some extent and the duty ratio decreases, as shown in FIG. 8A, the power supply voltage supplied to the lamp 2 is completely zero as the FET 4 is turned off.

  Therefore, the present applicant considered to mask on / off with a high duty of 95% or more, for example. However, when the power supply voltage stagnates in the vicinity of a predetermined value and a fluctuation occurs that crosses the predetermined value, the brightness frequently changes between 100% and 95%, causing the lamp to flicker. There was a fear.

JP 2009-65246 A

  Therefore, the present invention prevents the generation of radiation / conduction noise by preventing the switch from being turned on / off by a pulse signal having a duty ratio that does not completely turn off the switch, and the power supply voltage fluctuates over a predetermined value. It is an object of the present invention to provide a load control device that can suppress fluctuations in the duty ratio even in the case of such a failure.

  The invention according to claim 1 for solving the above-mentioned problem is a load control device for controlling a switch provided between a load and a power supply, and periodically increases or decreases between an upper limit value and a lower limit value. A periodic signal generator for generating a periodic signal, and a first comparator for comparing the periodic signal generated by the periodic signal generator with a power supply voltage of the power supply or a voltage corresponding to the power supply voltage, In the load control device, wherein the first comparator outputs a DC signal while the power supply voltage is less than a first predetermined value, and outputs a first pulse signal when the power supply voltage becomes equal to or higher than the first predetermined value. When the power supply voltage becomes equal to or higher than the first predetermined value, a second pulse signal having a constant duty ratio is output. While the second pulse signal is being output, the power supply voltage is lower than the first predetermined value. When the value falls below the value, the second pulse signal The second pulse signal output means for stopping the output, and when the first pulse signal and the second pulse signal are input, one is selected, and when the DC signal and the second pulse signal are input, Selecting means for selecting a second pulse signal and performing on / off control of the switch using the selected pulse signal, and when the first pulse signal is on / off controlled using the signal, The pulse signal is such that the duty ratio of the on period of the switch becomes smaller in accordance with the rise of the power supply voltage, and the one signal selected by the selection means uses the one signal to control the on / off of the switch. The off-period of the switch is longer than that when the other non-selected signal is used to control the switch on / off. It consists in a load control device, wherein the door.

  According to a second aspect of the present invention, the second pulse signal output means compares the periodic signal generated by the periodic signal generator with a voltage that internally divides the upper limit value and lower limit value of the periodic signal. The load control device according to claim 1, comprising two comparators.

  The invention according to claim 3 is characterized in that the second pulse signal output means compares the power supply voltage with the second predetermined value, and the output of the first comparator is input to a set terminal. A flip-flop in which the output of the third comparator is input to a reset terminal; and a first logic gate that receives the output of the flip-flop and the output of the second comparator and outputs the second pulse signal. Furthermore, it exists in the load control apparatus of Claim 2 characterized by the above-mentioned.

  The invention according to claim 4 is characterized in that the selection means comprises a second logic gate to which an output from the second pulse signal output means and an output of the first comparator are inputted. It exists in the load control apparatus of any one of Claims 1-3.

  As described above, according to the first aspect of the present invention, when the duty ratio is such that the first pulse signal does not completely turn off the switch, the switch is turned on / off using the second pulse signal rather than the first pulse signal. Since the switch off period becomes longer when the control is performed, the second pulse signal is selected by the selection means. On the other hand, when the duty ratio is such that the first pulse signal completely turns off the switch, the switch off period is longer when the switch is turned on / off using the first pulse signal than the second pulse signal. The first pulse signal is selected by the means. Therefore, the switch is not turned on / off by a pulse signal having a duty ratio that does not completely turn off the switch, and the generation of radiation / conduction noise can be prevented. In addition, even if the DC voltage is output from the first comparator immediately after the power supply voltage exceeds the first predetermined value and falls below the first predetermined value, the second pulse signal output means causes the power supply voltage to be the second predetermined value. In order to maintain the output of the second pulse signal until it falls below, the second pulse signal is selected by the selection means, and the on / off of the switch using the second pulse signal is maintained. For this reason, even when the power supply voltage fluctuates across the first predetermined value, variation in the duty ratio can be suppressed.

  According to the second aspect of the present invention, the second pulse signal output means compares the periodic signal generated by the periodic signal generator with a voltage that internally divides the upper limit value or lower limit value of the periodic signal. Since the comparator is provided, the second pulse signal having the same period as the first pulse signal can be easily output.

  According to the third aspect of the present invention, the second pulse signal output means can be easily provided from the third comparator, the flip-flop, and the first logic gate.

  According to the fourth aspect of the present invention, the selecting means can be easily provided from the second logic gate.

It is a circuit diagram showing one embodiment of a power supply device incorporating a load control device of the present invention. It is an electric circuit diagram which shows the detail of the load control apparatus shown in FIG. (A) to (G) are the power supply voltage VI, the triangular wave VT and the voltage Vk1, the output V1 of the first comparator, the output V2 of the second comparator, the output V3 of the flip-flop, the output V4 of the NOR gate, and the OR gate It is a time chart of output V5. (A) to (F) are time charts of the power supply voltage VI, the output V1 of the first comparator, the output V4 of the NOR gate, the output V6 of the third comparator, the output V3 of the flip-flop, and the output V5 of the OR gate. is there. 2 is a graph showing an effective voltage with respect to a power supply voltage and a duty ratio of an ON period of the FET shown in FIG. 1 according to the present embodiment. It is a circuit diagram which shows an example of the power supply device incorporating the conventional load control apparatus. It is a graph which shows the voltage ratio with respect to the conventional power supply voltage, and the duty ratio of the ON period of FET shown in FIG. (A) And (B) is a graph for demonstrating the problem of the power supply device shown in FIG.

  Hereinafter, a power supply apparatus incorporating the load control apparatus of the present invention will be described with reference to FIGS. As shown in FIG. 1, a power supply device 1 is provided between a lamp 2 as a load, a battery 3 as a power source for supplying power to the lamp 2, and between the lamp 2 and the battery 3. FET 4 as a switch for turning on and off the power supply to 2, and a load control device 5 for controlling the supply of the power supply voltage VI from the battery 3 to the lamp 2 by controlling on and off of the FET 4.

  The FET 4 is a P-channel FET, the source of which is connected to the + side of the in-vehicle battery 3, the drain of which is connected to the lamp 2, and the gate of which is connected to the load control device 5. The FET 4 is turned on when the L level is supplied to the gate and the power is supplied to the lamp 2, and is turned off when the H level is output to the gate and the power supply to the lamp 2 is cut off. As shown in FIG. 2, the load control device 5 is made into an IC and includes a power input terminal TP, an output terminal TO, and a ground terminal TG. In the present embodiment, an example in which the entire load control device 5 is integrated will be described. However, the present invention is not limited to this, and only a part of the load control device 5 may be integrated.

  The power input terminal TP is connected to the positive side of the battery 3. The output terminal TO is connected to the gate of the FET 4. The ground terminal TG is connected to the negative side of the battery 3. Note that the negative side of the battery 3 is connected to the ground.

  The load control device 5 includes a triangular wave generator 6 as a periodic signal generator generated by generating a triangular wave VT from the power supply voltage VI supplied to the lamp 2, and the triangular wave VT generated by the triangular wave generator 6 and the power supply voltage. A first comparator 7 for comparing with a voltage Vk1 corresponding to VI.

  The triangular wave generator 6 includes, for example, a capacitor, a first current mirror circuit that charges the capacitor with a constant charge current, a second current mirror circuit that discharges the capacitor with a constant discharge current, and both ends of the capacitor have upper limit values. When it exceeds, the output is inverted from L level to H level, and when both ends of the capacitor are below the lower limit value, the output is inverted from H level to L level, and the capacitor is charged when the output of the hysteresis comparator is L level. This is a known triangular wave generator provided with a charge / discharge control circuit (none of which is shown) for discharging the capacitor when it is at the H level. Then, a triangular wave VT as a periodic signal that periodically increases and decreases between an upper limit value and a lower limit value is generated in a voltage across a capacitor (not shown) of the triangular wave generator 6. In the present embodiment, the upper limit value and the lower limit value are obtained by dividing the power supply voltage VI and supplying it to the hysteresis comparator, so that the upper limit value Va and the lower limit value Vb of the triangular wave are as shown in FIG. The power supply voltage VI rises as it rises.

In the first comparator 7, a voltage Vk1 corresponding to the power supply voltage VI is input to the + terminal, and a triangular wave VT is supplied to the-terminal. The voltage Vk1 is a voltage obtained by dividing the power supply voltage VI by the Zener diode ZD and the first resistor R1. Therefore, when the power supply voltage VI is equal to or lower than the breakdown voltage of the Zener diode ZD, almost no current flows through the Zener diode ZD, and the voltage Vk1 becomes zero. On the other hand, when the power supply voltage VI exceeds the breakdown voltage of the Zener diode ZD, the voltage Vk1 has a value represented by the following formula (1).
Vk1 = VI−VZD (1)

  The VZD is a Zener voltage and is constant regardless of the increase or decrease of the power supply voltage VI. As is apparent from the equation (1), when the power supply voltage VI becomes equal to or higher than the breakdown voltage of the Zener diode ZD, the voltage Vk1 becomes a value corresponding to the power supply voltage VI, and as shown in FIG. As the voltage rises, the voltage Vk1 also rises. The rate of increase of voltage Vk1 at this time is greater than the rate of increase of upper limit value Va and lower limit value Vb of triangular wave VT.

  As shown in FIGS. 3B and 3C, the first comparator 7 compares the voltage Vk1 with the triangular wave VT, and outputs an L level when the voltage Vk1 is lower than the triangular wave VT. When it exceeds the triangular wave VT, H level is output. Accordingly, as shown in FIGS. 3A to 3C, the first comparator 7 always outputs an L level DC signal while the power supply voltage VI is less than the first predetermined value, and the power supply voltage VI is 1 When the voltage exceeds a predetermined value, the voltage Vk1 exceeds the lower limit value Vb of the triangular wave VT, and a first pulse signal whose duty ratio increases as the power supply voltage VI increases is output. As described above, the FET 4 is turned on when the L level is supplied to the gate, and is turned on when the H level is supplied. Therefore, the DC signal always at the L level output from the first comparator 7 always turns on the FET 4. The first pulse signal is a pulse signal that reduces the duty ratio of the on-period of the FET 4 as the power supply voltage VI increases.

  Further, as shown in FIG. 2, when the power supply voltage VI becomes equal to or higher than the first predetermined value, the load control device 5 outputs the second pulse signal having a constant duty ratio and outputs the second pulse signal. A second pulse signal output circuit 8 as second pulse signal output means for stopping the output of the second pulse signal when the power supply voltage VI falls below a second predetermined value smaller than the first predetermined value; When the second pulse signal is input, the pulse signal having the longer H level period is selected, and when the DC signal and the second pulse signal are input, the second pulse signal is selected and the selected pulse signal is used. Selection means for performing on / off control of the FET 4, an OR gate 9 as a second logic gate, and an FET drive circuit 10 for shifting the output of the OR gate 9 to a level at which the FET 4 can be turned on and off.

  The second pulse signal output circuit 8 compares the voltage dividing circuit 11 that outputs the voltages Vk2 and Vk3 obtained by dividing the power supply voltage VI with the triangular wave VT generated by the triangular wave generator 6 and the voltage Vk2, and compares them. The second comparator 12 that outputs the result, the voltage Vk1 and the voltage Vk3 are compared, the third comparator 15 that outputs the comparison result, and the output V1 of the first comparator 7 are input to the set terminal S. The flip-flop 13 to which the output V6 of the third comparator 15 is input to the reset terminal R, and the NOR gate 14 as the second logic gate to which the output V3 of the flip-flop 13 and the output V2 of the second comparator 12 are input. And having.

  The voltage dividing circuit 11 includes a second resistor R2 to a fourth resistor R4 connected in series between the power supply voltages VI. The power supply voltage VI is divided by the second resistor R2, the third resistor R3, and the fourth resistor R4. The divided voltage is output as the voltage Vk2 (= VI × (R3 + R4) / (R2 + R3 + R4)), and the voltage obtained by dividing the power supply voltage VI by the second resistor R2, the third resistor R3, and the fourth resistor R4 is the voltage Vk3 ( = VI × R4 / (R2 + R3 + R4)). The voltage Vk2 increases as the power supply voltage VI increases, but is a voltage that internally divides the upper limit value Va and the lower limit value Vb of the triangular wave.

  As shown in FIG. 3D, the second comparator 12 compares the voltage Vk2 with the triangular wave VT, outputs an H level when the voltage Vk2 is lower than the triangular wave VT, and the voltage Vk1 exceeds the triangular wave VT. And L level are output. Therefore, as described above, the voltage Vk2 is a voltage that internally divides the upper limit value Va and the lower limit value Vb of the triangular wave VT, so that the third pulse signal having a constant duty ratio is output from the output V2 of the second comparator 12. Is output. Since the third pulse signal is obtained by inputting the triangular wave VT input to the first comparator 7 to the second comparator 12, the center of the L level is the same as the center of the H level of the first pulse signal. .

  The third comparator 15 compares the voltage Vk1 with the voltage Vk3, the voltage Vk1 becomes lower than the voltage Vk3 and outputs an H level, and the voltage Vk1 exceeds the voltage Vk3 and outputs an L level. The voltage Vk3 is set to the voltage Vk1 when the power supply voltage VI becomes a second predetermined value smaller than the first predetermined value. Accordingly, as shown in FIGS. 4A and 4D, the third comparator 15 outputs an L level while the power supply voltage VI is equal to or higher than the second predetermined value, and the power supply voltage VI has the second predetermined value. When it falls below, H level is output.

  As shown in FIGS. 3E and 4E, when the power supply voltage VI becomes equal to or higher than the first predetermined value and the first pulse signal is output from the first comparator 7, the flip-flop 13 outputs its output V3. Is inverted from the H level to the L level, and the L level is maintained. As shown in FIG. 4E, the power supply voltage VI falls below the second predetermined value while maintaining the L level, and the output of the third comparator 15 is maintained. When V6 is inverted from L level to H level, it is reset and inverted to H level. As shown in FIGS. 3F and 4F, the NOR gate 14 maintains the L level while the output V3 of the flip-flop 13 outputs the H level, and the output V3 of the flip-flop 13 is When the L level is output, a second pulse signal obtained by inverting the third pulse signal is output. Since the second pulse signal is obtained by inverting the third pulse signal, the center of the H level is the same as the center of the H level of the first pulse signal.

  Next, the operation of the power supply device 1 having the above-described configuration will be described with reference to the time charts of FIGS. Since the voltage Vk1 is smaller than the lower limit value Vb while the power supply voltage VI is equal to or lower than the first predetermined value, an L level DC signal is always output from the output V1 of the first comparator 7 (FIG. 3C). 4 (B)). For this reason, the H level is always output from the output V3 of the flip-flop 13 (FIGS. 3E and 4E). On the other hand, the third pulse signal is output from the output V2 of the second comparator 12 (FIG. 3D). However, since the output V3 of the flip-flop 13 is always at the H level as described above, the NOR gate The second pulse signal is not output from the output V4 of 14, and the L level is always output (FIG. 3 (F), FIG. 4 (C)). As a result, since the L level signal is always supplied to the two inputs to the OR gate 9, the L level signal is always output from the output V5 (FIG. 3 (G), FIG. 4 (F)). The FET 4 is always turned on.

  On the other hand, when the power supply voltage VI exceeds the first predetermined value, the voltage Vk1 rises according to the power supply voltage VI. Therefore, a first pulse signal having a duty ratio corresponding to the power supply voltage VI is output from the output V1 of the first comparator 7. It is output (FIG. 3C, FIG. 4B). Naturally, when the power supply voltage VI exceeds the first predetermined value, the second predetermined value is also exceeded, and the output V6 of the third comparator 15 is at the L level. The output V3 of the flip-flop 13 is inverted from the H level to the L level and maintained at the L level (FIGS. 3E and 4E). Therefore, a second pulse signal obtained by inverting the third pulse signal is output from the output V4 of the NOR gate 14 (FIG. 3 (F), FIG. 4 (C)).

  As a result, the first pulse signal and the second pulse signal are input to the OR gate 9. The OR gate 9 selects a pulse signal having a longer H level period from the first pulse signal and the second pulse signal, and performs on / off control of the FET 4 using the selected pulse signal.

  The duty ratio of the second pulse signal is set to such a value that the FET 4 is completely turned off when the second pulse signal is supplied to the gate of the FET 4. For example, assume that the duty ratio of the second pulse signal is constant, for example, 5% (= the duty ratio of the on period is 95% when the second pulse signal is supplied to the gate of the FET 4). The OR gate 9 selects the second pulse signal while the power supply voltage VI is slightly higher than the first predetermined value and the duty ratio of the first pulse signal is less than 5% of the second pulse signal. And output. On the other hand, when the power supply voltage VI greatly exceeds the first predetermined value and the duty ratio of the first pulse signal exceeds 5% of the second pulse signal, the OR gate 9 selects and outputs the first pulse signal. .

  As a result, when the power supply voltage VI exceeds the first predetermined value (12.5 V), the FET 4 is turned on / off using the second pulse signal while the duty ratio of the first pulse signal is less than 5%, When the duty ratio of one pulse signal exceeds 5%, the FET 4 is turned on / off using the first pulse signal, so that the ON period of the FET 4 is turned on / off with a duty ratio of 95% or more as shown in FIG. There is no.

  When the power supply voltage VI falls below the first predetermined value in the state of outputting the second pulse signal, the output V1 of the first comparator 7 is changed from the first pulse signal to the DC signal as shown in FIG. Can be switched to. However, since the output V6 of the third comparator 15 maintains the L level until the power supply voltage VI falls below the second predetermined value even if the power supply voltage VI falls below the first predetermined value (FIG. 4D), the NOR gate 14 The output of the second pulse signal is maintained from the output V4 (FIG. 4C).

  As a result, the DC signal and the second pulse signal are input to the OR gate 9. Then, the OR gate 9 selects the second pulse signal from the DC signal and the second pulse signal, and continues the on / off control of the FET 4 using the selected second pulse signal. Thereafter, when the power supply voltage VI falls below the second predetermined value, the output V6 of the third comparator 15 is inverted from the L level to the H level, so that the flip-flop 13 is reset and its output changes from the L level to the H level. Inverted (FIG. 4E). As a result, the output of the NOR gate 14 becomes constant at the L level, so that the output of the second pulse signal is stopped from the OR gate 9 and a DC signal is output.

  That is, as shown in FIG. 5, once the power supply voltage VI becomes equal to or higher than the first predetermined value (12.5 V), control using the second pulse signal is continued even if the power supply voltage VI becomes equal to or lower than the first predetermined value. Only when the voltage falls below a second predetermined value (11.5 V) smaller than the first predetermined value, the control is switched to the control using the DC signal (duty 100%).

  According to the embodiment described above, when the duty ratio is such that the first pulse signal does not completely turn off the FET 4, the FET 4 is turned off by using the second pulse signal rather than the first pulse signal. Since the period becomes longer, the second pulse signal is selected by the OR gate 9. On the other hand, when the duty ratio is such that the first pulse signal completely turns off the FET 4, the FET 4 is turned on / off using the first pulse signal rather than the second pulse signal, and the off period of the FET 4 becomes longer. The first pulse signal is selected by the gate 9. For this reason, the FET 4 is not turned on / off by a pulse signal having a duty ratio that does not completely turn off the FET 4, and the generation of radiation / conduction noise can be prevented. Further, even if the DC voltage is output from the first comparator 7 immediately after the power supply voltage VI exceeds the first predetermined value and falls below the first predetermined value, the second pulse signal circuit 8 does not change the power supply voltage VI. 2 In order to maintain the output of the second pulse signal until it falls below a predetermined value, the second pulse signal is selected by the OR gate 9 and the FET 4 using the second pulse signal is kept on / off. For this reason, even when the power supply voltage fluctuates across the first predetermined value, variation in the duty ratio can be suppressed.

  According to the embodiment described above, the second pulse signal output circuit 8 compares the triangular wave VT generated by the triangular wave generator 6 with the voltage that internally divides the upper limit value Va or the lower limit value Vb of the triangular wave VT. Since the second comparator 12 is provided, a second pulse signal having the same period as the first pulse signal can be easily output.

  According to the above-described embodiment, the second pulse signal output circuit 8 further includes the third comparator 15, the flip-flop 13, and the NOR gate 14, and thus can be easily provided.

  According to the above-described embodiment, the selection means is composed of the OR gate 9, so that it can be easily provided.

  In the above-described embodiment, the triangular wave generator 6 that generates the triangular wave VT is used as the periodic signal generator. However, the present invention is not limited to this. For example, the periodic signal may be a signal that periodically increases or decreases between the upper limit value Va and the lower limit value Vb, and may be, for example, a sawtooth wave.

  In the above-described embodiment, the second pulse signal output circuit 8 includes the third comparator 15, the flip-flop 13, and the NOR gate 14. However, the present invention is not limited to this. Absent. For example, until the power supply voltage VI exceeds the first predetermined value, after the first predetermined value is exceeded and then falls below the second predetermined value, the voltage Vk2 that is equal to or higher than the upper limit value Va or lower limit value Vb of the triangular wave VT. A voltage Vk2 that divides the upper limit value Va and the lower limit value Vb of the triangular wave VT in a constant manner until the power supply voltage VI exceeds the first predetermined value and falls below the second predetermined value. It is also conceivable that the voltage dividing circuit 11 is variably provided so as to output.

  In the embodiment described above, the upper limit value Va and the lower limit value Vb of the triangular wave generator 6 are generated from the power supply voltage VI and fluctuate according to the fluctuation of the power supply voltage VI. However, the present invention is limited to this. is not. It is also conceivable that the upper limit value Va and the lower limit value Vb are generated from a constant voltage source and made constant. In this case, the voltage dividing circuit 11 also needs to divide the constant voltage from the constant voltage source and output it to the second comparator 12.

  Further, the above-described embodiments are merely representative forms of the present invention, and the present invention is not limited to the embodiments. That is, various modifications can be made without departing from the scope of the present invention.

2 Lamp (load)
3 Battery (Power)
4 FET (switch)
5 Load control device 6 Triangular wave generator (periodic signal generator)
7 first comparator 8 second pulse signal output circuit (second pulse signal output means)
9 OR gate (selection means, second logic gate)
12 Second comparator 13 Flip-flop 14 NOR gate (first logic gate)
15 Third comparator VT Triangular wave (periodic signal)
VI Power supply voltage Vk1 Voltage according to the power supply voltage

Claims (4)

A load control device for controlling a switch provided between a load and a power supply, wherein the periodic signal generator generates a periodic signal that periodically increases and decreases between an upper limit value and a lower limit value, and the periodic signal generation A first comparator that compares a periodic signal generated by a power supply with a power supply voltage of the power supply or a voltage corresponding to the power supply voltage, wherein the first comparator has the power supply voltage less than a first predetermined value. In the load control device that outputs a direct current signal during the period and outputs a first pulse signal when the power supply voltage is equal to or higher than the first predetermined value,
When the power supply voltage becomes equal to or higher than the first predetermined value, a second pulse signal having a constant duty ratio is output, and the second power supply voltage is smaller than the first predetermined value while the second pulse signal is being output. A second pulse signal output means for stopping the output of the second pulse signal when less than a predetermined value;
When the first pulse signal and the second pulse signal are input, one of them is selected. When the DC signal and the second pulse signal are input, the second pulse signal is selected, and the selected pulse signal is selected. And selecting means for performing on / off control of the switch using,
The first pulse signal is a pulse signal such that when the switch is turned on / off using the signal, the duty ratio of the on period of the switch is reduced as the power supply voltage increases.
The one signal selected by the selection means is an off period of the switch when the on / off control of the switch is performed using one signal, compared to a case where the switch is on / off controlled using the other signal not selected. The load control device is characterized in that the signal is such that becomes longer. The second pulse signal output means includes a second comparator that compares the periodic signal generated by the periodic signal generator with a voltage that internally divides the upper limit value and the lower limit value of the periodic signal. The load control device according to claim 1. The second pulse signal output means compares the power supply voltage with the second predetermined value, the output of the first comparator is input to a set terminal, and the output of the third comparator is A flip-flop input to a reset terminal, and a first logic gate that receives the output of the flip-flop and the output of the second comparator and outputs the second pulse signal. Item 3. The load control device according to Item 2. The said selection means is comprised from the 2nd logic gate into which the output from the said 2nd pulse signal output means and the output of the said 1st comparator are input. The any one of Claims 1-3 characterized by the above-mentioned. The load control device according to item.

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