JP2013253010A - Graphene structure, semiconductor device using the same, and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a graphene structure composed of a graphene nanoribbon oriented to an arbitrary direction in an arbitrary area on a substrate, a semiconductor device using the graphene structure, and a method of manufacturing them.SOLUTION: A graphene structure 1 includes: a substrate 2; a first electrode 3 formed on the substrate 2; a graphene nanoribbon 5 formed on the substrate 2; and a second electrode 4 formed on the substrate 2. One ends of the first electrode 3 and graphene nanoribbon 5 are connected to each other. The other ends of the graphene nanoribbon 5 and the second electrode 4 are connected to each other. The width of the graphene nanoribbon 5 is specified to be 100 nm or less that generates a forbidden band width as a semiconductor.

Description

  The present invention relates to a graphene structure, a semiconductor device using the same, and a method for manufacturing the graphene structure and the semiconductor device.

  Graphite is a compound in which hexagonal mesh-like carbon sheets are regularly stacked. Graphene is obtained by removing one layer of graphite. Graphene sheets composed of a single carbon atom thickness have been developed around the world since their discovery in 2004 (see Non-Patent Document 1) as a material that combines excellent electrical conductivity and flexible flexibility. ing.

  The main application of graphene is in the nanoscale electronics field, mainly semiconductor devices. However, in order to fabricate a transistor that is a minimum component of a semiconductor device, a switching operation that can define a clear on and off state is indispensable.

  However, graphene is known as a zero-gap semiconductor and does not have a clear band gap (hereinafter referred to as a forbidden band width). For this reason, the on / off ratio of the current conducting graphene is very low, making it difficult to use as a transistor.

  On the other hand, in recent years, it has been reported theoretically and experimentally that graphene, which is a two-dimensional sheet, is formed into a one-dimensional ribbon shape to generate a forbidden bandwidth, and has attracted a great deal of attention (non-patent literature). 2-5).

The main methods for synthesizing graphene nanoribbons reported so far are shown below.
(1) A method of forming a ribbon shape by etching a two-dimensional graphene sheet into a ribbon shape by lithography (see Non-Patent Document 6).
This method can be finely processed, but is not suitable for industrial applications because the drawing range is as small as a micrometer scale. In addition, many defects are introduced in the etching process, resulting in poor quality. Furthermore, since the position and area for producing the nanoribbon transistor are determined by the size and structure of the initial two-dimensional graphene sheet, it is unrealistic for industrial applications.

(2) A method of cutting a carbon nanotube known as a one-dimensional cylindrical material in the axial direction into a ribbon shape (see Non-Patent Document 7).
Although high-quality nanoribbons can be synthesized depending on conditions, it is extremely difficult to construct a logic circuit because a technique for arranging carbon nanotubes on a substrate has not yet been established.

(3) A method of synthesizing graphene nanoribbons by thermally decomposing prearranged SiC (see Non-Patent Document 8).
By arranging SiC in advance, graphene nanoribbons can be integrated, but the device performance is poor. Specifically, when the device is a transistor, the ratio of on-current to off-current flowing through the transistor, that is, the on / off ratio is about 30.

(4) A method of forming a graphene nanoribbon by connecting one-dimensionally high polymers into a ribbon shape (see Non-Patent Document 9).
In principle, graphene nanoribbons can be synthesized bottom-up on an arbitrary substrate, but the growth direction has not been controlled, and the operation of devices using graphene nanoribbons has not yet been demonstrated. Absent.

  Patent Document 1 discloses a method of forming a graphene film by forming a graphene film on a catalytic metal layer made of iron containing carbon by a thermal CVD method and etching the catalytic metal layer.

JP 2011-201735 A

Novoselov, KS, Geim, AK, Morozov, SV, Jiang, D., Zhang, Y, Dubonos, SV, Grigorieva, IV, & Firsov, AA, "Electric field effect in atomically thin carbon films", Science, Vol. 306 , pp.666-669, 2004 Nakada, K., Fujita, M, Dresselhaus, G. & Dresselhaus, M. S., "Edge state in graphene ribbons: nanometer size effect and edge shape dependence", Phys. Rev. B 54, pp.17954-17961, 1996 Wakabayashi, K., Fujita, M. Ajiki, H. & Sigrist, M., "Electronic and magnetic properties of nanographite ribbons", Phys. Rev. B Vol.59, pp.8271-8282, 1999 Ponomarenko, LA, Schedin, F, Katsnelson, M. I, Yang, R., Hill, EW, Novoselov, KS, & Geim, AK, "Chaotic dirac billiard in graphene quantum dots", Science, Vol.320, pp. 356-358, 2008 Li, X. L., Wang, X. R., Zhang, L., Lee, S. W. & Dai, H. J., "Chemically derived, ultrasmooth graphene nanoribbon semiconductors", Science Vol.319, pp.1229-1232, 2008 Han, M. Y, Ozyilmaz, B., Zhang, Y. B. & Kim, P. "Energy band-gap engineering of graphene nanoribbons", Phys. Rev. Lett., Vol.98, p.206805, 2007 Jiao, L. Y, Zhang, L., Wang, X. R., Diankov, G. & Dai, H. J., "Narrow graphene nanoribbons from carbon nanotubes", Nature 458, 877-880 (2009). Sprinkle, M, Ruan, M., Hu, Y, Hankinson, J., Rubio-Roy, M, Zhang, B., Wu, X., Berger, C, & de Heer, WA, "Scalable templated growth of graphene nanoribbons on SiC ”, Nature, Nanotechnol, Vol.5, pp.727-731, 2010 Cai, J., Ruffieux, P., Jaafar, R., Bien, M., Braun, T., Blankenburg, S., Muoth, M., Seitsonen, AP, Saleh, M, Feng, X., Mullen, K., & Fasel, R., "Atomically precise bottom-up fabrication of graphene nanoribbons", Nature, Vol.466, pp.470-473, 2010

  Most conventional graphene nanoribbon synthesis methods synthesize a small amount of graphene nanoribbons, and most of the basic research focuses on clarifying the characteristics of each obtained graphene nanoribbon.

  On the other hand, the biggest barrier to using graphene nanoribbons as actual semiconductor devices is how to integrate the small nanomaterials on the substrate, and this issue is still unclear. No solution has been derived.

  In view of the above problems, the present invention has a first object to provide a graphene structure using a graphene nanoribbon facing an arbitrary direction in an arbitrary region on a substrate, and a semiconductor device using the graphene structure The second object is to provide the above, and the third object is to provide these manufacturing methods.

  Under these circumstances, the present inventors have found a new method capable of completely controlling the growth position and growth direction of a high-performance graphene nanoribbon directly on a substrate, and further has an on / off ratio of 1. A transistor composed of more than ten thousand graphene nanoribbons was realized and the present invention was conceived. As a result, it can be said that the possibility of using a transistor made of graphene nanoribbons for actual industrial applications has greatly increased.

In order to achieve the first object, the graphene structure of the present invention includes a substrate and a graphene nanoribbon formed on the substrate, and the width of the graphene nanoribbon is 100 nm at which a forbidden body width as a semiconductor is generated. It is as follows.
Another graphene structure of the present invention includes a substrate, a first electrode formed on the substrate, a graphene nanoribbon formed on the substrate, and a second electrode formed on the substrate, The first electrode is connected to one end of the graphene nanoribbon, the other end of the graphene nanoribbon is connected to the second electrode, and the width of the graphene nanoribbon is set to 100 nm or less that produces a forbidden body width as a semiconductor. .

In the above configuration, the substrate is preferably a substrate with an insulating film.
The electrode is preferably made of any one of Ni, Cu, Co, Fe, Au, Pd, Al, and Pt.
The forbidden body width of the graphene nanoribbon is preferably 10 to 1000 meV.
The Raman spectroscopic characteristics of the graphene nanoribbon preferably have a D band, a G band, and a 2D band.
Preferably, at the junction between the graphene nanoribbon and the first and / or second electrode, the composition of the graphene nanoribbon and the first and / or second electrode changes continuously. In addition, preferably, the width of the graphene nanoribbon and the first and / or second electrode continuously changes at the joint between the graphene nanoribbon and the first and / or second electrode.
The graphene nanoribbon is preferably disposed with a gap between the graphene nanoribbon and the substrate.

In order to achieve the second object, a semiconductor device of the present invention uses any of the graphene structures described above.
In the above configuration, the semiconductor device preferably includes a pn junction made of graphene nanoribbons.
The semiconductor device is a MOSFET having a gate insulating film formed on a substrate and a channel made of graphene nanoribbons, a complementary MOSFET, or a spin semiconductor transistor that is spin-injected from an electrode formed on the substrate. It's okay. The semiconductor device may include a plurality of channels.

In order to achieve the third object, a method for producing a graphene structure according to any one of the above aspects of the present invention includes: forming an insulating film on a substrate; forming a metal layer on the insulating film; The graphene structure is formed by forming a pattern of the graphene structure, raising the temperature of the substrate to a predetermined temperature, then generating a plasma discharge composed of the raw material gas of the graphene nanoribbon, and cooling the temperature of the substrate to the predetermined temperature. Manufacturing.
Another graphene structure manufacturing method includes forming an insulating film on a substrate, forming a metal layer on the insulating film, forming a graphene structure pattern made of the metal layer, and bringing the temperature of the substrate to a predetermined temperature. Next, a graphene nanoribbon raw material gas is flowed, and the temperature of the substrate is cooled to a predetermined temperature to produce a graphene structure.
Still another graphene structure manufacturing method includes forming an insulating film on a substrate, forming a metal layer on the insulating film, forming a graphene structure pattern made of the metal layer, and forming a metal layer in a source gas atmosphere. A graphene structure is manufactured by performing local heating by passing an electric current through the graphene structure composed of layers and then cooling.
In the above structure, a region having a narrow line width may be provided in the pattern.

  According to the present invention, the growth position and growth direction of the graphene nanoribbon on the substrate can be completely controlled, and the graphene nanoribbon transistor can be directly synthesized on the substrate. This enables integration of graphene nanoribbon transistors.

BRIEF DESCRIPTION OF THE DRAWINGS The outline of the graphene structure of this invention is shown, (a) is a top view, (b) is sectional drawing along the II line | wire of (a). The modification of the graphene structure which concerns on this invention is shown, (a) is a schematic plan view, (b) is sectional drawing along the II-II line of (a). It is a schematic plan view showing a semiconductor device using a graphene structure of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS The outline of the MOS type field effect transistor using the graphene structure of this invention is shown, (a) is a top view, (b) is sectional drawing along the III-III line of (a). It is a schematic diagram of the modification of the semiconductor device using a graphene structure, (a) is a top view, (b) is sectional drawing along the IV-IV line of (a). BRIEF DESCRIPTION OF THE DRAWINGS The outline of the spin semiconductor transistor of this invention is shown, (a) is a top view, (b) is sectional drawing along the VV line of (a). It is a typical top view which shows the structure of the Coulomb dot of the single electron transistor of the present invention, and (a) is a case where Coulomb dots are formed on a graphene nanoribbon, and (b) is a residual metal between the graphene nanoribbons. The case where it forms is shown. BRIEF DESCRIPTION OF THE DRAWINGS The outline of the inverter which consists of MOSFET and resistance using the graphene structure of this invention is shown, (a) is a top view, (b) is sectional drawing along the VI-VI line of (a). BRIEF DESCRIPTION OF THE DRAWINGS The outline of the complementary MOS inverter which consists of n channel MOSFET and p channel MOSFET using the graphene structure of this invention is shown, (a) is a top view, (b) is the cross section along the VII-VII line of (a). FIG. The modification of the graphene structure of this invention is shown, (a) is a top view, (b) is sectional drawing along the VIII-VIII line of (a). The MOSFET using the modification of the graphene structure of this invention is shown, (a) is a top view, (b) is sectional drawing along the IX-IX line of (a). 1 schematically shows a method for producing a graphene structure according to the present invention, wherein (a) is a graphene structure pattern forming step, (b) is a plasma CVD step, (c) is a cooling step, and (d) is a manufactured graphene. It is a perspective view of a structure. It is explanatory drawing of a plasma CVD apparatus. FIG. 2 shows a scanning electron microscope (SEM) image of a pattern made of Ni, (a) taken at a low magnification and (b) taken at a high magnification. (A)-(h) is a SEM image which shows the produced various graphene structures. The SEM image which shows the measurement location of a Raman spectroscopy is shown, (a) is the low magnification, (b) is the figure image | photographed with high magnification. The image mapped by Raman spectroscopy is shown, (a) is Si, (b) is the D band of the graphene nanoribbon, (c) is the G band of the graphene nanoribbon, and (d) is the signal from the 2D band of the graphene nanoribbon. . Two typical examples of Raman spectral characteristics of the graphene nanoribbon 5 are shown, (a) and (b) are the characteristics of the sample 1, and (c) are the characteristics of the sample 2. FIG. The X-ray analysis result is shown, (a) is an SEM image of the measurement region, (b) is a graph of the EDX line analysis result of the region where the graphene nanoribbon is present, (c) is the EDX line analysis of the region where Ni is present It is a graph of a result. It is a figure which shows the relationship between the line width of a nickel nanobar, and the line width of the synthetic | combination graphene nanoribbon, (a)-(h) is a SEM image, (i) is the line width of a nickel nanobar, and the synthesized graphene nanoribbon It is a figure which shows the relationship with line | wire width. 2 shows a graphene structure floating between the electrodes shown in FIG. 2, wherein (a) is an SEM image, (b) is a Raman spectrum, (c) is a cross-sectional TEM image, and (d) is an enlarged TEM of (c). Image (e) is an enlarged TEM image of (d). The structure of the graphene structure formed radially is shown, (a) is an SEM image, (b) is a Raman spectrum, and (c) is an enlarged SEM image of (a). The structure which provided the some graphene structure between Ni electrodes is shown, (a) is a SEM image, (b) is a Raman spectrum of (a), (c) is an enlarged SEM image of (a). The measurement result of MOSFET using a graphene structure is shown, (a) is the SEM image of measured MOSFET, (b) is a Vgs-Ids characteristic figure in 13K. It is a figure which shows the temperature dependence of the minimum conductance (Gmin) of MOSFET of FIG. The IV characteristic of another MOSFET is shown, (a) is a SEM image of the measured MOSFET, and (b) is a Vgs-Ids characteristic diagram at 13K and 300K. It is a figure which shows Vds dependence of the ON current of the MOSFET in 13K of FIG. 26, an OFF current, and an ON / OFF ratio. It is the figure which displayed Ids with respect to Vds and Vgs on the log scale in MOSFET in 13K. It is IV characteristic figure of the low Vds of MOSFET in 13K. It is a figure which shows the Vgs-Ids characteristic of the multichannel MOSFET in 300K. It is a Vgs- _Ids characteristic figure of a single electron transistor in 30K.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Graphene structure)
1A and 1B show a graphene structure 1 according to the present invention, in which FIG. 1A is a schematic plan view, and FIG. 1B is a cross-sectional view taken along line II in FIG.
The graphene structure 1 includes a first electrode 3 formed on the substrate 2, a second electrode 4 formed on the substrate 2, a first electrode 3 formed on the substrate 2, and a second electrode It is comprised from the graphene nanoribbon 5 arrange | positioned between the electrodes 4. FIG. The first electrode 3 and one end of the graphene nanoribbon 5 are connected, and the other end of the graphene nanoribbon 5 and the second electrode 4 are connected. The substrate 2 is a substrate made of Si, a compound semiconductor, glass, or the like. The substrate 2 may be a substrate on which an insulating film 7 is further formed. The insulating film 7 is made of SiO ₂ or Si ₃ N ₄ .

  The materials of the first electrode 3 and the second electrode 4 are transition metals Ni (nickel), Co (cobalt) and Fe (iron) or Cu (copper), Au (gold), Pd (palladium), Al ( Aluminum) and Pt (platinum) can be used. The material of the first and second electrodes is preferably a material that can act as a catalyst in the step of depositing the graphene nanoribbon 5 such as plasma CVD described later. In addition, these electrode materials are also materials that evaporate in the plasma CVD process, and therefore, materials having a high vapor pressure are preferable.

  The graphene nanoribbon 5 has a thickness of about 1 nm, the width W of the linear region is 5 nm to 100 nm, and the length L is, for example, 500 to 1000 nm. The width W of the graphene nanoribbon 5 is set so as to operate as one-dimensional graphene. One-dimensional graphene has a semiconductor property and exhibits intrinsic semiconductor and further n-type or p-type conduction characteristics. The width of the graphene nanoribbon 5 is set to 100 nm or less in which a forbidden body width as a semiconductor is generated. By setting the width of the graphene nanoribbon 5 to 5 to 100 nm, the forbidden body width of the graphene nanoribbon 5 can be set to 1000 to 10 meV. The forbidden body width of the graphene nanoribbon 5 changes in inverse proportion to the width of the graphene nanoribbon 5.

(Modification of graphene structure)
2A and 2B show a modified example 1A of the graphene structure 1 according to the present invention, in which FIG. 2A is a plan view and FIG. 2B is a cross-sectional view taken along line II-II in FIG.
The graphene structure 1A is different from the graphene structure 1 shown in FIG. 1 in that the graphene nanoribbon 5 floats from the insulating film 7, that is, the gap 8 is formed between the first electrode 3 and the second electrode 4. It is the point comprised by bridge | crosslinking through. According to the graphene structure 1 </ b> A, the mobility of carriers in the graphene nanoribbon 5 is significantly higher than that existing on the substrate 2 covered with the insulating film 7. The graphene structure 1A can be applied to a microelectromechanical system (MEMS), a nanoelectromechanical system (NEMS) having a smaller scale, and a three-dimensional wiring.

(Pn junction diode)
FIG. 3 is a schematic plan view for explaining the semiconductor device 10 using the graphene structure 1.
The semiconductor device 10 using the graphene structure 1 of FIG. 3 is different from the graphene structure 1 shown in FIG. 1 in that the graphene nanoribbon 5 is a pn junction. In the illustrated case, the graphene nanoribbon 5 connected to the first electrode 3 is a p-type graphene nanoribbon 15, and the graphene nanoribbon 5 connected to the second electrode 4 is an n-type graphene nanoribbon 16. A pn junction is formed at the boundary between the p-type graphene nanoribbon 15 and the n-type graphene nanoribbon 16.

Next, a semiconductor device using the graphene structure 1 will be described.
(MOS field effect transistor)
4A and 4B are schematic views of a MOS field effect transistor 20 using the graphene structure 1, wherein FIG. 4A is a plan view and FIG. 4B is a cross-sectional view taken along line III-III in FIG.
As shown in FIG. 4, a MOS field effect transistor (referred to as MOSFET) 20 includes a substrate 2, a gate insulating film 7a formed on the substrate 2, and a source electrode 23 formed on the gate insulating film 7a. A drain electrode 24 formed on the gate insulating film 7a, a graphene nanoribbon 5 formed on the gate insulating film 7a and disposed between the source electrode 23 and the drain electrode 24 and serving as a channel; It is composed of
As the gate insulating film 7a, an insulating film made of SiO ₂ formed on the Si substrate 2 can be used. The gate electrode 25 is formed so as to contact the substrate 2. As the substrate 2, a conductive substrate can be used. The first electrode 3 and the second electrode 4 shown in FIG. 1 are a source electrode 23 and a drain electrode 24, respectively. That is, the configuration other than the gate insulating film 7a and the gate electrode 25 is the same as that of the graphene structure 1 in FIG.

  The MOSFET 20 shown in FIG. 4 operates as an n-channel MOSFET 20 when the graphene nanoribbon 5 serving as a channel is p-type. When the graphene nanoribbon 5 serving as a channel is n-type, it operates as a p-channel MOSFET 20. Advantages over existing silicon-based devices include high carrier mobility, high light transmission, flexibility, and a large number of transistors per unit area, that is, high integration.

(Modification of MOS field effect transistor)
5A and 5B are schematic views of a modification of the semiconductor device using the graphene structure 1, in which FIG. 5A is a plan view and FIG. 5B is a cross-sectional view taken along line IV-IV in FIG.
The MOS type field effect transistor 20A shown in FIG. 5 is different from the MOS type field effect transistor 20 shown in FIG. 4 in that a plurality of graphene nanoribbons 5 disposed between the source electrode 23 and the drain electrode 24 and serving as channels are provided. The points are arranged. The MOS field effect transistor 20A is a multi-channel MOS field effect transistor in which one-dimensional ribbon-like graphene nanoribbons are aligned in parallel, and is a so-called multi-channel MOS field effect transistor. Compared with the MOS field effect transistor 20 shown in FIG. 4, the MOS field effect transistor 20A has an increased current driving capability.

(Spin semiconductor transistor)
6A and 6B are schematic views of the spin semiconductor transistor 27, where FIG. 6A is a plan view and FIG. 6B is a cross-sectional view taken along the line V-V in FIG.
The spin semiconductor transistor 27 shown in FIG. 6 is different from the MOS field effect transistor 20 shown in FIG. 4 in that the electrodes 28 and 29 serving as the source and drain are provided with electrodes capable of injecting spin. As the electrodes 28 and 29, electrodes made of a ferromagnetic material are used. When a ferromagnetic metal is used as the electrodes 28 and 29, an operation as a spin semiconductor transistor is possible. Since the graphene nanoribbon 5 can function as a conduction channel that transports charges while retaining spin information from the electrodes 28 and 29, in addition to on / off of charges flowing through the channels, that is, current on / off, A high performance spin semiconductor transistor 27 can be realized by adding a degree of freedom of down.

(Single electron transistor)
Next, the single electron transistor 30 using the graphene structure 1 will be described. The graphene structure 1 can operate as a single-electron transistor 30 by the arrangement method of the graphene nanoribbon 5 and the residual metal 33.
FIG. 7 is a plan view schematically showing the structure of the Coulomb dots 32 of the single-electron transistor 30. FIG. 7A shows a case where the Coulomb dots 32 are formed on the graphene nanoribbon 5, and FIG. The case where it forms with the residual metal 33 between nanoribbons is shown.
As shown in FIG. 7A, the single electron transistor 30 can be operated by the Coulomb dots 32 generated in the defects 5 a at the edge of the graphene nanoribbon 5.
As shown in FIG. 7B, the residual metal 33 generated in the graphene nanoribbon 5 may be operated as a Coulomb dot 32 of the single electron transistor 30. Further, a wide portion is formed in a part of nickel 59 having a nickel nanobar structure, which will be described later, and the residual metal 33 is left in the wide portion, so that the Coulomb dots 32 are formed at a desired location. Good.

  Since the composition continuously changes in the junction between the first electrode 3 and the graphene nanoribbon 5, that is, in the junction region between the metal and the graphene nanoribbon, the interface between the metal and the semiconductor is not a so-called Schottky junction but a resistance. Since an electrode, a so-called ohmic electrode, is formed, rectification is less likely to occur. Thereby, contact resistance can be reduced, excessive heat generation is reduced, and power consumption of the MOSFET 20 can be reduced. In the spin semiconductor transistor 30, the composition continuously changes in the junction region between the metal and the graphene nanoribbon, so that the spin current can be efficiently injected into the graphene nanoribbon 5. That is, it is a great advantage in high-efficiency spin injection and the like. Further, since the conductivity type of the graphene nanoribbon 5 is changed, that is, the p-type and n-type MOSFET 20 can be manufactured, a logic circuit can be formed. Thereby, the application to the integrated circuit using the graphene nanoribbon 5 became possible.

(Resistive load inverter)
FIGS. 8A and 8B are schematic diagrams of the MOSFET 20 using the graphene structure 1 and an inverter 35 made of a resistor. FIG. 8A is a plan view, and FIG. 8B is a cross-sectional view taken along line VI-VI in FIG.
As shown in FIG. 8, the resistive load inverter 35 includes a MOSFET 20, a resistance graphene nanoribbon 36 connected to the drain electrode 24 of the MOSFET 20, and a power supply electrode 37 connected to the resistance graphene nanoribbon 36. Become.
The resistance graphene nanoribbon 36 has the same structure as the graphene structure 1 of FIG. For this reason, the same electrode as the resistance graphene nanoribbon 36 connected to the drain electrode 24 of the MOSFET 20 can be used. Further, the power supply electrode 37 connected to the resistance graphene nanoribbon 36 may be the same metal material as the source electrode 23 and the drain electrode 24 of the MOSFET 20.

  The resistive graphene nanoribbon 36 does not include the gate electrode 25 unlike the MOSFET 20. The conductivity type of the graphene nanoribbon 36 for resistance is the same conductivity type as the channel of the MOSFET 20. The resistance of the graphene nanoribbon 36 for resistance can be controlled by its length L (X direction in FIG. 8) and width W (Y direction in FIG. 8).

(CMOS inverter)
FIG. 9 shows an outline of a complementary MOS inverter 40 composed of an n-channel MOSFET 41 and a p-channel MOSFET 42 using the graphene structure 1, wherein (a) is a plan view and (b) is a VII-VII line in (a). FIG. The complementary MOS inverter 40 is also called a CMOS inverter.
As shown in FIG. 9, a complementary MOS inverter 40 using the graphene structure 1 is composed of an n-channel MOSFET 41 disposed on the left side and a p-channel MOSFET 42 disposed on the right side. The drain electrode 44 of the n-channel MOSFET 41 and the drain electrode 46 of the p-channel MOSFET 42 are connected to form an output electrode. The gate electrodes 45 and 45 ′ of the n-channel MOSFET 41 and the p-channel MOSFET 42 are connected to serve as input electrodes. The gate electrodes 45 and 45 'are connected in a multilayer wiring (not shown). The multilayer wiring is composed of an interlayer insulating film and a wiring layer. A source electrode 47 of the p-channel MOSFET 41 is connected to a power source (V _dd ). The source electrode 43 of the n-channel MOSFET 41 is grounded. This potential is, for example, 0V.

(Modification of graphene structure)
Next, a graphene structure 1 </ b> A having a structure with only graphene nanoribbons and no electrode will be described.
10A and 10B show a modification of the graphene structure, in which FIG. 10A is a plan view and FIG. 10B is a cross-sectional view taken along line VIII-VIII in FIG.
As shown in FIG. 10, the graphene structure 1 </ b> A has a structure in which the electrode of FIG. 1 is omitted, that is, a substrate 2 and a graphene nanoribbon 5 formed on the substrate 2. The width of the graphene nanoribbon 5 is set to 100 nm or less so that a forbidden body width as a semiconductor is generated.

(MOSFET using a modified graphene structure)
11 shows a MOSFET 20 using the graphene structure 1A shown in FIG. 8, wherein (a) is a plan view and (b) is a cross-sectional view taken along line IX-IX in (a).
As shown in FIG. 11, the MOSFET 50 using the graphene structure 1 </ b> A has a configuration in which the source electrode 53 and the drain electrode 54 are formed on both ends of the graphene nanoribbon 5, and the gate electrode 55 is provided on the conductive substrate 2. ing. In the illustrated case, an interlayer insulating film 56 is formed on the surface of the graphene structure 1A. The source electrode 53, drain electrode 54, and gate electrode 55 described above can be formed through openings provided in the interlayer insulating film 56. Other configurations are the same as those of the MOSFET 20 shown in FIG.

(Method for producing graphene structure)
FIG. 12 schematically shows a method of manufacturing the graphene structure 1, wherein (a) is a pattern forming process of the graphene structure 1, (b) is a plasma CVD process, (c) is a cooling process, and (d) is the above process. FIG. 13 is an explanatory view of a plasma CVD apparatus 60, which is a graphene structure 1 manufactured by the method.
A specific manufacturing process is shown below.
The surface of the substrate 2 made of Si is oxidized to produce a silicon substrate with an oxide film. The thickness of the oxide film 7 is about 10 nm to 500 nm. The thickness of the oxide film 7 is, for example, 300 nm.

  Next, a pattern 58 including two electrodes and a linear region connecting these electrodes is formed using an electron beam exposure apparatus or the like. The pattern 58 is formed from a metal layer such as Ni formed on the oxide film by vacuum deposition or sputtering. This pattern 58 is a substantially English “I” -shaped pattern, and is hereinafter referred to as a Ni nanobar (see FIG. 12A). The thickness of the pattern 58 is about 30 to 100 nm. The width of the linear region is 5 to 100 nm, and the length is 200 to 1000 nm.

As shown in FIG. 13, the plasma CVD apparatus 60 includes a reaction tube 61, a plasma generation unit 62, a substrate holder 63 on which the substrate 2 is placed, an electric furnace 64 that heats the substrate 2, and a substrate holder 63. It comprises a transfer unit 65, a gas supply unit 66, a vacuum exhaust unit 67, and the like. The reaction tube 61 is made of a quartz tube or the like, and an electric furnace 64 is disposed at substantially the center of the reaction tube 61. A gas 68 is supplied from a gas supply unit 66 to the left end of the reaction tube 61 via a flange (not shown). The gas 68 to be supplied includes methane (CH ₄ ) 68 a and hydrogen (H ₂ ) 68 b for forming the graphene nanoribbon 5 and an inert gas 68 c for purging. The inert gas 68c is, for example, argon (Ar).

  The substrate holder 63 is made of a mica plate and is mounted on a transport unit 65 using stainless steel or the like. The position of the substrate holder 63 in the reaction tube 61 is adjusted by the transport unit 65.

  The plasma generator 62 includes a coil 62a wound around the outside of the reaction tube 61 and a high-frequency power source 62b connected to the coil 62a in order to generate so-called inductively coupled plasma. The frequency of the high frequency power supply 62b is, for example, 13.56 MHz.

  The vacuum exhaust unit 67 includes a vacuum pump 67a, a pressure gauge (not shown), a stop valve 67b, and the like, and is connected to the right end of the reaction tube 61 via a flange (not shown).

  Using the plasma apparatus 60 described in FIG. 13, the substrate 2 on which the pattern 58 has been formed is heated from room temperature to about 900 ° C. rapidly in an atmosphere of hydrogen 68b at a pressure of about 30 Pa.

  Thereafter, a mixed gas of methane 68a and hydrogen 68b (mixing ratio: 9/1) is supplied to the reaction tube 61 at a pressure of about 250 Pa.

  Immediately thereafter, high frequency power (about 100 W) is applied to the coil 62a installed outside the quartz tube 61 to generate inductively coupled plasma (see FIG. 12B).

  After performing the plasma irradiation for several seconds to several tens of seconds, the plasma is stopped, and the substrate 2 is moved from the high temperature portion of the reaction tube 61 to the low temperature portion while keeping the vacuum state and rapidly cooled (FIG. 12 (c)). reference).

  Thereby, nickel 59 of the nickel nanobar structure is partially evaporated, and a structure in which the graphene nanoribbon 5 is deposited is formed (see FIG. 12D). When the nickel nanobar structure, that is, the width of the linear portion of the pattern 58 becomes 100 nm or less, the nickel nanobar structure evaporates by plasma CVD. Thereby, the graphene nanoribbon 5 bridges the nickel electrode pair, that is, has a crosslinked structure, and the graphene structure 1 shown in FIG. 1 is manufactured. When a modification of the graphene structure shown in FIG. 10 is manufactured, the pattern 58 made of a metal layer may be a pattern 58 made of a linear region.

  According to the method for producing the graphene structure 1 of the present invention, the graphene nanoribbons 5 oriented in an arbitrary direction can be formed in an arbitrary region of the substrate 2. The composition of the graphene nanoribbon 5 and the first and second electrodes 3 and 4 may continuously change at the joint between the graphene nanoribbon 5 and the first and second electrodes 3 and 4. In addition, the width of the graphene nanoribbon 5 and the first and second electrodes 3 and 4 may continuously change at the joint between the graphene nanoribbon 5 and the first and second electrodes 3 and 4. That is, the joining portion may be configured in a substantially triangular shape that is wider toward the first and / or second electrodes 3 and 4 in plan view. Thus, when the width | variety of the graphene nanoribbon 5 and the 1st electrode 3 and / or the 2nd electrode 4 changes continuously, the 1st electrode 3 and / or the 2nd electrode from the graphene nanoribbon 5 The band gap of the graphene nanoribbon 5 changes continuously toward 4. The graphene structure 1 in which the band gap of the graphene nanoribbon 5 is inclined can be applied to an optical sensor, a solar cell, or the like corresponding to a plurality of wavelength regions. As an optical sensor, for example, it can be used as an optical sensor for infrared rays.

(First modification of manufacturing method of graphene structure)
In the above manufacturing method, the graphene nanoribbon 5 is deposited by the plasma CVD method, but the graphene nanoribbon 5 may be deposited by the CVD method or the like.
In the case of the CVD method, the graphene structure 1 can be manufactured by the following steps.
(1) An insulating film 7 is formed on the substrate 2,
(2) forming a metal layer on the insulating film 7;
(3) forming a pattern 58 of the graphene structure 1 made of a metal layer;
(4) The temperature of the substrate 2 is raised to a predetermined temperature, and then a gas 68 as a raw material for the graphene nanoribbon 5 is flowed to cool the temperature of the substrate 2 to a predetermined temperature, whereby the graphene structure 1 is manufactured.

(Second Modification of Graphene Structure Manufacturing Method)
In the case of the CVD method, local heating may be performed in the following steps without heating the entire substrate 2.
(1) An insulating film 7 is formed on the substrate 2,
(2) forming a metal layer on the insulating film 7;
(3) A pattern 58 of the graphene structure 1 made of a metal layer is formed, and a current is passed through the graphene structure 1 made of a metal layer in an atmosphere of a gas 68 as a raw material, thereby performing local heating. Thereafter, the graphene structure 1 is manufactured by cooling.

  In the first and second modifications of the method for manufacturing the graphene structure 1 described above, the heating temperature of the CVD can be set to 700 ° C. to 900 ° C., for example.

  In the first and second modified examples of the manufacturing method of the graphene structure 1 described above, the width of the graphene nanoribbon 5 of the graphene structure 1 is controlled by controlling the width of the pattern 58 of the graphene structure 1 made of a metal layer. You can control. The synthesis of the graphene nanoribbon 5 in the graphene structure 1 has the property that it starts from the narrowest part of the pattern 58 of the graphene structure 1 made of a metal layer. By utilizing this property, the shape of the pattern 58 of the graphene structure 1 made of a metal layer is appropriately designed, so that the graphene nanoribbons 5 can be selectively synthesized at any location without changing other electrode shapes. It becomes.

(Conduction type control method of graphene structure)
As the carrier conductivity type of the graphene nanoribbon 5 manufactured as shown in FIG. 12, an intrinsic semiconductor or a p-type semiconductor has been obtained so far. In order to change the conductivity type of the graphene nanoribbon 5 to n-type, as described above, after the graphene structure 1 is manufactured, the graphene nanoribbon 5 is treated with nitrogen plasma or ammonia plasma. Nitrogen can be added to the graphene nanoribbon 5, that is, doping can be performed only by changing the amounts of nitrogen and ammonia by this treatment.

  Boron (B), aluminum (Al), gallium (Ga), and indium (In) may be added to control the impurity density of the p-type semiconductor made of graphene nanoribbons.

(Method of manufacturing pn junction made of graphene structure)
When the conductivity type of the graphene nanoribbon 5 manufactured as shown in FIG. 12 is p-type, the portion to be the n-type graphene nanoribbon 15 may be treated with nitrogen plasma or ammonia plasma. Specifically, the graphene nanoribbon 5 manufactured as shown in FIG. 12 is masked except for the portion to be the n-type graphene nanoribbon 15. In this step, only the region to be the n-type graphene nanoribbon 15 is opened. After making this region n-type, the mask is etched away to form a pn junction in the graphene nanoribbon 5.

(Manufacturing method of MOS field effect transistor using graphene structure)
The MOSFET 20 using the oxide film of the silicon substrate with oxide film 2 as the gate insulating film 7a can be manufactured by forming the graphene structure 1 by the method shown in FIG.
Specifically, a predetermined region of the oxide film where the graphene structure 1 is not formed is opened, and a gate electrode 25 is formed in the gate opening. As the gate electrode 25, a metal such as Al or poly-Si can be used. Formation of these oxide films and electrodes, that is, patterning can be performed by photolithography and etching. As a deposition method of the gate electrode 25, an evaporation method or a sputtering method can be used.

  When changing the conductivity type of the graphene structure 1, the graphene structure 1 is manufactured by the method shown in FIG. 12, and then the graphene nanoribbon 5 that becomes a channel is processed by nitrogen plasma or ammonia plasma. Can be. After this step, the gate electrode 25 may be formed as described above.

  According to the method for manufacturing a transistor using the graphene structure 1 of the present invention, it is possible to realize integration of a transistor and a transistor using the graphene nanoribbon 5 oriented in an arbitrary direction in an arbitrary region on the substrate 2. In the present invention, a nickel nanobar structure is formed by electron beam drawing or the like on a substrate 2 on which a transistor made of graphene nanoribbons 5 is to be placed in advance, so that a transistor made of graphene nanoribbons 5 directed to an arbitrary method can be placed in an arbitrary place. It becomes possible to arrange.

(Manufacturing method of CMOS inverter using graphene structure)
As shown in FIG. 9, the source electrode 43, the output electrode 44 and the power electrode 47, the p-type graphene nanoribbon 16 formed between the source electrode 43 and the output electrode 44, the output electrode 44 and the power electrode 47, A pattern 58 made of n-type graphene nanoribbons 15 formed between them is formed of a metal such as Ni. In other processes, the plasma CVD process is performed in the same manner as in FIG. 12, and the graphene structure 1 is manufactured. One graphene nanoribbon 16 serves as a mask, and the conductivity type of the other graphene nanoribbon 16 is converted to n-type by, for example, nitrogen plasma or ammonia plasma treatment. Thereafter, the CMOS inverter 40 can be manufactured by manufacturing each electrode by multilayer wiring.

According to the manufacturing method of the CMOS inverter 40 using the graphene structure 1 of the present invention, the CMOS inverter 40 using the graphene nanoribbon 5 facing an arbitrary direction in an arbitrary region of the substrate 2 can be manufactured. For this reason, a NAND gate, a NOR gate, etc. can be manufactured by CMOS, and a so-called CMOS integrated circuit can be realized. Furthermore, in order to manufacture the single-electron transistor 30 of the present invention, a wide portion is formed in a part of the nickel 59 in which the nickel nanobar structure evaporates, and a residual metal 33 is left in the part, so You may make it form the Coulomb dot 32 in a location.
Hereinafter, the present invention will be described in more detail by way of examples.

  Below, the Example about the graphene structure 1 produced with the manufacturing method of this invention and MOSFET20 using this graphene structure 1 is shown.

(Production of graphene structure)
The graphene structure 1 described with reference to FIGS. 12 and 13 was manufactured. The oxide film had a thickness of 300 nm, and an electron beam exposure apparatus was used to form a pattern 58 made of Ni having a thickness of 85 nm.

  FIG. 14 shows a scanning electron microscope (SEM) image of a pattern 58 made of Ni, where (a) is a photograph taken at a low magnification, and (b) is a photograph taken at a high magnification. As shown in FIG. 14, it can be seen that a linear pattern 58 made of Ni and having a width of the order of nm is formed between the source electrode 23 and the drain electrode 24.

  As a result, a graphene structure 1 in which the nickel electrode pair was bridged by the graphene nanoribbon 5 was manufactured. A so-called back gate MOSFET 20 (see FIG. 4) using the graphene nanoribbon 5 as a conductive channel and an oxide film formed on the substrate 2 as a gate was also manufactured.

The produced graphene structure 1 was observed with a scanning electron microscope (SEM).
FIGS. 15A to 15H are SEM images showing various graphene structures 1 produced. In FIG. 15, the portion where Ni is exposed is indicated by Ni, and the graphene nanoribbon 5 is indicated by GNR. FIG.15 (c) is explanatory drawing of FIG.15 (b), and the location where the graphene nanoribbon 5 was twisted and formed in this way was also observed. FIGS. 15A to 15G are locations where the graphene nanoribbons 5 formed between the Ni electrodes are partially formed, and FIG. 15H is a graph where the graphene nanoribbons 5 are continuous between the Ni electrodes. The part formed automatically is shown.

The width of the graphene nanoribbon 5 shown in FIG. 15A (see W in FIG. 1A) was 77 nm, and the length (see L in FIG. 1A) was 381 nm.
The width of the graphene nanoribbon 5 shown in FIG. 15D was 58 nm, and its length was 158 nm.
The graphene nanoribbon 5 shown in FIG. 15 (e) was formed at two locations between the first and second electrodes 3 and 4 made of Ni, both having a width of 23 nm and lengths of 270 nm and 282 nm.
The width of the graphene nanoribbon 5 shown in FIG. 15F was 39 nm, and its length was 590 nm.
The graphene nanoribbon 5 shown in FIG. 15 (g) is formed at two locations between the first and second electrodes 3 and 4 made of Ni, as in FIG. 15 (e), and the width is 28 nm. The lengths were 468 nm and 928 nm. As shown in FIGS. 15E and 15G, a Ni electrode may be further formed between the first and second electrodes 3 and 4.
The graphene nanoribbon 5 shown in FIG. 15 (h) was formed at two locations, both having a width of 28 nm and lengths of 468 nm and 928 nm.
The dimensions of the graphene nanoribbon 5 are summarized in Table 1.

  The structure of the obtained sample was confirmed by Raman spectroscopy. A measuring device manufactured by Joban Yvon was used. As the excitation light source, a helium-neon (He / Ne) laser having a wavelength of 632.8 nm was used. The interval of the mapping measurement in the measured sample is 200 nm to 500 nm step.

FIGS. 16A and 16B show SEM images showing the measurement locations of Raman spectroscopy, where FIG. 16A is a photograph taken at a low magnification, and FIG. 16B is a photograph taken at a high magnification.
A portion indicated by an arrow (←) in FIG. 16B is a region where the graphene nanoribbon 5 (GNR) is formed. Furthermore, it can be seen that the width of the graphene nanoribbon 5 and the first and second metals 3 and 4 continuously change at the joint between the graphene nanoribbon 5 and the first and second metals 3 and 4. . It can be seen that the shape of this joint is formed in a substantially triangular shape that is wider toward the first and second metals 3 and 4 in plan view.

  FIG. 17 shows an image mapped by Raman spectroscopy, where (a) is Si, (b) is the D band of the graphene nanoribbon 5, (c) is the G band of the graphene nanoribbon 5, and (d) is the graphene nanoribbon 5. It is a signal from the 2D band.

FIG. 18 shows two typical examples of Raman spectral characteristics of the graphene nanoribbon 5, wherein (a) and (b) show the characteristics of the sample 1, and (c) show the characteristics of the sample 2. In sample 1, (a) is the low wave number side, and (b) is the high wave number side. The horizontal axis in FIG. 18 is the Raman shift wavenumber (cm ⁻¹ ), and the vertical axis is the signal intensity (arbitrary scale).
As shown in FIG. 18 (a), the peak of the D band derived from the defect has a wave number of 1292 to 1360 cm ⁻¹ , and the peak of the G band inherent to graphite has a wave number of 1544 to 1626 cm ⁻¹ . As shown in FIG. 18B, the 2D band peak derived from the double resonance Raman band has a wave number of 2577 to 2700 cm ⁻¹ . From FIG. 18, the graphene nanoribbon 5 of the manufactured graphene structure 1 has a large G-band peak and a D-band and a 2D-band peak. The characteristic of this spectral characteristic is in agreement with the Raman spectral characteristic of the graphene nanoribbon 5 reported.
Note that the peak indicated by “*” in FIG. 18B is a unique signal generated from the spectroscope itself and is not the spectral characteristic of the graphene nanoribbon.

  In the sample 2 shown in FIG. 18C, the ratio (= 2D / G) between the peak of the 2D band and the peak of the G band is 1.5, which is larger than that of the sample 1. This is presumed to be caused by the fact that the graphene of sample 1 is composed of a plurality of layers, whereas the graphene of sample 2 is composed of one or two layers. .

  When the connection region between the graphene nanoribbon 5 and Ni was measured by Raman spectroscopy, it was found that the composition gradually changed in the boundary region. This revealed that the inner linear region of the nickel nanobar structure was changed to the graphene nanoribbon 5.

  Further, it was found that the ratio (G / D) between the peak intensity of the D band and the peak intensity of the G band was about 1.6 or more in the region composed of the graphene nanoribbon 5 alone.

The X-ray analysis of the linear part of the nickel nanobar obtained in the example was measured with an energy dispersive X-ray analysis (also called EDX) analyzer added to the SEM.
FIG. 19 shows X-ray analysis results, (a) is an SEM image of the measurement region, (b) is an EDX line analysis result of the region where the graphene nanoribbons 5 are present, and (c) is an EDX of the region where Ni is present. It is a line analysis result. 19B and 19C, the horizontal axis indicates the position (arbitrary scale), and the vertical axis indicates the characteristic X-ray count (arbitrary scale).
When line analysis is performed in the direction from C to D in FIG. 19A, as shown in FIG. 19B, carbon is detected from the linear portion, and the Ni signal is below the detection limit. It was not observed.
Further, when the line analysis is performed in the direction from E to F in FIG. 19A, as shown in FIG. 19C, Ni is detected and the signal of C is below the detection limit. Not observed.
Also from the above measurement results, it was found that the linear portion of the Ni nanobar pattern 58 was converted from Ni into the graphene nanoribbon 5.

  From the results of the above-described Raman spectroscopy and elemental analysis by X-ray, it was found that the graphene nanoribbon 5 was formed in the linear portion of the nickel nanobar.

  As described above, the arrangement position of the nickel nanobars can be set to an arbitrary region by plasma CVD using high-speed heating and high-speed cooling. Moreover, since the graphene nanoribbon 5 is converted into a shape in which the linear portion of Ni is replaced as it is, its formation direction can be controlled.

FIG. 20 is a diagram showing SEM images showing the relationship between the line width of nickel nanobars and the line width of synthesized graphene nanoribbons 5, (a) to (h) are SEM images, and (i) are nickel nanobars. It is a figure which shows the relationship of the line | wire width of the line width of this, and the synthetic | combination graphene nanoribbon 5. FIG.
The relationship between the line width of the nickel nanobars and the line width of the synthesized graphene nanoribbons 5 is as follows.
(1) When the line width of the nickel nanobar was 50 nm, the line width of the synthesized graphene nanoribbon 5 was about 23 nm.
(2) When the line width of the nickel nanobar was 80 nm, the line width of the synthesized graphene nanoribbon 5 was about 37 nm to 87 nm.
(3) When the line width of the nickel nanobar was 120 nm, the line width of the synthesized graphene nanoribbon 5 was about 105 nm.
As shown in FIG. 20 (e), the width of the graphene nanoribbon can be controlled by controlling the width of the pattern 5 of the graphene structure 1 made of a metal layer, that is, the line width of the nickel nanobar.

FIG. 21 shows the graphene structure 1A floating between the electrodes shown in FIG. 2, where (a) is an SEM image, (b) is a Raman spectrum, (c) is a cross-sectional TEM image, and (d) is (c) ) Is an enlarged TEM image, and (e) is an enlarged TEM image of (d).
21A and 21C show that the graphene structure 1A is formed between the Ni electrodes, and FIG. 21D shows that the graphene nanoribbons 5 are floating from the insulating film 7. .
From the Raman spectrum of FIG. 21B, it was found that the ratio of the 2D peak to the G peak was 0.54.
From FIG. 21 (e), it can be seen that the graphene nanoribbons 5 are arranged in 5 to 10 layers at an interval of 0.34 nm.

FIG. 22 shows the structure of the graphene structure 1 formed radially, where (a) is an SEM image, (b) is a Raman spectrum, and (c) is an enlarged SEM image of (a).
As shown in FIG. 22, by forming a narrow region in the structure of Ni nanobars formed radially, the graphene nanoribbon 5 can be formed in any narrow region, and other Ni electrodes can be formed. It was found that the area can be maintained in the same state as the first.

FIG. 23 shows a structure in which a plurality of graphene structures 1 are provided between Ni electrodes, (a) is an SEM image, (b) is a Raman spectrum of (a), and (c) is an enlarged view of (a). It is a SEM image.
From FIG. 23, it was found that the graphene structure 1 composed of the plurality of graphene nanoribbons 5 was formed between the Ni electrodes by the structure in which the plurality of nickel bars were provided between the Ni electrodes.

(Measurement of MOSFET using graphene structure 1)
Next, characteristics of the back gate type MOSFET 20 using the graphene nanoribbon 5 as a conduction channel will be described.
The MOSFET 20 manufactured in the embodiment operates as a MOS gate field effect transistor by using one of the Ni electrodes as the source electrode 23, the other of the Ni electrodes as the drain electrode 24, and the conductive substrate 2 as the gate electrode 25. To do. The IV characteristics of the MOSFET 20 were measured. The MOSFET 20 was inserted into a vacuum chamber, each electrode was contacted by a probe, and IV characteristics were measured with a semiconductor parameter analyzer (Agilent Technology, Agilent 4155C).

FIG. 24 shows the measurement results of the MOSFET 20 using the graphene structure 1, wherein (a) shows the measured SEM image of the MOSFET 20 and (b) shows the Vgs-Ids characteristics at 13K. In the Vgs-Ids characteristic, the voltage (Vds) applied between the drain and the source was set to 500 mV.
As shown in FIG. 24A, the measured width of the graphene nanoribbon 5 of the MOSFET 20 was 33 nm. With respect to the IV characteristics of the MOSFET 20, Ids increased linearly with the increase of Vgs in the positive / negative of Vgs.

FIG. 25 is a diagram showing the temperature dependence of the minimum conductance (Gmin) of the MOSFET 20 of FIG. The horizontal axis of FIG. 25 is the reciprocal (K ⁻¹ ) of absolute temperature (T), and the vertical axis is Gmin (S).
The temperature dependence of the minimum conductance (Gmin) shown in FIG. 25 coincides with the characteristics of the graphene nanoribbon 5 formed by lithography. From this result, it was found that the width of the graphene nanoribbon 5 is narrow.

FIG. 26 shows IV characteristics of another MOSFET 20, (a) shows the measured SEM image of the MOSFET 20, and (b) shows Vgs-Ids characteristics at 13K and 300K. Vds is 50 mV.
As shown to Fig.26 (a), the width | variety of the graphene nanoribbon 5 of measured MOSFET20 is 23 nm, and it forms in order of Ni-graphene nanoribbon-Ni-graphene nanoribbon-Ni. That is, the Ni nanobars are partially converted into two graphene nanoribbons 5, and an island-like Ni bar exists between the two graphene nanoribbons 5.
The IV characteristics of the MOSFET 20 are bipolar characteristics in which current flows with positive and negative Vgs at 300K, and the on / off ratio is about 16.
On the other hand, the IV characteristics at 13K of the MOSFET 20 indicate that the drain current flows well when the negative voltage is increased, and the drain current does not flow easily at Vgs, and the on / off ratio is about 15,000 (1. A very large value of 5 × 10 ⁴ ) was obtained.

  The results of direct synthesis between devices by controlling the synthesis position and growth direction of graphene nanoribbons 5 were realized for the first time in the world, and further demonstrated that they have a clear on / off ratio. This is a direct result of actual device application.

  Further, at 300 K and 13 K, when Vgs was measured in the directions of the solid and dotted arrows in the figure, no hysteresis of Ids was measured. This indicates that the formed graphene nanoribbon 5 is in a very clean state.

FIG. 27 is a diagram showing the Vds dependence of the on-current, off-current, and on / off ratio of MOSFET 20 at 13K in FIG. In FIG. 27, the horizontal axis represents Vds (mV), the left vertical axis represents the on / off ratio, and the right vertical axis represents the on-current and off-current (A).
As is apparent from FIG. 27, it can be seen that the on / off ratio indicated by the x mark increases until Vds reaches 50 mV, and decreases when it exceeds 50 mV. This decrease in the on / off ratio is due to the saturation of the on-current indicated by Vds and at the same time the increase of the off-current indicated by a black square (■ mark). From this, it is estimated that the measured transport gap of the graphene nanoribbon 5 of the MOSFET 20 is about 50 mV.

  FIG. 28 is a diagram illustrating Ids with respect to Vds and Vgs on a log scale in the MOSFET 20 at 13K. The horizontal axis of FIG. 28 is Vgs (V), and the vertical axis is Vds (V). As is apparent from FIG. 28, the low current region has a substantially diamond shape surrounded by a dotted line. An off-current gap occurs when Vgs is −16 V in the Vds direction (see 2ΔVds in FIG. 28).

  FIG. 29 shows the IV characteristic of the low Vds of the MOSFET 20 at 13K. The horizontal axis is Vds (V), the left vertical axis is on-current Ids (pA), and the right vertical axis is off-current Ids (A). As is apparent from FIG. 29, 2ΔVds is 117 mV. From this, ΔVds is 58.5 mV, which is in good agreement with the transport gap determined in FIG.

(Measurement of multi-channel MOSFET)
The current-voltage characteristics of a multichannel MOSFET 20A that was prototyped with 10 to 20 graphene nanoribbons serving as channels were measured.
FIG. 30 is a diagram illustrating Vgs-Ids characteristics of the multichannel MOSFET 20A at 300K. The voltage (Vds) applied between the drain and the source was 10 mV. The horizontal axis is Vgs (V), and the vertical axis is the source-drain current Ids (nA).
From FIG. 30, it was found that the current driving force is increased in the multichannel MOSFET 20 </ b> A as compared with the MOSFET 20 including the graphene nanoribbon 5 having one channel.

(Measurement of single electron transistor)
FIG. 31 shows the Vgs- _Ids characteristic of the single electron transistor 30 at 30K. In FIG. 31, the horizontal axis represents Vgs (V), and the vertical axis represents current Ids (1 × 10 ⁻¹¹ A). Vds is 5 mV.
As is clear from FIG. 31, a current (Ids) flows through the graphene nanoribbon 5 at Vgs indicated by an arrow (↓) in the figure. Thereby, a so-called Coulomb vibration characteristic in which Ids vibrates with respect to Vgs is obtained. This is a phenomenon in which on / off of the current is changed by charging and discharging a Coulomb barrier in the graphene nanoribbon 5 with one electron, and as a single electron transistor 30 that controls on / off with one electron. This is to demonstrate the operation. As a result of observing the single electron transistor 30 measured in FIG. 31 with SEM, the residual electrode 33 (see FIG. 7B) was not observed on the graphene nanoribbon 5. From this, it is presumed that the Coulomb dot 32 of the single electron transistor 30 measured in FIG. 31 is derived from the defect 5a at the edge of the graphene nanoribbon 5 as shown in FIG.

When the dimensions of the MOS transistor of the present invention are 30 nm in width and 500 nm in length, the number of transistors per 1 μm ² is about 100, and the integration density can be improved to about 10 times that of current Si transistors. it can. When the size of the MOS transistor of the present invention is reduced to 10 nm in width and 50 nm in length, the number of transistors per 1 μm ² is about 2000, which is several hundred times that of a Si transistor having a current minimum processing size of 45 nm. Is expected to be possible to integrate. These are summarized in Table 2.

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope of the invention described in the claims, and it goes without saying that these are also included in the scope of the present invention. .

DESCRIPTION OF SYMBOLS 1,1A: Graphene structure 2: Board | substrate 3: 1st electrode 4: 2nd electrode 5: Graphene nanoribbon 5a: Defect of edge of graphene nanoribbon 7: Insulating film 7a: Gate insulating film 8: Air gap 10: Semiconductor device 15: p-type graphene nanoribbon 16: n-type graphene nanoribbon 20, 20A: MOSFET
23, 28, 43, 47, 53: Source electrodes 24, 29, 44, 54: Drain electrodes 25, 45, 45 ', 55: Gate electrode 27: Spin semiconductor transistor 30: Single electron transistor 32: Coulomb dot 33: Residual Metal 35: Inverter 36: Graphene nanoribbon for resistance 37: Electrode for power supply 40: CMOS inverter 41: n-channel MOSFET
42: p-channel MOSFET
50: MOSFET using a modification of graphene structure
56: Interlayer insulating film 58: Pattern 59: Ni evaporated
60: Plasma CVD apparatus 61: Reaction tube 62: Plasma generating part 62a: Coil 62b: High frequency power supply 63: Substrate holder 64: Electric furnace 65: Transfer part 66: Gas supply part 67: Vacuum exhaust part 67a: Vacuum pump 67b: Stop Valve 68: Gas 68a: Methane 68b: Hydrogen 68c: Inert gas

Claims (19)

A substrate, and a graphene nanoribbon formed on the substrate,
The graphene nanoribbon has a width of 100 nm or less in which a forbidden body width as a semiconductor is generated. A substrate, a first electrode formed on the substrate, a graphene nanoribbon formed on the substrate, and a second electrode formed on the substrate,
The first electrode and one end of the graphene nanoribbon are connected,
The other end of the graphene nanoribbon and the second electrode are connected,
The graphene nanoribbon has a width of 100 nm or less in which a forbidden body width as a semiconductor is generated.   The graphene structure according to claim 1, wherein the substrate is a substrate with an insulating film.   The graphene structure according to claim 2, wherein the electrode is made of any one of Ni, Cu, Co, Fe, Au, Pd, Al, and Pt.   The graphene structure according to claim 1 or 2, wherein the forbidden body width of the graphene nanoribbon is 10 to 1000 meV.   The graphene structure according to claim 1 or 2, which has a D band, a G band, and a 2D band in Raman spectral characteristics of the graphene nanoribbon.   The composition of the graphene nanoribbon and the first and / or second electrode continuously changes at a joint between the graphene nanoribbon and the first and / or second electrode. Graphene structure.   The width of the graphene nanoribbon and the first and / or second electrode continuously changes at a joint between the graphene nanoribbon and the first and / or second electrode. Graphene structure.   3. The graphene structure according to claim 1, wherein the graphene nanoribbon is disposed with a gap between the graphene nanoribbon and the substrate.   A semiconductor device using the graphene structure according to claim 1.   The semiconductor device according to claim 10, wherein the semiconductor device includes a pn junction made of graphene nanoribbons.   The semiconductor device according to claim 10, wherein the semiconductor device includes a MOSFET including a gate insulating film formed on the substrate and a channel made of graphene nanoribbons.   The semiconductor device according to claim 12, wherein the semiconductor device includes a complementary MOSFET.   The semiconductor device according to claim 10, wherein the semiconductor device is a spin semiconductor transistor that is spin-injected from an electrode formed on the substrate.   The semiconductor device according to claim 12, comprising a plurality of channels. A method for producing a graphene structure according to any one of claims 1 to 9,
An insulating film is formed on the substrate,
Forming a metal layer on the insulating film;
Forming a graphene structure pattern composed of the metal layer,
Raise the temperature of the substrate to a predetermined temperature, then generate a plasma discharge consisting of raw material gas of graphene nanoribbons,
A method for producing a graphene structure, wherein the temperature of the substrate is cooled to a predetermined temperature to obtain a graphene structure. A method for producing a graphene structure according to any one of claims 1 to 9,
An insulating film is formed on the substrate,
Forming a metal layer on the insulating film;
Forming a graphene structure pattern composed of the metal layer,
Raise the temperature of the substrate to a predetermined temperature, then flow graphene nanoribbon source gas,
A method for producing a graphene structure, wherein the temperature of the substrate is cooled to a predetermined temperature to obtain a graphene structure. A method for producing a graphene structure according to any one of claims 1 to 9,
An insulating film is formed on the substrate,
Forming a metal layer on the insulating film;
A pattern of the graphene structure composed of the metal layer is formed, and in a source gas atmosphere, a current is passed through the graphene structure composed of the metal layer to perform local heating, followed by cooling to obtain a graphene structure. Manufacturing method of graphene structure.   The method for producing a graphene structure according to claim 16, wherein a region having a narrow line width is provided in the pattern.