JP2012256690A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory capable of easily being manufactured and equipped with a cell transistor which can drive a current sufficiently large for writing data into an MTJ element.SOLUTION: A memory of a present embodiment comprises: an active area; cell transistors formed in the active area; MTJ elements with one ends each electrically connected to one of source/drain of the cell transistor; a first bit line electrically connected to the other of the source/drain of the cell transistor; second bit lines electrically connected to the other ends of the MTJ elements; and word lines each electrically connected to a gate of the cell transistor, or serving as the gate of the cell transistor. The plurality of second bit lines corresponds to one first bit line. The MTJ elements share the same word line and the same active area. The active area is formed continuously in an extension direction of the first and the second bit lines.

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  One of the resistance change type memories is a magnetic random access memory (MRAM). The MRAM writing method includes a magnetic field writing method and a spin injection writing method. Among these, the spin injection writing method has the property that the smaller the size of the magnetic material, the smaller the spin injection current necessary for the magnetization reversal, which is advantageous for high integration, low power consumption and high performance. .

Conventionally, a plurality of MTJ elements sharing a word line are arranged on different active areas, and cell transistors are provided on both sides of each MTJ element. Then, when accessing a certain MTJ element, the two cell transistors on both sides of the MTJ element become conductive and current flows through the MTJ element. Since the gate width of one cell transistor is 2F (F is Feature Size), the total gate width of the two cell transistors is 4F. In addition, the size of the memory cell was 12F ^2.

  In order to write data to the MTJ element of the spin injection writing method, a current equal to or higher than the inversion threshold current must be passed through the MTJ element. In order to flow a current sufficiently larger than the inversion threshold current to the MTJ element, it is desired to further increase the gate width of the cell transistor.

  Further, in order to increase the gate width of the cell transistor, an active area having a large area is required. However, it is difficult to manufacture the active area having a large area with a thin STI.

JP 2010-16193 A

  Provided is a semiconductor memory device which includes a cell transistor capable of driving a sufficiently large current for writing data to an MTJ element and can be easily manufactured.

  The semiconductor memory device according to the present embodiment includes a semiconductor substrate and an active area formed on the semiconductor substrate. The cell transistor is formed in the active area. One end of the magnetic tunnel junction element is electrically connected to one of the source and drain of the cell transistor. The first bit line is electrically connected to the other of the source and the drain of the cell transistor. The second bit line is electrically connected to the other end of the magnetic tunnel junction element. The word line is electrically connected to the gate of the cell transistor or functions as the gate of the cell transistor. A plurality of second bit lines correspond to one first bit line. A plurality of magnetic tunnel junction elements share the same word line and the same active area. The active area is formed continuously in the extending direction of the first and second bit lines.

The block diagram which shows the memory chip of MRAM according to 1st Embodiment. 3 is an explanatory diagram showing a configuration of a single memory cell MC. FIG. FIG. 4 is a partial plan layout diagram of the memory cell array MCA of the MRAM according to the first embodiment. FIG. 4 is a cross-sectional view taken along line 4-4 of FIG. Sectional drawing along line 5-5 in FIG. Sectional drawing along line 6-6 in FIG. FIG. 10 is a partial plan layout diagram of an MRAM memory cell array MCA according to a second embodiment. Sectional drawing along line 8-8 in FIG. Sectional drawing along line 9-9 in FIG.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a block diagram showing a memory chip of a magnetic random access memory (hereinafter referred to as MRAM) according to the first embodiment. The present embodiment can also be applied to a memory (for example, PCRAM, RRAM, etc.) using a resistance variable element other than MRAM.

  The MRAM according to the present embodiment includes a memory cell array MCA, a sense amplifier SA, a main data controller MDC, a DQ buffer DQB, a column controller CC, a row controller RC, a clock buffer CLKB, a command controller CMDC, and an address controller. An ADDC and an array controller AC are provided.

  The memory cell array MCA includes a plurality of memory cells MC that are two-dimensionally arranged in a matrix. Each memory cell MC is arranged corresponding to the intersection of the bit line BL (or bit line pair) and the word line WL. The bit line BL extends in the column direction. The word line WL extends in the row direction orthogonal to the column direction.

  The sense amplifier SA is connected to the memory cell MC via the bit line BL, and is configured to detect data in the memory cell MC. The write driver WD is connected to the memory cell MC via the bit line BL, and is configured to write data to the memory cell MC.

  The main data controller MDC transfers the data received from the DQ buffer DQB to the write driver WD so as to write to the desired column under the control of the column controller CC, or receives the desired data under the control of the column controller CC. The data read from the first column is transferred to the DQ buffer DQB. Further, as will be described later, the main data controller MDC is configured to prohibit data writing in accordance with the write mask data WM or the write prohibited area address WOADD.

  The DQ buffer DQB temporarily holds read data via the DQ pad DQ, and outputs the read data to the outside of the memory chip 1. Alternatively, the DQ buffer DQB receives write data from the outside of the memory chip 1 via the DQ pad DQ and temporarily holds it.

  The column controller CC operates the sense amplifier SA or the write driver WD so as to selectively drive the bit line BL of a desired column according to the column address.

  The row controller RC operates the word line driver WLD so as to selectively drive a desired word line WL according to the row address.

  The clock buffer CLKB receives a clock signal that determines the operation timing of the entire memory chip 1.

  The command controller CMDC receives commands indicating various operations such as a read operation and a write operation, and controls the column controller CC and the row controller RC according to those commands.

  The address controller ADDC receives a row address and a column address, decodes these addresses, and sends these addresses to the column controller CC and the row controller RC.

  The array controller AC performs overall control of the memory cell array MCA.

  FIG. 2 is an explanatory diagram showing a configuration of a single memory cell MC. Each memory cell MC includes a magnetic tunnel junction element (MTJ (Magnetic Tunnel Junction) element) and a cell transistor CT. The MTJ element and the cell transistor CT are connected in series between the bit line BL and the source line SL. In the memory cell MC, the cell transistor CT is disposed on the bit line BL side, and the MTJ element is disposed on the source line SL side. The gate of the cell transistor CT is connected to the word line WL.

  An MTJ element using the TMR (tunneling magnetoresistive) effect has a laminated structure composed of two ferromagnetic layers and a nonmagnetic layer (insulating thin film) sandwiched between them, and exhibits magnetoresistance due to the spin-polarized tunnel effect. Stores digital data with changes. The MTJ element can take a low resistance state and a high resistance state depending on the magnetization arrangement of the two ferromagnetic layers. For example, if the low resistance state is defined as data “0” and the high resistance state is defined as data “1”, 1-bit data can be recorded in the MTJ element. Of course, the low resistance state may be defined as data “1”, and the high resistance state may be defined as data “0”. For example, the MTJ element is configured by sequentially laminating a fixed layer, a tunnel barrier layer, and a recording layer. The fixed layer P and the recording layer Fr are made of a ferromagnetic material, and the tunnel barrier layer is made of an insulating film. The fixed layer P is a layer whose magnetization direction is fixed, and the recording layer Fr has a variable magnetization direction, and stores data according to the magnetization direction.

  When a current equal to or greater than the reversal threshold current is passed in the direction of the arrow A1 during writing, the recording layer Fr is in an anti-parallel state with respect to the magnetization direction of the fixed layer P, and is in a high resistance state (data “1”). When a current equal to or greater than the inversion threshold current is passed in the direction of the arrow A2 at the time of writing, the magnetization directions of the fixed layer P and the recording layer Fr are in a parallel state and a low resistance state (data “0”). Thus, the TMJ element can write different data depending on the direction of current.

  FIG. 3 is a partial plan layout view of the memory cell array MCA of the MRAM according to the first embodiment. 4 is a cross-sectional view taken along line 4-4 of FIG. FIG. 5 is a cross-sectional view taken along line 5-5 of FIG. 6 is a cross-sectional view taken along line 6-6 of FIG.

  In the MRAM according to the present embodiment, as shown in FIG. 3, the first bit line BL1 and the second bit line BL2 extend in the column direction, and the word line WL extends in the row direction substantially orthogonal to the column direction. is doing. The first bit line BL1 is electrically connected to the cell transistor CT via the via contact V2, and the second bit line BL2 is electrically connected to the upper end of the MTJ element. A plurality of second bit lines BL2 corresponding to a plurality of MTJ elements arranged in the row direction are provided corresponding to one first bit line BL1, and one first bit line BL1. Share.

  In the planar layout, a plurality of MTJ elements are provided between two adjacent word lines WL. MTJ elements provided between two adjacent word lines WL share the two word lines WL. The two word lines WL function as the gate electrode GC of the cell transistor CT, and become conductive when one of the MTJ elements provided between the two word lines WL is selected.

  The active area AA extends continuously in the column direction in the memory cell array MCA. Therefore, the MTJ elements arranged in the column direction share the active area AA. The active areas AA are separated by element isolation regions STI (Shallow Trench Isolation) in the row direction.

  As shown in FIGS. 5 and 6, the MRAM according to the present embodiment includes a silicon substrate 10 as a semiconductor substrate and an active area AA formed on the silicon substrate 10. The cell transistor CT formed on the active area AA includes a source layer S, a drain layer D, and a gate electrode GC. The gate electrode GC is insulated from the silicon substrate 10 by the gate insulating film 20, and insulated from the contact plug CB by the insulating film 30.

  As shown in FIG. 5, a contact plug CB is provided on the source layer S of the cell transistor CT. A lower electrode LE is provided on the contact plug CB, and an MTJ element is provided on the lower electrode LE. Thus, the source layer S of the cell transistor CT is electrically connected to the lower end of the MTJ element via the contact plug CB and the lower electrode LE. Further, an upper electrode UE is provided on the MTJ element, and a via contact V1 is provided on the upper electrode UE. A second bit line BL2 is provided on the via contact V1. Thus, the upper end of the MTJ element is connected to the second bit line BL2 via the upper electrode UE and the via contact V1.

  On the other hand, as shown in FIG. 6, another contact plug CB is provided on the drain layer D of the cell transistor CT. A via contact V1 is provided on the contact plug CB. As a result, the drain layer D of the cell transistor CT is electrically connected to the first bit line BL1 via the contact plug CB and the via contact V1.

  Therefore, as shown in FIGS. 5 and 6, the source layer S of the cell transistor CT is electrically connected to the lower end of the MTJ element, and the drain layer D of the cell transistor CT is electrically connected to the first bit line BL1. It is connected to the. The upper end of the MTJ element is electrically connected to the second bit line BL2. Thus, the MTJ element and the cell transistor CT are connected in series between the first bit line BL1 and the second bit line BL2.

  As shown in FIG. 4, the lower ends of a plurality of MTJ elements adjacent in the row direction are electrically short-circuited by a contact plug CB extending in the row direction. The source layer S of the cell transistor CT is also formed along the contact plug CB under the contact plug CB. Accordingly, cell transistors CT having a large channel width extending in the row direction are provided below the two word lines WL on both sides of the plurality of MTJ elements shown in FIG. In other words, the plurality of cell transistors CT arranged in the row direction and connected to the plurality of MTJ elements sharing the word line WL and the active area AA may be connected in parallel in the gate width direction. Note that the contact plug CB is preferably formed of a low-resistance metal (for example, Cu, W, etc.) in order to reduce the resistance difference at both ends in the gate width direction of the cell transistor CT.

  The plurality of MTJ elements provided between two adjacent word lines WL shown in FIG. 3 share the two word lines WL on both sides of the MTJ elements and have the same active area AA. Will share. Accordingly, the plurality of MTJ elements are connected to the different second bit lines BL2 at the upper ends thereof, but are commonly connected to the two cell transistors CT provided on both sides of the plurality of MTJ elements at the lower ends thereof. Has been.

  Note that the names of the source layer S and the drain layer D of the cell transistor CT are for convenience, and the positional relationship between the source layer S and the drain layer D may be reversed depending on the direction of current flow. Further, although the gate electrode GC itself of the cell transistor CT may function as the word line WL, the word line WL may be provided in a layer different from the gate electrode GC. In this case, the gate electrode GC is electrically connected to one of the word lines WL through a contact (not shown).

  As described above, in the MRAM according to the present embodiment, a plurality of MTJ elements are provided between two adjacent word lines WL and share the two word lines WL. The cell transistors CT corresponding to the two word lines WL are provided on the same active area AA, and are commonly connected to a plurality of MTJ elements provided between the two word lines WL. A plurality of cell transistors CT corresponding to one of the two word lines WL are connected in parallel (or one cell transistor CT having a wide gate width is provided), and the cell transistor CT corresponding to the other is also connected in parallel. (Or one cell transistor CT having a wide gate width is provided). With such a configuration, the MRAM according to the present embodiment can provide the cell transistor CT having a wide gate width on both sides of the MTJ element. In other words, the plurality of MTJ elements provided between the two word lines WL are not connected to the individual cell transistors corresponding to each, but are connected to the common cell transistor CT having a wide gate width. The gate width of each cell transistor CT corresponding to two adjacent word lines WL is substantially equal to the width Waa of the active area AA in the row direction. Accordingly, the cell transistor CT can supply a sufficiently large current to any selected MTJ element among the plurality of MTJ elements provided between the two word lines WL.

Further, in the example shown in FIG. 3, the four second bit lines BL2 commonly use one first bit line BL1, and four MTJs provided between the two word lines WL. The cell transistor CT corresponding to the element is shared. Therefore, the area of the unit pattern UP indicated by the broken line in FIG. 3 is 40F ² . The unit pattern UP is a pattern indicating one unit of the planar layout, and the planar layout of the memory cell array MCA is formed by repeating this pattern in the plane of the silicon substrate 10. Here, F (Feature Size) is a minimum processing dimension using a lithography technique and an etching technique. Since one unit pattern UP includes four MTJ elements, the area per one MTJ element is 10F ² . The gate width of the cell transistor CT is equal to the width of the active area AA in the row direction and is 10F. Since the cell transistors CT are provided on both sides of the MTJ element, the total gate width of the two cell transistors CT is 20F.

In the conventional MRAM, the area of the memory cell is usually 12F ² , and the gate width of the cell transistor per memory cell is 4F.

  Therefore, the MRAM according to the present embodiment can reduce the area per MTJ element (or memory cell) and increase the gate width of the cell transistor per MTJ element (memory cell).

  Thereby, even if the current required for data writing is large, the MRAM according to the present embodiment can supply a sufficient current for writing to the MTJ element. Even if the current required for data writing is small, the MRAM according to the present embodiment can perform stable writing with a large current.

In the present embodiment, the number of MTJ elements that share two adjacent word lines WL and share the active area AA is four. However, the number of MTJ elements may be further increased. In that case, the width Waa of the active area AA in the row direction may be increased. Even if the number of MTJ elements sharing the word line WL and the active area AA increases, the layout area of the first bit line BL1 and the via contact V2 (8F ^{2 in} the example of FIG. 3) does not change. Therefore, as the number of MTJ elements sharing the word line WL and the active area AA increases, the influence of the layout area of the first bit line BL1 and the via contact V2 on the area per MTJ element is reduced. In the example shown in FIG. 3, if the number of MTJ elements sharing the word line WL and the active area AA is increased infinitely, the area per MTJ element converges to 8F ² .

  Furthermore, the active area AA of the MRAM according to the present embodiment is continuously formed in the column direction and is not separated into a plurality by the element isolation region STI. Therefore, the active area AA of the MRAM according to the present embodiment can be easily formed by the lithography technique and the etching technique.

  As described above, the MRAM according to the present embodiment has a small memory cell area, can pass a sufficiently large current for writing data to the MTJ element, and can be manufactured more easily than in the past.

  In the MRAM having the above configuration, the MTJ element is selectively driven as follows.

(Write operation)
For example, when writing data to the MTJ element MTJsel shown in FIG. 3, the write driver WD applies the write voltage Vwrite to the first bit line BL1, and the voltage Vout to the bit line BL2sel among the plurality of second bit lines BL2. Apply. As the voltage Vwrite, a power supply voltage is usually used, and as the voltage Vout, 0 V (GND) is usually used. Further, the word line driver WLD drives the word lines WL0 and WL1 on both sides of the MTJ element MTJsel, thereby turning on the plurality of cell transistors CT corresponding to the word lines WL0 and WL1. Accordingly, the plurality of cell transistors CT corresponding to the word lines WL0 and WL1 can supply current to the MTJ element MTJsel. In the present embodiment, the total gate width of the cell transistors CT is as wide as 20 F, so that a sufficiently large current can be supplied to the MTJ element MTJsel.

  On the other hand, the write driver WD has the voltage of the second bit line BL2 other than the second bit line BL2sel between the write voltage Vwrite of the first bit line BL1 and the voltage Vout of the second bit line BL2sel. The voltage is fixed to a predetermined voltage Vwmed. The voltage Vwmed is set so that the voltage difference between the upper and lower ends of the non-selected MTJ elements other than the MTJ element MTJsel is as close to zero as possible. This is to prevent data from being written to the non-selected MTJ element. In general, the voltage Vwmed can be calculated in consideration of the resistance from the first bit line BL1 to the lower end of the MTJ element and the resistance from the second bit line BL2 to the upper end of the MTJ element. Alternatively, the voltage Vwmed may be obtained experimentally using an actual product. Even if the voltage Vwmed is an intermediate value (| Vwrite−Vout | / 2) between the write voltage Vwrite and the voltage Vout, if data is not written to the non-selected MTJ element and this does not cause a problem, the voltage Vwmed is set as the voltage Vwmed. The intermediate value (| Vwrite−Vout | / 2) may be used.

  Thus, the MRAM according to the present embodiment can select one memory cell MCsel while a plurality of MTJ elements share the same word line WL and the same active area AA.

  The selected MTJ element MTJsel is connected between the first bit line BL1 and the second bit line BL2sel, and the MTJ element MTJsel includes the first bit line BL1 and the second bit line BL2sel. Current flows due to the voltage difference between the two (| Vwrite−Vout |). With this current, data is written into the selected MTJ element MTJsel.

  In this manner, the MRAM according to the present embodiment can selectively write data to the MTJ element MTJsel. In the above writing operation, when data opposite to the data to be written is written, the voltage application direction may be reversed from the voltage application direction. That is, the voltage Vwrite may be applied to the second bit line BL2sel and the voltage Vout may be applied to the first bit line BL1.

  When writing data to the MTJ element MTJsel, the non-selected second bit line BL2 can write data to the MTJ element MTJsel even if it is in a floating state. However, in this case, since the non-selected second bit line BL2 is also charged through the cell transistor CT, the voltage application speed to the MTJ element MTJsel is increased by the capacity of the non-selected second bit line BL2. Become slow. Therefore, in consideration of the operation speed, the voltage of the non-selected second bit line BL2 is preferably fixed to the predetermined voltage Vwmed.

(Read operation)
For example, when reading data from the MTJ element MTJsel, the sense amplifier SA as a driver applies a read voltage Vread to the first bit line BL1. Further, the word line driver WLD drives the word lines WL0 and WL1 on both sides of the MTJ element MTJsel, thereby bringing the cell transistors CT corresponding to the word lines WL0 and WL1 into a conductive state. Accordingly, the plurality of cell transistors CT corresponding to the word lines WL0 and WL1 can supply current to the MTJ element MTJsel.

  The MTJ element MTJsel is connected between the first bit line BL1 and the second bit line BL2sel, and the MTJ element MTJsel has a voltage difference between the first bit line BL1 and the second bit line BL2sel. Current flows by (| Vread−Vout |). Then, the sense amplifier SA may detect the current Icell flowing through the second bit line BL2sel connected to the selected MTJ element MTJsel. Note that the power supply voltage is normally used as the voltage Vwrite, and 0 V (GND) is usually used as the voltage Vout.

  At this time, the write driver WD sets the voltage of the second bit line BL2 other than the second bit line BL2sel between the read voltage Vread of the first bit line BL1 and the voltage Vout of the second bit line BL2sel. The voltage is fixed to a predetermined voltage Vrmed. The voltage Vrmed is set so that the voltage difference between the upper and lower ends of the non-selected MTJ elements other than the MTJ element MTJsel is as close to zero as possible. This is to prevent the data stored in the non-selected MTJ element from being disturbed during reading. The method for setting the voltage Vrmed is as described above. If the voltage Vrmed is an intermediate value (| Vread−Vout | / 2) between the read voltage Vread and the voltage Vout, the data of the non-selected MTJ element is not disturbed and does not cause a problem. The intermediate value (| Vread−Vout | / 2) may be used as Vrmed.

  When reading data from the MTJ element MTJsel, the non-selected second bit line BL2 can read data from the MTJ element MTJsel even if it is in a floating state. However, in this case, since the non-selected second bit line BL2 is also charged through the cell transistor CT, the voltage application speed to the MTJ element MTJsel is increased by the capacity of the non-selected second bit line BL2. Become slow. Therefore, in consideration of the operation speed, the voltage of the non-selected second bit line BL2 is preferably fixed to the predetermined voltage Vrmed.

(Second Embodiment)
FIG. 7 is a partial plan layout view of the memory cell array MCA of the MRAM according to the second embodiment. 8 is a cross-sectional view taken along line 8-8 in FIG. FIG. 9 is a cross-sectional view taken along line 9-9 in FIG. Note that the cross-sectional view taken along line 4-4 of FIG. 7 is the same as that shown in FIG.

  The second embodiment further includes an element isolation word line WLiso that is provided between a plurality of MTJ elements adjacent in the column direction and always insulates between the plurality of MTJ elements. A plurality of MTJ elements are arranged in the row direction on both sides of the element isolation word line WLiso. The plurality of MTJ elements share the word line WL provided on one side of the MTJ element, the element isolation word line WLiso provided on the other side of the MTJ element, and the active area AA.

  The element isolation word line WLiso is fixed at, for example, 0 V, and electrically insulates MTJ elements on both sides of the element isolation word line WLiso. Therefore, the plurality of MTJ elements on both sides of the element isolation word line WLiso can be controlled independently. The element isolation word line WLiso has the same configuration as other normal word lines WL, except that the applied voltage is different.

  Other configurations of the second embodiment may be the same as the configurations of the first embodiment.

  Thus, in the MRAM according to the second embodiment, a plurality of MTJ elements are provided on both sides of the element isolation word line WLiso. The plurality of MTJ elements provided on one side of the element isolation word line WLiso are provided between the element isolation word line WLiso and the first word line WL1, and the first word line WL1 and the element isolation word line WLiso Share. The plurality of MTJ elements provided on the other side of the element isolation word line WLiso are provided between the element isolation word line WLiso and the second word line WL2, and the second word line WL2 and the element isolation word line Share WLiso.

  Cell transistors CT1 and CT2 corresponding to two word lines WL1 and WL2 on both sides of one element isolation word line WLiso are provided on the same active area AA. However, the cell transistors CT1 and CT2 are electrically isolated from each other by the element isolation word line WLiso. The cell transistors CT1 and CT2 have a wide gate width similarly to the cell transistor CT of the first embodiment. The gate widths of the cell transistors CT1 and CT2 are substantially equal to the width Waa in the row direction of the active area AA. Therefore, the cell transistor CT1 can supply a sufficiently large current to any selected MTJ element among the plurality of MTJ elements provided between the word line WL1 and the cell transistor CT1. The cell transistor CT2 can supply a sufficiently large current to any MTJ element selected from among a plurality of MTJ elements provided between the word line WL2 and the cell transistor CT2. However, since the MTJ element corresponding to the cell transistor CT1 and the MTJ element corresponding to the cell transistor CT2 share the second bit line BL2, they correspond to the cell transistors CT1 and CT2 in the data write or read operation. One MTJ element is selected from a plurality of MTJ elements.

The area of the unit pattern UP indicated by the broken line in FIG. 7 is 30F ² . Since one unit pattern UP includes four MTJ elements, the area per one MTJ element is 7.5F ² . The gate width of the cell transistor CT is equal to the width of the active area AA in the row direction and is 10F.

  Therefore, the MRAM according to the second embodiment can also reduce the area per MTJ element (or memory cell) and increase the gate width of the cell transistor per MTJ element (memory cell). .

  Thereby, 2nd Embodiment can acquire the effect similar to 1st Embodiment.

In the second embodiment, the number of MTJ elements between the word line WL1 and the cell transistor CT1 and the number of MTJ elements between the word line WL2 and the cell transistor CT2 are four, respectively. However, the number of MTJ elements may be further increased. In that case, the width Waa of the active area AA in the row direction may be increased. In this case, the influence of the layout area of the first bit line BL1 and the via contact V2 on the area per MTJ element is reduced. In the example shown in FIG. 7, if the number of MTJ elements sharing the word line WL and the active area AA is increased infinitely, the area per one MTJ element converges to 6F ² .

  In the MRAM having the above configuration, the MTJ element is selectively driven as follows.

(Write operation)
For example, when writing data to the MTJ element MTJsel shown in FIG. 7, the write driver WD applies the write voltage Vwrite to the first bit line BL1, and the voltage Vout to the bit line BL2sel among the plurality of second bit lines BL2. Apply. The word line driver WLD drives the word line WL1 on one side of the MTJ element MTJsel, thereby bringing the cell transistor CT1 corresponding to the word line WL1 into a conductive state. Thereby, the cell transistor CT1 corresponding to the word line WL1 can supply current to the MTJ element MTJsel. Since the gate width of the cell transistor CT is as wide as 10 F, a sufficiently large current can be supplied to the MTJ element MTJsel.

  The MTJ element MTJsel is connected between the first bit line BL1 and the second bit line BL2sel, and the MTJ element MTJsel has a voltage difference between the first bit line BL1 and the second bit line BL2sel. Current flows by (| Vwrite-Vout |). With this current, data is written into the selected MTJ element MTJsel. Note that the power supply voltage is normally used as the voltage Vwrite, and 0 V (GND) is usually used as the voltage Vout.

  At this time, the element isolation word line WLiso is fixed at 0 V, for example, and electrically isolates MTJ elements on both sides thereof.

  On the other hand, the write driver WD fixes the voltage of the second bit line BL2 other than the second bit line BL2sel to the predetermined voltage Vwmed. The voltage Vwmed is as described above.

  In this manner, the MRAM according to the present embodiment can selectively write data to the MTJ element MTJsel. In addition, when writing data having an opposite logic to the above data, the voltage application direction may be reversed to the voltage application direction.

(Read operation)
For example, when reading data from the MTJ element MTJsel, the sense amplifier SA as a driver applies a read voltage Vread to the first bit line BL1. The word line driver WLD drives the word line WL1 on one side of the MTJ element MTJsel, thereby bringing the cell transistor CT1 corresponding to the word line WL1 into a conductive state. Thereby, the cell transistor CT1 corresponding to the word line WL1 can supply current to the MTJ element MTJsel.

  The MTJ element MTJsel is connected between the first bit line BL1 and the second bit line BL2sel, and the MTJ element MTJsel has a voltage difference between the first bit line BL1 and the second bit line BL2sel. Current flows by (| Vread−Vout |). Then, the sense amplifier SA may detect the current Icell flowing through the second bit line BL2sel connected to the selected MTJ element MTJsel. Note that the power supply voltage is normally used as the voltage Vwrite, and 0 V (GND) is usually used as the voltage Vout.

  At this time, the write driver WD fixes the voltage of the second bit line BL2 other than the second bit line BL2sel to the predetermined voltage Vrmed. The voltage Vrmed is as described above.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

MTJ ... MTJ element, CT ... cell transistor, S ... source layer, D ... drain layer, BL1, BL2 ... bit line, WL ... word line, AA ... active area , STI ... element isolation region, V1, V2 ... via contact, CB ... contact plug, UE ... upper electrode, LE ... lower electrode, 10 ... silicon substrate, 20 ... Gate insulation film

Claims (7)

A semiconductor substrate;
An active area formed in the semiconductor substrate;
A cell transistor formed in the active area;
A magnetic tunnel junction element having one end electrically connected to one of a source or a drain of the cell transistor;
A first bit line electrically connected to the other of the source or drain of the cell transistor;
A second bit line electrically connected to the other end of the magnetic tunnel junction element;
A word line electrically connected to the gate of the cell transistor or functioning as the gate of the cell transistor;
A plurality of the second bit lines correspond to one first bit line,
A plurality of the magnetic tunnel junction elements share the same word line and the same active area;
The active area is formed continuously in the extending direction of the first and second bit lines.   2. The cell transistor connected to one end of the plurality of magnetic tunnel junction elements sharing the word line and the active area is shared by the plurality of magnetic tunnel junction elements. Semiconductor memory device.   3. The semiconductor memory device according to claim 1, wherein the plurality of magnetic tunnel junction elements share the two word lines provided on both sides of the plurality of magnetic tunnel junction elements.   The plurality of cell transistors corresponding to the two word lines provided on both sides of the plurality of magnetic tunnel junction elements supply current to the magnetic tunnel junction element selected from the plurality of magnetic tunnel junction elements. The semiconductor memory device according to claim 3. An element isolation word line that is provided between the two magnetic tunnel junction elements adjacent to each other in the extending direction of the first and second bit lines, and that always insulates between the two magnetic tunnel junction elements;
A plurality of the magnetic tunnel junction elements are provided on both sides of the element isolation word line,
The plurality of magnetic tunnel junction elements share the active area with the word line provided on one side thereof, the element isolation word line provided on the other side, and the active area. 2. The semiconductor memory device according to 2.   When one of the plurality of magnetic tunnel junction elements sharing the word line and the active area is selected, other than the second bit line connected to the selected magnetic tunnel junction element 5. The semiconductor memory device according to claim 1, further comprising a write driver that fixes a voltage of the second bit line to a predetermined voltage. 6.   When selecting one of the plurality of magnetic tunnel junction elements that share the word line, the element isolation word line, and the active area, the magnetic tunnel junction element connected to the selected magnetic tunnel junction element 6. The semiconductor memory device according to claim 5, further comprising a write driver that fixes a voltage of the second bit line other than the second bit line to a predetermined voltage.

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