JP2012059873A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that surely stabilizes a potential of a P well in which a channel is formed.SOLUTION: Polysilicon gate electrodes G are formed in trenches 6 formed in P wells 4. Two N+ regions 13 as source regions are formed in a region of the P well 4. In the portion of each P well 4 sandwiched between one N+ region 13 and the other N+ region 13, a P+ region 5 as a contact region to maintain the P well 4 at a predetermined potential is formed so as to contact the surface of the P well 4. A thermal oxide film 11 is formed between one (the other) N+ region 13 and the P+ region 5. Silicon oxide films 15 are formed so as to cover the polysilicon gate electrodes G. Metal wiring 18 is formed which is electrically connected to the P+ regions 5 and the N+ regions 13.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an insulated gate bipolar transistor.

  In household appliances and industrial equipment, insulated gate bipolar transistors (IGBTs) are used for power control. For example, in home appliances, a vertical IGBT is applied to a light emitting circuit that controls light emission of a strobe of a mobile phone camera or a digital still camera.

  In the vertical IGBT, a plurality of trenches are formed at intervals from each other, and a gate electrode is formed inside each trench. A P well in which a channel is formed is formed in a region sandwiched between one trench and the other trench adjacent to each other. In the P well, a P + region is formed as a contact region for fixing the P well to a predetermined potential. In the P well, an N + region is formed as a source (or emitter) region. A drain region electrically connected to the source region through the channel is formed below the P well. In addition, there exists a nonpatent literature 1 as one of the nonpatent literatures which disclosed vertical IGBT.

  In recent years, in order to cope with downsizing of mobile phones or digital still cameras, IGBTs are also required to be downsized and low voltage. If the size of the IGBT is to be reduced, it is necessary to reduce the area occupied by the P + region formed in the P well. Then, the parasitic resistance value in the P + region as a contact region for fixing the potential of the P well becomes high, and the potential of the P well may become unstable, such as the potential of the P well floating. If a current is passed between the source and drain of the IGBT in a state where the potential of the P well is unstable, a latch-up occurs, causing a problem that the IGBT cannot be turned off. In order to solve such a problem, means for lowering the parasitic resistance by increasing the impurity concentration of the P + region has been taken.

Michio Nemoto et.al., “The Recessed-Gate IGBT Structure” Power Semiconductor Devices and ICs, 1999. ISPSD '99. Proceedings., The 11th International Symposium on.

  However, the conventional semiconductor device has the following problems. If the impurity concentration in the P + region is increased to reduce the parasitic resistance, the p-type impurity diffuses into the N + region as the source, while the n + impurity in the N + region diffuses into the P + region. Impurities sometimes diffused between the P + region and the N + region. For this reason, there is a limit to the method of increasing the impurity concentration in the P + region and reducing the parasitic resistance.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device in which the potential of a P-well in which a channel is formed is reliably stabilized.

  A semiconductor device according to the present invention includes a first conductivity type semiconductor substrate having a main surface, a second conductivity type semiconductor layer, a first conductivity type first impurity region, a trench, a gate electrode, A conductive second impurity region, a second conductive type third impurity region, and an insulating film are provided. The second conductivity type semiconductor layer is formed in contact with the main surface of the semiconductor substrate. The first impurity region of the first conductivity type is formed from the surface of the semiconductor layer to the first depth. The trench is formed from the surface of the first impurity region to a second depth deeper than the first depth so as to reach the semiconductor layer. The gate electrode is formed with a gate insulating film interposed on the sidewall of the trench. The second impurity region of the first conductivity type is formed in contact with the surface of a predetermined region in the first impurity region. The third impurity region of the second conductivity type is formed so as to be in contact with the surface of another predetermined region in the first impurity region. The insulating film is formed between the second impurity region and the third impurity region.

  According to the semiconductor device of the present invention, the first conductivity type as a contact for fixing the first impurity region of the first conductivity type in which the channel is formed to a predetermined potential by applying a predetermined voltage to the gate electrode. An insulating film is formed between the second impurity region and the third impurity region of the second conductivity type as the source. Thereby, even if the impurity concentration of the second impurity region is increased, the interdiffusion of impurities between the second impurity region and the third impurity region is suppressed, and the potential of the first impurity region can be reliably fixed. it can.

1 is a partial plan view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a cross-sectional view taken along a cross-sectional line II-II shown in FIG. 1 in the same embodiment. FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the embodiment. FIG. 4 is a cross-sectional view showing a step performed after the step shown in FIG. 3 in the same embodiment. FIG. 5 is a cross-sectional view showing a step performed after the step shown in FIG. 4 in the same embodiment. FIG. 6 is a partial plan view showing a process performed after the process shown in FIG. 5 in the same embodiment. FIG. 7 is a cross-sectional view taken along a cross-sectional line VII-VII shown in FIG. 6 in the same embodiment. FIG. 8 is a cross-sectional view showing a process performed after the process shown in FIGS. 6 and 7 in the embodiment. FIG. 9 is a cross-sectional view showing a step performed after the step shown in FIG. 8 in the same embodiment. FIG. 10 is a partial plan view showing a step performed after the step shown in FIG. 9 in the same embodiment. FIG. 11 is a cross sectional view taken along a cross sectional line XI-XI shown in FIG. 10 in the same embodiment. It is sectional drawing of the semiconductor device which concerns on a comparative example. It is a fragmentary top view of the semiconductor device which concerns on Embodiment 2 of this invention. FIG. 14 is a cross sectional view taken along a cross sectional line XIV-XIV shown in FIG. 13 in the same embodiment. FIG. 14 is a cross sectional view taken along a cross sectional line XV-XV shown in FIG. 13 in the same embodiment. FIG. 14 is a cross sectional view taken along a cross sectional line XVI-XVI shown in FIG. 13 in the same embodiment. FIG. 10 is a cross-sectional view showing a step of the method of manufacturing a semiconductor device in the embodiment. FIG. 18 is a partial plan view showing a step performed after the step shown in FIG. 17 in the same embodiment. FIG. 19 is a cross-sectional view taken along a cross-sectional line XIX-XIX shown in FIG. 18 in the same embodiment. FIG. 20 is a partial plan view showing a process performed after the process shown in FIGS. 18 and 19 in the embodiment. FIG. 21 is a cross sectional view taken along a cross sectional line XXI-XXI shown in FIG. 20 in the embodiment. FIG. 21 is a cross sectional view taken along a cross sectional line XXII-XXII shown in FIG. 20 in the same embodiment. FIG. 23 is a partial plan view showing a process performed after the process shown in FIGS. 20 to 22 in the embodiment. FIG. 24 is a cross sectional view taken along a cross sectional line XXIV-XXIV shown in FIG. 23 in the same embodiment. FIG. 24 is a cross sectional view taken along a cross sectional line XXV-XXV shown in FIG. 23 in the same embodiment. FIG. 26 is a partial plan view showing a process performed after the process shown in FIGS. 23 to 25 in the embodiment. FIG. 27 is a cross sectional view taken along a cross sectional line XXVII-XXVII shown in FIG. 26 in the embodiment. FIG. 27 is a cross sectional view taken along a cross sectional line XXVIII-XXVIII shown in FIG. 26 in the embodiment.

Embodiment 1
Here, a first example of the IGBT will be described. As shown in FIG. 1, in this IGBT, an N + region 13 as a source region and a P + region 5 as a P well contact region are formed along the direction in which the polysilicon gate electrode G extends. ing. A region R1 shown in FIG. 1 is a region where the silicon oxide film 15 is removed in order to show the lower pattern. Further, as shown in FIG. 2, N + epitaxial layer 2 is formed so as to be in contact with one main surface of semiconductor substrate 1, and N − epitaxial layer 3 is formed so as to be in contact with the surface of N + epitaxial layer 2. Has been. P well 4 is formed in a predetermined region of N − epitaxial layer 3 from the surface of N − epitaxial layer 3 to a predetermined depth. A plurality of trenches 6 are formed in a predetermined region of the P well 4. Each of the plurality of trenches 6 is formed so as to extend in one direction at a distance from each other and reach N − epitaxial layer 3. In each trench 6, a polysilicon gate electrode G is formed with a gate oxide film 7 interposed on the side wall of the trench 6.

In a region of the P well 4 sandwiched between one trench 6 and the other trench 6 adjacent to each other, two N + regions 13 as source regions are formed. The order of the impurity concentration of the N + region 13 is about 10 ²¹ / cm ³ . One N + region 13 located on the side of one trench 6 is in contact with the surface of P well 4 and is also in contact with the portion of gate oxide film 7 formed on the side wall of trench 6. Yes. The other N + region 13 located on the other trench 6 side is in contact with the surface of the P well 4 and is in contact with the portion of the gate oxide film 7 formed on the side wall of the trench 6. Yes. N + region 13 is electrically connected to N − epitaxial layer 3 as a drain region via a channel formed in P well 4.

In a portion of the P well 4 sandwiched between one N + region 13 and the other N + region 13, a P + region 5 is provided as a contact region for fixing the P well 4 to a predetermined potential. It is formed so as to be in contact with the surface. The order of the impurity concentration of the P + region 5 is about 10 ²⁰ / cm ³ . A thermal oxide film 11 is formed between one N + region 13 and the P + region 5, and a thermal oxide film 11 is formed between the other N + region 13 and the P + region 5.

  A silicon oxide film 15 is formed so as to cover the polysilicon gate electrode G. Opening 16 is formed in silicon oxide film 15 to expose the surface of P + region 5 and the surface of N + region 13. Metal wiring 18 electrically connected to P + region 5 and N + region 13 is formed so as to fill opening 16. The metal wiring 18 includes a titanium tungsten film 18a and an aluminum silicon film 18b. The titanium tungsten film 18 a is formed so as to be in contact with the surface of the silicon oxide film 15 including the side wall of the opening 16. The aluminum silicon film 18b is formed in contact with the surface of the titanium tungsten film 18a. A glass coat film 20 is formed so as to be in contact with the surface of the aluminum silicon film 19. A collector electrode 21 is formed on the other main surface of the semiconductor substrate 1.

  Next, the operation of the above-described IGBT will be described. First, by applying a voltage higher than a predetermined threshold voltage (for example, about 0.6 to 0.8 V) to the polysilicon gate electrode G, the P well 4 located on the side of the polysilicon gate electrode G A channel is formed in this part. When the channel is formed, electrons e are injected from the N + region 13 serving as the source region (emitter) through the channel to the N − epitaxial layer 3 serving as the drain region. 1, holes h are injected into the N − epitaxial layer 3. As a result, the resistance value of the N − epitaxial layer 3 is lowered by the conductivity modulation, and the current flows from the collector side to the source (emitter) side (on state).

  On the other hand, when a voltage lower than the threshold voltage is applied to the polysilicon gate electrode G, the channel formed in the P well 4 disappears. When the channel disappears, the injection of electrons into the N − epitaxial layer 3 stops, and the electrons and holes accumulated in the N − epitaxial layer 3 disappear due to recombination, or the N + region 13 or the collector electrode 21. It is extinguished by being discharged into the state, and finally it becomes a state where the current is cut off (off state).

Next, a method for manufacturing the above-described IGBT will be described. As shown in FIG. 3, an N + epitaxial layer 2 is formed so as to be in contact with the main surface of a P-type semiconductor substrate 1 by an epitaxial growth method, and further, an N − epitaxial layer is brought into contact with the N + epitaxial layer 2. 3 is formed. Next, a silicon oxide film 22 is formed in contact with the surface of the N − epitaxial layer 3 by performing a thermal oxidation process. Next, boron (B) is implanted through the silicon oxide film 22 by ion implantation, whereby the P well 4 is formed. Subsequently, P + region 5 is formed by implanting boron difluoride (BF ₂ ). As the substrate, a substrate in which the N − epitaxial layer 3 is formed is used.

  Next, a resist (not shown) for forming a trench is formed by performing a predetermined photolithography process. Using the resist as a mask, the silicon oxide film 22 is etched to expose the surface of the P + region 5. Thereafter, the resist is removed. Next, using the remaining silicon oxide film 22 as a mask, the exposed P + region 5, P well 4 and N-epitaxial layer 3 are etched to form an N-epitaxial layer 3 as shown in FIG. A trench 6 is formed so as to pass through. Thereafter, the silicon oxide film 22 is removed. Next, a gate oxide film 7 (see FIG. 5) is formed on the exposed sidewall of the trench by performing a thermal oxidation process. At this time, a silicon oxide film is also formed on the exposed surface of the P + region 5.

  Next, a polysilicon film (not shown) doped with phosphorus is formed so as to fill the trench 6. Next, an etch back process is performed on the entire surface of the polysilicon film to remove a portion of the polysilicon film located on the upper surface of the P + region 5, thereby removing the polysilicon in the trench 6 as shown in FIG. A gate electrode G is formed. Next, as shown in FIGS. 6 and 7, silicon oxide film 10 is formed so as to cover polysilicon gate electrode G. A region R2 shown in FIG. 6 is a region where the silicon oxide film 10 is removed to show the lower pattern. Next, a predetermined photoengraving process is performed to form a resist 31 that covers the polysilicon gate electrode G and covers a part of the P + region 5 along the direction in which the polysilicon gate electrode G extends. . Next, by etching the silicon oxide film 10 using the resist 31 as a mask, the surface of the P + region 5 is exposed. Thereafter, the resist 31 is removed. Next, as shown in FIG. 8, the surface of the P well 4 is exposed by etching the exposed surface of the P + region 5 using the remaining silicon oxide film 10 as a mask.

  Next, a thermal oxidation process is performed to form a thermal oxide film on the exposed side wall of the P + region 5 and the surface of the P well 4. Next, by performing a predetermined etching process, the portion of the thermal oxide film formed on the surface of the P well 4 is left, leaving the thermal oxide film 11 (see FIG. 9) formed on the side wall of the P + region 5. Removed. Next, a polysilicon film (not shown) doped with phosphorus is formed so as to be in contact with the exposed surface of the P well 4 and the remaining surface of the silicon oxide film 10. Next, an etch-back process is performed on the entire surface of the polysilicon film to leave a portion of the polysilicon film located between the P + region 5 and the polysilicon gate electrode G, and on the upper surface of the silicon oxide film 10. The portion of the polysilicon film that is positioned is removed. Thereafter, activation is performed by applying a predetermined heat treatment, whereby an N + region 13 is formed between the P + region 5 and the polysilicon gate electrode G as shown in FIG.

  Next, a silicon oxide film 15 (see FIG. 11) is formed so as to cover N + region 13 and silicon oxide film 10. Next, a predetermined photolithography process is performed to form a resist (not shown) for forming an opening that exposes the P + region 5. Next, using the resist as a mask, the silicon oxide film 15 is etched to form an opening 16 (see FIG. 11) that exposes the surface of the P + region 5. Next, the resist is removed, and an opening 16 exposing P + region 5 is formed in silicon oxide film 15, as shown in FIGS. Note that a region R3 shown in FIG. 10 is a region where the silicon oxide film 15 is removed to show the lower pattern.

  Next, a titanium tungsten film (not shown) is formed so as to be in contact with the surface of the P + region 5 and the surface of the N + region 13 exposed by sputtering or the like, and further, in contact with the surface of the titanium tungsten film. Thus, an aluminum silicon film (not shown) is formed. Next, a predetermined photoengraving process is performed to form a resist (not shown) for forming wiring. Next, using the resist as a mask, the aluminum silicon film and the titanium tungsten film are etched to form a metal wiring 18 (see FIG. 2) made of the titanium tungsten film and the aluminum silicon film. Thus, as shown in FIG. 2, the main part of the IGBT is formed.

  In the IGBT described above, the thermal oxide film 11 is formed between the N + region 13 as the source region and the P + region 5 as the contact region, so that even if the impurity concentration of the P + region 5 is increased, Impurity interdiffusion is suppressed and parasitic resistance can be lowered. This will be described with the IGBT according to the comparative example.

  As shown in FIG. 12, in the IGBT according to the comparative example, an N + epitaxial layer 102 is formed so as to be in contact with the main surface of the semiconductor substrate 101, and an N − epitaxial is formed so as to be in contact with the surface of the N + epitaxial layer 102. A layer 103 is formed. P well 104 is formed in a predetermined region of N − epitaxial layer 103 from the surface of N − epitaxial layer 103 to a predetermined depth with a space therebetween. A plurality of trenches 106 reaching the N − epitaxial layer 103 are formed at predetermined intervals in the P well 4 so as to penetrate the P well 4. In each trench 106, a polysilicon gate electrode JG is formed with a gate oxide film 107 interposed on the sidewall of the trench 106.

  In the P well 104 sandwiched between one trench 106 and the other trench 106 that are adjacent to each other, the gate oxide film 107 formed on the side wall of the trench 106 is brought into contact with the portion located on the side of the trench 106. One N + region 113 is formed on the other trench 106, and the other N + region 113 is formed on the portion located on the other trench 106 side so as to contact the gate oxide film 107 formed on the side wall of the trench 106. ing. One (the other) N + region 113 is formed from the surface of the P well 104 to a predetermined depth shallower than the depth of the P well 104. In a portion of the P well 104 sandwiched between one N + region 113 and the other N + region 113, a P + region 105 is formed from the surface to a predetermined depth.

  Interlayer insulating film 110 is formed so as to cover polysilicon gate electrode JG and one (the other) N + region 113. A titanium tungsten (TiW) film 118 is formed as a metal wiring 180 so as to cover the interlayer insulating film 110 and come into contact with the P + region 105, and aluminum silicon (AlSi) is brought into contact with the titanium tungsten film 118 a. ) A film 118b is formed. A glass coat film 120 is formed so as to be in contact with the aluminum silicon film 118b. A collector electrode 121 is formed on the other main surface of the semiconductor substrate 101.

  In the IGBT according to the comparative example, if the size of the IGBT is to be reduced in order to cope with the downsizing of home appliances and the like, it is necessary to reduce the distance L and reduce the occupied area of the P + region 105 as the contact region. is there. For this reason, the parasitic resistance value in the P + region 105 becomes high, and the potential of the P well 104 becomes unstable, causing latch-up. In order to solve such a problem, if the impurity concentration of the P + region 105 is increased to reduce the parasitic resistance, the p-type impurity in the P + region 105 diffuses into the N + region 113, while N + The n-type impurity in region 113 diffuses into P + region 105. For this reason, there is a limit to increasing the impurity concentration of the P + region 105.

  In the IGBT according to the embodiment with respect to the comparative example, a thermal oxide film 11 is formed between an N + region 13 as a source (emitter) region and a P + region 5 as a contact region. Thereby, even if the impurity concentration of P + region 5 is increased, it is possible to reliably prevent the p-type impurity in P + region 5 from diffusing into N + region 13. On the other hand, it is possible to reliably prevent the n-type impurity in the N + region 13 from diffusing into the P + region 5. In this way, the interdiffusion of impurities is suppressed, the parasitic resistance of the P + region 5 can be lowered, the cause of latch-up can be eliminated, and the IGBT can be operated stably.

Embodiment 2
Here, a second example of the IGBT will be described. As shown in FIG. 13, in this IGBT, an N + region 13 as a source region and a P + region 5 as a P well contact region extend along a direction orthogonal to the direction in which the polysilicon gate electrode G extends. N + regions 13 and P + regions 5 are alternately arranged along the polysilicon gate electrode G. As shown in FIGS. 13 and 14, a P + region serving as a contact region is in contact with the surface of the P well 4 in a cross section perpendicular to the extending direction of the polysilicon gate electrode G and crossing the P + region 5. 5 is formed. Metal wiring 18 electrically connected to P + region 5 is formed.

  As shown in FIGS. 13 and 15, the N + region as the source region is in contact with the surface of the P well 4 in a cross section perpendicular to the extending direction of the polysilicon gate electrode G and crossing the N + region 13. 13 is formed. A silicon oxide film 15 is formed so as to cover N + region 13 and polysilicon gate electrode G. Metal wiring 18 is formed so as to be in contact with silicon oxide film 15.

  As shown in FIGS. 13 and 16, the cross section across the N + region 13 and the P + region 5 along the direction in which the polysilicon gate electrode G extends extends to contact the surface of the P well 4. + Regions 13 and P + regions 5 are alternately formed. A thermal oxide film 11 is formed on the side wall of P + region 5 and is interposed between N + region 13 and P + region 5. A silicon oxide film 15 is formed so as to cover N + region 13. Metal wiring 18 electrically connected to P + region 5 and N + region 13 is formed so as to be in contact with silicon oxide film 15. In addition, since it is the same as that of IGBT shown by FIG. 1 and FIG. 2 about another structure, the same code | symbol is attached | subjected to the same member and the description is not repeated.

  Next, the operation of the above-described IGBT will be described. The operation of the IGBT described above is basically the same as the operation of the IGBT described above. First, by applying a voltage higher than a predetermined threshold voltage to the polysilicon gate electrode G, a channel is formed in the portion of the P well 4 and electrons e are injected into the N − epitaxial layer 3. Holes h are injected from the collector electrode 21 into the N − epitaxial layer 3, and the resistance value of the N − epitaxial layer 3 decreases due to conductivity modulation. As a result, a current flows from the collector side toward the source (emitter) side (on state).

  On the other hand, when a voltage lower than the threshold voltage is applied to the polysilicon gate electrode G, the channel formed in the P well 4 disappears, and the electrons and holes accumulated in the N − epitaxial layer 3 are recombined. Or disappears by being discharged to the N + region 13 or the collector electrode 21, and finally the current is cut off (off state).

  Next, a method for manufacturing the above-described IGBT will be described. First, a polysilicon gate electrode G is formed in the trench 6 as shown in FIG. 17 through steps similar to those shown in FIGS. Next, as shown in FIGS. 18 and 19, a silicon oxide film 10 (see FIG. 19) is formed so as to cover the polysilicon gate electrode G. Next, by performing a predetermined photoengraving process, a resist 32 that covers the polysilicon gate electrode G and covers a part of the P + region 5 along a direction orthogonal to the direction in which the polysilicon gate electrode G extends. Is formed. Note that a region R4 shown in FIG. 18 is a region where the silicon oxide film 10 is removed to show the lower pattern.

  Next, by etching the silicon oxide film 10 using the resist 32 as a mask, the surface of the P + region 5 is exposed. Thereafter, the resist 32 is removed. Next, as shown in FIGS. 20, 21, and 22, the surface of the P well 4 is exposed by etching the exposed surface of the P + region 5 using the remaining silicon oxide film 10 as a mask. Let

  Next, a thermal oxidation process is performed to form a thermal oxide film on the exposed side wall of the P + region 5 and the surface of the P well 4. Next, by performing a predetermined etching process, the portion of the thermal oxide film formed on the surface of the P well 4 is left, leaving the thermal oxide film 11 (see FIG. 23) formed on the side wall of the P + region 5. Removed. Next, a polysilicon film (not shown) doped with phosphorus is formed so as to be in contact with the exposed surface of the P well 4 and the remaining surface of the silicon oxide film 10. Next, by performing an etch-back process on the entire surface of the polysilicon film, the polysilicon film is sandwiched between the polysilicon gate electrode G and the polysilicon gate electrode G, and at the region sandwiched between the P + region 5 and the P + region 5. The portion of the polysilicon film located on the upper surface of the silicon oxide film 10 is removed leaving the portion of the polysilicon film located. Thereafter, activation is performed by applying a predetermined heat treatment, whereby N + region 13 is formed as shown in FIGS.

  Next, a silicon oxide film 15 (see FIG. 28) is formed so as to cover N + region 13 and silicon oxide film 10. Next, a predetermined photolithography process is performed to form a resist (not shown) for forming an opening that exposes the P + region 5. Next, using the resist as a mask, the silicon oxide film 15 is etched to form an opening 16 (see FIG. 26) that exposes the surface of the P + region 5. Next, the resist is removed, and an opening 16 exposing P + region 5 is formed in silicon oxide film 15, as shown in FIGS.

  Next, a titanium tungsten film (not shown) is formed so as to be in contact with the surface of the P + region 5 and the surface of the N + region 13 exposed by sputtering or the like, and further, in contact with the surface of the titanium tungsten film. Thus, an aluminum silicon film (not shown) is formed. Next, a predetermined photoengraving process is performed to form a resist (not shown) for forming wiring. Next, using the resist as a mask, the aluminum silicon film and the titanium tungsten film are etched to form the metal wiring 18 made of the titanium tungsten film and the aluminum silicon film, as shown in FIGS. The main part of the IGBT is formed.

  In the IGBT described above, a thermal oxide film 11 is formed between an N + region 13 as a source (emitter) region and a P + region 5 as a contact region. As a result, as described above for the IGBT, even if the impurity concentration of the P + region 5 is increased, it is possible to reliably prevent the p-type impurity in the P + region 5 from diffusing into the N + region 13. it can. On the other hand, it is possible to reliably prevent the n-type impurity in the N + region 13 from diffusing into the P + region 5. As a result, the interdiffusion of impurities is suppressed, the parasitic resistance of the P + region 5 can be lowered, the cause of latch-up can be eliminated, and the IGBT can be operated stably.

  In the IGBT described above, the N + region 13 and the P + region 5 are formed along a direction perpendicular to the direction in which the polysilicon gate electrode G extends, and along the polysilicon gate electrode G, N + regions 13 and P + regions 5 are alternately arranged. Thereby, compared with the case of IGBT mentioned above, the occupation area of N <+> region 13 as a source can be set larger with respect to the same element area of IGBT.

  In each of the embodiments, the thermal oxide film 11 has been described as an example of the film in which the impurity in the P + region 5 and the impurity in the N + region 13 prevent mutual diffusion. A silicon oxynitride film (SiON) film is more preferable in order to more reliably prevent interdiffusion of type impurities. In this case, the silicon oxynitride film can be formed as a sidewall film that covers the sidewall of the P + region 5 by, for example, a CVD (Chemical Vapor Deposition) method. In addition to the silicon oxynitride film, for example, a TEOS (Tetra Ethoxy Ortho Silicate) film can be applied.

  The embodiment disclosed this time is an example, and the present invention is not limited to this. The present invention is defined by the terms of the claims, rather than the scope described above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is effectively used for a semiconductor device having a vertical gate insulating bipolar transistor.

  1 Semiconductor substrate, 2 N + epitaxial layer, 3 N- epitaxial layer, 4 P well, 5 P + region, 6 trench, 7 gate oxide film, G polysilicon gate electrode, 10 silicon oxide film, 11 thermal oxide film, 13 N + region, 15 silicon oxide film, 16 opening, 18 metal wiring, 18a titanium tungsten film, 18b aluminum silicon film, 21 collector electrode, 22 silicon oxide film, 31 resist, 32 resist.

Claims (1)

A first conductivity type semiconductor substrate having a main surface;
A second conductivity type semiconductor layer formed so as to be in contact with the main surface of the semiconductor substrate;
A first impurity region of a first conductivity type formed from the surface of the semiconductor layer to a first depth;
A groove formed from the surface of the first impurity region to a second depth deeper than the first depth so as to reach the semiconductor layer;
A gate electrode formed by interposing a gate insulating film on the side wall of the groove;
A second impurity region of a first conductivity type formed so as to be in contact with a surface of a predetermined region in the first impurity region;
A third impurity region of a second conductivity type formed so as to be in contact with the surface of another predetermined region in the first impurity region;
A semiconductor device comprising: an insulating film formed between the second impurity region and the third impurity region.

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