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JP2011238951A - Semiconductor device and method of manufacturing same - Google Patents

Semiconductor device and method of manufacturing same Download PDF

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Publication number
JP2011238951A
JP2011238951A JP2011151968A JP2011151968A JP2011238951A JP 2011238951 A JP2011238951 A JP 2011238951A JP 2011151968 A JP2011151968 A JP 2011151968A JP 2011151968 A JP2011151968 A JP 2011151968A JP 2011238951 A JP2011238951 A JP 2011238951A
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film
forming
layer
insulating film
semiconductor device
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Shigeru Harada
繁 原田
Takeru Matsuoka
長 松岡
Hiroki Takewaka
博基 竹若
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Renesas Electronics Corp
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Renesas Electronics Corp
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  • Engineering & Computer Science (AREA)
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device having such structure as cracking is hard to occur on a surrounding insulating film even if a load or impact is applied on a pad electrode.SOLUTION: The method of manufacturing a semiconductor device includes a recess formation step for forming a recess of such planer shape as selected from a group comprising a substantial circle, a substantial oval, a substantial polygon of which at least one internal angle is larger than 90°, a substantial polygon of which at least one corner part is beveled or rounded, and a combination of shapes containing at least a part of them, an underlay film formation step for forming an underlay film that covers at least a part of the inner surface of the recess, and a pad part formation step for embedding a conductive electrode material in the recess covered with an insulating film. The recess formation step includes a step for forming a first recess, and a step for forming a second recess on a part of the first recess to be further deeper.

Description

本発明は、半導体装置およびその製造方法に関するものであり、特に、半導体基板上の半導体素子と外部端子とを接続するための電極として用いられるパッド電極の構造を有する、半導体装置およびその製造方法に関するものである。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a semiconductor device having a structure of a pad electrode used as an electrode for connecting a semiconductor element on a semiconductor substrate and an external terminal, and a manufacturing method thereof. Is.

半導体装置において、デバイスの高速化・高性能化実現のための配線遅延低減（配線抵抗低減）や配線許容電流密度増加の目的で、従来のアルミニウム（Ａｌ）を主成分にする配線に代わり、より抵抗が低く信頼性の高い銅（Ｃｕ）を主成分とする配線が用いられるようになってきた。   In semiconductor devices, instead of conventional aluminum (Al) as the main component for reducing wiring delay (reducing wiring resistance) and increasing wiring allowable current density to achieve higher speed and higher performance of devices, Wiring composed mainly of copper (Cu) having low resistance and high reliability has been used.

パッド電極は、通常、最上層の金属配線を用いて配線と同時に形成され、この部分に直接ワイヤをボンディングするワイヤボンディング法や、バンプ電極のような接続電極を形成した後にこれらを介して接続するフリップチップ法などの方法により、外部端子と接続している。なお、配線の材料として用いられる銅は、ドライエッチングでの微細加工性に乏しいので、配線の形成には、化学機械研磨（ＣＭＰ：Chemical Mechanical Polishing）法を用いた埋込配線（ダマシン）法が主に用いられている。そのため、通常、ボンディングパッド電極も埋込配線法を利用して形成される。   The pad electrode is usually formed at the same time as the wiring using the uppermost metal wiring, and a wire bonding method in which a wire is directly bonded to this portion or a connection electrode such as a bump electrode is formed and then connected through these. It is connected to an external terminal by a method such as a flip chip method. Note that copper used as a wiring material is poor in fine workability by dry etching, and therefore, an embedded wiring (damascene) method using a chemical mechanical polishing (CMP) method is used for forming the wiring. Mainly used. Therefore, usually, the bonding pad electrode is also formed using a buried wiring method.

このような銅配線を用いた従来の半導体装置の断面構造の一例を図１２２に示す。
図１２２に示されるように、半導体基板１の上に素子分離絶縁膜２、ゲート絶縁膜３、ゲート電極４、不純物拡散層５が形成され、ＭＯＳ（Metal Oxide Semiconductor）トランジスタ６を構成している。さらにその上側に下地絶縁膜７が形成されており、第１の配線溝９を含む第１の金属（Ｗ）配線層１０から下に向けて下地絶縁膜７を貫通する形にコンタクトホール８が構成されている。さらに下地絶縁膜７の上側に第１の層間絶縁膜１１が形成されており、第２の配線溝１３を含む第２の金属（Ｃｕ）配線層１４から下に向けて第１の層間絶縁膜１１を貫通する形に第１のビアホール１２が形成されている。さらに第１の層間絶縁膜１１の上側に第２の層間絶縁膜１５が形成されており、第３の配線溝１７を含む第３の金属（Ｃｕ）配線層１８から下に向けて第２の層間絶縁膜１５を貫通する形に第２のビアホール１６が形成されている。第３の金属（Ｃｕ）配線層１８の一部は、パッド電極１９となっている。第２の層間絶縁膜１５の上側には、保護絶縁膜２０、バッファコート膜２１が覆っているが、パッド電極１９に対応する箇所には、パッド電極開口部２２としてパッド電極１９が露出する形になっている。 An example of a cross-sectional structure of a conventional semiconductor device using such a copper wiring is shown in FIG.
As shown in FIG. 122, an element isolation insulating film 2, a gate insulating film 3, a gate electrode 4, and an impurity diffusion layer 5 are formed on a semiconductor substrate 1 to constitute a MOS (Metal Oxide Semiconductor) transistor 6. . A base insulating film 7 is further formed on the upper side, and a contact hole 8 is formed so as to penetrate the base insulating film 7 downward from the first metal (W) wiring layer 10 including the first wiring trench 9. It is configured. Further, a first interlayer insulating film 11 is formed on the upper side of the base insulating film 7, and the first interlayer insulating film faces downward from the second metal (Cu) wiring layer 14 including the second wiring trench 13. A first via hole 12 is formed so as to penetrate 11. Further, a second interlayer insulating film 15 is formed on the upper side of the first interlayer insulating film 11, and the second interlayer insulating film 15 including the third wiring trench 17 is directed downward from the third metal (Cu) wiring layer 18. A second via hole 16 is formed so as to penetrate the interlayer insulating film 15. Part of the third metal (Cu) wiring layer 18 is a pad electrode 19. The protective insulating film 20 and the buffer coat film 21 are covered on the upper side of the second interlayer insulating film 15, but the pad electrode 19 is exposed as a pad electrode opening 22 at a position corresponding to the pad electrode 19. It has become.

また、図１２２に示した従来の半導体装置の製造方法を図１２３〜図１３２を参照して、説明する。   A conventional method for manufacturing the semiconductor device shown in FIG. 122 will be described with reference to FIGS.

この例では、配線層としてタングステン（Ｗ）配線と２層の銅（Ｃｕ）を重ねた３層金属配線構造であり、最上層の銅配線でパッド電極を形成している。なお、この場合、各々の金属配線層は、予め、接続孔と配線溝とを形成しておき、これらに金属膜を埋込んだ後に、化学機械研磨（ＣＭＰ）法で研磨して不要な部分の金属膜を除去するというデュアルダマシン（Dual Damascene）法と呼ばれる方法で形成する場合を例として示している。   In this example, the wiring layer has a three-layer metal wiring structure in which a tungsten (W) wiring and a two-layer copper (Cu) are stacked, and a pad electrode is formed by the uppermost copper wiring. In this case, each metal wiring layer is formed with a connection hole and a wiring groove in advance, and after embedding a metal film in them, polishing is performed by a chemical mechanical polishing (CMP) method. In this example, the metal film is formed by a method called a dual damascene method in which the metal film is removed.

図１２３に示すように、半導体基板１上に、素子分離絶縁膜２、ゲート絶縁膜３、ゲート電極４、不純物拡散層５からなるＭＯＳトランジスタなどの半導体素子６を形成する。次に、半導体素子６上の全面にシリコン酸化膜（ＳｉＯ）、リン（Ｐ）やボロン（Ｂ）などの不純物元素を含むシリコン酸化膜などからなる絶縁膜７ａ、配線溝加工の際のエッチングストッパ層としてのシリコン窒化膜（ＳｉＮ）７ｂ、配線溝を形成するためのシリコン酸化膜（ＳｉＯ）などの絶縁膜７ｃからなる３層構造の下地絶縁膜７を熱ＣＶＤ（Chemical Vapor Deposition）法やプラズマＣＶＤ法などの方法で堆積する。   As shown in FIG. 123, a semiconductor element 6 such as a MOS transistor including an element isolation insulating film 2, a gate insulating film 3, a gate electrode 4, and an impurity diffusion layer 5 is formed on a semiconductor substrate 1. Next, an insulating film 7a made of a silicon oxide film containing an impurity element such as a silicon oxide film (SiO), phosphorus (P), boron (B), or the like is formed on the entire surface of the semiconductor element 6, and an etching stopper at the time of wiring groove processing. A base insulating film 7 having a three-layer structure including a silicon nitride film (SiN) 7b as a layer and an insulating film 7c such as a silicon oxide film (SiO) for forming a wiring trench is formed by a thermal CVD (Chemical Vapor Deposition) method or plasma. It deposits by methods, such as CVD method.

図１２４に示すように、写真製版・エッチング技術を用いて、下地絶縁膜７の所望の部分にコンタクトホール８と第１の配線溝９を形成する。このとき、シリコン窒化膜（ＳｉＮ）７ｂはシリコン酸化膜７ｃに対するエッチング選択比が高いので、第１の配線溝９を加工する際のストッパ膜として作用する。   As shown in FIG. 124, a contact hole 8 and a first wiring groove 9 are formed in a desired portion of the base insulating film 7 using photolithography and etching techniques. At this time, since the silicon nitride film (SiN) 7b has a high etching selection ratio with respect to the silicon oxide film 7c, it functions as a stopper film when the first wiring groove 9 is processed.

図１２５に示すように、コンタクトホール８および第１の配線溝９を埋込むように、バリアメタル膜１０ａとタングステン（Ｗ）膜１０ｂを全面に堆積する。バリアメタル膜１０ａとしては、半導体素子６の不純物拡散領域５と良好なオーミックコンタクトを得るために、たとえば、チタン（Ｔｉ）５〜５０ｎｍと窒化チタン（ＴｉＮ）１０〜１００ｎｍの積層膜が用いられ、ＰＶＤ（Physical Vapor Deposition）法やＣＶＤ法で堆積する。一方、タングステン（Ｗ）膜１０ｂは、六フッ化タングステン（ＷＦ6）と水素（Ｈ2）の還元反応を利用した熱ＣＶＤ法で堆積する。 As shown in FIG. 125, a barrier metal film 10a and a tungsten (W) film 10b are deposited on the entire surface so as to fill the contact hole 8 and the first wiring groove 9. As the barrier metal film 10a, in order to obtain a good ohmic contact with the impurity diffusion region 5 of the semiconductor element 6, for example, a laminated film of titanium (Ti) 5 to 50 nm and titanium nitride (TiN) 10 to 100 nm is used. Deposited by PVD (Physical Vapor Deposition) method or CVD method. On the other hand, the tungsten (W) film 10b is deposited by a thermal CVD method using a reduction reaction of tungsten hexafluoride (WF 6 ) and hydrogen (H 2 ).

図１２６に示すように、たとえば、過酸化水素水（Ｈ2Ｏ2）ベースのアルミナ研磨剤を用いた化学機械研磨（ＣＭＰ）法で、コンタクトホール８と第１の配線溝９以外のタングステン膜１０ｂ、バリアメタル（ＴｉＮ／Ｔｉ）膜１０ａを除去し、第１の埋込金属（Ｗ）配線層１０を形成する。タングステン配線層１０の膜厚は、通常１００〜３００ｎｍ程度である。 As shown in FIG. 126, for example, a tungsten film other than the contact hole 8 and the first wiring groove 9 is formed by a chemical mechanical polishing (CMP) method using an alumina abrasive based on hydrogen peroxide (H 2 O 2 ). 10b, the barrier metal (TiN / Ti) film 10a is removed, and a first buried metal (W) wiring layer 10 is formed. The film thickness of the tungsten wiring layer 10 is usually about 100 to 300 nm.

図１２７に示すように、第１の金属（Ｗ）配線層１０の上に、シリコン酸化膜（ＳｉＯ）などの絶縁膜１１ａ、シリコン窒化膜（ＳｉＮ）１１ｂ、シリコン酸化膜（ＳｉＯ）などの絶縁膜１１ｃからなる３層構造の第１の層間絶縁膜１１をプラズマＣＶＤ法などの方法で堆積する。さらに、写真製版・エッチング技術を用いて、第１の層間絶縁膜１１の所望の部分に第１のビアホール１２と第２の配線溝１３を形成する。   As shown in FIG. 127, on the first metal (W) wiring layer 10, an insulating film 11a such as a silicon oxide film (SiO), an insulating film such as a silicon nitride film (SiN) 11b, and a silicon oxide film (SiO) is formed. A first interlayer insulating film 11 having a three-layer structure made of the film 11c is deposited by a method such as a plasma CVD method. Further, the first via hole 12 and the second wiring trench 13 are formed in a desired portion of the first interlayer insulating film 11 using photolithography and etching techniques.

図１２８に示すように、第１のビアホール１２および第２の配線溝１３を埋込むように、下敷膜１４ａと銅（Ｃｕ）膜１４ｂ，１４ｃを全面に堆積する。下敷膜１４ａは、銅（Ｃｕ）が周囲のシリコン酸化膜などの絶縁膜中に拡散するのを防止する作用を有し、通常、タンタル（Ｔａ）膜、窒化タンタル（ＴａＮ）膜、タンタルと窒化タンタルの積層膜（ＴａＮ／Ｔａ）、窒化チタン（ＴｉＮ）膜、チタンと窒化チタンの積層膜（ＴｉＮ／Ｔｉ）などを１０〜１００ｎｍ程度ＰＶＤ法やＣＶＤ法を用いて堆積する。さらに、電解めっき用の下敷膜として銅シード膜１４ｂをＰＶＤ法やＣＶＤ法で全面に堆積した後に、たとえば、硫酸銅を主成分とするめっき液を用いた電解めっき法により銅めっき膜１４ｃを５００〜１０００ｎｍ程度全面に堆積する。   As shown in FIG. 128, underlying film 14a and copper (Cu) films 14b and 14c are deposited on the entire surface so as to fill first via hole 12 and second wiring trench 13. The underlying film 14a has a function of preventing diffusion of copper (Cu) into an insulating film such as a surrounding silicon oxide film, and is usually a tantalum (Ta) film, a tantalum nitride (TaN) film, tantalum and nitride. A laminated film of tantalum (TaN / Ta), a titanium nitride (TiN) film, a laminated film of titanium and titanium nitride (TiN / Ti), or the like is deposited using a PVD method or a CVD method to a thickness of about 10 to 100 nm. Further, after depositing a copper seed film 14b on the entire surface by an PVD method or a CVD method as an underlayer film for electrolytic plating, for example, the copper plating film 14c is formed by an electrolytic plating method using a plating solution mainly composed of copper sulfate. Deposited on the entire surface of about ~ 1000 nm.

図１２９に示すように、たとえば、過酸化水素水（Ｈ2Ｏ2）ベースのアルミナ研磨剤を用いた化学機械研磨（ＣＭＰ）法で、第１のビアホール１２と第２の配線溝１３以外の銅（Ｃｕ）膜１４ｃ、１４ｂ、下敷膜１４ａを除去し、第２の埋込金属（Ｃｕ）配線層１４を形成する。銅配線層の膜厚は、用途にもよるが、通常、３００〜５００ｎｍ程度である。 As shown in FIG. 129, for example, by a chemical mechanical polishing (CMP) method using an aqueous hydrogen peroxide (H 2 O 2 ) -based alumina polishing agent, except for the first via hole 12 and the second wiring groove 13. The copper (Cu) films 14c and 14b and the underlying film 14a are removed, and a second embedded metal (Cu) wiring layer 14 is formed. The film thickness of the copper wiring layer is usually about 300 to 500 nm, although it depends on the application.

図１３０に示すように、第２の金属配線層１４の上に、銅の拡散防止膜としてシリコン窒化膜１５ａ、シリコン酸化膜などの絶縁膜１５ｂ、シリコン窒化膜１５ｃ、シリコン酸化膜などの絶縁膜１５ｄからなる４層構造の第２の層間絶縁膜１５をプラズマＣＶＤ法などの方法で堆積する。写真製版・エッチング技術を用いて、第２の層間絶縁膜１５の所望の部分に第２のビアホール１６と第３の配線溝１７を形成する。前述と同様の方法により、第２のビアホール１６および第３の配線溝１７を埋込むように、下敷膜１８ａと銅シード膜１８ｂ、銅めっき膜１８ｃを全面に１．５〜３．０μｍ程度堆積した後に、化学機械研磨法で第２のビアホール１６と第３の配線溝１７以外の銅膜１８ｃ，１８ｂ、下敷膜１８ａを除去し、第３の埋込金属（Ｃｕ）配線層１８を形成する。なお、通常、最上層の金属配線層で外部端子と接続するためのパッド電極１９も同時に形成する。最上層の金属配線層としては、ワイヤボンディング性を考慮して、通常、０．８〜１．５μｍ程度の比較的厚膜の金属（Ｃｕ）配線が用いられる。   As shown in FIG. 130, on the second metal wiring layer 14, as a copper diffusion prevention film, a silicon nitride film 15a, an insulating film 15b such as a silicon oxide film, an insulating film such as a silicon nitride film 15c and a silicon oxide film A second interlayer insulating film 15 having a four-layer structure of 15d is deposited by a method such as a plasma CVD method. A second via hole 16 and a third wiring groove 17 are formed in a desired portion of the second interlayer insulating film 15 using photolithography and etching techniques. By the same method as described above, an underlay film 18a, a copper seed film 18b, and a copper plating film 18c are deposited on the entire surface so as to fill the second via hole 16 and the third wiring groove 17 by about 1.5 to 3.0 μm. After that, the copper films 18c and 18b and the underlying film 18a other than the second via hole 16 and the third wiring groove 17 are removed by a chemical mechanical polishing method, and a third buried metal (Cu) wiring layer 18 is formed. . Normally, a pad electrode 19 for connecting to an external terminal is also formed simultaneously with the uppermost metal wiring layer. As the uppermost metal wiring layer, a relatively thick metal (Cu) wiring of about 0.8 to 1.5 μm is usually used in consideration of wire bonding properties.

図１３１に示すように、第３の金属（Ｃｕ）配線層１８の上に、銅（Ｃｕ）の拡散防止層としての緻密なシリコン窒化膜（ＳｉＮ）２０ａを堆積した後、シリコン窒化膜（ＳｉＮ）、シリコン酸化膜（ＳｉＯ）、シリコン酸窒化膜（ＳｉＯＮ）、あるいは、これらの積層構造膜などの保護絶縁膜２０ｂを１．０μｍ程度堆積する。なお、保護絶縁膜２０ｂとして用いられるシリコン窒化膜（ＳｉＮ）は、半導体基板の反りを低減したり、金属配線に過剰な荷重が加わるのを防止するために、膜応力を下げる必要があることから、銅の拡散防止層として用いられるシリコン窒化膜（ＳｉＮ）２０ａよりは膜密度は小さい。さらに、その上に、必要に応じてポリイミドなどのバッファコート膜２１を５〜１０μｍ程度、第２の保護絶縁膜として形成し、ワイヤボンディング法などの方法で外部端子（図示せず）と接続するために、パッド電極１９の所望部分に開口部２２を設ける。   As shown in FIG. 131, a dense silicon nitride film (SiN) 20a as a copper (Cu) diffusion prevention layer is deposited on the third metal (Cu) wiring layer 18 and then a silicon nitride film (SiN). ), A silicon oxide film (SiO), a silicon oxynitride film (SiON), or a protective insulating film 20b such as a laminated structure film thereof is deposited to a thickness of about 1.0 μm. Note that the silicon nitride film (SiN) used as the protective insulating film 20b is required to reduce the film stress in order to reduce the warpage of the semiconductor substrate and to prevent an excessive load from being applied to the metal wiring. The film density is smaller than that of the silicon nitride film (SiN) 20a used as a copper diffusion prevention layer. Further, a buffer coat film 21 made of polyimide or the like is formed as a second protective insulating film about 5 to 10 μm thereon as necessary, and is connected to an external terminal (not shown) by a method such as a wire bonding method. For this purpose, an opening 22 is provided in a desired portion of the pad electrode 19.

図１３２に示すように、半導体基板１を個々のチップに分割し、これらのチップ裏面をリードフレームや実装基板に樹脂や半田などにより接着し（図示省略）、その後、パッド電極開口部２２の露出した銅配線層の部分に、超音波や熱圧着などの方法で金（Ａｕ）や銅（Ｃｕ）ワイヤ２３をボンディングし、パッド電極１９とボンディングワイヤ２３の接続界面に金属間化合物層（Ｃｕパッド電極とＡｕワイヤの場合）、あるいは、相互拡散膜（Ｃｕパッド電極とＣｕワイヤの場合）２４を形成する。最後に、全体をモールド樹脂２５で封じることにより、図５１に示す従来の半導体装置が得られる。   As shown in FIG. 132, the semiconductor substrate 1 is divided into individual chips, and the back surfaces of these chips are bonded to a lead frame or a mounting substrate with a resin or solder (not shown), and then the pad electrode opening 22 is exposed. A gold (Au) or copper (Cu) wire 23 is bonded to the copper wiring layer by ultrasonic or thermocompression bonding, and an intermetallic compound layer (Cu pad) is formed at the connection interface between the pad electrode 19 and the bonding wire 23. In the case of an electrode and an Au wire), or an interdiffusion film (in the case of a Cu pad electrode and a Cu wire) 24 is formed. Finally, the whole is sealed with the mold resin 25 to obtain the conventional semiconductor device shown in FIG.

特開平０３−１５３０４８号公報Japanese Patent Laid-Open No. 03-153048

ただ、上述のような方法で形成した埋込配線構造でパッド電極を形成した場合、パッド電極６１の底面と側壁に硬い下敷膜６１ａがあり、パッド電極６１の周囲を囲んでいる絶縁膜層と強く接着しているため、図１３４、図１３５に示すように、ワイヤボンディング時に加わる荷重または衝撃力が周囲の絶縁膜層に直接伝わり、絶縁膜層にクラックが発生しやすいという問題があった。   However, when the pad electrode is formed by the embedded wiring structure formed by the above-described method, there is a hard underlayer film 61a on the bottom surface and the side wall of the pad electrode 61, and the insulating film layer surrounding the pad electrode 61 and As shown in FIG. 134 and FIG. 135, there is a problem that a load or impact force applied during wire bonding is directly transmitted to the surrounding insulating film layer, and cracks are likely to occur in the insulating film layer.

たとえば、図１３３のように、ドライエッチング法によりパターニングするという方法でパッド電極５１を形成した場合は、パッド電極５１の側面には硬い下敷膜５１ａはなく、パッド電極５１の側壁を覆っている保護絶縁膜５２の膜厚も比較的小さい。また、その上のポリイミドなどのバッファコート膜５３の機械的弾性が大きい。そのため、ワイヤ５５をパッド電極５１にボンディングする際に、荷重または衝撃力５６，５７が加わっても、パッド電極５１が横方向にわずかに変形し、これを緩衝する作用を及ぼすので、層間絶縁膜５０や保護絶縁膜５２にクラックが発生することはない。   For example, when the pad electrode 51 is formed by patterning by dry etching as shown in FIG. 133, the side surface of the pad electrode 51 does not have the hard underlayer film 51a, but protects the side wall of the pad electrode 51. The film thickness of the insulating film 52 is also relatively small. Further, the mechanical elasticity of the buffer coat film 53 made of polyimide or the like is large. Therefore, when bonding the wire 55 to the pad electrode 51, even if a load or impact force 56, 57 is applied, the pad electrode 51 slightly deforms in the lateral direction and acts to buffer this, so that the interlayer insulating film 50 and the protective insulating film 52 are not cracked.

一方、図１３４のように、ダマシン法のような埋込配線プロセスで形成したパッド電極６１の場合には、パッド電極６１の底面と側壁はともに硬い下敷膜６１ａがあり、パッド電極６１周囲を一面に覆っている層間絶縁膜６０と強く接着している。そのため、ワイヤ６５をパッド電極６１にボンディングする際に、荷重または衝撃力６６，６７が加わると、この荷重または衝撃力は、周囲の層間絶縁膜６０に直接伝わってしまう。特に、パッド電極６１の角部６８には応力（衝撃力）集中が起こり、層間絶縁膜６０のクラック６９が発生し、ボンディングワイヤ６５の剥がれや強度低下、あるいは、信頼性上の不具合を引き起こすという問題点があった。   On the other hand, as shown in FIG. 134, in the case of the pad electrode 61 formed by an embedded wiring process such as the damascene method, the bottom surface and the side wall of the pad electrode 61 both have a hard underlayer film 61a. It is strongly bonded to the interlayer insulating film 60 covering the surface. Therefore, when a load or impact force 66, 67 is applied when bonding the wire 65 to the pad electrode 61, the load or impact force is directly transmitted to the surrounding interlayer insulating film 60. In particular, stress (impact force) concentration occurs in the corner portion 68 of the pad electrode 61, and a crack 69 occurs in the interlayer insulating film 60, causing peeling of the bonding wire 65, a decrease in strength, or a problem in reliability. There was a problem.

なお、パッド電極上にバンプ電極などの接続用電極を設けている場合でも、外部端子とのボンディング時に、バンプ電極を介して荷重または衝撃力が加わるので、上記と同様に層間絶縁膜にクラックが発生するという問題点があった。   Even when a connection electrode such as a bump electrode is provided on the pad electrode, a load or an impact force is applied via the bump electrode when bonding to the external terminal, so that the interlayer insulating film is cracked in the same manner as described above. There was a problem that it occurred.

そこで、本発明は、パッド電極上に外部端子をボンディングする際に、バンプ電極を介して荷重または衝撃力が加わっても、周囲の絶縁膜層にクラックが発生しにくいパッド電極を有する半導体装置を提供することを目的とする。   Accordingly, the present invention provides a semiconductor device having a pad electrode that is less likely to crack in the surrounding insulating film layer even when a load or impact force is applied via the bump electrode when bonding an external terminal on the pad electrode. The purpose is to provide.

上記目的を達成するため、本発明に基づく半導体装置の一つの局面では、導電性の電極材質から実質的に構成されたパッド部と、上記パッド部の少なくとも底面と側面とにおいて、上記パッド部の少なくとも一部を被覆する下敷膜とを含む、パッド電極を備え、上記下敷膜の材質が上記電極材質より硬い材質であり、上記パッド部の上面の少なくとも一部を配線と接続するために露出し、上記パッド電極の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状であり、上記パッド電極は、下方に向かって部分的に突出した下側突出部を含み、上記下側突出部の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状である。   In order to achieve the above object, in one aspect of the semiconductor device according to the present invention, a pad portion substantially composed of a conductive electrode material, and at least a bottom surface and a side surface of the pad portion, A pad electrode including at least a part of the underlying film, and the material of the underlying film is harder than the electrode material, and at least a part of the upper surface of the pad part is exposed to connect to the wiring. The planar shape of the pad electrode is a combination of a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, and a substantially polygonal shape in which at least one corner portion is chamfered or rounded. A planar shape selected from the group, wherein the pad electrode includes a lower protruding portion partially protruding downward, and the planar shape of the lower protruding portion is substantially circular, substantially elliptical, at least One internal angles greater than 90 ° substantially polygonal shape, and a planar shape selected from the group consisting of a combination of a substantially polygon with a chamfered or rounded on at least one corner.

上記構成を採用することにより、パッド電極に下側突出部が加わった分、パッド電極の実効厚みが大きくなるため、ワイヤボンディング時の衝撃力を緩和することができる。また、下側突出部が上記平面形状であることによって、下側突出部の角部への応力集中が緩和される。したがって、外部端子との接続強度を十分に確保し得る条件で安定してワイヤボンディングすることができる。   By adopting the above configuration, since the effective thickness of the pad electrode is increased as much as the lower protrusion is added to the pad electrode, the impact force during wire bonding can be mitigated. Moreover, the stress concentration to the corner | angular part of a lower side protrusion part is relieve | moderated because a lower side protrusion part is the said planar shape. Therefore, wire bonding can be stably performed under the condition that sufficient connection strength with the external terminal can be secured.

また、本発明に基づく半導体装置の他の局面では、導電性の電極材質から実質的に構成されたパッド部と、上記パッド部の少なくとも底面と側面とにおいて、上記パッド部の少なくとも一部を被覆する下敷膜とを含む、パッド電極を備え、上記下敷膜の材質が上記電極材質より硬い材質であり、上記パッド部の上面の少なくとも一部を配線と接続するために露出し、上記パッド電極の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状であり、上記パッド電極は、上記電極材質からなる主電極層と、上記主電極層の上側に接する上側電極層とを含み、上記上側電極層は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状である。   In another aspect of the semiconductor device according to the present invention, at least a part of the pad portion is covered with a pad portion substantially composed of a conductive electrode material and at least a bottom surface and a side surface of the pad portion. A pad electrode, and a material of the underlayer film is harder than the electrode material, and at least a part of an upper surface of the pad portion is exposed to connect to the wiring, and the pad electrode The planar shape was selected from the group consisting of a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, and a substantially polygonal shape in which at least one corner portion is chamfered or rounded. The pad electrode includes a main electrode layer made of the electrode material and an upper electrode layer in contact with the upper side of the main electrode layer, and the upper electrode layer is substantially circular, substantially elliptical, at least One internal angles greater than 90 ° substantially polygonal shape, and a planar shape selected from the group consisting of a combination of a substantially polygon with a chamfered or rounded on at least one corner.

上記構成を採用することにより、パッド電極が主電極層と上側電極層との２枚重ねの構造となるため、実効厚みが増し、ワイヤボンディング時の衝撃力を緩和することができる。また、主電極層、上側電極層とも上記平面形状としているため角部への応力集中を緩和することができる。したがって、層間絶縁膜にクラックが発生することを防止することができる。   By adopting the above configuration, since the pad electrode has a two-layer structure of the main electrode layer and the upper electrode layer, the effective thickness is increased and the impact force during wire bonding can be reduced. In addition, since both the main electrode layer and the upper electrode layer have the above planar shape, stress concentration at the corners can be reduced. Therefore, cracks can be prevented from occurring in the interlayer insulating film.

本発明に基づく半導体装置のさらに他の局面においては、導電性の電極材質から実質的に構成されたパッド部と、上記パッド部の少なくとも底面と側面とにおいて、上記パッド部の少なくとも一部を被覆する下敷膜とを含む、パッド電極を備え、上記下敷膜の材質が上記電極材質より硬い材質であり、上記パッド部の上面の少なくとも一部を配線と接続するために露出し、上記パッド電極の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状であり、上記パッド電極は、上記電極材質からなる主電極層と、上記主電極層の下側に、上記主電極層の平面形状の外周の内側近傍において上記外周に沿う形状の外周を有する接続孔を介して接続された下側電極層とを含み、上記下側電極層および上記接続孔の少なくとも一方の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状である。   In still another aspect of the semiconductor device according to the present invention, at least a part of the pad portion is covered with a pad portion substantially composed of a conductive electrode material and at least a bottom surface and a side surface of the pad portion. A pad electrode, and a material of the underlayer film is harder than the electrode material, and at least a part of an upper surface of the pad portion is exposed to connect to the wiring, and the pad electrode The planar shape was selected from the group consisting of a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, and a substantially polygonal shape in which at least one corner portion is chamfered or rounded. The pad electrode has a shape along the outer periphery in the vicinity of the inner side of the outer periphery of the main electrode layer on the lower side of the main electrode layer and the main electrode layer made of the electrode material. A lower electrode layer connected via a connection hole having an outer periphery of at least one of the lower electrode layer and the connection hole. The planar shape of at least one of the lower electrode layer and the connection hole is substantially circular, substantially elliptical, and at least one inner angle is 90. It is a planar shape selected from the group consisting of a substantially polygon larger than 0 ° and a combination of substantially polygons with chamfered or rounded at least one corner.

上記構成を採用することにより、パッド電極の実効厚みが増え、ワイヤボンディング時の衝撃力を緩和させることができる。また、応力の集中しやすい下側電極層や接続孔の角部への応力集中も四角形の場合に比べて大幅に低減できる。したがって、層間絶縁膜にクラックが発生することを防止することができる。   By adopting the above configuration, the effective thickness of the pad electrode is increased, and the impact force during wire bonding can be reduced. Further, the stress concentration at the corners of the lower electrode layer and the connection hole where stress tends to concentrate can be greatly reduced as compared with the case of the quadrangular shape. Therefore, cracks can be prevented from occurring in the interlayer insulating film.

上記発明において好ましくは、上記下側電極層は、下方に向かって部分的に突出した下側突出部を有し、上記下側突出部の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状である。   Preferably, in the above invention, the lower electrode layer has a lower protrusion that partially protrudes downward, and the planar shape of the lower protrusion is substantially circular, substantially elliptical, or at least one. It is a planar shape selected from the group consisting of a substantially polygon having an inner angle greater than 90 ° and a substantially polygon having at least one corner chamfered or rounded.

上記構成を採用することにより、パッド電極の実効厚みをさらに増すこととなり、ワイヤボンディング時の下側突出部の角部への応力集中も緩和することができる。したがって、層間絶縁膜にクラックが発生するのを防止することができる。   By adopting the above configuration, the effective thickness of the pad electrode is further increased, and stress concentration at the corners of the lower protruding portion during wire bonding can be reduced. Therefore, it is possible to prevent cracks from occurring in the interlayer insulating film.

本発明に基づく半導体装置のさらに他の局面においては、導電性の電極材質から実質的に構成されたパッド部と、上記パッド部の少なくとも底面と側面とにおいて、上記パッド部の少なくとも一部を被覆する下敷膜とを含む、パッド電極を備え、上記下敷膜の材質が上記電極材質より硬い材質であり、上記パッド部の上面の少なくとも一部を配線と接続するために露出し、上記パッド電極は、その角部領域において上記パッド部を分割する応力緩衝用絶縁壁を含む。   In still another aspect of the semiconductor device according to the present invention, at least a part of the pad portion is covered with a pad portion substantially composed of a conductive electrode material and at least a bottom surface and a side surface of the pad portion. A pad electrode, and the material of the underlying film is harder than the electrode material, and at least a part of the upper surface of the pad portion is exposed to connect to the wiring, and the pad electrode is , Including a stress buffering insulating wall that divides the pad portion in the corner region.

上記構成を採用することにより、ワイヤボンディングなどの際に、荷重または衝撃力が加わったとしても、応力集中の起こりやすいパッド電極角部において、応力緩衝用絶縁壁３０１が微小な弾性変形をすることにより応力を緩衝するため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、パッド電極角部の層間絶縁膜にクラックが発生することを防止することができる。   By adopting the above configuration, even when a load or impact force is applied during wire bonding or the like, the stress buffer insulating wall 301 undergoes minute elastic deformation at the corner of the pad electrode where stress concentration is likely to occur. Therefore, only a small stress (impact force) is applied to the interlayer insulating film in this portion. Therefore, it is possible to prevent cracks from occurring in the interlayer insulating film at the corners of the pad electrode.

上記発明において好ましくは、上記下側突出部は、その角部領域において上記パッド部を分割する応力緩衝用絶縁壁を含む。   Preferably, in the above invention, the lower protrusion includes an insulating wall for stress buffering that divides the pad in the corner region.

上記構成を採用することにより、ワイヤボンディングの際に荷重または衝撃力が加わったとしても、応力集中の起こりやすい下側突出部の角部において、応力緩衝用絶縁壁が微小な弾性変形をすることにより応力を緩衝するため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、下側突出部の角部近傍における層間絶縁膜のクラックの発生を防止することができる。   By adopting the above configuration, even if a load or impact force is applied during wire bonding, the stress buffer insulating wall undergoes minute elastic deformation at the corner of the lower protruding portion where stress concentration is likely to occur. Therefore, only a small stress (impact force) is applied to the interlayer insulating film in this portion. Therefore, generation of cracks in the interlayer insulating film in the vicinity of the corners of the lower protrusions can be prevented.

上記発明において好ましくは、上記主電極層は、その角部領域において上記パッド部を分割する応力緩衝用絶縁壁を含む。   In the present invention, preferably, the main electrode layer includes a stress buffering insulating wall that divides the pad portion in the corner region.

上記構成を採用することにより、ワイヤボンディングの際に荷重または衝撃力が加わったとしても、応力集中の起こりやすい主電極層の角部において、応力緩衝用絶縁壁が微小な弾性変形をすることにより応力を緩衝するため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、主電極層の角部近傍における層間絶縁膜のクラックの発生を防止することができる。   By adopting the above configuration, even if a load or impact force is applied during wire bonding, the stress buffer insulating wall undergoes minute elastic deformation at the corner of the main electrode layer where stress concentration is likely to occur. In order to buffer the stress, only a small stress (impact force) is applied to the interlayer insulating film in this portion. Therefore, generation of cracks in the interlayer insulating film in the vicinity of the corners of the main electrode layer can be prevented.

上記発明において好ましくは、上記下側電極層および上記接続孔の少なくとも一方は、その角部領域において上記パッド部を分割する応力緩衝用絶縁壁を含む。   Preferably, in the above invention, at least one of the lower electrode layer and the connection hole includes a stress buffering insulating wall that divides the pad portion in a corner region thereof.

上記構成を採用することにより、特に応力集中の起こりやすい下側電極層や接続孔の角部において、応力緩衝用絶縁壁が微小な弾性変形をすることにより応力を緩衝するため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、下側電極層や接続孔の角部近傍の層間膜クラックを防止することができる。   By adopting the above configuration, the stress buffering insulating wall undergoes minute elastic deformation in the lower electrode layer where the stress concentration is likely to occur and the corners of the connection hole to buffer the stress. Only a small stress (impact force) is applied to the insulating film. Therefore, interlayer film cracks near the corners of the lower electrode layer and the connection hole can be prevented.

上記発明において好ましくは、上記下側突出部は、その角部領域において上記パッド部を分割する応力緩衝用絶縁壁を含む。   Preferably, in the above invention, the lower protrusion includes an insulating wall for stress buffering that divides the pad in the corner region.

上記構成を採用することにより、下側電極層の下側突出部の角部において、応力緩衝用絶縁壁が微小な弾性変形をすることにより応力を緩衝するため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、下側突出部の角部の層間膜クラックを防止することができる。   By adopting the above configuration, the stress buffering insulating wall is subjected to minute elastic deformation at the corner of the lower protruding portion of the lower electrode layer, so that the stress is buffered. Only a small stress (impact force) is applied. Therefore, interlayer film cracks at the corners of the lower protrusion can be prevented.

本発明に基づく半導体装置のさらに他の局面においては、導電性の電極材質から実質的に構成されたパッド部と、上記パッド部の少なくとも底面と側面とにおいて、上記パッド部の少なくとも一部を被覆する下敷膜とを含む、パッド電極を備え、上記下敷膜の材質が上記電極材質より硬い材質であり、上記パッド部の上面の少なくとも一部を配線と接続するために露出し、上記パッド電極は、その角部領域において突出した応力緩衝用突出部を含む。   In still another aspect of the semiconductor device according to the present invention, at least a part of the pad portion is covered with a pad portion substantially composed of a conductive electrode material and at least a bottom surface and a side surface of the pad portion. A pad electrode, and the material of the underlying film is harder than the electrode material, and at least a part of the upper surface of the pad portion is exposed to connect to the wiring, and the pad electrode is , Including a stress buffering protrusion protruding in the corner region.

上記構成を採用することにより、ワイヤボンディングなどによってパッド電極１０１に荷重または衝撃力が加わっても、特に、応力集中の起こりやすいパッド電極の角部において、応力緩衝用突出部が微小な弾性変形をして応力（衝撃力）を緩衝する作用を及ぼすため、この近傍部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、パッド電極１０１の角部の層間膜クラックを防止することができる。   By adopting the above-described configuration, even when a load or impact force is applied to the pad electrode 101 by wire bonding or the like, the stress buffering protrusions undergo minute elastic deformation, particularly at the corners of the pad electrode where stress concentration is likely to occur. Therefore, since the stress (impact force) is buffered, only a small stress (impact force) is applied to the interlayer insulating film in the vicinity. Therefore, interlayer film cracks at the corners of the pad electrode 101 can be prevented.

上記発明において好ましくは、上記下側突出部は、その角部領域において突出した応力緩衝用突出部を含む。   Preferably, in the above invention, the lower protrusion includes a stress buffering protrusion protruding in the corner region.

上記構成を採用することにより、ワイヤボンディング時にパッド電極に荷重または衝撃力が加わっても、特に応力集中の起こりやすい下側突出部の角部において、応力緩衝用突出部が微小な弾性変形をして応力（衝撃力）を緩衝する作用をするため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、下側突出部の角部の層間膜クラックを防止することができる。   By adopting the above configuration, even when a load or impact force is applied to the pad electrode during wire bonding, the stress buffering protrusions undergo minute elastic deformation, particularly at the corners of the lower protruding parts where stress concentration tends to occur. In order to buffer the stress (impact force), only a small stress (impact force) is applied to this portion of the interlayer insulating film. Therefore, interlayer film cracks at the corners of the lower protrusion can be prevented.

上記発明において好ましくは、上記主電極層は、その角部領域において突出した応力緩衝用突出部を含む。   Preferably, in the above invention, the main electrode layer includes a stress buffering protrusion protruding in the corner region.

上記構成を採用することにより、ワイヤボンディング時にパッド電極に荷重または衝撃力が加わっても、特に応力集中の起こりやすい主電極層の角部において、応力緩衝用突出部が微小な弾性変形をして応力（衝撃力）を緩衝する作用を及ぼすため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、主電極層の角部の層間膜クラックを防止することができる。   By adopting the above configuration, even when a load or impact force is applied to the pad electrode during wire bonding, the stress buffering protrusions undergo minute elastic deformation, particularly at the corners of the main electrode layer where stress concentration is likely to occur. In order to buffer the stress (impact force), only a small stress (impact force) is applied to the interlayer insulating film in this portion. Therefore, interlayer film cracks at the corners of the main electrode layer can be prevented.

上記発明において好ましくは、上記下側電極層および上記接続孔の少なくとも一方は、その角部領域において突出した応力緩衝用突出部を含む。   In the above invention, preferably, at least one of the lower electrode layer and the connection hole includes a stress buffering protrusion protruding in a corner region.

上記構成を採用することにより、ワイヤボンディング時にパッド電極に荷重または衝撃力が加わっても、特に応力集中の起こりやすい下側電極層や接続孔の角部において、応力緩衝用突出部が微小な弾性変形をして応力（衝撃力）を緩衝する作用を及ぼすため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、下側電極層や接続孔の角部の層間膜クラックを防止することができる。   By adopting the above configuration, even if a load or impact force is applied to the pad electrode during wire bonding, the stress buffering protrusions have minute elasticity especially at the corners of the lower electrode layer and connection holes where stress concentration tends to occur. Since the deformation acts to buffer the stress (impact force), only a small stress (impact force) is applied to this portion of the interlayer insulating film. Therefore, interlayer film cracks at the corners of the lower electrode layer and the connection hole can be prevented.

上記発明において好ましくは、上記下側突出部は、その角部領域において上記パッド部を分割する応力緩衝用突出部を含む。   In the present invention, preferably, the lower protrusion includes a stress buffering protrusion that divides the pad in the corner region.

上記構成を採用することにより、ワイヤボンディング時にパッド電極に荷重または衝撃力が加わっても、特に応力集中の起こりやすい下側電極層の下側突出部の角部において、応力緩衝用突出部が微小な弾性変形をして応力（衝撃力）を緩衝する作用を及ぼすため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、下側電極層の下側突出部の角部の層間膜クラックを防止することができる。   By adopting the above configuration, even when a load or impact force is applied to the pad electrode during wire bonding, the stress buffering protrusions are very small at the corners of the lower protrusions of the lower electrode layer where stress concentration is likely to occur. In order to buffer the stress (impact force) by performing an elastic deformation, only a small stress (impact force) is applied to the interlayer insulating film in this portion. Therefore, interlayer film cracks at the corners of the lower protrusions of the lower electrode layer can be prevented.

本発明に基づく半導体装置の製造方法の一つの局面においては、平面形状が、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形、ならびに、これらの少なくとも一部分を含む形状の組合せからなる群から選ばれた平面形状となるような凹部を形成する凹部形成工程と、上記凹部の内面に少なくとも一部を被覆する下敷膜を形成する下敷膜形成工程と、上記絶縁膜で覆われた上記凹部に導電性の電極材質を埋め込むパッド部形成工程とを含み、上記凹部形成工程は、第１の凹部を形成する工程と、上記第１の凹部の一部分においてさらに深く凹む第２の凹部を形成する工程とを含む。   In one aspect of the method for manufacturing a semiconductor device according to the present invention, the planar shape is a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, and at least one corner portion is chamfered. A concave portion forming step for forming a concave portion having a planar shape selected from the group consisting of a rounded substantially polygonal shape and a combination of shapes including at least a portion thereof; and at least a portion of the inner surface of the concave portion. An undercoat film forming step for forming an undercoat film to be coated; and a pad portion forming step for embedding a conductive electrode material in the recess covered with the insulating film, wherein the recess forming step forms a first recess. And a step of forming a second recess that is further deeply recessed in a part of the first recess.

上記方法を採用することにより、上記平面形状を有し、かつ、下側突出部を含むパッド部を形成することとなるため、層間絶縁膜のクラックの発生を防止できる半導体装置を得ることができる。   By adopting the above method, the pad portion having the above planar shape and including the lower protruding portion is formed, so that a semiconductor device capable of preventing the occurrence of cracks in the interlayer insulating film can be obtained. .

本発明に基づく半導体装置の製造方法の他の局面においては、平面形状が、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形、ならびに、これらの少なくとも一部分を含む形状の組合せからなる群から選ばれた平面形状となるような凹部を形成する凹部形成工程と、上記凹部の内面に少なくとも一部を被覆する下敷膜を形成する下敷膜形成工程と、上記絶縁膜で覆われた上記凹部に導電性の電極材質を埋め込むパッド部形成工程とを含み、上記凹部形成工程は、パッド部本体となる凹部本体を形成する工程と、その角部領域に応力緩衝用絶縁壁を形成するための絶縁壁凹部を形成する工程とを含む。   In another aspect of the method for manufacturing a semiconductor device according to the present invention, the planar shape is approximately circular, approximately elliptical, approximately polygonal with at least one interior angle greater than 90 °, and at least one corner is chamfered. A concave portion forming step for forming a concave portion having a planar shape selected from the group consisting of a rounded substantially polygonal shape and a combination of shapes including at least a portion thereof; and at least a portion of the inner surface of the concave portion. An underlay film forming step for forming an undercoat film to be coated; and a pad portion forming step for embedding a conductive electrode material in the recess covered with the insulating film, wherein the recess forming step is a recess serving as a pad portion main body. Forming a main body, and forming an insulating wall recess for forming a stress buffering insulating wall in the corner region.

上記方法を採用することにより、上記平面形状を有し、かつ、応力緩衝用絶縁壁を含むパッド部を形成することとなるため、層間絶縁膜のクラックの発生を防止できる半導体装置を得ることができる。   By adopting the above method, a pad portion having the above planar shape and including an insulating wall for stress buffering is formed, so that a semiconductor device capable of preventing the occurrence of cracks in the interlayer insulating film can be obtained. it can.

本発明に基づく半導体装置の製造方法のさらに他の局面においては、平面形状が、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形、ならびに、これらの少なくとも一部分を含む形状の組合せからなる群から選ばれた平面形状となるような凹部を形成する凹部形成工程と、上記凹部の内面に少なくとも一部を被覆する下敷膜を形成する下敷膜形成工程と、上記絶縁膜で覆われた上記凹部に導電性の電極材質を埋め込むパッド部形成工程とを含み、上記凹部形成工程は、パッド部本体となる凹部本体を形成する工程と、その角部領域に突出した応力緩衝用突出部を形成するための緩衝用凹部を形成する工程とを含む。   In still another aspect of the method for manufacturing a semiconductor device according to the present invention, the planar shape is a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, and a chamfer at at least one corner portion. A recessed portion forming step for forming a recessed portion having a planar shape selected from the group consisting of a substantially polygonal shape with round or round shape, and a combination of shapes including at least a portion thereof, and at least a portion on the inner surface of the recessed portion An underlay film forming step for forming an undercoat film covering the pad and a pad portion forming step for embedding a conductive electrode material in the recess covered with the insulating film, wherein the recess forming step serves as a pad portion main body. A step of forming a concave body, and a step of forming a buffering recess for forming a stress buffering protrusion protruding in the corner region.

上記方法を採用することにより、上記平面形状を有し、かつ、応力緩衝用突出部を含むパッド部を形成することとなるため、層間絶縁膜のクラックの発生を防止できる半導体装置を得ることができる。   By adopting the above method, a pad portion having the above planar shape and including a stress buffering protruding portion is formed, so that a semiconductor device capable of preventing the occurrence of cracks in the interlayer insulating film can be obtained. it can.

本発明によれば、パッド電極を所定の平面形状とし、さらに、パッド部として、下側突出部、応力緩衝用絶縁壁、応力緩衝用突出部などを適宜組合せて、含めることとしているため、パッド電極にワイヤボンディングを行なう際に荷重または衝撃力が加わっても、角部への応力集中を緩和することができる。その結果、角部近傍における層間絶縁膜のクラックの発生を防止することができる。このようにして、ワイヤボンディング時に許容される荷重または衝撃力が大きくなることから、十分な接続強度となるようにワイヤボンディングを行なうことができ、信頼性の高い半導体装置とすることができる。   According to the present invention, the pad electrode has a predetermined planar shape, and the pad portion includes a lower protruding portion, a stress buffer insulating wall, a stress buffer protruding portion, and the like as appropriate. Even if a load or an impact force is applied when wire bonding is performed on the electrode, the stress concentration on the corner can be reduced. As a result, generation of cracks in the interlayer insulating film in the vicinity of the corner can be prevented. In this manner, since the load or impact force allowed at the time of wire bonding is increased, wire bonding can be performed so that sufficient connection strength can be obtained, and a highly reliable semiconductor device can be obtained.

本発明に基づく実施の形態１における半導体装置の、（ａ）は平面図、（ｂ）は断面図である。BRIEF DESCRIPTION OF THE DRAWINGS (a) of the semiconductor device in Embodiment 1 based on this invention is a top view, (b) is sectional drawing. 本発明に基づく実施の形態１における半導体装置の製造方法の第１の工程を示す説明図である。It is explanatory drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 1 based on this invention. 本発明に基づく実施の形態１における半導体装置の製造方法の第２の工程を示す説明図である。It is explanatory drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 1 based on this invention. 本発明に基づく実施の形態１における半導体装置への衝撃力の伝達を説明する断面図である。It is sectional drawing explaining transmission of the impact force to the semiconductor device in Embodiment 1 based on this invention. 本発明に基づく実施の形態１における半導体装置への衝撃力の伝達を説明する平面図である。It is a top view explaining transmission of the impact force to the semiconductor device in Embodiment 1 based on this invention. 本発明に基づく実施の形態１における半導体装置への衝撃力の伝達を説明する部分拡大図である。It is the elements on larger scale explaining transmission of the impact force to the semiconductor device in Embodiment 1 based on this invention. 本発明に基づく実施の形態１における半導体装置の主要部の断面図である。It is sectional drawing of the principal part of the semiconductor device in Embodiment 1 based on this invention. 本発明に基づく実施の形態１における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 1 based on this invention. 本発明に基づく実施の形態１における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 1 based on this invention. 本発明に基づく実施の形態１における半導体装置の他の第３の例の主要部の平面図である。It is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 1 based on this invention. 本発明に基づく実施の形態２における半導体装置の、（ａ）は平面図、（ｂ）は断面図である。(A) of the semiconductor device in Embodiment 2 based on this invention is a top view, (b) is sectional drawing. 本発明に基づく実施の形態２における半導体装置の製造方法の第１の工程を示す説明図である。It is explanatory drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 2 based on this invention. 本発明に基づく実施の形態２における半導体装置の製造方法の第２の工程を示す説明図である。It is explanatory drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 2 based on this invention. 本発明に基づく実施の形態２における半導体装置の主要部の断面図である。It is sectional drawing of the principal part of the semiconductor device in Embodiment 2 based on this invention. 本発明に基づく実施の形態２における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 2 based on this invention. 本発明に基づく実施の形態２における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 2 based on this invention. 本発明に基づく実施の形態２における半導体装置の他の第３の例の主要部の平面図である。It is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 2 based on this invention. 本発明に基づく実施の形態２における半導体装置の他の第４の例の主要部の平面図である。It is a top view of the principal part of the other 4th example of the semiconductor device in Embodiment 2 based on this invention. 本発明に基づく実施の形態３における半導体装置の、（ａ）は平面図、（ｂ）は断面図である。(A) of the semiconductor device in Embodiment 3 based on this invention is a top view, (b) is sectional drawing. 本発明に基づく実施の形態３における半導体装置の製造方法の第１の工程を示す説明図である。It is explanatory drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 3 based on this invention. 本発明に基づく実施の形態３における半導体装置の製造方法の第２の工程を示す説明図である。It is explanatory drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 3 based on this invention. 本発明に基づく実施の形態３における半導体装置の主要部の断面図である。It is sectional drawing of the principal part of the semiconductor device in Embodiment 3 based on this invention. 本発明に基づく実施の形態３における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 3 based on this invention. 本発明に基づく実施の形態３における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 3 based on this invention. 本発明に基づく実施の形態３における半導体装置の他の第３の例の主要部の平面図である。It is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 3 based on this invention. 本発明に基づく実施の形態３における半導体装置の他の第４の例の主要部の平面図である。It is a top view of the principal part of the other 4th example of the semiconductor device in Embodiment 3 based on this invention. 本発明に基づく実施の形態４における半導体装置の、（ａ）は平面図、（ｂ）は断面図である。(A) of the semiconductor device in Embodiment 4 based on this invention is a top view, (b) is sectional drawing. 本発明に基づく実施の形態４における半導体装置の製造方法の第１の工程を示す説明図である。It is explanatory drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 4 based on this invention. 本発明に基づく実施の形態４における半導体装置の製造方法の第２の工程を示す説明図である。It is explanatory drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 4 based on this invention. 本発明に基づく実施の形態４における半導体装置の製造方法の第３の工程を示す説明図である。It is explanatory drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 4 based on this invention. 本発明に基づく実施の形態４における半導体装置の主要部の断面図である。It is sectional drawing of the principal part of the semiconductor device in Embodiment 4 based on this invention. 本発明に基づく実施の形態４における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 4 based on this invention. 本発明に基づく実施の形態４における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 4 based on this invention. 本発明に基づく実施の形態４における半導体装置の他の第３の例の主要部の平面図である。It is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 4 based on this invention. 本発明に基づく実施の形態４における半導体装置の他の第４の例の主要部の平面図である。It is a top view of the principal part of the other 4th example of the semiconductor device in Embodiment 4 based on this invention. 本発明に基づく実施の形態５における半導体装置の、（ａ）は平面図、（ｂ）は断面図である。(A) of the semiconductor device in Embodiment 5 based on this invention is a top view, (b) is sectional drawing. 本発明に基づく実施の形態５における半導体装置の製造方法の第１の工程を示す説明図である。It is explanatory drawing which shows the 1st process of the manufacturing method of the semiconductor device in Embodiment 5 based on this invention. 本発明に基づく実施の形態５における半導体装置の製造方法の第２の工程を示す説明図である。It is explanatory drawing which shows the 2nd process of the manufacturing method of the semiconductor device in Embodiment 5 based on this invention. 本発明に基づく実施の形態５における半導体装置の製造方法の第３の工程を示す説明図である。It is explanatory drawing which shows the 3rd process of the manufacturing method of the semiconductor device in Embodiment 5 based on this invention. 本発明に基づく実施の形態５における半導体装置の主要部の断面図である。It is sectional drawing of the principal part of the semiconductor device in Embodiment 5 based on this invention. 本発明に基づく実施の形態５における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 5 based on this invention. 本発明に基づく実施の形態５における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 5 based on this invention. 本発明に基づく実施の形態５における半導体装置の他の第３の例の主要部の平面図である。It is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 5 based on this invention. 本発明に基づく実施の形態５における半導体装置の他の第４の例の主要部の平面図である。It is a top view of the principal part of the other 4th example of the semiconductor device in Embodiment 5 based on this invention. 本発明に基づく実施の形態６における半導体装置の、（ａ）は平面図、（ｂ）は（ａ）のＸＬＶＢ−ＸＬＶＢ線に関する矢視断面図、（ｃ）は断面図である。(A) of the semiconductor device in Embodiment 6 based on this invention is a top view, (b) is arrow sectional drawing regarding the XLVB-XLVB line | wire of (a), (c) is sectional drawing. 本発明に基づく実施の形態６における半導体装置への衝撃力の伝達を説明する断面図である。It is sectional drawing explaining transmission of the impact force to the semiconductor device in Embodiment 6 based on this invention. 本発明に基づく実施の形態６における半導体装置への衝撃力の伝達を説明する平面図である。It is a top view explaining transmission of the impact force to the semiconductor device in Embodiment 6 based on this invention. 本発明に基づく実施の形態６における半導体装置の主要部の、図４９のＸＬＶＩＩＩ−ＸＬＶＩＩＩ線に関する矢視断面図である。FIG. 50 is a cross-sectional view of the main part of the semiconductor device according to the sixth embodiment of the present invention, taken along line XLVIII-XLVIII in FIG. 49. 本発明に基づく実施の形態６における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 6 based on this invention. 本発明に基づく実施の形態６における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 6 based on this invention. 本発明に基づく実施の形態６における半導体装置の他の第３の例の主要部の平面図である。It is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 6 based on this invention. 本発明に基づく実施の形態６における半導体装置の他の第４の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＩＩＢ−ＬＩＩＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other 4th example of the semiconductor device in Embodiment 6 based on this invention, (b) is arrow sectional drawing regarding the LIIB-LIIB line | wire of (a) It is. 本発明に基づく実施の形態６における半導体装置の他の第５の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＩＩＩＢ−ＬＩＩＩＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other 5th example of the semiconductor device in Embodiment 6 based on this invention, (b) is arrow sectional drawing regarding the LIIIB-LIIIB line | wire of (a). It is. 本発明に基づく実施の形態７における半導体装置の、（ａ）は平面図、（ｂ）は、（ａ）のＸＬＶＢ−ＸＬＶＢ線に関する矢視断面図、（ｃ）は断面図である。(A) is a top view of the semiconductor device in Embodiment 7 based on this invention, (b) is arrow sectional drawing regarding the XLVB-XLVB line | wire of (a), (c) is sectional drawing. 本発明に基づく実施の形態７における半導体装置の主要部の、図４９のＸＬＶＩＩＩ−ＸＬＶＩＩＩ線に関する矢視断面図である。It is arrow sectional drawing regarding the XLVIII-XLVIII line | wire of FIG. 49 of the principal part of the semiconductor device in Embodiment 7 based on this invention. 本発明に基づく実施の形態７における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 7 based on this invention. 本発明に基づく実施の形態７における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 7 based on this invention. 本発明に基づく実施の形態７における半導体装置の他の第３の例の主要部の平面図である。It is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 7 based on this invention. 本発明に基づく実施の形態７における半導体装置の他の第４の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＩＸＢ−ＬＩＸＢ線に関する矢視断面図である。(A) is a top view of the principal part of other 4th example of the semiconductor device in Embodiment 7 based on this invention, (b) is arrow sectional drawing regarding the LIXB-LIXB line | wire of (a) It is. 本発明に基づく実施の形態７における半導体装置の他の第５の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＸＢ−ＬＸＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other 5th example of the semiconductor device in Embodiment 7 based on this invention, (b) is arrow sectional drawing regarding the LXB-LXB line | wire of (a). It is. 本発明に基づく実施の形態８における半導体装置の、（ａ）は平面図、（ｂ）は（ａ）のＬＸＩＢ−ＬＸＩＢ線に関する矢視断面図、（ｃ）は断面図である。(A) is a top view of the semiconductor device in Embodiment 8 based on this invention, (b) is arrow sectional drawing regarding the LXIB-LXIB line | wire of (a), (c) is sectional drawing. 本発明に基づく実施の形態８における半導体装置の主要部の、図６３のＬＸＩＩ−ＬＸＩＩ線に関する矢視断面図である。FIG. 66 is a cross-sectional view taken along the line LXII-LXII in FIG. 63 of the main part of the semiconductor device according to the eighth embodiment of the present invention. 本発明に基づく実施の形態８における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 8 based on this invention. 本発明に基づく実施の形態８における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 8 based on this invention. 本発明に基づく実施の形態８における半導体装置の他の第３の例の主要部の平面図である。It is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 8 based on this invention. 本発明に基づく実施の形態８における半導体装置の他の第４の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＸＶＩＢ−ＬＸＶＩＢ線に関する矢視断面図である。(A) is a top view of the principal part of other 4th example of the semiconductor device in Embodiment 8 based on this invention, (b) is arrow sectional drawing regarding the LXVIB-LXVIB line | wire of (a) It is. 本発明に基づく実施の形態８における半導体装置の他の第５の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＸＶＩＩＢ−ＬＸＶＩＩＢ線に関する矢視断面図である。(A) is a top view of the principal part of other 5th example of the semiconductor device in Embodiment 8 based on this invention, (b) is arrow sectional drawing regarding the LXVIIB-LXVIIB line | wire of (a) It is. 本発明に基づく実施の形態９における半導体装置の、（ａ）は平面図、（ｂ）は（ａ）のＬＸＩＩＩＢ−ＬＸＩＩＩＢ線に関する矢視断面図、（ｃ）は断面図である。(A) is a top view of the semiconductor device in Embodiment 9 based on this invention, (b) is arrow sectional drawing regarding the LXIIIB-LXIIIB line | wire of (a), (c) is sectional drawing. 本発明に基づく実施の形態９における半導体装置の主要部の、図７０のＬＸＩＸ−ＬＸＩＸ線に関する矢視断面図である。FIG. 71 is a cross-sectional view taken along the line LXIX-LXIX in FIG. 70 of the main part of the semiconductor device according to the ninth embodiment of the present invention; 本発明に基づく実施の形態９における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 9 based on this invention. 本発明に基づく実施の形態９における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 9 based on this invention. 本発明に基づく実施の形態９における半導体装置の他の第３の例の主要部の平面図である。It is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 9 based on this invention. 本発明に基づく実施の形態９における半導体装置の他の第４の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＸＸＩＩＩＢ−ＬＸＸＩＩＩＢ線に関する矢視断面図である。(A) is a top view of the principal part of other 4th example of the semiconductor device in Embodiment 9 based on this invention, (b) is arrow sectional drawing regarding the LXXIIIB-LXXIIIB line | wire of (a) It is. 本発明に基づく実施の形態９における半導体装置の他の第５の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＸＸＩＶＢ−ＬＸＸＩＶＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other 5th example of the semiconductor device in Embodiment 9 based on this invention, (b) is arrow sectional drawing regarding the LXXIVB-LXXIVB line | wire of (a) It is. 本発明に基づく実施の形態９における半導体装置の他の第６の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＸＸＶＢ−ＬＸＸＶＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other sixth example of the semiconductor device according to the ninth embodiment of the present invention, and (b) is a cross-sectional view taken along line LXXVB-LXXVB in (a). It is. 本発明に基づく実施の形態９における半導体装置の他の第７の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＸＸＶＩＢ−ＬＸＸＶＩＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other seventh example of the semiconductor device according to the ninth embodiment of the present invention, and (b) is a sectional view taken along line LXXVIB-LXXVIB in (a). It is. 本発明に基づく実施の形態１０における半導体装置の、（ａ）は平面図、（ｂ）は、（ａ）のＬＸＸＶＩＩＢ−ＬＸＸＶＩＩＢ線に関する矢視断面図、（ｃ）は断面図である。(A) is a top view of the semiconductor device in Embodiment 10 based on this invention, (b) is arrow sectional drawing regarding the LXXVIIB-LXXVIIB line | wire of (a), (c) is sectional drawing. 本発明に基づく実施の形態１０における半導体装置の主要部の、図７９のＬＸＸＶＩＩＩ−ＬＸＸＶＩＩＩ線に関する矢視断面図である。FIG. 80 is a cross sectional view of the main part of the semiconductor device according to the tenth embodiment according to the invention, taken along the line LXXVIII-LXXVIII in FIG. 79; 本発明に基づく実施の形態１０における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 10 based on this invention. 本発明に基づく実施の形態１０における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 10 based on this invention. 本発明に基づく実施の形態１０における半導体装置の他の第３の例の主要部の平面図である。It is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 10 based on this invention. 本発明に基づく実施の形態１０における半導体装置の他の第４の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＸＸＸＩＩＢ−ＬＸＸＸＩＩＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other 4th example of the semiconductor device in Embodiment 10 based on this invention, (b) is arrow sectional drawing regarding the LXXXIIB-LXXXIIB line | wire of (a) It is. 本発明に基づく実施の形態１０における半導体装置の他の第５の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＸＸＸＩＩＩＢ−ＬＸＸＸＩＩＩＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other fifth example of the semiconductor device according to the tenth embodiment of the present invention, and (b) is a cross-sectional view taken along the line LXXXIIIB-LXXXIIIB in (a). It is. 本発明に基づく実施の形態１０における半導体装置の他の第６の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＸＸＸＩＶＢ−ＬＸＸＸＩＶＢ線に関する矢視断面図である。(A) is a top view of the principal part of another sixth example of the semiconductor device according to the tenth embodiment of the present invention, and (b) is a cross-sectional view taken along line LXXXIVB-LXXXIVB in (a). It is. 本発明に基づく実施の形態１０における半導体装置の他の第７の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＬＸＸＸＶＢ−ＬＸＸＸＶＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other seventh example of the semiconductor device according to the tenth embodiment of the present invention, and (b) is a sectional view taken along line LXXXVB-LXXXVB in (a). It is. 本発明に基づく実施の形態１１における半導体装置の、（ａ）は平面図、（ｂ）は、（ａ）のＬＸＸＸＶＩＢ−ＬＸＸＸＶＩＢ線に関する矢視断面図、（ｃ）は断面図である。(A) is a top view of the semiconductor device in Embodiment 11 based on this invention, (b) is arrow sectional drawing regarding the LXXXVIB-LXXXVIB line | wire of (a), (c) is sectional drawing. 本発明に基づく実施の形態１１における半導体装置への衝撃力の伝達を説明する断面図である。It is sectional drawing explaining transmission of the impact force to the semiconductor device in Embodiment 11 based on this invention. 本発明に基づく実施の形態１１における半導体装置への衝撃力の伝達を説明する平面図である。It is a top view explaining transmission of the impact force to the semiconductor device in Embodiment 11 based on this invention. 本発明に基づく実施の形態１１における半導体装置の主要部の、図９０のＬＸＸＸＩＸ−ＬＸＸＸＩＸ線に関する矢視断面図である。90 is a cross-sectional view of the main part of the semiconductor device according to the eleventh embodiment of the present invention, taken along the line LXXXIX-LXXXIX in FIG. 90. FIG. 本発明に基づく実施の形態１１における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 11 based on this invention. 本発明に基づく実施の形態１１における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 11 based on this invention. 本発明に基づく実施の形態１１における半導体装置の他の第３の例の主要部の平面図である。It is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 11 based on this invention. 本発明に基づく実施の形態１１における半導体装置の他の第４の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＸＣＩＩＩＢ−ＸＣＩＩＩＢ線に関する矢視断面図である。(A) is a top view of the principal part of other 4th example of the semiconductor device in Embodiment 11 based on this invention, (b) is arrow sectional drawing regarding the XCIIIB-XCIIIB line | wire of (a) It is. 本発明に基づく実施の形態１２における半導体装置の、（ａ）は平面図、（ｂ）は（ａ）のＸＣＩＶＢ−ＸＣＩＶＢ線に関する矢視断面図、（ｃ）は断面図である。(A) is a top view of the semiconductor device in Embodiment 12 based on this invention, (b) is arrow sectional drawing regarding the XCIVB-XCIVB line | wire of (a), (c) is sectional drawing. 本発明に基づく実施の形態１２における半導体装置の主要部の、図９６のＸＣＶ−ＸＣＶ線に関する矢視断面図である。FIG. 96 is a cross sectional view of the main part of the semiconductor device according to the twelfth embodiment according to the invention, taken along the line XCV-XCV in FIG. 96; 本発明に基づく実施の形態１２における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 12 based on this invention. 本発明に基づく実施の形態１２における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 12 based on this invention. 本発明に基づく実施の形態１２における半導体装置の他の第３の例の主要部の平面図である。It is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 12 based on this invention. 本発明に基づく実施の形態１２における半導体装置の他の第４の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＸＣＩＸＢ−ＸＣＩＸＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other fourth example of the semiconductor device according to the twelfth embodiment of the present invention, and (b) is a cross-sectional view taken along line XCIXB-XCIXB in (a). It is. 本発明に基づく実施の形態１２における半導体装置の他の第５の例の主要部の平面図である。It is a top view of the principal part of the other 5th example of the semiconductor device in Embodiment 12 based on this invention. 本発明に基づく実施の形態１３における半導体装置の、（ａ）は平面図、（ｂ）は（ａ）のＣＩＢ−ＣＩＢ線に関する矢視断面図、（ｃ）は断面図である。(A) is a top view of the semiconductor device in Embodiment 13 based on this invention, (b) is arrow sectional drawing regarding the CIB-CIB line | wire of (a), (c) is sectional drawing. 本発明に基づく実施の形態１３における半導体装置の主要部の、図１０３のＣＩＩ−ＣＩＩ線に関する矢視断面図である。It is arrow sectional drawing regarding the CII-CII line | wire of FIG. 103 of the principal part of the semiconductor device in Embodiment 13 based on this invention. 本発明に基づく実施の形態１３における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 13 based on this invention. 本発明に基づく実施の形態１３における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 13 based on this invention. 本発明に基づく実施の形態１３における半導体装置の他の第３の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＣＶＢ−ＣＶＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 13 based on this invention, (b) is arrow sectional drawing regarding the CVB-CVB line | wire of (a). It is. 本発明に基づく実施の形態１３における半導体装置の他の第４の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＣＶＩＢ−ＣＶＩＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other fourth example of the semiconductor device according to the thirteenth embodiment of the present invention, and (b) is a cross-sectional view taken along the line CVIB-CVIB in (a). It is. 本発明に基づく実施の形態１３における半導体装置の他の第５の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＣＶＩＩＢ−ＣＶＩＩＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other fifth example of the semiconductor device according to the thirteenth embodiment of the present invention, and (b) is a cross-sectional view taken along line CVIIB-CVIIB in (a). It is. 本発明に基づく実施の形態１４における半導体装置の、（ａ）は平面図、（ｂ）は、（ａ）のＣＶＩＩＩＢ−ＣＶＩＩＩＢ線に関する矢視断面図、（ｃ）は断面図である。(A) is a top view of the semiconductor device in Embodiment 14 based on this invention, (b) is arrow sectional drawing regarding the CVIIIB-CVIIIB line | wire of (a), (c) is sectional drawing. 本発明に基づく実施の形態１４における半導体装置の主要部の、図１１０のＣＩＸ−ＣＩＸ線に関する矢視断面図である。It is arrow sectional drawing regarding the CIX-CIX line | wire of FIG. 110 of the principal part of the semiconductor device in Embodiment 14 based on this invention. 本発明に基づく実施の形態１４における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 14 based on this invention. 本発明に基づく実施の形態１４における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 14 based on this invention. 本発明に基づく実施の形態１４における半導体装置の他の第３の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＣＸＩＩＢ−ＣＸＩＩＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other third example of the semiconductor device according to the fourteenth embodiment of the present invention, and (b) is a cross-sectional view taken along line CXIIB-CXIIB in (a). It is. 本発明に基づく実施の形態１４における半導体装置の他の第４の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＣＸＩＩＩＢ−ＣＸＩＩＩＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other fourth example of the semiconductor device according to the fourteenth embodiment of the present invention, and (b) is a cross-sectional view taken along line CXIIIB-CXIIIB in (a). It is. 本発明に基づく実施の形態１４における半導体装置の他の第５の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＣＸＩＶＢ−ＣＸＩＶＢ線に関する矢視断面図である。(A) is a top view of the principal part of the other fifth example of the semiconductor device according to the fourteenth embodiment of the present invention, and (b) is a cross-sectional view taken along line CXIVB-CXIVB in (a). It is. 本発明に基づく実施の形態１５における半導体装置の、（ａ）は平面図、（ｂ）は、（ａ）のＣＸＶＢ−ＣＸＶＢ線に関する矢視断面図、（ｃ）は断面図である。(A) is a top view of the semiconductor device in Embodiment 15 based on this invention, (b) is arrow sectional drawing regarding the CXVB-CXVB line | wire of (a), (c) is sectional drawing. 本発明に基づく実施の形態１５における半導体装置の主要部の、図１１７のＣＸＶＩ−ＣＸＶＩ線に関する矢視断面図である。It is arrow sectional drawing regarding the CXVI-CXVI line | wire of FIG. 117 of the principal part of the semiconductor device in Embodiment 15 based on this invention. 本発明に基づく実施の形態１５における半導体装置の他の第１の例の主要部の平面図である。It is a top view of the principal part of the other 1st example of the semiconductor device in Embodiment 15 based on this invention. 本発明に基づく実施の形態１５における半導体装置の他の第２の例の主要部の平面図である。It is a top view of the principal part of the other 2nd example of the semiconductor device in Embodiment 15 based on this invention. 本発明に基づく実施の形態１５における半導体装置の他の第３の例の主要部の平面図である。It is a top view of the principal part of the other 3rd example of the semiconductor device in Embodiment 15 based on this invention. 本発明に基づく実施の形態１５における半導体装置の他の第４の例の主要部の、（ａ）は平面図であり、（ｂ）は、（ａ）のＣＸＸＢ−ＣＸＸＢ線に関する矢視断面図である。(A) is a top view of the principal part of other 4th example of the semiconductor device in Embodiment 15 based on this invention, (b) is arrow sectional drawing regarding the CXXB-CXXB line | wire of (a) It is. 本発明に基づく実施の形態１５における半導体装置の他の第５の例の主要部の平面図である。It is a top view of the principal part of the other 5th example of the semiconductor device in Embodiment 15 based on this invention. 従来技術に基づく半導体装置の、（ａ）は平面図、（ｂ）は断面図である。(A) of the semiconductor device based on a prior art is a top view, (b) is sectional drawing. 従来技術に基づく半導体装置の製造方法の第１の工程を示す説明図である。It is explanatory drawing which shows the 1st process of the manufacturing method of the semiconductor device based on a prior art. 従来技術に基づく半導体装置の製造方法の第２の工程を示す説明図である。It is explanatory drawing which shows the 2nd process of the manufacturing method of the semiconductor device based on a prior art. 従来技術に基づく半導体装置の製造方法の第３の工程を示す説明図である。It is explanatory drawing which shows the 3rd process of the manufacturing method of the semiconductor device based on a prior art. 従来技術に基づく半導体装置の製造方法の第４の工程を示す説明図である。It is explanatory drawing which shows the 4th process of the manufacturing method of the semiconductor device based on a prior art. 従来技術に基づく半導体装置の製造方法の第５の工程を示す説明図である。It is explanatory drawing which shows the 5th process of the manufacturing method of the semiconductor device based on a prior art. 従来技術に基づく半導体装置の製造方法の第６の工程を示す説明図である。It is explanatory drawing which shows the 6th process of the manufacturing method of the semiconductor device based on a prior art. 従来技術に基づく半導体装置の製造方法の第７の工程を示す説明図である。It is explanatory drawing which shows the 7th process of the manufacturing method of the semiconductor device based on a prior art. 従来技術に基づく半導体装置の製造方法の第８の工程を示す説明図である。It is explanatory drawing which shows the 8th process of the manufacturing method of the semiconductor device based on a prior art. 従来技術に基づく半導体装置の製造方法の第９の工程を示す説明図である。It is explanatory drawing which shows the 9th process of the manufacturing method of the semiconductor device based on a prior art. 従来技術に基づく半導体装置の製造方法の第１０の工程を示す説明図である。It is explanatory drawing which shows the 10th process of the manufacturing method of the semiconductor device based on a prior art. 従来技術に基づく半導体装置への衝撃力の伝達を説明する断面図である。It is sectional drawing explaining transmission of the impact force to the semiconductor device based on a prior art. 従来技術に基づく半導体装置への衝撃力の伝達を説明する断面図である。It is sectional drawing explaining transmission of the impact force to the semiconductor device based on a prior art. 従来技術に基づく半導体装置への衝撃力の伝達を説明する平面図である。It is a top view explaining transmission of the impact force to the semiconductor device based on a prior art.

本発明は、銅配線などの形成方法として使われている埋込配線法で形成したパッド電極においても、ワイヤボンディングなどの外部端子との接続工程で荷重または衝撃力が加わったとしても、パッド電極の周囲や角の絶縁膜にクラックが発生しにくいようにするためのものである。   The present invention provides a pad electrode formed by a buried wiring method used as a method for forming a copper wiring or the like, even if a load or impact force is applied in a connection process with an external terminal such as wire bonding. This is intended to prevent cracks from occurring in the insulating film around the corners and corners.

（実施の形態１）
（構成）
本実施の形態における半導体装置の断面構造図を図１に示す。 (Embodiment 1)
(Constitution)
FIG. 1 shows a cross-sectional structure diagram of the semiconductor device in this embodiment.

図１に示されるように、半導体基板１の上に素子分離絶縁膜２、ゲート絶縁膜３、ゲート電極４、不純物拡散層５が形成され、ＭＯＳトランジスタ６を構成している。さらにその上側に下地絶縁膜７が形成されており、第１の配線溝９を含む第１の金属（Ｗ）配線層１０から下に向けて下地絶縁膜７を貫通する形にコンタクトホール８が構成されている。さらに下地絶縁膜７の上側に第１の層間絶縁膜１１が形成されており、第２の配線溝１３を含む第２の金属（Ｃｕ）配線層１４から下に向けて第１の層間絶縁膜１１を貫通する形に第１のビアホール１２が形成されている。さらに第１の層間絶縁膜１１の上側に第２の層間絶縁膜１５が形成されており、第３の配線溝１７を含む第３の金属（Ｃｕ）配線層１８から下に向けて第２の層間絶縁膜１５を貫通する形に第２のビアホール１６が形成されている。第３の金属（Ｃｕ）配線層１００の一部は、パッド電極１０１となっている。第２の層間絶縁膜１５の上側には、保護絶縁膜１０２、バッファコート膜１０３が覆っているが、パッド電極１０１に対応する箇所には、パッド電極開口部１０４としてパッド電極１０１が露出する形になっている。   As shown in FIG. 1, an element isolation insulating film 2, a gate insulating film 3, a gate electrode 4, and an impurity diffusion layer 5 are formed on a semiconductor substrate 1 to constitute a MOS transistor 6. A base insulating film 7 is further formed on the upper side, and a contact hole 8 is formed so as to penetrate the base insulating film 7 downward from the first metal (W) wiring layer 10 including the first wiring trench 9. It is configured. Further, a first interlayer insulating film 11 is formed on the upper side of the base insulating film 7, and the first interlayer insulating film faces downward from the second metal (Cu) wiring layer 14 including the second wiring trench 13. A first via hole 12 is formed so as to penetrate 11. Further, a second interlayer insulating film 15 is formed on the upper side of the first interlayer insulating film 11, and the second interlayer insulating film 15 including the third wiring trench 17 is directed downward from the third metal (Cu) wiring layer 18. A second via hole 16 is formed so as to penetrate the interlayer insulating film 15. Part of the third metal (Cu) wiring layer 100 is a pad electrode 101. A protective insulating film 102 and a buffer coat film 103 are covered on the upper side of the second interlayer insulating film 15, but the pad electrode 101 is exposed as a pad electrode opening 104 at a position corresponding to the pad electrode 101. It has become.

（製造方法）
また、図１に示した本実施の形態における半導体装置の製造方法を図２、図３に示す。従来技術に基づいて図１２９に示した構造を形成した後、図２に示すように、第２の金属（Ｃｕ）配線層１４の上に、銅（Ｃｕ）の拡散防止層としてシリコン窒化膜（ＳｉＮ）１５ａ、シリコン酸化膜（ＳｉＯ）などの絶縁膜１５ｂ、シリコン窒化膜（ＳｉＮ）１５ｃ、シリコン酸化膜（ＳｉＯ）などの絶縁膜１５ｄからなる４層構造の第２の層間絶縁膜１５をプラズマＣＶＤ法などの方法で堆積する。 (Production method)
2 and 3 show a method for manufacturing the semiconductor device in the present embodiment shown in FIG. After the structure shown in FIG. 129 is formed based on the conventional technique, as shown in FIG. 2, a silicon nitride film (as a copper (Cu) diffusion prevention layer) is formed on the second metal (Cu) wiring layer 14. The second interlayer insulating film 15 having a four-layer structure composed of an insulating film 15b such as SiN) 15a, a silicon oxide film (SiO), a silicon nitride film (SiN) 15c, and an insulating film 15d such as a silicon oxide film (SiO) is plasma treated. It deposits by methods, such as CVD method.

写真製版・エッチング技術を用いて、第２の層間絶縁膜１５の所望の部分に第２のビアホール１６と第３の配線溝１７としての凹部を形成する。このとき、同時に、パッド電極を設ける部分にも凹部を形成するが、その形状を、従来の四角形に変わり、内角が９０°よりも大きい多角形、たとえば、図１（ａ）に示すような八角形とする。   A second via hole 16 and a recess as a third wiring groove 17 are formed in a desired portion of the second interlayer insulating film 15 by using photolithography and etching techniques. At the same time, a recess is also formed in the portion where the pad electrode is provided, but the shape is changed to a conventional square, and a polygon having an interior angle larger than 90 °, for example, eight as shown in FIG. It is a square.

前述と同様の方法により、第２のビアホール１６および第３の配線溝１７を埋込むように、下敷膜１００ａと銅シード膜１００ｂ、銅めっき膜１００ｃを全面に１．５〜３．０μｍ程度堆積した後に、化学機械研磨法で第２のビアホール１６と第３の配線溝１７以外の銅膜１８ｃ，１８ｂ、下敷膜１８ａを除去し、第３の埋込金属（Ｃｕ）配線層１００、パッド電極１０１を形成する。   By the same method as described above, an underlayer film 100a, a copper seed film 100b, and a copper plating film 100c are deposited on the entire surface so as to fill the second via hole 16 and the third wiring groove 17 by about 1.5 to 3.0 μm. After that, the copper films 18c and 18b and the underlying film 18a other than the second via hole 16 and the third wiring groove 17 are removed by a chemical mechanical polishing method, the third buried metal (Cu) wiring layer 100, the pad electrode 101 is formed.

なお、通常、最上層の金属（Ｃｕ）配線層はワイヤボンディングされることを考慮して、０．８〜１．５μｍ程度の比較的厚膜の金属配線が用いられる。   In general, a metal wiring with a relatively thick film of about 0.8 to 1.5 μm is used in consideration of wire bonding for the uppermost metal (Cu) wiring layer.

図３に示すように、第３の金属（Ｃｕ）配線層１００の上に、銅の拡散防止層としての緻密なシリコン窒化膜１０２ａを堆積した後、シリコン窒化膜、シリコン酸化膜、シリコン酸窒化膜、あるいは、これらの積層構造膜などの保護絶縁膜１０２ｂを１．０μｍ程度堆積する。さらに、その上に、必要に応じてポリイミドなどのバッファコート膜１０３を５〜１０μｍ程度、第２の保護絶縁膜として形成し、ワイヤボンディング法などの方法で外部端子（図示省略）と接続するために、パッド電極１０１の所望部分に開口部１０４を設ける。   As shown in FIG. 3, after depositing a dense silicon nitride film 102a as a copper diffusion prevention layer on the third metal (Cu) wiring layer 100, a silicon nitride film, a silicon oxide film, and a silicon oxynitride A protective insulating film 102b such as a film or a laminated structure film thereof is deposited by about 1.0 μm. Further, a buffer coat film 103 such as polyimide is formed thereon as a second protective insulating film as necessary, and is connected to an external terminal (not shown) by a method such as a wire bonding method. In addition, an opening 104 is provided in a desired portion of the pad electrode 101.

（作用・効果）
以上のように、このような本発明の実施の形態によれば、図４、図５に示すように、パッド電極１０１の形状を正八角形としたので、ワイヤ１０５をボンディングするときに荷重または衝撃力１０６，１０７が加わっても、図６のように、パッド電極１０１の角部１０８への応力集中は四角形の場合に比べて大幅に低減できる。そのため、層間絶縁膜にクラックが発生するのを防止することが可能になる。 (Action / Effect)
As described above, according to such an embodiment of the present invention, as shown in FIGS. 4 and 5, since the shape of the pad electrode 101 is a regular octagon, a load or an impact is applied when the wire 105 is bonded. Even if the forces 106 and 107 are applied, the stress concentration on the corner 108 of the pad electrode 101 can be significantly reduced as compared with the case of the quadrangular shape as shown in FIG. Therefore, it is possible to prevent cracks from occurring in the interlayer insulating film.

したがって、外部端子との接続強度を十分に確保し得る条件でボンディングできるので、接続を安定に、かつ、容易に行なうことができ、高品質の半導体装置が低コストで得られるという効果がある。また、相対的にボンディング時の荷重または衝撃力の許容値を高くする必要のあるパッド電極を縮小化した場合にも有効な方法となる。   Therefore, since bonding can be performed under conditions that can sufficiently secure the connection strength with the external terminal, the connection can be performed stably and easily, and there is an effect that a high-quality semiconductor device can be obtained at low cost. This method is also effective when the pad electrode that needs to have a relatively high allowable load or impact force during bonding is reduced.

なお、図１では、パッド電極１０１の形状が正八角形の場合について述べたが、所望の部分の内角を９０°よりも大きい多角形としても同様の効果を奏する。   In FIG. 1, the case where the pad electrode 101 has a regular octagonal shape has been described. However, the same effect can be obtained even when the interior angle of a desired portion is a polygon larger than 90 °.

また、図７に断面図を示すが、平面図においては、図８に示すような円形のパッド電極あるいは楕円形のパッド電極、図９や図１０に示すような所望の部分の角部に丸みや面取りをつけた形状としてもよい。さらに、これらの形状を部分的に採用したり、組合せて採用したパッド電極の形状としてもよい。   FIG. 7 shows a cross-sectional view. In a plan view, a circular pad electrode or an elliptical pad electrode as shown in FIG. 8 is rounded at a corner of a desired portion as shown in FIG. 9 or FIG. Alternatively, the shape may be chamfered. Furthermore, it is good also as a shape of the pad electrode which employ | adopted these shapes partially or employ | adopted combining them.

また、上記の実施の形態では、ボンディングパッド電極を構成する金属電極の主たる構成金属が銅である場合について述べたが、同様な埋込配線プロセスで形成する他の金属の場合でも同様の効果を奏する。たとえば、アルミニウムあるいはその合金を含む金属電極、金、銀、白金などの貴金属を含む金属電極に適用してもよい。   In the above embodiment, the case where the main constituent metal of the metal electrode constituting the bonding pad electrode is copper has been described. However, the same effect can be obtained in the case of another metal formed by a similar embedded wiring process. Play. For example, the present invention may be applied to a metal electrode including aluminum or an alloy thereof, or a metal electrode including a noble metal such as gold, silver, or platinum.

（実施の形態２）
（構成）
上記実施の形態では、パッド電極が最上層の金属（Ｃｕ）配線層で形成されており、均一な厚みである場合について述べたが、ボンディング時の荷重または衝撃力を緩和させるために、パッド電極の厚みを部分的に厚くし、この部分の主要な平面形状を実施の形態１と同様に、円形、楕円形、少なくとも１つの内角が９０°よりも大きい多角形、少なくとも１つの角部に面取りや丸みをつけた多角形のいずれか、あるいは、これらの形状の部分適用や組合せとしても、同様の効果を奏する。このような本発明の他の実施の形態による半導体装置の構造を図１１に示す。 (Embodiment 2)
(Constitution)
In the above embodiment, the case where the pad electrode is formed of the uppermost metal (Cu) wiring layer and has a uniform thickness has been described. In order to reduce the load or impact force during bonding, the pad electrode In the same manner as in the first embodiment, the main planar shape of this portion is circular, elliptical, a polygon having at least one interior angle greater than 90 °, and chamfering at least one corner. The same effect can be obtained by applying any one of or a rounded polygon, or partial application or combination of these shapes. FIG. 11 shows the structure of a semiconductor device according to another embodiment of the present invention.

図１１（ｂ）に示すように、パッド電極１０１には、下側突出部１５０が含まれている。他は、図１（ｂ）に示したものと同様である。   As illustrated in FIG. 11B, the pad electrode 101 includes a lower protrusion 150. Others are the same as those shown in FIG.

（製造方法）
また、図１１に示した構造の製造方法を図１２、図１３に示す。図１２９に示した構造を形成した後、図１２に示すように、第２の金属（Ｃｕ）配線層１４の上に、銅の拡散防止層としてシリコン窒化膜１５ａ、シリコン酸化膜などの絶縁膜１５ｂ、シリコン窒化膜１５ｃ、シリコン酸化膜などの絶縁膜１５ｄからなる４層構造の第２の層間絶縁膜１５をプラズマＣＶＤ法などの方法で堆積する。 (Production method)
Moreover, the manufacturing method of the structure shown in FIG. 11 is shown in FIGS. After forming the structure shown in FIG. 129, as shown in FIG. 12, an insulating film such as a silicon nitride film 15a and a silicon oxide film is formed on the second metal (Cu) wiring layer 14 as a copper diffusion prevention layer. A second interlayer insulating film 15 having a four-layer structure made of an insulating film 15d such as 15b, a silicon nitride film 15c, and a silicon oxide film is deposited by a method such as plasma CVD.

写真製版・エッチング技術を用いて、第２の層間絶縁膜１５の所望の部分に第２のビアホール１６と第３の配線溝１７を形成する。このとき、第２のビアホール形成時にパッド電極形成領域の一部に凹部１５０を同時に形成するが、凹部の平面形状を内角９０°よりも大きい多角形、たとえば図１１（ａ）に示すように正八角形とする。また、配線溝形成時に、パッド電極を設ける部分にも配線溝を形成するが、その形状も実施の形態１と同様に内角が９０°よりも大きい多角形、たとえば、正八角形とする。   A second via hole 16 and a third wiring groove 17 are formed in a desired portion of the second interlayer insulating film 15 using photolithography and etching techniques. At this time, the recess 150 is simultaneously formed in a part of the pad electrode formation region at the time of forming the second via hole. However, the planar shape of the recess is a polygon larger than an internal angle of 90 °, for example, as shown in FIG. It is a square. Further, when forming the wiring groove, the wiring groove is also formed in the portion where the pad electrode is provided, and the shape thereof is also a polygon having an inner angle larger than 90 °, for example, a regular octagon like the first embodiment.

前述と同様の方法により、第２のビアホール１６、第３の配線溝１７（パッド電極形成部を含む）、およびパッド電極形成領域の凹部１５０を埋込むように、下敷膜１００ａと銅シード膜１００ｂ、銅めっき膜１００ｃとを全面に堆積した後に、化学機械研磨（ＣＭＰ）法で第２のビアホール１６と第３の配線溝１７、パッド電極部１０１以外の銅膜１８ｃ，１８ｂ、下敷膜１８ａを除去し、第３の埋込金属（Ｃｕ）配線層１００、パッド電極１０１を形成する。   By the same method as described above, the underlying film 100a and the copper seed film 100b are embedded so as to fill the second via hole 16, the third wiring groove 17 (including the pad electrode formation portion), and the recess 150 in the pad electrode formation region. After the copper plating film 100c is deposited on the entire surface, the second via hole 16, the third wiring groove 17, the copper films 18c and 18b other than the pad electrode portion 101, and the underlying film 18a are formed by chemical mechanical polishing (CMP). The third buried metal (Cu) wiring layer 100 and the pad electrode 101 are formed by removing.

なお、通常、最上層の金属（Ｃｕ）配線層はワイヤボンディング性を考慮して、０．８〜１．５μｍ程度の比較的厚膜の金属（Ｃｕ）配線が用いられる。   In general, the uppermost metal (Cu) wiring layer is a relatively thick metal (Cu) wiring of about 0.8 to 1.5 μm in consideration of wire bonding.

図１３に示すように、第３の金属（Ｃｕ）配線層１００の上に、銅の拡散防止層としての緻密なシリコン窒化膜１０２ａを堆積した後、シリコン窒化膜、シリコン酸化膜、シリコン酸窒化膜、あるいは、これらの積層構造膜などの保護絶縁膜１０２ｂを１．０μｍ程度堆積する。さらに、その上に、必要に応じてポリイミドなどのバッファコート膜１０３を５〜１０μｍ程度、第２の保護絶縁膜として形成し、ワイヤボンディング法などの方法で外部端子（図示省略）と接続するために、パッド電極１０１の所望部分に開口部１０４を設ける。   As shown in FIG. 13, after a dense silicon nitride film 102a is deposited as a copper diffusion prevention layer on the third metal (Cu) wiring layer 100, a silicon nitride film, a silicon oxide film, and a silicon oxynitride are deposited. A protective insulating film 102b such as a film or a laminated structure film thereof is deposited by about 1.0 μm. Further, a buffer coat film 103 such as polyimide is formed thereon as a second protective insulating film as necessary, and is connected to an external terminal (not shown) by a method such as a wire bonding method. In addition, an opening 104 is provided in a desired portion of the pad electrode 101.

（作用・効果）
以上のように、このような本発明の実施の形態によれば、図１１に示すように、パッド電極１０１の一部分である下側突出部１５０を含ませることとして実質的なパッド電極厚みを厚くし、かつ、その部分の形状を正八角形としたので、ワイヤボンディングの際に荷重または衝撃力が加わっても、パッド電極の実効厚みが増えただけ緩和させることができ、また、応力が集中しやすい下側突出部１５０の角部への応力集中も四角形の場合に比べて大幅に低減できる。そのため、層間絶縁膜にクラックが発生することを防止することができる。したがって、外部端子との接続強度を十分に確保し得る条件でワイヤボンディングできるので、接続を安定に、かつ、容易に行なうことができ、高品質の半導体装置が低コストで得られるという効果がある。 (Action / Effect)
As described above, according to such an embodiment of the present invention, as shown in FIG. 11, the substantial thickness of the pad electrode is increased by including the lower protrusion 150 which is a part of the pad electrode 101. In addition, since the shape of the portion is a regular octagon, even if a load or impact force is applied during wire bonding, the effective thickness of the pad electrode can be reduced and stress is concentrated. The concentration of stress on the corners of the lower protrusion 150, which is easy to perform, can be greatly reduced as compared to the case of the quadrangular shape. Therefore, it is possible to prevent cracks from occurring in the interlayer insulating film. Therefore, since wire bonding can be performed under conditions that can sufficiently secure the connection strength with the external terminal, the connection can be performed stably and easily, and a high-quality semiconductor device can be obtained at low cost. .

また、相対的にボンディング時の荷重または衝撃力の許容値を高くする必要のあるパッド電極を縮小化した場合にも有効な方法となる。   This method is also effective when the pad electrode that needs to have a relatively high allowable load or impact force during bonding is reduced.

なお、図１１では、下側突出部１５０の形状が正八角形の場合について述べたが、所望の部分の内角を９０°よりも大きい多角形としても、同様の効果を奏する。また、図１４、図１５に示すような円形のパッド電極、あるいは、楕円形のパッド電極、図１６や図１７に示すような所望の部分の角部に丸みや面取りをつけた形状としてもよい。また、図１８のように、下側突出部１５０の形状のみを上記のようにして、パッド電極１０１は従来形状、たとえば四角形としてもよい。さらに、下側突出部の形状として、これらの形状を部分的に採用したり組合せて採用してもよい。   In FIG. 11, the case where the shape of the lower protrusion 150 is a regular octagon has been described, but the same effect can be achieved even if the interior angle of a desired portion is a polygon larger than 90 °. Moreover, it is good also as a circular pad electrode as shown in FIG. 14, FIG. 15, or an elliptical pad electrode, and the shape which rounded and chamfered the corner | angular part of the desired part as shown in FIG.16 and FIG.17. . Further, as shown in FIG. 18, only the shape of the lower protrusion 150 may be formed as described above, and the pad electrode 101 may have a conventional shape, for example, a quadrangle. Further, as the shape of the lower protrusion, these shapes may be partially employed or combined.

（実施の形態３）
（構成）
さらに、パッド電極が第１の金属電極とその上に形成された第２の金属電極とからなり、第１の金属電極の主要な平面形状を、円形、楕円形、少なくとも１つの内角が９０°よりも大きい多角形、少なくとも１つの角部に面取りや丸みをつけた多角形のいずれか、あるいは、その部分形状、または、それらの組合せとしても、同様の効果を奏する。 (Embodiment 3)
(Constitution)
Further, the pad electrode includes a first metal electrode and a second metal electrode formed thereon, and the main planar shape of the first metal electrode is circular, elliptical, and at least one interior angle is 90 °. The same effect can be achieved with a larger polygon, a polygon with chamfered or rounded at least one corner, a partial shape thereof, or a combination thereof.

本実施の形態における半導体装置の構造を図１９に示す。
図１９（ｂ）に示すように、主電極層１０１の上側に上側電極層２０１が接している。パッド電極開口部２０４には、上側電極層２０１が露出している。
他は、図１（ｂ）に示したものと同様である。 FIG. 19 shows the structure of the semiconductor device in this embodiment.
As shown in FIG. 19B, the upper electrode layer 201 is in contact with the upper side of the main electrode layer 101. The upper electrode layer 201 is exposed in the pad electrode opening 204.
Others are the same as those shown in FIG.

（製造方法）
また、図１９の構造の製造方法を図２０、図２１に示す。図２に示した構造を形成するところまでは、実施の形態１と同じである。図２に示す第３の配線溝１７形成時に、パッド電極を設ける部分にも配線溝を形成するが、その形状も実施の形態１と同様に、内角が９０°よりも大きい多角形、たとえば、正八角形とする。その後、前述と同じ方法で、第３の金属（Ｃｕ）配線層１００と第１のパッド電極１０１とを形成する。 (Production method)
Further, a manufacturing method of the structure of FIG. 19 is shown in FIGS. The process until the structure shown in FIG. 2 is formed is the same as that of the first embodiment. When the third wiring groove 17 shown in FIG. 2 is formed, the wiring groove is also formed in the portion where the pad electrode is provided. The shape of the third wiring groove 17 is a polygon having an interior angle larger than 90 °, for example, as in the first embodiment. It is a regular octagon. Thereafter, the third metal (Cu) wiring layer 100 and the first pad electrode 101 are formed by the same method as described above.

図２０に示すように、第３の金属（Ｃｕ）配線層１００や第１のパッド電極１０１の上に重ねるように、第４の金属配線層２００と第２のパッド電極２０１とを形成する。この金属配線層としては、たとえば、アルミニウムを主成分とする配線を用いることができる。下層の銅配線層とアルミニウムとの相互反応を防止するために、下敷膜２００ａとして、窒化チタン膜、チタンと窒化チタン膜の積層膜、タンタル膜、窒化タンタル膜、タンタルと窒化タンタルとの積層膜などをＰＶＤ法やＣＶＤ法を用いて全面に堆積する。その上に、Ａｌ−Ｃｕ膜などのアルミニウム合金膜２００ｂと窒化チタン膜やシリコン酸窒化膜などの反射防止膜２００ｃを堆積した後に、写真製版・エッチング技術を用いて、第４の金属配線層２００や第２のパッド電極２０１を形成する。このアルミニウム配線層２００やパッド電極２０１の厚みは、パッド電極を第１のパッド電極と離れた構造にしているので、０．３〜１．０μｍ程度の厚みでよい。   As shown in FIG. 20, a fourth metal wiring layer 200 and a second pad electrode 201 are formed so as to overlap the third metal (Cu) wiring layer 100 and the first pad electrode 101. As this metal wiring layer, for example, a wiring mainly composed of aluminum can be used. In order to prevent the interaction between the lower copper wiring layer and aluminum, the underlying film 200a is a titanium nitride film, a laminated film of titanium and titanium nitride film, a tantalum film, a tantalum nitride film, or a laminated film of tantalum and tantalum nitride. Are deposited on the entire surface using PVD or CVD. On top of this, after depositing an aluminum alloy film 200b such as an Al—Cu film and an antireflection film 200c such as a titanium nitride film or a silicon oxynitride film, the fourth metal wiring layer 200 is formed using photolithography and etching techniques. And the second pad electrode 201 is formed. The aluminum wiring layer 200 and the pad electrode 201 may have a thickness of about 0.3 to 1.0 μm because the pad electrode is separated from the first pad electrode.

なお、これらのアルミニウム配線形成工程における銅配線表面のダメージや酸化防止のために、第４の金属（Ａｌ）配線層２００や第２のパッド電極２０１は、下層の第３の金属（Ｃｕ）配線層１００や第１のパッド電極１０１を完全に覆うようにするのが望ましい。   Note that the fourth metal (Al) wiring layer 200 and the second pad electrode 201 are formed as a lower third metal (Cu) wiring in order to prevent damage and oxidation of the copper wiring surface in these aluminum wiring forming steps. It is desirable to completely cover the layer 100 and the first pad electrode 101.

図２１に示すように、第４の金属（Ａｌ）配線層２００および第２のパッド電極２０１の上に、銅の拡散防止層としての緻密なシリコン窒化膜２０２ａを堆積した後、シリコン窒化膜、シリコン酸化膜、シリコン酸窒化膜、あるいは、これらの積層構造膜などの保護絶縁膜２０２ｂを１．０μｍ程度堆積する。さらに、その上に、必要に応じてポリイミドなどのバッファコート膜２０３を５〜１０μｍ程度、第２の保護絶縁膜として形成し、ワイヤボンディング法などの方法で外部端子（図示省略）と接続するために、パッド電極２０１の所望部分に開口部２０４を設ける。   As shown in FIG. 21, after depositing a dense silicon nitride film 202a as a copper diffusion prevention layer on the fourth metal (Al) wiring layer 200 and the second pad electrode 201, a silicon nitride film, A protective insulating film 202b such as a silicon oxide film, a silicon oxynitride film, or a laminated structure film thereof is deposited to a thickness of about 1.0 μm. Further, a buffer coating film 203 such as polyimide is formed thereon as a second protective insulating film as necessary to a thickness of about 5 to 10 μm, and is connected to an external terminal (not shown) by a wire bonding method or the like. In addition, an opening 204 is provided in a desired portion of the pad electrode 201.

（作用・効果）
以上のように、このような本発明の実施の形態によれば、図１９に示すように、パッド電極を埋込金属配線層で形成した第１のパッド電極１０１と、エッチング法で形成した第２のパッド電極２０１とを重ねた構造とし、かつ、第１のパッド電極１０１の形状を正八角形としたので、ワイヤをボンディングするときに荷重または衝撃力が加わっても、パッド電極の実効厚みが増えただけ緩和させることができ、また、応力の集中しやすい第１のパッド電極１０１の角部への応力集中も四角形の場合に比べて大幅に低減できる。そのため、層間絶縁膜にクラックが発生することを防止することができる。 (Action / Effect)
As described above, according to such an embodiment of the present invention, as shown in FIG. 19, the first pad electrode 101 in which the pad electrode is formed by the embedded metal wiring layer and the first electrode formed by the etching method are used. 2 and the shape of the first pad electrode 101 is a regular octagon, so even if a load or impact force is applied when bonding the wire, the effective thickness of the pad electrode can be reduced. It can be relaxed as much as it increases, and the stress concentration at the corners of the first pad electrode 101 where stress tends to concentrate can be greatly reduced compared to the case of the quadrangular shape. Therefore, it is possible to prevent cracks from occurring in the interlayer insulating film.

したがって、外部端子との接続強度を十分に確保し得る条件でボンディングできるので、接続を安定に、かつ、容易に行なうことができ、高品質の半導体装置が低コストで得られるという効果がある。また、相対的にボンディング時の荷重または衝撃力の許容値を高くする必要のあるパッド電極を縮小化した場合にも有効な方法となる。さらに、最上層の金属配線層が第３の金属配線層１００と第４の金属配線２００とを重ねたもので、実効膜厚が厚くなるので、低抵抗化でき、配線遅延やノイズマージン低減などにも有効である。   Therefore, since bonding can be performed under conditions that can sufficiently secure the connection strength with the external terminal, the connection can be performed stably and easily, and there is an effect that a high-quality semiconductor device can be obtained at low cost. This method is also effective when the pad electrode that needs to have a relatively high allowable load or impact force during bonding is reduced. Furthermore, the uppermost metal wiring layer is formed by overlapping the third metal wiring layer 100 and the fourth metal wiring 200, and the effective film thickness is increased, so that the resistance can be reduced, wiring delay, noise margin reduction, etc. Also effective.

なお、図１９では、第１のパッド電極と第２のパッド電極とを重ねた構造で、第１のパッド電極１０１の形状が正八角形の場合について述べたが、所望の部分の内角を９０°よりも大きい多角形としても、同様の効果を奏する。   In FIG. 19, the first pad electrode and the second pad electrode are stacked and the first pad electrode 101 has a regular octagonal shape. However, the inner angle of a desired portion is 90 °. The same effect can be achieved with a larger polygon.

また、図２２、図２３に示すような円形のパッド電極あるいは、楕円形のパッド電極、図２４や図２５に示すような所望の部分の角部に丸みや面取りをつけた形状としてもよい。また、図２６のように、第１のパッド電極１０１の形状のみを上記のようにして、第２のパッド電極２０１やパッド電極開口部の形状は従来形状、たとえば、四角形としてもよい。さらに、第１のパッド電極の形状として、これらの形状を部分的に採用したり、組合せて採用してもよい。   Moreover, it is good also as a shape which rounded or chamfered the corner | angular part of the desired part as shown in FIG. 24 and FIG. Further, as shown in FIG. 26, only the shape of the first pad electrode 101 may be as described above, and the shape of the second pad electrode 201 and the pad electrode opening may be a conventional shape, for example, a quadrangle. Further, as the shape of the first pad electrode, these shapes may be partially adopted or combined.

（実施の形態４）
（構成）
さらに、パッド電極が第１の金属電極と第２の金属電極とを大面積の接続孔を介して重ねた構造であり、接続孔の主要な平面形状を、円形、楕円形、少なくとも１つの内角が９０°よりも大きい多角形、少なくとも１つの角部に面取りや丸みをつけた多角形のいずれか、あるいはその部分形状、またはそれらの組合せとしても、同様の効果を奏する。「大面積の接続孔」とは、主電極層の平面形状の外周の内側近傍において主電極層の外周に沿う形状の外周を有する接続孔のことである。このような本発明の他の実施の形態による半導体装置の構造を図２７に示す。 (Embodiment 4)
(Constitution)
Further, the pad electrode has a structure in which the first metal electrode and the second metal electrode are overlapped via a large-area connection hole, and the main planar shape of the connection hole is circular, elliptical, or at least one internal angle. The same effect can be obtained when the polygon is larger than 90 °, the polygon is chamfered or rounded at least at one corner, or a partial shape thereof, or a combination thereof. The “large-area connection hole” is a connection hole having an outer periphery having a shape along the outer periphery of the main electrode layer in the vicinity of the inner periphery of the outer periphery of the planar shape of the main electrode layer. The structure of such a semiconductor device according to another embodiment of the present invention is shown in FIG.

図２７（ｂ）に示すように、パッド電極は、主電極層１０１の下方に下側電極層２５０を含む。パッド電極開口部２０４には、主電極層１０１が露出している。主電極層１０１と下側電極層２５０との間は、接続孔２５１によって接続されている。接続孔２５１は、図２７（ａ）に示すように、いわゆる大面積の接続孔、すなわち、主電極層１０１の平面形状の外周の内側近傍において主電極層１０１の外周に沿う形状の外周を有する接続孔である。他は、図１１（ｂ）に示したものと同様である。   As shown in FIG. 27B, the pad electrode includes a lower electrode layer 250 below the main electrode layer 101. The main electrode layer 101 is exposed in the pad electrode opening 204. The main electrode layer 101 and the lower electrode layer 250 are connected by a connection hole 251. As shown in FIG. 27A, the connection hole 251 has a so-called large-area connection hole, that is, an outer periphery having a shape along the outer periphery of the main electrode layer 101 in the vicinity of the inner periphery of the planar outer periphery of the main electrode layer 101. It is a connection hole. Others are the same as those shown in FIG.

（製造方法）
図２７に示した構造の製造方法を図２８〜図３０に示す。 (Production method)
A method of manufacturing the structure shown in FIG. 27 is shown in FIGS.

図２８に示すように、第１の金属（Ｗ）配線層１０を形成するところまでは、図１２２に示す従来の半導体装置の製造方法（図１２３〜図１２６）と同じである。   As shown in FIG. 28, the process up to the formation of the first metal (W) wiring layer 10 is the same as the conventional method of manufacturing the semiconductor device shown in FIG. 122 (FIGS. 123 to 126).

この第１の金属（Ｗ）配線１０の上に、シリコン酸化膜などの絶縁膜１１ａ、シリコン窒化膜１１ｂ、シリコン酸化膜などの絶縁膜１１ｃからなる３層構造の第１の層間絶縁膜１１をプラズマＣＶＤ法などの方法で堆積する。   A first interlayer insulating film 11 having a three-layer structure including an insulating film 11a such as a silicon oxide film, a silicon nitride film 11b, and an insulating film 11c such as a silicon oxide film is formed on the first metal (W) wiring 10. Deposited by a method such as plasma CVD.

さらに、写真製版・エッチング技術を用いて、第１の層間絶縁膜１１の所望の部分に第１のビアホール１２と第２の配線溝１３とを形成する。第２の配線溝１３を形成するときに、同時に、第１のパッド電極を設ける部分にも、配線溝を形成するが、その形状を、内角が９０°よりも大きい多角形、たとえば正八角形とする。   Further, the first via hole 12 and the second wiring trench 13 are formed in a desired portion of the first interlayer insulating film 11 using photolithography and etching techniques. When the second wiring groove 13 is formed, the wiring groove is also formed in the portion where the first pad electrode is provided at the same time. The shape of the second wiring groove 13 is a polygon having an inner angle larger than 90 °, for example, a regular octagon. To do.

その後、第１のビアホール１２および第２の配線溝１３（下側電極層の形成部を含む）を埋込むように、下敷膜１４ａと銅膜１４ｂ，１４ｃを全面に堆積し、化学機械研磨法で、第１のビアホール１２と第２の配線溝１３以外の銅１４ｃ，１４ｂ、下敷膜１４ａを除去し、第２の埋込金属（Ｃｕ）配線層１４と下側電極層とを形成する。   Thereafter, an underlay film 14a and copper films 14b and 14c are deposited on the entire surface so as to fill the first via hole 12 and the second wiring groove 13 (including the lower electrode layer forming portion), and a chemical mechanical polishing method is performed. Then, the copper 14c, 14b and the underlying film 14a other than the first via hole 12 and the second wiring groove 13 are removed, and the second buried metal (Cu) wiring layer 14 and the lower electrode layer are formed.

図２９に示すように、第２の金属（Ｃｕ）配線層１４の上に、シリコン窒化膜１５ａ、シリコン酸化膜などの絶縁膜１５ｂ、シリコン窒化膜１５ｃ、シリコン酸化膜などの絶縁膜１５ｄからなる４層構造の第２の層間絶縁膜１５をプラズマＣＶＤ法などの方法で堆積する。写真製版・エッチング技術を用いて、第２の層間絶縁膜１５の所望の部分に第２のビアホール１６と第３の配線溝１７とを形成する。このとき、第２のビアホール形成時に、下側電極層の上にも接続孔２５１を同時に形成するが、この平面形状も、内角が９０°よりも大きい多角形、たとえば、正八角形とする。   As shown in FIG. 29, a silicon nitride film 15a, an insulating film 15b such as a silicon oxide film, a silicon nitride film 15c, and an insulating film 15d such as a silicon oxide film are formed on the second metal (Cu) wiring layer 14. A second interlayer insulating film 15 having a four-layer structure is deposited by a method such as a plasma CVD method. A second via hole 16 and a third wiring groove 17 are formed in a desired portion of the second interlayer insulating film 15 using photolithography and etching techniques. At this time, when the second via hole is formed, the connection hole 251 is also formed on the lower electrode layer at the same time. This planar shape is also a polygon having an interior angle larger than 90 °, for example, a regular octagon.

また、第３の配線溝形成時に、主電極層を設ける部分にも配線溝を形成するが、その形状も、内角が９０°よりも大きい多角形、たとえば、正八角形とする。   In addition, when the third wiring groove is formed, the wiring groove is also formed in the portion where the main electrode layer is provided, and the shape thereof is also a polygon having an inner angle larger than 90 °, for example, a regular octagon.

前述と同様の方法により、第２のビアホール１６、第３の配線溝１７、下側電極層上の接続孔２５１、主電極層１０１を埋込むように、下敷膜１００ａと銅膜１００ｂ，１００ｃを全面に堆積し、化学機械研磨法により不要部分を除去することにより、第３の埋込金属（Ｃｕ）配線層１００と主電極層１０１を形成する。   By the same method as described above, the underlying film 100a and the copper films 100b and 100c are formed so as to fill the second via hole 16, the third wiring groove 17, the connection hole 251 on the lower electrode layer, and the main electrode layer 101. A third embedded metal (Cu) wiring layer 100 and a main electrode layer 101 are formed by depositing on the entire surface and removing unnecessary portions by a chemical mechanical polishing method.

図３０に示すように、第３の金属（Ｃｕ）配線層１００および第２のパッド電極１０１の上に、銅の拡散防止層としての緻密なシリコン窒化膜２０２ａを堆積した後、シリコン窒化膜、シリコン酸化膜、シリコン酸窒化膜、あるいはこれらの積層構造膜などの保護絶縁膜２０２ｂを１．０μｍ程度堆積する。さらに、その上に、必要に応じてポリイミドなどのバッファコート膜２０３を５〜１０μｍ程度、第２の保護絶縁膜として形成し、ワイヤボンディング法などの方法で外部端子（図示省略）と接続するために、主電極層１０１の所望部分に開口部２０４を設ける。   As shown in FIG. 30, after depositing a dense silicon nitride film 202a as a copper diffusion prevention layer on the third metal (Cu) wiring layer 100 and the second pad electrode 101, a silicon nitride film, A protective insulating film 202b such as a silicon oxide film, a silicon oxynitride film, or a laminated structure film thereof is deposited to about 1.0 μm. Further, a buffer coating film 203 such as polyimide is formed thereon as a second protective insulating film as necessary to a thickness of about 5 to 10 μm, and is connected to an external terminal (not shown) by a wire bonding method or the like. In addition, an opening 204 is provided in a desired portion of the main electrode layer 101.

（作用・効果）
以上のように、このような本発明の実施例によれば、図２７に示すように、パッド電極を埋込金属配線層で形成した下側電極層２５０と主電極層１０１とを、大面積の接続孔２５１を介して重ねた構造とし、かつ、下側電極層２５０および接続孔２５１の少なくとも一方の形状を正八角形としたので、ワイヤをボンディングするなどの外部端子との接続時に荷重または衝撃力が加わっても、パッド電極の実効厚みが増えただけで緩和させることができ、また、応力の集中しやすい下側電極層２５０や接続孔２５１の角部への応力集中も四角形の場合に比べて大幅に低減できる。そのため、層間絶縁膜にクラックが発生することを防止することができる。 (Action / Effect)
As described above, according to the embodiment of the present invention, as shown in FIG. 27, the lower electrode layer 250 in which the pad electrode is formed of the buried metal wiring layer and the main electrode layer 101 are formed in a large area. And the shape of the lower electrode layer 250 and the connection hole 251 are regular octagons, so that a load or impact is applied when connecting to an external terminal such as wire bonding. Even if force is applied, it can be alleviated simply by increasing the effective thickness of the pad electrode, and the stress concentration at the corners of the lower electrode layer 250 and the connection hole 251 where stress is likely to concentrate is also square. Compared to a significant reduction. Therefore, it is possible to prevent cracks from occurring in the interlayer insulating film.

したがって、外部端子との接続強度を十分に確保し得る条件でボンディングできるので、接続を安定に、かつ容易に行なうことができ、高品質の半導体装置が低コストで得られるという効果がある。   Therefore, since bonding can be performed under conditions that can sufficiently secure the connection strength with the external terminal, the connection can be performed stably and easily, and there is an effect that a high-quality semiconductor device can be obtained at low cost.

また、相対的にボンディング時の荷重または衝撃力の許容値を高くする必要のあるパッド電極を縮小化した場合にも有効な方法となる。   This method is also effective when the pad electrode that needs to have a relatively high allowable load or impact force during bonding is reduced.

さらに、最上層の金属配線層が第３の金属配線層１００と第４の金属配線２００とを重ねたもので、実効膜厚が厚くなるので、低抵抗化でき、配線遅延やノイズマージン低減などにも有効である。   Furthermore, the uppermost metal wiring layer is formed by overlapping the third metal wiring layer 100 and the fourth metal wiring 200, and the effective film thickness is increased, so that the resistance can be reduced, wiring delay, noise margin reduction, etc. Also effective.

さらに、通常、最上層の金属（Ｃｕ）配線層には、ワイヤボンディングなどによる外部端子との接続信頼性を考慮して、０．８〜１．５μｍ程度の比較的厚膜の金属配線が用いられるが、本実施の形態のようにパッド電極を大面積の接続孔を介して重ねた構造とすることにより、実効的なパッド電極厚みを厚くできるので、最上層の金属（Ｃｕ）配線の厚みを微細化に適したさらに薄い配線層とすることも可能となる。   Furthermore, a metal wiring with a relatively thick film of about 0.8 to 1.5 μm is usually used for the uppermost metal (Cu) wiring layer in consideration of connection reliability with an external terminal by wire bonding or the like. However, since the effective pad electrode thickness can be increased by adopting a structure in which the pad electrode is overlapped via a large-area connection hole as in the present embodiment, the thickness of the uppermost metal (Cu) wiring is increased. It is possible to form a thinner wiring layer suitable for miniaturization.

なお、図２７では下側電極層と主電極層とを大面積の接続孔を介して重ねた構造とし、下側電極層２５０の形状が正八角形の場合について述べたが、所望の部分の内角を９０°よりも大きい多角形としても同様の効果を奏する。   In FIG. 27, the case where the lower electrode layer and the main electrode layer are stacked through a large-area connection hole and the shape of the lower electrode layer 250 is a regular octagon has been described. The same effect can be obtained even when the polygon is larger than 90 °.

また、図３１に断面図を示すが、平面図においては、下側電極層２５０を図３２に示すような円形のパッド電極あるいは楕円形のパッド電極、図３３や図３４に示すような所望の部分の角部に丸みや面取りをつけた形状としてもよい。また、図３５のように、下側電極層２５０の形状のみを上記のようにして、接続孔２５１、主電極層１０１やパッド電極開口部２０４の形状は従来形状、たとえば、四角形としてもよい。さらに、下側電極層２５０の形状として、これらの形状を部分的に採用したり、組合せて採用してもよい。   FIG. 31 shows a cross-sectional view. In the plan view, the lower electrode layer 250 has a circular pad electrode or an elliptical pad electrode as shown in FIG. 32, and a desired electrode as shown in FIG. 33 or FIG. The corner may be rounded or chamfered. Further, as shown in FIG. 35, only the shape of the lower electrode layer 250 may be as described above, and the shapes of the connection hole 251, the main electrode layer 101, and the pad electrode opening 204 may be a conventional shape, for example, a quadrangle. Furthermore, as the shape of the lower electrode layer 250, these shapes may be partially adopted or combined.

（実施の形態５）
（構成）
さらに、パッド電極が下側電極層と主電極層とを大面積の接続孔を介して重ねた構造において、下側電極層の厚みを部分的に厚くし、下側突出部とする。この下側突出部の主要な平面形状を、円形、楕円形、少なくとも１つの内角が９０°よりも大きい多角形、少なくとも１つの角部に面取りや丸みをつけた多角形のいずれか、あるいは、その部分形状、または、それらの組合せとしても、同様の効果を奏する。このような本発明の他の実施の形態による半導体装置の構造を図３６に示す。 (Embodiment 5)
(Constitution)
Further, in the structure in which the pad electrode is formed by overlapping the lower electrode layer and the main electrode layer through the large-area connection hole, the thickness of the lower electrode layer is partially increased to form the lower protruding portion. The main planar shape of this lower protrusion is either a circle, an ellipse, a polygon with at least one interior angle greater than 90 °, a polygon with at least one corner chamfered or rounded, or The same effect can be achieved by the partial shape or a combination thereof. FIG. 36 shows the structure of a semiconductor device according to another embodiment of the present invention.

図３６（ｂ）に示すように、パッド電極は、下側電極層２５０の下側に下側突出部２４０を含む。他は、実施の形態４に示したものと同様である。   As shown in FIG. 36B, the pad electrode includes a lower protrusion 240 below the lower electrode layer 250. Others are the same as those shown in the fourth embodiment.

（製造方法）
図３６に示した構造の製造方法を図３７〜図３９に示す。 (Production method)
A method of manufacturing the structure shown in FIG. 36 is shown in FIGS.

図３７に示すように、第１の金属（Ｗ）配線層１０を形成するところまでは、図１２２に示す従来の半導体装置の製造方法（図１２３〜図１２４）と同じである。   As shown in FIG. 37, the process up to the formation of the first metal (W) wiring layer 10 is the same as the conventional method of manufacturing the semiconductor device shown in FIG. 122 (FIGS. 123 to 124).

この第１の金属（Ｗ）配線１０の上に、シリコン窒化膜２３０ａ、シリコン酸化膜などの絶縁膜２３０ｂ、シリコン窒化膜２３０ｃ、シリコン酸化膜などの絶縁膜２３０ｄからなる４層構造の第１の層間絶縁膜２３０をプラズマＣＶＤ法などの方法で堆積する。さらに、写真製版・エッチング技術を用いて、第１の層間絶縁膜１１の所望の部分に第１のビアホール１２と第２の配線溝１３とを形成する。   On the first metal (W) wiring 10, a first four-layer structure comprising a silicon nitride film 230a, an insulating film 230b such as a silicon oxide film, a silicon nitride film 230c, and an insulating film 230d such as a silicon oxide film. An interlayer insulating film 230 is deposited by a method such as a plasma CVD method. Further, the first via hole 12 and the second wiring trench 13 are formed in a desired portion of the first interlayer insulating film 11 using photolithography and etching techniques.

第１のビアホール１２を形成するときに、下側電極層形成領域の一部に凹部２４０を同時に形成するが、その形状を、内角が９０°よりも大きい多角形、たとえば正八角形とする。   When the first via hole 12 is formed, the recess 240 is simultaneously formed in a part of the lower electrode layer formation region, and the shape thereof is a polygon having an inner angle larger than 90 °, for example, a regular octagon.

なお、シリコン窒化膜２３０ａは、第１のビアホール１２形成時に、下側電極層形成領域の凹部２４０が過度にエッチングされるのを防止するためのもので、シリコン窒化膜２３０ａをストッパ膜としてドライエッチングした後に、シリコン窒化膜２３０ａを軽くエッチングすることにより、凹部を制御性よく加工する。   The silicon nitride film 230a is for preventing the recess 240 in the lower electrode layer formation region from being excessively etched when the first via hole 12 is formed. The silicon nitride film 230a is dry-etched using the silicon nitride film 230a as a stopper film. After that, the silicon nitride film 230a is lightly etched to process the recess with good controllability.

また、第２の配線溝１３を形成する際に、下側電極層を設ける領域にも、配線溝を形成するが、その形状も同様に、内角が９０°よりも大きい多角形、たとえば正八角形とする。   Further, when the second wiring groove 13 is formed, the wiring groove is also formed in the region where the lower electrode layer is provided. The shape of the wiring groove 13 is also a polygon having an inner angle larger than 90 °, for example, a regular octagon. And

その後、第１のビアホール１２、第２の配線溝１３、下側電極層形成領域部を埋込むように、下敷膜１４ａと銅膜１４ｂ，１４ｃを全面に堆積し、化学機械研磨法で不要な部分の銅膜１４ｃ，１４ｂ、下敷膜１４ａを除去し、第２の埋込金属（Ｃｕ）配線層１４と部分的に厚膜となった部分２４０を持つ下側電極層２５０を形成する。   Thereafter, an underlay film 14a and copper films 14b and 14c are deposited on the entire surface so as to fill the first via hole 12, the second wiring groove 13, and the lower electrode layer formation region, and are unnecessary by chemical mechanical polishing. The portions of the copper films 14c and 14b and the underlying film 14a are removed to form the lower electrode layer 250 having the second buried metal (Cu) wiring layer 14 and a partially thickened portion 240.

図３８に示すように、第２の金属（Ｃｕ）配線層１４、下側電極層２５０の上に、シリコン窒化膜１５ａ、シリコン酸化膜などの絶縁膜１５ｂ、シリコン窒化膜１５ｃ、シリコン酸化膜などの絶縁膜１５ｄからなる４層構造の第２の層間絶縁膜１５をプラズマＣＶＤ法などの方法で堆積する。写真製版・エッチング技術を用いて、第２の層間絶縁膜１５の所望の部分に第２のビアホール１６と第３の配線溝１７とを形成する。   As shown in FIG. 38, on the second metal (Cu) wiring layer 14 and the lower electrode layer 250, a silicon nitride film 15a, an insulating film 15b such as a silicon oxide film, a silicon nitride film 15c, a silicon oxide film, etc. A second interlayer insulating film 15 having a four-layer structure made of the insulating film 15d is deposited by a method such as plasma CVD. A second via hole 16 and a third wiring groove 17 are formed in a desired portion of the second interlayer insulating film 15 using photolithography and etching techniques.

この際、第２のビアホール形成時に、下側電極層の上にも接続孔２５１を同時に形成するが、この平面形状も、内角が９０°よりも大きい多角形、たとえば、正八角形とする。   At this time, when the second via hole is formed, the connection hole 251 is also formed on the lower electrode layer at the same time. This planar shape is also a polygon having an interior angle larger than 90 °, for example, a regular octagon.

また、第３の配線溝形成時に、主電極層を設ける部分にも配線溝を形成するが、その形状も、内角が９０°よりも大きい多角形、たとえば、正八角形とする。   In addition, when the third wiring groove is formed, the wiring groove is also formed in the portion where the main electrode layer is provided, and the shape thereof is also a polygon having an inner angle larger than 90 °, for example, a regular octagon.

前述と同様の方法により、第２のビアホール１６、第３の配線溝１７、第１のパッド電極上の接続孔部２５１、第２のパッド電極形成部１０１を埋込むように、下敷膜１００ａと銅膜１００ｂ，１００ｃを全面に堆積し，化学機械研磨法で不要部分を除去することにより、第３の埋込金属（Ｃｕ）配線層１００と主電極層１０１とを形成する。   By using the same method as described above, the underlying film 100a and the second via hole 16, the third wiring groove 17, the connection hole 251 on the first pad electrode, and the second pad electrode forming portion 101 are embedded. Copper films 100b and 100c are deposited on the entire surface, and unnecessary portions are removed by a chemical mechanical polishing method to form a third buried metal (Cu) wiring layer 100 and a main electrode layer 101.

図３９に示すように、第３の金属（Ｃｕ）配線層１００、および、主電極層１０１の上に、銅の拡散防止層としての緻密なシリコン窒化膜２０２ａを堆積した後、シリコン窒化膜、シリコン酸化膜、シリコン酸窒化膜、あるいは、これらの積層構造膜などの保護絶縁膜２０２ｂを１．０μｍ程度堆積する。さらに、その上に、必要に応じてポリイミドなどのバッファコート膜２０３を５〜１０μｍ程度、第２の保護絶縁膜として形成し、ワイヤボンディング法などの方法で外部端子（図示省略）と接続するために、パッド電極１０１の所望部分に開口部２０４を設ける。   As shown in FIG. 39, after depositing a dense silicon nitride film 202a as a copper diffusion prevention layer on the third metal (Cu) wiring layer 100 and the main electrode layer 101, a silicon nitride film, A protective insulating film 202b such as a silicon oxide film, a silicon oxynitride film, or a laminated structure film thereof is deposited to a thickness of about 1.0 μm. Further, a buffer coating film 203 such as polyimide is formed thereon as a second protective insulating film as necessary to a thickness of about 5 to 10 μm, and is connected to an external terminal (not shown) by a wire bonding method or the like. In addition, an opening 204 is provided in a desired portion of the pad electrode 101.

（作用・効果）
以上のように、このような本発明の実施の形態によれば、図３６に示すように、パッド電極を埋込金属配線層で形成した下側電極層２５０と、主電極層１０１とを大面積の絶縁膜孔２５１を介して重ねて、下側電極層２５０の一部分の厚みを下向きに厚くし、下側突出部２４０として、かつ、その部分２４０の平面形状を正八角形としたので、ワイヤボンディングなどにより外部端子との接続時に荷重または衝撃力が加わっても、パッド電極の実効厚みが増えただけ緩和させることができ、また、応力の集中しやすい下側電極層の下側突出部２４０の角部への応力集中も、四角形の場合に比べて大幅に低減できる。そのため、層間絶縁膜にクラックが発生するのを防止することができる。 (Action / Effect)
As described above, according to such an embodiment of the present invention, as shown in FIG. 36, the lower electrode layer 250 in which the pad electrode is formed of the embedded metal wiring layer and the main electrode layer 101 are largely formed. Since the insulating film hole 251 having the area is overlapped, the thickness of a part of the lower electrode layer 250 is increased downward to form the lower projecting portion 240 and the planar shape of the portion 240 is a regular octagon. Even if a load or impact force is applied during connection to an external terminal by bonding or the like, the effective thickness of the pad electrode can be alleviated and the lower protrusion 240 of the lower electrode layer where stress tends to concentrate. The stress concentration at the corners can be greatly reduced as compared with the case of the quadrangular shape. Therefore, it is possible to prevent cracks from occurring in the interlayer insulating film.

したがって、外部端子との接続強度を十分に確保し得る条件でボンディングできるので、接続を安定に、かつ容易に行なうことができ、高品質の半導体装置が低コストで得られるという効果がある。   Therefore, since bonding can be performed under conditions that can sufficiently secure the connection strength with the external terminal, the connection can be performed stably and easily, and there is an effect that a high-quality semiconductor device can be obtained at low cost.

また、相対的にボンディング時の荷重または衝撃力の許容値を高くする必要のあるパッド電極を縮小化した場合にも有効な方法となる。   This method is also effective when the pad electrode that needs to have a relatively high allowable load or impact force during bonding is reduced.

さらに、通常、最上層の金属（Ｃｕ）配線層は、ワイヤボンディングなどによる外部端子との接続信頼性を考慮して、０．８〜１．５μｍ程度の比較的厚膜の金属（Ｃｕ）配線が用いられるが、本実施の形態のように、パッド電極を大面積の接続孔を介して重ねた構造とすることにより、実効的なパッド電極厚みを厚くできるので、最上層の金属（Ｃｕ）配線の厚みを微細化に適したさらに薄い配線層とすることが可能となる。   Further, the uppermost metal (Cu) wiring layer is generally a relatively thick metal (Cu) wiring of about 0.8 to 1.5 μm in consideration of connection reliability with an external terminal by wire bonding or the like. However, since the effective pad electrode thickness can be increased by using a structure in which the pad electrodes are stacked through the large-area connection holes as in the present embodiment, the uppermost layer metal (Cu) is used. A thinner wiring layer suitable for miniaturization can be obtained.

なお、図３６では、下側電極層と主電極層とを大面積の接続孔を介して重ねた構造とし、下側電極層の下側突出部２４０の形状が正八角形の場合について述べたが、所望の部分の内角を９０°よりも大きい多角形としても、同様の効果を奏する。   In FIG. 36, the lower electrode layer and the main electrode layer are stacked through a large-area connection hole, and the lower protruding portion 240 of the lower electrode layer has a regular octagonal shape. The same effect can be obtained even if the interior angle of the desired portion is a polygon larger than 90 °.

また、図４０に断面図を示すが、平面図においては、下側電極層の下側突出部２４０を図４１に示すような円形、あるいは、楕円形とする。図４２や図４３に示すような所望の部分の角部に丸みや面取りをつけた形状としてもよい。   40 is a cross-sectional view. In the plan view, the lower protrusion 240 of the lower electrode layer is circular or elliptical as shown in FIG. It is good also as a shape which rounded and chamfered the corner | angular part of the desired part as shown in FIG.42 and FIG.43.

また、図４４のように、下側電極層の下側突出部２４０の形状のみを上記のようにして、下側電極層２５０、接続孔２５１、主電極層１０１やパッド電極開口部２０４の形状は従来形状、たとえば、四角形としてもよい。   Further, as shown in FIG. 44, only the shape of the lower protrusion 240 of the lower electrode layer is as described above, and the shapes of the lower electrode layer 250, the connection hole 251, the main electrode layer 101, and the pad electrode opening 204 are formed. May have a conventional shape, for example, a quadrangle.

さらに、下側電極層の下側突出部２４０の形状として、これらの形状を部分的に採用したり組合せて採用してもよい。   Further, as the shape of the lower protrusion 240 of the lower electrode layer, these shapes may be partially adopted or combined.

（実施の形態６）
さらに、パッド電極の少なくとも一部が埋込金属配線層で構成された構造において、パッド電極の角部に応力緩衝用絶縁壁を設けても同様の効果を奏する。 (Embodiment 6)
Further, in a structure in which at least a part of the pad electrode is formed of a buried metal wiring layer, the same effect can be obtained by providing a stress buffer insulating wall at the corner of the pad electrode.

（構成）
このような本実施の形態における半導体装置の構造を図４５（ａ）〜（ｃ）に示す。 (Constitution)
The structure of the semiconductor device in this embodiment is shown in FIGS.

図４５（ａ）に示すように、パッド電極の角部領域には、その角部領域を応力緩衝用金属（Ｃｕ）層３００として分離分割するように応力緩衝用絶縁壁３０１がある。他は、図１に示したものと同様である。   As shown in FIG. 45A, there is a stress buffering insulating wall 301 in the corner region of the pad electrode so as to separate and divide the corner region as a stress buffering metal (Cu) layer 300. Others are the same as those shown in FIG.

（製造方法）
図４５（ａ）〜（ｃ）に示した半導体装置を製造する方法は、図１に示した実施の形態１における半導体装置の製造方法と同様である。 (Production method)
The method for manufacturing the semiconductor device shown in FIGS. 45A to 45C is the same as the method for manufacturing the semiconductor device in the first embodiment shown in FIG.

すなわち、従来技術に基づいて図１２９に示す構造を形成した後、図２に示すように、第２の金属（Ｃｕ）配線層１４の上に、銅（Ｃｕ）の拡散防止層としてシリコン窒化膜（ＳｉＮ）１５ａ、シリコン酸化膜（ＳｉＯ）などの絶縁膜１５ｂ、シリコン窒化膜（ＳｉＮ）１５ｃ、シリコン酸化膜（ＳｉＯ）などの絶縁膜１５ｄからなる４層構造の第２の層間絶縁膜１５をプラズマＣＶＤ法などの方法で堆積する。   That is, after the structure shown in FIG. 129 is formed based on the prior art, as shown in FIG. 2, a silicon nitride film as a copper (Cu) diffusion prevention layer is formed on the second metal (Cu) wiring layer 14. A second interlayer insulating film 15 having a four-layer structure including an insulating film 15b such as (SiN) 15a, a silicon oxide film (SiO), an insulating film 15d such as a silicon nitride film (SiN) 15c, and a silicon oxide film (SiO) is formed. Deposited by a method such as plasma CVD.

写真製版・エッチング技術を用いて、第２の層間絶縁膜１５の所望の部分に第２のビアホール１６と第３の配線溝１７としての凹部を形成する。このとき、同時に、パッド電極を設ける部分にも凹部を形成するが、その形状の角部領域に応力緩衝用絶縁壁を形成するための絶縁壁凹部を形成する。絶縁壁凹部とは、図４８の応力緩衝用金属層３００となるものであり、図４５（ａ）、図４９〜図５１、図５２（ａ）、図５３（ａ）に例示する応力緩衝用金属層３００のような平面形状に形成される。   A second via hole 16 and a recess as a third wiring groove 17 are formed in a desired portion of the second interlayer insulating film 15 by using photolithography and etching techniques. At the same time, a recess is formed in the portion where the pad electrode is provided, but an insulating wall recess for forming a stress buffering insulating wall is formed in the corner region of the shape. The insulating wall recess is the metal layer 300 for stress buffering in FIG. 48, and is for stress buffering illustrated in FIGS. 45 (a), 49-51, 52 (a), and 53 (a). The metal layer 300 is formed in a planar shape.

前述と同様の方法により、第２のビアホール１６および第３の配線溝１７としての凹部と絶縁壁凹部を埋込むように、下敷膜１００ａと銅シード膜１００ｂ、銅めっき膜１００ｃを全面に１．５〜３．０μｍ程度堆積した後に、化学機械研磨法で不要部分の銅膜１８ｃ，１８ｂ、下敷膜１８ａを除去し、第３の埋込金属（Ｃｕ）配線層１００、パッド電極１０１、応力緩衝用金属層３００を形成する。   In the same manner as described above, the underlying film 100a, the copper seed film 100b, and the copper plating film 100c are formed on the entire surface so as to fill the recesses as the second via holes 16 and the third wiring grooves 17 and the insulating wall recesses. After depositing about 5 to 3.0 μm, unnecessary portions of the copper films 18c and 18b and the underlying film 18a are removed by a chemical mechanical polishing method, and the third embedded metal (Cu) wiring layer 100, the pad electrode 101, the stress buffering are removed. A metal layer 300 is formed.

この後に続く工程は、実施の形態１で説明したものと同じである。
（作用・効果）
このような本実施の形態によれば、図４６、図４７に示すように、パッド電極角部に応力緩衝用金属層３００を置いて、パッド電極１０１との間に応力緩衝用絶縁壁３０１が設けられている。そのため、ワイヤボンディングなどの外部端子との接続の際にパッド電極１０１に荷重または衝撃力３０４，３０５が加わっても、特に、応力集中の起こりやすいパッド電極角部において、応力緩衝用絶縁壁３０１が微小な弾性変形をすることにより応力を緩衝するため、この部分の層間絶縁膜には小さな応力（衝撃力）３０６しか加わらない。したがって、パッド電極１０１角部の層間膜クラックを防止することができる。 The subsequent steps are the same as those described in the first embodiment.
(Action / Effect)
According to this embodiment, as shown in FIGS. 46 and 47, the stress buffering metal layer 300 is placed at the corner of the pad electrode, and the stress buffering insulating wall 301 is provided between the pad electrode 101 and the pad. Is provided. Therefore, even when a load or impact force 304, 305 is applied to the pad electrode 101 during connection to an external terminal such as wire bonding, the stress buffer insulating wall 301 is formed at the corner of the pad electrode where stress concentration is likely to occur. Since the stress is buffered by minute elastic deformation, only a small stress (impact force) 306 is applied to the interlayer insulating film in this portion. Therefore, interlayer film cracks at the corners of the pad electrode 101 can be prevented.

なお、図４５では、パッド電極１０１の角部に三角形の応力緩衝用金属（Ｃｕ）層３００を置くことにより、応力緩衝用絶縁壁３０１を設けたが、他の形状の絶縁壁でも同様の効果を奏する。また、それらを複数個設けてもよい。   In FIG. 45, the stress buffering insulating wall 301 is provided by placing a triangular stress buffering metal (Cu) layer 300 at the corner of the pad electrode 101, but the same effect can be obtained with insulating walls of other shapes. Play. A plurality of them may be provided.

たとえば、断面図を図４８に示し、平面図を図４９〜図５２に示すように、パッド電極１０１の角部に複数個の応力緩衝用金属層３００を置くことにより、応力緩衝用絶縁壁３０１を複数個設けるようにすれば、さらに効果を高めることができる。また、図５３にように、パッド電極１０１の角部に置く応力緩衝用金属層３００の下向きの厚みを他のパッド電極部分と変えるようにしてもよい。   For example, as shown in FIG. 48 as a cross-sectional view and as shown in FIGS. If a plurality of is provided, the effect can be further enhanced. As shown in FIG. 53, the downward thickness of the stress buffering metal layer 300 placed at the corner of the pad electrode 101 may be changed from that of the other pad electrode portions.

（実施の形態７）
さらに、パッド電極の少なくとも一部が埋込金属配線層で構成された構造で、金属電極の厚みが下向きに部分的に厚くなっており、その角部の領域に応力緩衝用絶縁壁を設けても同様の効果を奏する。 (Embodiment 7)
Further, the pad electrode has a structure in which at least a part is formed of a buried metal wiring layer, and the thickness of the metal electrode is partially increased downward, and a stress buffer insulating wall is provided in the corner area. Produces the same effect.

（構成）
このような本実施の形態における半導体装置の構造を図５４に示す。
パッド部は、下側突出部１５０を含む。下側突出部１５０は、その角部領域において、応力緩衝用金属層３１０として角部を分離する、応力緩衝用絶縁壁３１１を含む。 (Constitution)
FIG. 54 shows the structure of such a semiconductor device in this embodiment.
The pad portion includes a lower protrusion 150. The lower protrusion 150 includes a stress buffer insulating wall 311 that separates the corner as the stress buffer metal layer 310 in the corner region.

（作用・効果）
このような本実施の形態によれば、図５４に示すように、パッド電極の下側突出部の角部に応力緩衝用金属（Ｃｕ）層３１０を置いて、パッド電極の下側突出部１５０との間に応力緩衝用絶縁壁３１１を設けるようにした。 (Action / Effect)
According to this embodiment, as shown in FIG. 54, the stress buffer metal (Cu) layer 310 is placed at the corner of the lower protrusion of the pad electrode, and the lower protrusion 150 of the pad electrode. Insulating wall 311 for stress buffering is provided between the two.

そのため、ワイヤボンディングなどの外部端子との接続時にパッド電極の下側突出部１５０に荷重または衝撃力が加わっても、特に、応力集中の起こりやすい下側突出部の角部において、応力緩衝用絶縁壁３１１が微小な弾性変形をすることにより応力を緩衝するため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、パッド電極厚膜部分１５０角部の層間膜クラックを防止することができる。   Therefore, even if a load or impact force is applied to the lower protrusion 150 of the pad electrode during connection to an external terminal such as wire bonding, the insulation for stress buffering is applied particularly at the corner of the lower protrusion where stress concentration is likely to occur. Since the wall 311 undergoes minute elastic deformation to buffer the stress, only a small stress (impact force) is applied to the interlayer insulating film in this portion. Therefore, an interlayer film crack at the corner portion of the pad electrode thick film portion 150 can be prevented.

なお、図５４では、パッド電極厚膜部分１５０角部に三角形の応力緩衝用金属層３１０を置くことにより応力緩衝用絶縁壁３１１を設けたが、他の形状の絶縁壁でも同様の効果を奏する。また、それらを複数個設けてもよい。   In FIG. 54, the stress buffering insulating wall 311 is provided by placing a triangular stress buffering metal layer 310 at the corner portion of the pad electrode thick film portion 150, but the same effect can be obtained with insulating walls of other shapes. . A plurality of them may be provided.

たとえば、図５５〜図５７に示すように、パッド電極厚膜部分１５０の角部に置く応力緩衝用金属（Ｃｕ）層３１０としては、四角形や四分の一円などの形状が可能である。   For example, as shown in FIGS. 55 to 57, the stress buffering metal (Cu) layer 310 placed at the corner of the pad electrode thick film portion 150 can have a shape such as a quadrangle or a quarter circle.

また、図５８や図５９のように、パッド電極厚膜部分１５０の角部に複数個の応力緩衝用金属（Ｃｕ）層３１０を置くことにより、応力緩衝用絶縁壁３１１を複数個設けるようにすれば、さらに効果を高めることができる。   58 and 59, a plurality of stress buffering insulating walls 311 are provided by placing a plurality of stress buffering metal (Cu) layers 310 at the corners of the pad electrode thick film portion 150. If so, the effect can be further enhanced.

また、図６０のように、下側突出部１５０の角部に配置する応力緩衝用金属（Ｃｕ）層３１０と上部のパッド電極１０１角部に配置する応力緩衝用金属層を重ねることにより、図６０（ｂ）に示すようにパッド電極表面まで到達する絶縁壁３０１，３１１を形成してもよい。   60, the stress buffering metal (Cu) layer 310 disposed at the corner of the lower protrusion 150 and the stress buffering metal layer disposed at the corner of the upper pad electrode 101 are overlapped. As shown in FIG. 60B, insulating walls 301 and 311 that reach the pad electrode surface may be formed.

（実施の形態８）
（構成）
さらに、パッド電極の少なくとも一部が埋込金属配線層で構成され、パッド電極が主電極層１０１とその上に形成された上側電極層２０１を含む構造において、図６１に示すように、主電極層１０１の角部の領域に応力緩衝用絶縁壁３２１を設けても同様の効果を奏する。主電極層１０１の角部の領域に応力緩衝用絶縁壁３２１がある以外は、実施の形態３における構造（図１９参照）と同様である。 (Embodiment 8)
(Constitution)
Further, in a structure in which at least a part of the pad electrode is formed of a buried metal wiring layer and the pad electrode includes the main electrode layer 101 and the upper electrode layer 201 formed thereon, as shown in FIG. Even if the stress buffer insulating wall 321 is provided in the corner region of the layer 101, the same effect can be obtained. Except for the stress buffer insulating wall 321 in the corner region of the main electrode layer 101, the structure is the same as that of the third embodiment (see FIG. 19).

（作用・効果）
このような本実施の形態によれば、図６１に示すように、主電極層１０１の角部に応力緩衝用金属層３２０を置いて、主電極層１０１との間に応力緩衝用絶縁壁３２１を設けるようにした。 (Action / Effect)
According to this embodiment, as shown in FIG. 61, the stress buffering metal layer 320 is placed at the corner of the main electrode layer 101, and the stress buffering insulating wall 321 is placed between the main electrode layer 101 and the stress buffering metal layer 320. It was made to provide.

そのため、ワイヤボンディングなどによる外部端子との接続時にパッド電極に荷重または衝撃力が加わっても、特に、応力集中の起こりやすい主電極層１０１の角部において、応力緩衝用絶縁壁３２１が微小な弾性変形をすることにより応力を緩衝するため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、主電極層１０１の角部の層間膜クラックを防止することができる。   Therefore, even when a load or impact force is applied to the pad electrode during connection to an external terminal by wire bonding or the like, the stress buffer insulating wall 321 has a minute elasticity, particularly at the corner of the main electrode layer 101 where stress concentration is likely to occur. Since the stress is buffered by the deformation, only a small stress (impact force) is applied to the interlayer insulating film in this portion. Therefore, interlayer film cracks at the corners of the main electrode layer 101 can be prevented.

なお、図６１に示した例では、主電極層１０１の角部に三角形の応力緩衝用金属層３２０を置くことにより応力緩衝用絶縁壁３２１を設けたが、他の形状の絶縁壁でも同様の効果を奏する。また、それらを複数個設けてもよい。   In the example shown in FIG. 61, the stress buffering insulating wall 321 is provided by placing a triangular stress buffering metal layer 320 at the corner of the main electrode layer 101, but the same applies to insulating walls of other shapes. There is an effect. A plurality of them may be provided.

たとえば、断面図を図６２に示し、平面図を図６３や図６４に示すように、主電極層１０１の角部に置く応力緩衝用金属配線３２０としては、四角形や１／４円などの形状が可能である。   For example, as shown in FIG. 62 as a cross-sectional view and as shown in FIG. 63 and FIG. 64 as a plan view, the stress buffering metal wiring 320 placed at the corner of the main electrode layer 101 has a shape such as a square or a quarter circle. Is possible.

また、図６５や図６６に示すように、主電極層１０１の角部に複数個の応力緩衝用金属層３２０を置くことにより、応力緩衝用絶縁壁３２１を複数個設けるようにすれば、さらに効果を高めることができる。また、図６７に示すように、主電極層１０１の角部に置く応力緩衝用金属層３２０の下方向の厚みを他の主電極層１０１の深さと変えるようにしてもよい。   As shown in FIGS. 65 and 66, if a plurality of stress buffering insulating walls 321 are provided by placing a plurality of stress buffering metal layers 320 at the corners of the main electrode layer 101, The effect can be enhanced. In addition, as shown in FIG. 67, the downward thickness of the stress buffer metal layer 320 placed at the corner of the main electrode layer 101 may be changed from the depth of the other main electrode layer 101.

（実施の形態９）
（構成）
さらに、パッド電極の少なくとも一部が埋込金属配線層で構成され、パッド電極が下側電極層と主電極層とを大面積の接続孔を介して重ねた構造において、下側電極層の角部の領域や接続孔の角部に応力緩衝用絶縁壁を設けても同様の効果を奏する。本実施の形態における半導体装置の構造を図６８に示す。 (Embodiment 9)
(Constitution)
Further, in a structure in which at least a part of the pad electrode is formed of a buried metal wiring layer, and the pad electrode overlaps the lower electrode layer and the main electrode layer via a large-area connection hole, the corner of the lower electrode layer is Even if the insulating wall for stress buffering is provided in the region of the portion or the corner portion of the connection hole, the same effect can be obtained. The structure of the semiconductor device in this embodiment is shown in FIG.

下側電極層の角部の領域および接続孔の角部のうち少なくとも一方に応力緩衝用絶縁壁を設けている点以外は、実施の形態４における構造（図２７参照）と同様である。   The structure is the same as that in Embodiment 4 (see FIG. 27) except that at least one of the corner region of the lower electrode layer and the corner portion of the connection hole is provided with a stress buffering insulating wall.

（作用・効果）
このような本実施の形態によれば、図６８に示すように、下側電極層２５０の角部に応力緩衝用金属層３３０を置いて、下側電極層２５０との間に応力緩衝用絶縁壁３３１を設けるようにした。 (Action / Effect)
According to the present embodiment as described above, as shown in FIG. 68, the stress buffering metal layer 330 is placed at the corner of the lower electrode layer 250, and the stress buffer insulating layer is interposed between the lower electrode layer 250 and the lower electrode layer 250. A wall 331 was provided.

そのため、ワイヤボンディングなどによる外部端子との接続時にパッド電極に荷重または衝撃力が加わっても、特に応力集中の起こりやすい下側電極層２５０の角部において、応力緩衝用絶縁壁３３１が微小な弾性変形をすることにより応力を緩衝するため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、下側電極層２５０の角部の層間膜クラックを防止することができる。   Therefore, even when a load or impact force is applied to the pad electrode during connection to an external terminal by wire bonding or the like, the stress buffer insulating wall 331 has a very small elasticity at the corner portion of the lower electrode layer 250 where stress concentration easily occurs. Since the stress is buffered by the deformation, only a small stress (impact force) is applied to the interlayer insulating film in this portion. Therefore, interlayer film cracks at the corners of the lower electrode layer 250 can be prevented.

なお、図６８では、下側電極層２５０の角部に三角形の応力緩衝用金属層３３０を置くことにより、応力緩衝用絶縁壁３３１を設けたが、他の形状の絶縁壁でも同様の効果を奏する。また、それらを複数個設けてもよい。   In FIG. 68, the stress buffering insulating wall 331 is provided by placing the triangular stress buffering metal layer 330 at the corners of the lower electrode layer 250, but the same effect can be obtained with insulating walls of other shapes. Play. A plurality of them may be provided.

たとえば、断面図を図６９に示し、平面図を図７０や図７１に示すように、下側電極層２５０の角部に置く応力緩衝用金属層３３０としては、四角形や１／４円などの形状が可能である。また、図７２や図７３に示すように、下側電極層２５０の角部に複数個の応力緩衝用金属層３３０を置くことにより、応力緩衝用絶縁壁３３１を複数個設けるようにすれば、さらに効果を高めることができる。また、図７４、図７５に示すように、下側電極層２５０の角部の応力緩衝用金属層３３０だけでなく、接続孔２５１の角部や主電極層１０１の角部にも同様な応力緩衝用金属層３２０，３００を設けて、これらを重ねる形で応力緩衝用絶縁壁３３１，３２１，３０１を構成してもよい。   For example, as shown in FIG. 69 as a cross-sectional view and as shown in FIG. 70 and FIG. 71 as a plan view, the stress buffering metal layer 330 placed at the corner of the lower electrode layer 250 may be a square or a quarter circle. Shape is possible. In addition, as shown in FIGS. 72 and 73, by placing a plurality of stress buffering metal layers 330 at the corners of the lower electrode layer 250, a plurality of stress buffering insulating walls 331 can be provided. Furthermore, the effect can be enhanced. 74 and 75, similar stress is applied not only to the stress buffer metal layer 330 at the corner of the lower electrode layer 250 but also to the corner of the connection hole 251 and the corner of the main electrode layer 101. The buffering metal layers 320 and 300 may be provided, and the stress buffering insulating walls 331, 321, and 301 may be configured by overlapping them.

また、図７６のように、大面積の接続孔２５１の角部のみ、応力緩衝用金属層３２０を置き、接続孔２５１との間にのみ応力緩衝用絶縁壁３２１を設けるようにしてもよい。   Further, as shown in FIG. 76, the stress buffering metal layer 320 may be placed only at the corners of the large-area connection hole 251, and the stress buffering insulating wall 321 may be provided only between the connection hole 251.

（実施の形態１０）
（構成）
さらに、パッド電極の少なくとも一部が埋込金属配線層で構成され、パッド電極が下側電極層と主電極層とを重ねた構造を含み、下側電極層の厚みが下向きに部分的に厚くなった下側突出部を有する構造において、その角部の領域に応力緩衝用絶縁壁を設けても同様の効果を奏する。このような本実施の形態による半導体装置の構造を図７７に示す。 (Embodiment 10)
(Constitution)
Furthermore, at least a part of the pad electrode is formed of a buried metal wiring layer, the pad electrode includes a structure in which the lower electrode layer and the main electrode layer are overlapped, and the thickness of the lower electrode layer is partially increased downward. In the structure having the lower protruding portion, the same effect can be obtained even if a stress buffer insulating wall is provided in the corner region. FIG. 77 shows the structure of the semiconductor device according to the present embodiment.

下側突出部の角部の領域に応力緩衝用絶縁壁が設けられている点以外は、実施の形態５における構造（図３６参照）と同様である。   The structure is the same as that of the fifth embodiment (see FIG. 36) except that a stress buffer insulating wall is provided in the corner area of the lower protrusion.

（作用・効果）
このような本発明によれば、図７７に示すように、下側電極層２５０の下側突出部２４０の角部に応力緩衝用金属層３４０を置いて、下側突出部２４０との間に応力緩衝用絶縁壁３４１を設けるようにした。そのため、ワイヤボンディングなどによる外部端子との接続時に主電極層１０１に荷重または衝撃力が加わっても、特に、応力集中の起こりやすい下側突出部２４０の角部において、応力緩衝用絶縁壁３４１が微小な弾性変形をすることにより応力を緩衝するため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、下側突出部２４０の角部の層間膜クラックを防止することができる。 (Action / Effect)
According to the present invention as described above, as shown in FIG. 77, the stress buffering metal layer 340 is placed at the corner of the lower protruding portion 240 of the lower electrode layer 250 and between the lower protruding portion 240. An insulating wall 341 for stress buffering is provided. Therefore, even if a load or impact force is applied to the main electrode layer 101 when connecting to an external terminal by wire bonding or the like, the stress buffer insulating wall 341 is formed at the corner portion of the lower protrusion 240 where stress concentration is likely to occur. Since the stress is buffered by minute elastic deformation, only a small stress (impact force) is applied to the interlayer insulating film in this portion. Therefore, interlayer film cracks at the corners of the lower protrusion 240 can be prevented.

なお、図７７では、下側突出部２４０の角部に三角形の応力緩衝用金属層３４０を置くことにより、応力緩衝用絶縁壁３４１を設けたが、他の形状の絶縁壁でも同様の効果を奏する。また、それらを複数個設けてもよい。   In FIG. 77, the stress buffering insulating wall 341 is provided by placing the triangular stress buffering metal layer 340 at the corners of the lower protrusion 240, but the same effect can be obtained with insulating walls of other shapes. Play. A plurality of them may be provided.

たとえば、図７８〜図８０に示すように、第１のパッド電極厚膜部２４０の角部に置く応力緩衝用金属層３４０としては、四角形や１／４円などの形状が可能である。また、図８１や図８２のように、第１のパッド電極厚膜部２４０の角部に複数個の応力緩衝用金属層３４０を置くことにより、応力緩衝用絶縁壁３４１を複数個設けるようにすれば、さらに効果を高めることができる。また、図８３、図８４、図８５のように、下側突出部２４０の角部の応力緩衝用金属層３４０だけでなく、下側電極層２５０の角部、接続孔２５１の角部や主電極層１０１の角部にも同様な応力緩衝用金属層３３０，３２０，３００を設けて、これらを重ねる形で応力緩衝用絶縁壁３４１，３３１，３２１，３０１も構成してもよい。   For example, as shown in FIGS. 78 to 80, the stress buffering metal layer 340 placed at the corner of the first pad electrode thick film portion 240 can have a shape such as a square or a quarter circle. Further, as shown in FIGS. 81 and 82, a plurality of stress buffering insulating walls 341 are provided by placing a plurality of stress buffering metal layers 340 at the corners of the first pad electrode thick film portion 240. If so, the effect can be further enhanced. 83, 84, and 85, not only the stress buffering metal layer 340 at the corner of the lower protrusion 240 but also the corner of the lower electrode layer 250, the corner of the connection hole 251 and the main portion. The stress buffering insulating walls 341, 331, 321, and 301 may also be configured by providing similar stress buffering metal layers 330, 320, and 300 at the corners of the electrode layer 101 and overlapping them.

（実施の形態１１）
（構成）
さらに、パッド電極の少なくとも一部が埋込金属配線層で構成された構造において、パッド電極の角部の領域に応力緩衝用突出部を設けても同様の効果を奏する。このような本実施の形態における半導体装置の構造を図８６に示す。 (Embodiment 11)
(Constitution)
Further, in a structure in which at least a part of the pad electrode is formed of a buried metal wiring layer, the same effect can be obtained even if a stress buffering protrusion is provided in the corner region of the pad electrode. A structure of such a semiconductor device in this embodiment is shown in FIG.

パッド電極１０１の角部の領域に応力緩衝用突出部４００がある点以外は、実施の形態１における構造（図１）と同様である。   The structure is the same as that in the first embodiment (FIG. 1) except that the stress buffering protrusion 400 is provided in the corner area of the pad electrode 101.

（製造方法）
図８６（ａ）〜（ｃ）に示した半導体装置を製造する方法は、図１に示した実施の形態１における半導体装置の製造方法と同様である。 (Production method)
The method for manufacturing the semiconductor device shown in FIGS. 86A to 86C is the same as the method for manufacturing the semiconductor device in the first embodiment shown in FIG.

すなわち、従来技術に基づいて図１２９に示す構造を形成した後、図２に示すように、第２の金属（Ｃｕ）配線層１４の上に、銅（Ｃｕ）の拡散防止層としてシリコン窒化膜（ＳｉＮ）１５ａ、シリコン酸化膜（ＳｉＯ）などの絶縁膜１５ｂ、シリコン窒化膜（ＳｉＮ）１５ｃ、シリコン酸化膜（ＳｉＯ）などの絶縁膜１５ｄからなる４層構造の第２の層間絶縁膜１５をプラズマＣＶＤ法などの方法で堆積する。   That is, after the structure shown in FIG. 129 is formed based on the prior art, as shown in FIG. 2, a silicon nitride film as a copper (Cu) diffusion prevention layer is formed on the second metal (Cu) wiring layer 14. A second interlayer insulating film 15 having a four-layer structure including an insulating film 15b such as (SiN) 15a, a silicon oxide film (SiO), an insulating film 15d such as a silicon nitride film (SiN) 15c, and a silicon oxide film (SiO) is formed. Deposited by a method such as plasma CVD.

写真製版・エッチング技術を用いて、第２の層間絶縁膜１５の所望の部分に第２のビアホール１６と第３の配線溝１７としての凹部を形成する。このとき、同時に、パッド電極を設ける部分にも凹部を形成するが、その形状の角部領域に応力緩衝用突出部を形成するための緩衝用凹部を形成する。緩衝用凹部とは、図８６（ａ），（ｂ）、図８９の応力緩衝用突出部４００となるものであり、図９０〜図９２、図９３（ａ）に例示する応力緩衝用突出部４００，４０１，４０２のような平面形状に形成される。   A second via hole 16 and a recess as a third wiring groove 17 are formed in a desired portion of the second interlayer insulating film 15 by using photolithography and etching techniques. At the same time, a recess is formed in the portion where the pad electrode is provided, but a buffer recess for forming a stress buffering protrusion is formed in the corner region of the shape. The buffer recess is the stress buffer protrusion 400 shown in FIGS. 86 (a), 86 (b), and 89, and the stress buffer protrusion illustrated in FIGS. 90 to 92 and 93 (a). It is formed in a planar shape such as 400, 401, 402.

前述と同様の方法により、第２のビアホール１６および第３の配線溝１７としての凹部と緩衝用凹部を埋込むように、下敷膜１００ａと銅シード膜１００ｂ、銅めっき膜１００ｃを全面に１．５〜３．０μｍ程度堆積した後に、化学機械研磨法で不要部分の銅膜１８ｃ，１８ｂ、下敷膜１８ａを除去し、第３の埋込金属（Ｃｕ）配線層１００、パッド電極１０１、応力緩衝用突出部４００，４０１，４０２を形成する。   In the same manner as described above, the underlying film 100a, the copper seed film 100b, and the copper plating film 100c are formed on the entire surface so as to fill the recesses as the second via holes 16 and the third wiring grooves 17 and the buffer recesses. After depositing about 5 to 3.0 μm, unnecessary portions of the copper films 18c and 18b and the underlying film 18a are removed by a chemical mechanical polishing method, and the third embedded metal (Cu) wiring layer 100, the pad electrode 101, the stress buffering are removed. Protrusion portions 400, 401, and 402 are formed.

この後に続く工程は、実施の形態１で説明したものと同じである。
（作用・効果）
このような本発明によれば、図８６に示すように、パッド電極１０１の角部に応力緩衝用突出部４００が設けられている。そのため、ワイヤボンディングなどによる外部端子との接続時にパッド電極１０１に荷重または衝撃力３０４，３０５が加わっても、特に、応力集中の起こりやすいパッド電極１０１の角部において、図８７、図８８に示すように、応力緩衝用突出部４００が微小な弾性変形をして応力（衝撃力）を緩衝する作用を及ぼすため、この部分の層間絶縁膜には小さな応力（衝撃力）３０６しか加わらない。したがって、パッド電極１０１の角部の層間膜クラックを防止することができる。 The subsequent steps are the same as those described in the first embodiment.
(Action / Effect)
According to the present invention as described above, as shown in FIG. 86, the stress buffering protrusion 400 is provided at the corner of the pad electrode 101. Therefore, even when a load or impact force 304, 305 is applied to the pad electrode 101 during connection to an external terminal by wire bonding or the like, particularly in the corner portion of the pad electrode 101 where stress concentration is likely to occur, FIG. 87 and FIG. As described above, since the stress buffering protrusion 400 exerts an action of buffering stress (impact force) by performing minute elastic deformation, only a small stress (impact force) 306 is applied to the interlayer insulating film in this portion. Therefore, interlayer film cracks at the corners of the pad electrode 101 can be prevented.

なお、図８６では、パッド電極１０１の角部に四角形の応力緩衝用突出部４００を設けたが、他の形状の応力緩衝用突出部でも同様の効果を奏する。また、それらを複数個組合せて設けてもよい。   In FIG. 86, the quadrangular stress buffering protrusions 400 are provided at the corners of the pad electrode 101. However, the stress buffering protrusions of other shapes also have the same effect. Further, a plurality of them may be provided in combination.

たとえば、図８９〜図９１に示すように、パッド電極１０１の角部に置く応力緩衝用突出部４００としては、円や楕円の一部や多角形の一部などの他のパターンなどを用いることが可能である。また、図９２に示すように、パッド電極１０１の角部に複数の応力緩衝用突出部４０１，４０２を組合せて配置してもよい。また、より高い応力緩衝効果を持たせるために、図９３に示すように、応力緩衝用突出部４００上の保護絶縁膜１０２，１０３を除去した構造としてもよい。   For example, as shown in FIGS. 89 to 91, as the stress buffering protrusion 400 placed at the corner of the pad electrode 101, other patterns such as a circle, a part of an ellipse, or a part of a polygon are used. Is possible. In addition, as shown in FIG. 92, a plurality of stress buffering protrusions 401 and 402 may be arranged in combination at the corner of the pad electrode 101. Further, in order to have a higher stress buffering effect, as shown in FIG. 93, the protective insulating films 102 and 103 on the stress buffering protrusion 400 may be removed.

（実施の形態１２）
（構成）
さらに、パッド電極の少なくとも一部が埋込金属配線層で構成され、パッド電極の厚みが下向きに部分的に厚くなった下側突出部を有する構造において、下側突出部の角部の領域に応力緩衝用突出部を設けても同様の効果を奏する。このような本実施の形態における半導体装置の構造を図９４に示す。 (Embodiment 12)
(Constitution)
Further, in a structure having a lower protruding portion in which at least a part of the pad electrode is formed of a buried metal wiring layer and the thickness of the pad electrode is partially increased downward, it is formed in a corner region of the lower protruding portion. Even if the stress buffering protrusion is provided, the same effect can be obtained. FIG. 94 shows the structure of such a semiconductor device in this embodiment.

（作用・効果）
このような本発明によれば、図９４に示すように、下側突出部１５０の角部に応力緩衝用突出部４１０が設けられている。そのため、ワイヤボンディングなどによる外部端子との接続時にパッド電極１０１に荷重または衝撃力が加わっても、特に、応力集中の起こりやすい下側突出部１５０の角部において、応力緩衝用突出部が微小な弾性変形をして応力（衝撃力）を緩衝する作用をするため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、下側突出部１５０の角部の層間膜クラックを防止することができる。 (Action / Effect)
According to the present invention as described above, as shown in FIG. 94, the stress buffering protrusion 410 is provided at the corner of the lower protrusion 150. Therefore, even when a load or impact force is applied to the pad electrode 101 during connection to an external terminal by wire bonding or the like, the stress buffering protrusion is very small, particularly at the corner of the lower protrusion 150 where stress concentration is likely to occur. Since this acts to elastically deform and buffer the stress (impact force), only a small stress (impact force) is applied to the interlayer insulating film in this portion. Therefore, interlayer film cracks at the corners of the lower protrusion 150 can be prevented.

なお、図９４では、下側突出部１５０の角部に四角形の応力緩衝用突出部４１０を設けたが、他の形状の応力緩衝用突出部でも同様の効果を奏する。また、それらを複数個組合せて設けてもよい。   In FIG. 94, the quadrangular stress buffering protrusions 410 are provided at the corners of the lower protrusions 150. However, the stress buffering protrusions of other shapes have the same effect. Further, a plurality of them may be provided in combination.

たとえば、図９５〜図９７に示すように、下側突出部１５０の角部に置く応力緩衝用突出部４１０としては、円や楕円の一部や多角形の一部などの他のパターンなどを用いることが可能である。また、図９８に示すように、下側突出部１５０の角部に複数の応力緩衝用突出部４２１，４１２を組合せて配置してもよい。また、より高い応力緩衝効果を持たせるために、図９９のように、応力緩衝用突出部４１０上の保護絶縁膜１０２，１０３を除去した構造としてもよい。さらに、図１００のように下側突出部１５０の角部やパッド電極１０１の角部の両方に応力緩衝用突出部４１０，４００を設けて、かつ、応力緩衝用突出部の上部の保護絶縁膜１０２，１０３を除去するなど、複数の対応策を組合せて実施してもよい。   For example, as shown in FIGS. 95 to 97, as the stress buffering protrusions 410 placed at the corners of the lower protrusions 150, other patterns such as a part of a circle or an ellipse or a part of a polygon may be used. It is possible to use. Also, as shown in FIG. 98, a plurality of stress buffering protrusions 421 and 412 may be arranged in combination at the corners of the lower protrusion 150. In order to provide a higher stress buffering effect, a structure in which the protective insulating films 102 and 103 on the stress buffering protrusions 410 are removed as shown in FIG. Further, as shown in FIG. 100, stress buffering protrusions 410 and 400 are provided at both the corners of the lower protrusion 150 and the corners of the pad electrode 101, and the protective insulating film above the stress buffering protrusions. A plurality of countermeasures such as removing 102 and 103 may be combined and implemented.

（実施の形態１３）
（構成）
さらに、パッド電極の少なくとも一部が埋込金属配線層で構成され、パッド電極が主電極層とその上に形成された上側電極層とを含む構造において、主電極層の角部の領域に応力緩衝用突出部を設けても同様の効果を奏する。このような本実施の形態における半導体装置の構造を図１０１に示す。主電極層の角部の領域に応力緩衝用突出部がある点以外は、実施の形態３における構造（図１９参照）と同様である。 (Embodiment 13)
(Constitution)
Further, in a structure in which at least a part of the pad electrode is composed of a buried metal wiring layer, and the pad electrode includes the main electrode layer and the upper electrode layer formed thereon, stress is applied to the corner region of the main electrode layer. The same effect can be obtained by providing a buffering protrusion. FIG. 101 shows the structure of such a semiconductor device in this embodiment. The structure is the same as that of the third embodiment (see FIG. 19) except that there is a stress buffering protrusion in the corner area of the main electrode layer.

（作用・効果）
このような本実施の形態によれば、図１０１に示すように、主電極層１０１の角部に応力緩衝用突出部４２０が設けられている。そのため、ワイヤボンディングなどによる外部端子との接続時に上側電極層２０１に荷重または衝撃力が加わっても、特に、応力集中の起こりやすい主電極層１０１の角部において、応力緩衝用突出部４２０が微小な弾性変形をして応力（衝撃力）を緩衝する作用を及ぼすため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、主電極層１０１の角部の層間膜クラックを防止することができる。 (Action / Effect)
According to this embodiment, as shown in FIG. 101, the stress buffering protrusion 420 is provided at the corner of the main electrode layer 101. Therefore, even when a load or impact force is applied to the upper electrode layer 201 when connected to an external terminal by wire bonding or the like, the stress buffering protrusion 420 is very small particularly at the corner of the main electrode layer 101 where stress concentration is likely to occur. In order to buffer the stress (impact force) by performing an elastic deformation, only a small stress (impact force) is applied to the interlayer insulating film in this portion. Therefore, interlayer film cracks at the corners of the main electrode layer 101 can be prevented.

なお、図１０１では、主電極層１０１の角部に四角形の応力緩衝用突出部４２０を設けたが、他の形状の応力緩衝用突出部でも同様の効果を奏する。また、それらを複数個組合せて設けてもよい。   In FIG. 101, square stress buffering protrusions 420 are provided at the corners of the main electrode layer 101. However, the stress buffering protrusions of other shapes also have the same effect. Further, a plurality of them may be provided in combination.

たとえば、図１０２〜図１０４に示すように、主電極層１０１の角部に置く応力緩衝用突出部４２０としては、円や楕円の一部や多角形の一部などの他の形状とすることが可能である。また、図１０５に示すように、主電極層１０１の角部に複数の応力緩衝用突出部４２１，４１２を組合せて配置してもよい。また、より高い応力緩衝効果を持たせるために、図１０６に示すように、応力緩衝用突出部４２０上の保護絶縁膜２０２，２０３を除去した構造としてもよい。さらに、図１０７に示すように主電極層１０１の角部や上側電極層２０１の角部の両方に応力緩衝用突出部４２０，４３０を設けて、かつ、応力緩衝用突出部の上部の保護絶縁膜１０２，１０３を除去するなど、複数の対応策を組合せて実施してもよい。   For example, as shown in FIGS. 102 to 104, the stress buffering protrusion 420 placed at the corner of the main electrode layer 101 may have another shape such as a circle, a part of an ellipse, or a part of a polygon. Is possible. In addition, as shown in FIG. 105, a plurality of stress buffering protrusions 421 and 412 may be arranged in combination at the corner of the main electrode layer 101. Further, in order to have a higher stress buffering effect, as shown in FIG. 106, the protective insulating films 202 and 203 on the stress buffering protrusion 420 may be removed. Furthermore, as shown in FIG. 107, stress buffering protrusions 420 and 430 are provided at both the corners of the main electrode layer 101 and the upper electrode layer 201, and the protective insulation is provided above the stress buffering protrusions. A plurality of countermeasures, such as removing the films 102 and 103, may be combined.

（実施の形態１４）
（構成）
さらに、パッド電極の少なくとも一部が埋込金属配線層で構成され、パッド電極が下側電極層と主電極層とを接続孔を介して重ねた構造を含み、下側電極層の角部の領域に応力緩衝用突出部を設けても同様の効果を奏する。このような本実施の形態における半導体装置の構造を図１０８に示す。下側電極層の角部の領域に応力緩衝用突出部がある以外は、実施の形態４における構造（図２７参照）と同様である。 (Embodiment 14)
(Constitution)
Further, at least a part of the pad electrode is formed of a buried metal wiring layer, and the pad electrode includes a structure in which the lower electrode layer and the main electrode layer are overlapped with each other through a connection hole. Even if a stress buffering protrusion is provided in the region, the same effect can be obtained. FIG. 108 shows the structure of such a semiconductor device in this embodiment. The structure is the same as that of the fourth embodiment (see FIG. 27) except that there is a stress buffering protrusion in the corner area of the lower electrode layer.

（作用・効果）
このような本発明によれば、図１０８に示すように、下側電極層２５０の角部に応力緩衝用突出部４４０が設けられている。 (Action / Effect)
According to the present invention as described above, as shown in FIG. 108, the stress buffering protrusions 440 are provided at the corners of the lower electrode layer 250.

そのため、ワイヤボンディングなどによる外部端子との接続時に主電極層１０１に荷重または衝撃力が加わっても、特に、応力集中の起こりやすい下側電極層２５０の角部において、応力緩衝用突出部４４０が微小な弾性変形をして応力（衝撃力）を緩衝する作用を及ぼすため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、下側電極層２５０の角部の層間膜クラックを防止することができる。   Therefore, even when a load or impact force is applied to the main electrode layer 101 during connection to an external terminal by wire bonding or the like, the stress buffering protrusions 440 are formed particularly at the corners of the lower electrode layer 250 where stress concentration easily occurs. Since it exerts an action of buffering stress (impact force) by performing minute elastic deformation, only a small stress (impact force) is applied to the interlayer insulating film in this portion. Therefore, interlayer film cracks at the corners of the lower electrode layer 250 can be prevented.

なお、図１０８では、下側電極層２５０の角部に四角形の応力緩衝用突出部４４０を設けたが、他の形状の応力緩衝用突出部でも同様の効果を奏する。また、それらを複数個組合せて設けてもよい。   In FIG. 108, the quadrangular stress buffering protrusions 440 are provided at the corners of the lower electrode layer 250. However, the stress buffering protrusions of other shapes also have the same effect. Further, a plurality of them may be provided in combination.

たとえば、図１０９〜図１１１に示すように、下側電極層２５０の角部に置く応力緩衝用突出部４４０としては、円や楕円の一部や多角形の一部などの他の形状とすることが可能である。また、図１１２に示すように、下側電極層２５０の角部に複数の応力緩衝用突出部４４１，４４２を組合せて配置してもよい。また、より高い応力緩衝効果を持たせるために、図１１３のように、下側電極層の角部の応力緩衝用突出部４４０、接続孔２５１の角部の応力緩衝用突出部４４３を重ねて、これらの上部の保護絶縁膜１０２，１０３を除去した構造としてもよい。   For example, as shown in FIGS. 109 to 111, the stress buffering protrusion 440 placed at the corner of the lower electrode layer 250 has another shape such as a circle, a part of an ellipse, or a part of a polygon. It is possible. In addition, as shown in FIG. 112, a plurality of stress buffering protrusions 441 and 442 may be arranged in combination at the corner of the lower electrode layer 250. In order to provide a higher stress buffering effect, as shown in FIG. 113, the stress buffering protrusions 440 at the corners of the lower electrode layer and the stress buffering protrusions 443 at the corners of the connection holes 251 are overlapped. A structure in which the upper protective insulating films 102 and 103 are removed may be employed.

さらに、図１１４に示したもののように、下側電極層２５０の角部、接続孔２５１の角部、主電極層１０１の角部のすべてに応力緩衝用突出部４４０，４４３，４００を設けて、かつ、応力緩衝用突出部の上部の保護絶縁膜１０２，１０３を除去するなど、複数の対応策を組合せて実施してもよい。   Further, as shown in FIG. 114, stress buffering protrusions 440, 443, and 400 are provided at all corners of the lower electrode layer 250, corners of the connection holes 251, and corners of the main electrode layer 101. In addition, a plurality of countermeasures may be implemented in combination, such as removing the protective insulating films 102 and 103 above the stress buffering protrusions.

（実施の形態１５）
さらに、パッド電極の少なくとも一部が埋込金属配線層で構成され、パッド電極が下側電極層と主電極層とを接続孔を介して重ねた構造を含み、下側電極層の厚みが下向きに部分的に厚くなった下側突出部を有し、下側突出部の角部の領域に応力緩衝用突出部を設けても同様の効果を奏する。このような本実施の形態における半導体装置の構造を図１１５に示す。 (Embodiment 15)
Furthermore, at least a part of the pad electrode is composed of a buried metal wiring layer, and the pad electrode includes a structure in which the lower electrode layer and the main electrode layer are stacked via the connection hole, and the thickness of the lower electrode layer is downward A similar effect can be obtained even if the lower protrusion is partially thickened and a stress buffer protrusion is provided in the corner area of the lower protrusion. FIG. 115 shows the structure of the semiconductor device in this embodiment.

下側突出部の角部の領域に応力緩衝用突出部がある点以外は、実施の形態５に示した構造（図３６参照）と同様である。   The structure is the same as the structure shown in the fifth embodiment (see FIG. 36) except that there is a stress buffering protrusion in the corner area of the lower protrusion.

（作用・効果）
このような本実施の形態によれば、図１１５に示すように、下側電極層の下側突出部２４０の角部に応力緩衝用突出部４５０が設けられている。 (Action / Effect)
According to this embodiment, as shown in FIG. 115, the stress buffering protrusion 450 is provided at the corner of the lower protrusion 240 of the lower electrode layer.

そのため、ワイヤボンディングなどによる外部端子との接続時に主電極層１０１に荷重または衝撃力が加わっても、特に、応力集中の起こりやすい下側突出部２４０の角部において、応力緩衝用突出部４５０が微小な弾性変形をして応力（衝撃力）を緩衝する作用を及ぼすため、この部分の層間絶縁膜には小さな応力（衝撃力）しか加わらない。したがって、下側突出部２４０の角部の層間絶縁膜にクラックが生じるのを防止することができる。   Therefore, even when a load or impact force is applied to the main electrode layer 101 during connection to an external terminal by wire bonding or the like, the stress buffering protrusion 450 is formed at the corner of the lower protrusion 240 where stress concentration is likely to occur. Since it exerts an action of buffering stress (impact force) by performing minute elastic deformation, only a small stress (impact force) is applied to the interlayer insulating film in this portion. Therefore, it is possible to prevent cracks from occurring in the interlayer insulating film at the corners of the lower protrusion 240.

なお、図１１５では、下側突出部２４０の角部に四角形の応力緩衝用突出部４５０を設けたが、他の形状の応力緩衝用突出部でも同様の効果を奏する。また、それらを複数個組合せて設けてもよい。   In FIG. 115, the quadrangular stress buffering protrusions 450 are provided at the corners of the lower protrusions 240, but the same effects can be obtained with the stress buffering protrusions of other shapes. Further, a plurality of them may be provided in combination.

たとえば、図１１６〜図１１８に示すように、下側突出部２４０の角部に置く応力緩衝用突出部４５０としては、円や楕円の一部や多角形の一部などの他のパターンなどを用いることが可能である。   For example, as shown in FIGS. 116 to 118, as the stress buffering protrusion 450 placed at the corner of the lower protrusion 240, other patterns such as a part of a circle or an ellipse or a part of a polygon may be used. It is possible to use.

また、図１１９に示すように、下側突出部２４０の角部に複数の応力緩衝用突出部４５１，４５２を組合せて配置してもよい。また、より高い応力緩衝効果を持たせるために、図１２０に示すように、下側突出部２４０の角部の応力緩衝用突出部４５０、下側電極層２５０の角部の応力緩衝用突出部４５３、接続孔２５１の角部の応力緩衝用突出部４５４を重ねて、これらの上部の保護絶縁膜１０２，１０３を除去した構造としてもよい。   Further, as shown in FIG. 119, a plurality of stress buffering protrusions 451 and 452 may be arranged in combination at the corner of the lower protrusion 240. In order to provide a higher stress buffering effect, as shown in FIG. 120, the stress buffering protrusion 450 at the corner of the lower protrusion 240 and the stress buffering protrusion at the corner of the lower electrode layer 250 are provided. 453 and the stress buffering protrusions 454 at the corners of the connection hole 251 may be overlapped, and the protective insulating films 102 and 103 may be removed.

さらに、図１２１に示すように、下側突出部２４０の角部、下側電極層２５０の角部、接続孔２５１の角部、主電極層１０１の角部のすべてに応力緩衝用突出部４５０，４５３，４５４，４００を設けて、かつ、応力緩衝用突出部の上部の保護絶縁膜１０２，１０３を除去するなど、複数の対応策を組合せて実施してもよい。   Furthermore, as shown in FIG. 121, the stress buffering protrusions 450 are formed on all of the corners of the lower protrusions 240, the corners of the lower electrode layer 250, the corners of the connection holes 251 and the corners of the main electrode layer 101. , 453, 454, and 400, and a plurality of countermeasures may be implemented in combination, such as removing the protective insulating films 102 and 103 above the stress buffering protrusions.

なお、今回開示した上記実施の形態はすべての点で例示であって制限的なものではない。本発明の範囲は上記した説明ではなくて特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更を含むものである。   In addition, the said embodiment disclosed this time is an illustration in all the points, Comprising: It is not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and includes all modifications within the scope and meaning equivalent to the terms of the claims.

１ 半導体基板、２ 素子分離絶縁膜、３ ゲート絶縁膜、４ ゲート電極、５ 不純物拡散層、６ ＭＯＳトランジスタ、７ 下地絶縁膜、８ コンタクトホール、９ 第１の配線溝、１０ 第１の金属（Ｗ）配線層、１１，２３０ 第１の層間絶縁膜、１２ 第１のビアホール、１３ 第２の配線溝、１４ 第２の金属（Ｃｕ）配線層、１４ａ，１８ａ，６１ａ，１００ａ 下敷膜、１４ｂ，１８ｂ，１００ｂ 銅シード膜、１４ｃ，１８ｃ，１００ｃ 銅めっき膜、１５ 第２の層間絶縁膜、１５ａ，１５ｃ，２０ａ，１０２ａ，２０２ａ シリコン窒化膜、１５ｂ，１５ｄ，２０ｂ，１０２ｂ，２０２ｂ 絶縁膜、１６ 第２のビアホール、１７ 第３の配線溝、１８，１００ 第３の金属（Ｃｕ）配線層、１９，６１，１０１ パッド電極（主電極層）、２０，１０２，２０２ 保護絶縁膜、２１，１０３，２０３ バッファコート膜、２２，１０４，２０４ パッド電極開口部、２５ モールド樹脂、６０ 層間絶縁膜、６５ ワイヤ、６６，６７，１０６，１０７ 荷重または衝撃力、６８ 角部、６９ クラック、１５０，２４０ 下側突出部、２００ 第４の金属（Ａｌ）配線層、２００ａ 下敷膜、２００ｂ アルミニウム合金膜、２００ｃ 反射防止膜、２０１ 上側電極層、２５０ 下側電極層、２５１ 接続孔、３００，３１０，３２０，３３０，３４０ 応力緩衝用金属（Ｃｕ）層、３０１，３１１，３２１，３３１，３４１ 応力緩衝用絶縁壁、４００，４０１，４０２，４１０，４２０，４３０，４４０，４５０ 応力緩衝用突出部。   DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Element isolation insulating film, 3 Gate insulating film, 4 Gate electrode, 5 Impurity diffusion layer, 6 MOS transistor, 7 Base insulating film, 8 Contact hole, 9 1st wiring groove, 10 1st metal ( W) wiring layer, 11, 230 first interlayer insulating film, 12 first via hole, 13 second wiring groove, 14 second metal (Cu) wiring layer, 14a, 18a, 61a, 100a underlay film, 14b , 18b, 100b Copper seed film, 14c, 18c, 100c Copper plating film, 15 Second interlayer insulating film, 15a, 15c, 20a, 102a, 202a Silicon nitride film, 15b, 15d, 20b, 102b, 202b Insulating film, 16 Second via hole, 17 Third wiring groove, 18, 100 Third metal (Cu) wiring layer, 19, 61, 101 Pad electrode (main electrode) ), 20, 102, 202 Protective insulating film, 21, 103, 203 Buffer coat film, 22, 104, 204 Pad electrode opening, 25 Mold resin, 60 interlayer insulating film, 65 wires, 66, 67, 106, 107 Load Or impact force, 68 corners, 69 cracks, 150, 240 lower protrusion, 200 fourth metal (Al) wiring layer, 200a underlay film, 200b aluminum alloy film, 200c antireflection film, 201 upper electrode layer, 250 Lower electrode layer, 251 connection hole, 300, 310, 320, 330, 340 Stress buffer metal (Cu) layer, 301, 311, 321, 331, 341 Stress buffer insulating wall, 400, 401, 402, 410, 420, 430, 440, 450 Protrusion for stress buffering.

Claims (11)

平面形状が、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形、ならびに、これらの少なくとも一部分を含む形状の組合せからなる群から選ばれた平面形状となるような凹部を形成する凹部形成工程と、
前記凹部の内面に少なくとも一部を被覆する下敷膜を形成する下敷膜形成工程と、
絶縁膜で覆われた前記凹部に導電性の電極材質を埋め込むパッド部形成工程とを含み、
前記凹部形成工程は、第１の凹部を形成する工程と、前記第１の凹部の一部分においてさらに深く凹む第２の凹部を形成する工程とを含む、半導体装置の製造方法。 The planar shape includes a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, a substantially polygonal shape having chamfered or rounded at least one corner portion, and at least a part thereof. A recess forming step for forming a recess that has a planar shape selected from the group consisting of a combination of shapes;
An underlay film forming step of forming an undercoat film covering at least part of the inner surface of the recess;
A pad portion forming step of embedding a conductive electrode material in the recess covered with an insulating film,
The recess forming step includes a step of forming a first recess and a step of forming a second recess that is further deeply recessed in a part of the first recess. 平面形状が、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形、ならびに、これらの少なくとも一部分を含む形状の組合せからなる群から選ばれた平面形状となるような凹部を形成する凹部形成工程と、
前記凹部の内面に少なくとも一部を被覆する下敷膜を形成する下敷膜形成工程と、
絶縁膜で覆われた前記凹部に導電性の電極材質を埋め込むパッド部形成工程とを含み、
前記凹部形成工程は、パッド部本体となる凹部本体とその角部領域に応力緩衝用絶縁壁を形成するための絶縁壁凹部とを形成する工程を含む、半導体装置の製造方法。 The planar shape includes a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, a substantially polygonal shape having chamfered or rounded at least one corner portion, and at least a part thereof. A recess forming step for forming a recess that has a planar shape selected from the group consisting of a combination of shapes;
An underlay film forming step of forming an undercoat film covering at least part of the inner surface of the recess;
A pad portion forming step of embedding a conductive electrode material in the recess covered with an insulating film,
The recessed portion forming step includes a step of forming a recessed portion main body serving as a pad portion main body and an insulating wall recessed portion for forming a stress buffering insulating wall in a corner region thereof. 平面形状が、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形、ならびに、これらの少なくとも一部分を含む形状の組合せからなる群から選ばれた平面形状となるような凹部を形成する凹部形成工程と、
前記凹部の内面に少なくとも一部を被覆する下敷膜を形成する下敷膜形成工程と、
絶縁膜で覆われた前記凹部に導電性の電極材質を埋め込むパッド部形成工程とを含み、
前記凹部形成工程は、パッド部本体となる凹部本体とその角部領域に突出した応力緩衝用突出部を形成するための緩衝用凹部とを形成する工程を含む、半導体装置の製造方法。 The planar shape includes a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, a substantially polygonal shape having chamfered or rounded at least one corner portion, and at least a part thereof. A recess forming step for forming a recess that has a planar shape selected from the group consisting of a combination of shapes;
An underlay film forming step of forming an undercoat film covering at least part of the inner surface of the recess;
A pad portion forming step of embedding a conductive electrode material in the recess covered with an insulating film,
The recessed portion forming step includes a step of forming a recessed portion main body serving as a pad portion main body and a buffer recessed portion for forming a stress buffer protruding portion protruding in a corner region thereof. 半導体基板と、
前記半導体基板上に配置され、トランジスタと第一層間絶縁膜とを有する第一層と、
前記第一層上に配置され、配線と第二層間絶縁膜とを有する第二層と、
前記第二層上に配置され、第一溝を有する第三層間絶縁膜と前記第一溝の側面および底面上に形成された下敷膜と前記第一溝内の前記下敷膜上に形成された銅を含有する第一金属部とを有する第三層と、
前記第三層上に配置され、保護膜を有する第四層とを備え、
前記第一金属部上の前記保護膜には開口部が形成されており、
前記下敷膜は前記第一金属部よりも硬く、
前記第一金属部の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状であり、
前記開口部を通して前記第一金属部にワイヤまたはバンプ電極が接続されている、半導体装置。 A semiconductor substrate;
A first layer disposed on the semiconductor substrate and having a transistor and a first interlayer insulating film;
A second layer disposed on the first layer and having a wiring and a second interlayer insulating film;
A third interlayer insulating film having a first groove disposed on the second layer, an underlying film formed on a side surface and a bottom surface of the first groove, and formed on the underlying film in the first groove A third layer having a first metal part containing copper;
A fourth layer disposed on the third layer and having a protective film;
An opening is formed in the protective film on the first metal part,
The underlay film is harder than the first metal part,
The planar shape of the first metal part is a combination of a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, and a substantially polygonal shape in which at least one corner portion is chamfered or rounded. A planar shape selected from the group consisting of:
A semiconductor device, wherein a wire or a bump electrode is connected to the first metal part through the opening. 前記ワイヤまたは前記バンプ電極は、アルミニウムを含有する第二金属部を介して前記第一金属部に接続され、
前記第二金属部は前記第一金属部の上でかつ、前記保護膜の前記開口部の下に設けられ、
前記第二金属部の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状である、請求項４に記載の半導体装置。 The wire or the bump electrode is connected to the first metal part via a second metal part containing aluminum,
The second metal part is provided on the first metal part and below the opening of the protective film,
The planar shape of the second metal part is a combination of a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, and a substantially polygonal shape in which at least one corner portion is chamfered or rounded. The semiconductor device according to claim 4, wherein the semiconductor device has a planar shape selected from the group consisting of: 半導体基板と、
前記半導体基板上に配置され、トランジスタと第一層間絶縁膜とを有する第一層と、
前記第一層上に配置され、配線と第二層間絶縁膜とを有する第二層と、
前記第二層上に配置され、第一溝を有する第三層間絶縁膜と前記第一溝の側面および底面上に形成された第一金属膜と前記第一溝内の前記第一金属膜上に形成された銅を含有する第一金属部とを有する第三層と、
前記第三層上に配置され、保護膜を有する第四層とを備え、
前記第一金属部上の前記保護膜には開口部が形成されており、
前記第一金属膜は、タンタルまたはチタンを含有し、
前記第一金属部の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状であり、
前記開口部を通して前記第一金属部にワイヤまたはバンプ電極が接続されている、半導体装置。 A semiconductor substrate;
A first layer disposed on the semiconductor substrate and having a transistor and a first interlayer insulating film;
A second layer disposed on the first layer and having a wiring and a second interlayer insulating film;
A third interlayer insulating film having a first groove disposed on the second layer, a first metal film formed on the side and bottom surfaces of the first groove, and the first metal film in the first groove A third layer having a first metal part containing copper formed in
A fourth layer disposed on the third layer and having a protective film;
An opening is formed in the protective film on the first metal part,
The first metal film contains tantalum or titanium,
The planar shape of the first metal part is a combination of a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, and a substantially polygonal shape in which at least one corner portion is chamfered or rounded. A planar shape selected from the group consisting of:
A semiconductor device, wherein a wire or a bump electrode is connected to the first metal part through the opening. 前記第一金属膜は窒素を含有し、
前記ワイヤまたは前記バンプ電極は、アルミニウムを含有する第二金属部を介して前記第一金属部に接続され、
前記第二金属部は前記第一金属部の上でかつ、前記保護膜の前記開口部の下に設けられ、
前記第二金属部の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状である、請求項６に記載の半導体装置。 The first metal film contains nitrogen;
The wire or the bump electrode is connected to the first metal part via a second metal part containing aluminum,
The second metal part is provided on the first metal part and below the opening of the protective film,
The planar shape of the second metal part is a combination of a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, and a substantially polygonal shape in which at least one corner portion is chamfered or rounded. The semiconductor device according to claim 6, wherein the semiconductor device has a planar shape selected from the group consisting of: 半導体基板を準備する工程と、
前記半導体基板上にトランジスタと第一層間絶縁膜とを形成することによって第一層を形成する工程と、
前記第一層上に配線と第二層間絶縁膜とを形成することによって第二層を形成する工程と、
前記第二層上に第三層間絶縁膜を形成する工程と、
前記第三層間絶縁膜に第一溝を形成する工程と、
前記第一溝の側面および底面ならびに前記第三層間絶縁膜の上面に下敷膜を形成する工程と、
前記第一溝内の前記下敷膜上および前記第三層間絶縁膜の上面の前記下敷膜上に銅めっき膜を形成する工程と、
化学機械研磨法で前記第三層間絶縁膜上の前記下敷膜および前記銅めっき膜を取り除いて前記第一溝内に第一金属部を設けることにより、前記第三層間絶縁膜、前記下敷膜、および前記第一金属部で構成される第三層を形成する工程と、
前記第三層上に保護膜を形成する工程と、
前記第一金属部上の前記保護膜に開口部を設けることにより、前記開口部を有する前記保護膜で構成される第四層を形成する工程と、
前記開口部を通して前記第一金属部にワイヤまたはバンプ電極を接続する工程とを含み、
前記第一溝の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状である、半導体装置の製造方法。 Preparing a semiconductor substrate;
Forming a first layer by forming a transistor and a first interlayer insulating film on the semiconductor substrate;
Forming a second layer by forming a wiring and a second interlayer insulating film on the first layer;
Forming a third interlayer insulating film on the second layer;
Forming a first groove in the third interlayer insulating film;
Forming an underlay film on the side and bottom surfaces of the first groove and the upper surface of the third interlayer insulating film;
Forming a copper plating film on the underlying film in the first groove and on the underlying film on the upper surface of the third interlayer insulating film;
By removing the underlying film and the copper plating film on the third interlayer insulating film by a chemical mechanical polishing method and providing a first metal part in the first groove, the third interlayer insulating film, the underlying film, And forming a third layer composed of the first metal part,
Forming a protective film on the third layer;
Forming a fourth layer composed of the protective film having the opening by providing an opening in the protective film on the first metal part; and
Connecting a wire or bump electrode to the first metal part through the opening,
The planar shape of the first groove is a combination of a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, and a substantially polygonal shape in which at least one corner portion is chamfered or rounded. A method for manufacturing a semiconductor device, which is a planar shape selected from a group. 前記第三層を形成する工程と前記保護膜を形成する工程との間に、
前記第三層上にアルミニウム膜を堆積する工程と、
前記アルミニウム膜をエッチングして前記第一金属部上に第二金属部を形成する工程とをさらに含み、
前記ワイヤまたはバンプ電極を接続する工程においては、前記ワイヤまたは前記バンプ電極は、前記第二金属部を介して前記第一金属部に接続され、
前記第二金属部の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状である、請求項８に記載の半導体装置の製造方法。 Between the step of forming the third layer and the step of forming the protective film,
Depositing an aluminum film on the third layer;
Etching the aluminum film to form a second metal part on the first metal part,
In the step of connecting the wire or the bump electrode, the wire or the bump electrode is connected to the first metal part via the second metal part,
The planar shape of the second metal part is a combination of a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, and a substantially polygonal shape in which at least one corner portion is chamfered or rounded. The method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor device has a planar shape selected from the group consisting of: 半導体基板を準備する工程と、
前記半導体基板上にトランジスタと第一層間絶縁膜とを形成することによって第一層を形成する工程と、
前記第一層上に配線と第二層間絶縁膜とを形成することによって第二層を形成する工程と、
前記第二層上に第三層間絶縁膜を形成する工程と、
前記第三層間絶縁膜に第一溝を形成する工程と、
前記第一溝の側面および底面ならびに前記第三層間絶縁膜の上面に、タンタルまたはチタンを含有する第一金属膜を形成する工程と、
前記第一溝内の前記第一金属膜上および前記第三層間絶縁膜の上面の前記第一金属膜上に銅めっき膜を形成する工程と、
化学機械研磨法で前記第三層間絶縁膜上の前記第一金属膜および前記銅めっき膜を取り除いて前記第一溝内に第一金属部を設けることにより、前記第三層間絶縁膜、前記第一金属膜、および前記第一金属部で構成される第三層を形成する工程と、
前記第三層上に保護膜を形成する工程と、
前記第一金属部上の前記保護膜に開口部を設けることにより、前記開口部を有する前記保護膜で構成される第四層を形成する工程と、
前記開口部を通して前記第一金属部にワイヤまたはバンプ電極を接続する工程とを含み、
前記第一溝の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状である、半導体装置の製造方法。 Preparing a semiconductor substrate;
Forming a first layer by forming a transistor and a first interlayer insulating film on the semiconductor substrate;
Forming a second layer by forming a wiring and a second interlayer insulating film on the first layer;
Forming a third interlayer insulating film on the second layer;
Forming a first groove in the third interlayer insulating film;
Forming a first metal film containing tantalum or titanium on a side surface and a bottom surface of the first groove and an upper surface of the third interlayer insulating film;
Forming a copper plating film on the first metal film in the first groove and on the first metal film on the upper surface of the third interlayer insulating film;
By removing the first metal film and the copper plating film on the third interlayer insulating film by a chemical mechanical polishing method and providing a first metal portion in the first groove, the third interlayer insulating film, the first Forming a third layer composed of one metal film and the first metal part;
Forming a protective film on the third layer;
Forming a fourth layer composed of the protective film having the opening by providing an opening in the protective film on the first metal part; and
Connecting a wire or bump electrode to the first metal part through the opening,
The planar shape of the first groove is a combination of a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, and a substantially polygonal shape in which at least one corner portion is chamfered or rounded. A method for manufacturing a semiconductor device, which is a planar shape selected from a group. 前記第三層を形成する工程と前記保護膜を形成する工程との間に、
前記第三層上にアルミニウム膜を堆積する工程と、
前記アルミニウム膜をエッチングして前記第一金属部上に第二金属部を形成する工程とをさらに含み、
前記第一金属部は窒素を含有し、
前記ワイヤまたはバンプ電極を接続する工程においては、前記ワイヤまたは前記バンプ電極は、前記第二金属部を介して前記第一金属部に接続され、
前記第二金属部の平面形状は、略円形、略楕円形、少なくとも１つの内角が９０°より大きい略多角形、および、少なくとも１つの角部に面取りや丸みをつけた略多角形の組合せからなる群から選ばれた平面形状である、請求項１０に記載の半導体装置の製造方法。 Between the step of forming the third layer and the step of forming the protective film,
Depositing an aluminum film on the third layer;
Etching the aluminum film to form a second metal part on the first metal part,
The first metal part contains nitrogen;
In the step of connecting the wire or the bump electrode, the wire or the bump electrode is connected to the first metal part via the second metal part,
The planar shape of the second metal part is a combination of a substantially circular shape, a substantially elliptical shape, a substantially polygonal shape having at least one interior angle greater than 90 °, and a substantially polygonal shape in which at least one corner portion is chamfered or rounded. The method for manufacturing a semiconductor device according to claim 10, wherein the semiconductor device has a planar shape selected from the group consisting of:
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