JP2011129828A - Semiconductor substrate, electronic device, and method of manufacturing semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a good-quality GaN-based semiconductor crystal layer by using a silicon substrate. <P>SOLUTION: A semiconductor substrate 100 includes a substrate 102 having a first area 104 and a second area 106 on a surface, and a first semiconductor formed over the first area. The surface of the substrate is composed of Si<SB>x</SB>Ge<SB>1-x</SB>(0≤x≤1) and the first area is surrounded by the second area. The first semiconductor is a group III-V compound semiconductor containing a nitrogen atom, is a single crystal, and provides lattice matching or pseudo-lattice matching with the Si<SB>x</SB>Ge<SB>1-x</SB>. The second area has a shape different from that of the first area. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor substrate, an electronic device, and a method for manufacturing a semiconductor substrate.

  Patent Document 1 discloses a method for forming a nitride semiconductor capable of improving the flatness and crystallinity of a nitride semiconductor layer. In this forming method, a plurality of cylindrical portions made of Si are formed on the upper surface of the Si substrate by processing the upper surface of the Si substrate, and an n-type GaN layer is formed on the plurality of cylindrical portions.

JP 2003-22973 A

For example, if an inhibitor made of SiO ₂ is formed on a substrate, an opening reaching the substrate is formed in the inhibitor, and GaN is selectively epitaxially grown in the opening using the inhibitor as a mask, a crystal is grown in a limited region. Therefore, a thick GaN layer can be formed. Here, when a Si substrate is used as the substrate, an intermediate layer such as AlN must be formed between the Si substrate and GaN for the purpose of preventing Si erosion by Ga. However, since AlN cannot be selectively epitaxially grown, it is necessary to epitaxially grow AlN before the inhibitor is formed, and AlN and GaN cannot be continuously epitaxially grown. When selective epitaxial growth of AlN and GaN cannot be performed continuously, there is a problem that the manufacturing cost increases. Further, GaN selectively epitaxially grown in the opening tends to be thick at the boundary with the inhibitor, and there is a problem that the layer thickness is not uniform.

In order to solve the above problems, in a first aspect of the present invention, a substrate having a first region and a second region on a surface, a first semiconductor formed above the first region, and the first semiconductor A second semiconductor formed above two regions, the surface of the substrate is Si _x Ge _1-x (0 ≦ x ≦ 1), the second region surrounds the first region, The first region is different from the first region in that the first semiconductor is a single crystal, is a group 3-5 compound semiconductor containing a nitrogen atom, and lattice-matched or pseudo-lattice-matched with the surface of the substrate. Provided is a semiconductor substrate in which a semiconductor is polycrystalline and is a Group 3-5 compound semiconductor containing a nitrogen atom.

  The substrate may further include a third region surrounding the second region on the surface of the substrate, and may further include an inhibitor formed above the third region. Here, the inhibitor inhibits crystal growth of the first semiconductor and the second semiconductor.

In the second aspect of the present invention, a substrate having a first region, a second region surrounding the first region, and a fourth region surrounding the second region on the surface, and formed on the surface of the fourth region A plurality of grooves formed, a first semiconductor formed above the first region, and a third semiconductor formed across the plurality of grooves, wherein the surface of the substrate is Si _x Ge _{1− x} (0 ≦ x ≦ 1), the second region is different from the first region, the first semiconductor is a single crystal, and is a group 3-5 compound semiconductor containing a nitrogen atom, In addition, the third semiconductor is a group 3-5 compound semiconductor containing a nitrogen atom and lattice-matched or pseudo-lattice-matched with the Si _x Ge _1-x, and the interval between the plurality of grooves is larger than the width of the first region. A short semiconductor substrate is provided.

In the third aspect of the present invention, a substrate having a first region, a second region surrounding the first region, and a fifth region surrounding the second region on the surface, and formed on the surface of the fifth region A plurality of trenches, a first semiconductor formed above the first region, and a fourth semiconductor formed across the plurality of trenches, wherein the surface of the substrate is Si _x Ge _{1− x} (0 ≦ x ≦ 1), the second region is different from the first region, the first semiconductor is a single crystal, and is a group 3-5 compound semiconductor containing a nitrogen atom, In addition, the fourth semiconductor is a group 3-5 compound semiconductor containing a nitrogen atom and lattice-matched or pseudo-lattice-matched with the Si _x Ge _1-x, and the interval between the plurality of grooves is larger than the width of the first region. Provide a long semiconductor substrate.

Examples of the first region and the second region include those having different plane orientations. Examples of the first region and the second region include those having different surface roughness. Examples of the first region and the second region include those having different impurity concentrations. Examples of the substrate include those having a groove surrounding the first region on the surface, and examples of the second region include a side wall surface of the groove. Examples of the substrate include those having grooves on the surface, examples of the first region include those that are the bottom surfaces of the grooves, and examples of the second region include those that are side walls of the grooves.
It is preferable that the first semiconductor is formed on both the surface of the substrate other than the groove and the bottom surface of the groove, and is divided on the side wall of the groove. The intermediate crystal may further include an intermediate crystal formed between the surface of the substrate and the first semiconductor, and the composition of the intermediate crystal is B _x Al _y Ga _z In _1-xyz N (0 ≦ x <1, 0 ≦ y ≦ 1, 0 ≦ z ≦ 1, and 0 <x + y + z ≦ 1), and the Si _x Ge _1-x and the intermediate crystal are pseudo-lattice matched It is preferable that the intermediate crystal and the first semiconductor are pseudo-lattice matched. The plurality of intermediate crystals formed above regions having different properties inherit the difference in properties of the underlying region and have different properties. The first region may have a substantially square planar shape, and the length of the long side of the square may be 300 μm or less.

  According to a fourth aspect of the present invention, there is provided an electronic device having an element obtained using the first semiconductor in the semiconductor substrate as an active region.

In a fifth aspect of the present invention, the step (a) of forming a first region and a second region surrounding the first region on the surface of the substrate, and nitrogen atoms in the first region and the second region are formed. (B) forming a Group 3-5 compound semiconductor containing, wherein the surface of the substrate is Si _x Ge _1-x (0 <x ≦ 1), and in the step (a), The property of the second region is made different from the property of the first region, and in the step (b), the semiconductor of the first region is lattice-matched or pseudo-lattice-matched with the Si _x Ge _1-x and single-layered. Provided is a method for manufacturing a semiconductor substrate, which is formed into a crystal and the semiconductor in the second region is formed into a polycrystal.

An example of a cross section of a semiconductor substrate 100 is shown. An example of a plan view of a semiconductor substrate 100 is shown. An example of a cross section of a semiconductor substrate 300 is shown. An example of a cross section of a semiconductor substrate 400 is shown. An example of a cross section of a semiconductor substrate 500 is shown. An example of a cross section of a semiconductor substrate 600 is shown. An example of a plan view of a semiconductor substrate 600 is shown. An example of a cross section of a semiconductor substrate 700 is shown. An example of a cross section of a semiconductor substrate 800 is shown. An example of a cross section of a semiconductor substrate 900 is shown. The drain current-drain voltage characteristic of the HEMT device formed in the 1st semiconductor 108 is shown.

  Hereinafter, the present invention will be described through embodiments of the invention. FIG. 1 shows an example of a cross section of a semiconductor substrate 100. FIG. 2 shows a plan example of the semiconductor substrate 100. The semiconductor substrate 100 includes a substrate 102 that is a base substrate. A surface of the substrate 102 has a first region 104 and a second region 106. A first semiconductor 108 is formed on the first region 104 of the substrate 102, and a second semiconductor 110 is formed on the second region 106 of the substrate 102.

The surface of the substrate 102 is Si _x Ge _1-x (0 ≦ x ≦ 1). The substrate 102 may be Si _x Ge _1-x (0 ≦ x ≦ 1) over the entire surface and bulk, and only the surface is Si _x Ge _1-x (0 ≦ x ≦ 1), The bulk may be Si. For example, as the substrate 102, a silicon wafer whose surface is made of Si _x Ge _1-x can be cited. By using a silicon wafer as the substrate 102, the material cost of the semiconductor substrate 100 can be reduced. In addition, the thermal characteristics of an electronic device formed using the semiconductor substrate 100 are improved. The substrate 102 may be GaAs, sapphire, SiC, AlN, or GaN.

  The first area 104 is surrounded by the second area 106. The first region 104 preferably has a substantially square planar shape, and the length of the long side of the square is preferably 300 μm or less. The second region 106 has a different property from the first region 104. For example, the first region 104 and the second region 106 have different surface roughness. Here, the “surface roughness” is a measurable value indicating the degree of roughness of the material surface, and for example, 5-point average roughness Ra can be exemplified. Note that the difference in properties between the first region 104 and the second region 106 may be that the impurity concentration of the substrate 102 in the first region 104 is different from the impurity concentration of the substrate 102 in the second region 106.

  By surrounding the first region 104 with the second region 106 having different properties, the first semiconductor 108 formed in the first region 104 can be partitioned into small rectangular regions of, for example, 300 μm or less. As a result, the crystallinity of the first semiconductor 108 can be improved. That is, by forming the first semiconductor 108 in a small region and performing a heat treatment such as annealing, crystal defects existing in the first semiconductor 108 are moved to the peripheral portion of the first semiconductor 108 and stabilized. As a result, crystal defects inside the first semiconductor 108 can be eliminated.

The first semiconductor 108 is a group 3-5 compound semiconductor containing a nitrogen atom, is a single crystal, and lattice matches or pseudo-lattice matches with Si _x Ge _1-x . An example of the first semiconductor 108 is GaN. Here, pseudo-lattice matching is not perfect lattice matching because the difference between the lattice constants of the two semiconductor layers in contact with each other is small, but it is almost lattice-matched within a range where defects due to lattice mismatch are not significant. Thus, it means a state in which two semiconductor layers in contact with each other can be stacked. For example, a stacked state of a Ge layer and a GaAs layer is called pseudo lattice matching.

  The second semiconductor 110 is a group 3-5 compound semiconductor containing nitrogen atoms and is polycrystalline. An example of the second semiconductor 108 is GaN. Although the second semiconductor 110 is formed at the same time as the first semiconductor 108, the second region 106 is different from the first region 104 in nature, so that it grows as a polycrystal instead of a single crystal.

  According to the semiconductor substrate 100 described above, the cost can be reduced and the thermal characteristics can be improved by using a silicon wafer. In addition, the crystallinity of the first semiconductor 108 can be increased. Since the first semiconductor 108 can be partitioned and formed in the first region 104 without using the selective epitaxial growth technique, GaN is applied as the first semiconductor 108 and AlN that cannot be selectively epitaxially grown is used as the intermediate layer. Even if it exists, GaN can be continuously epitaxially grown following AlN. As a result, the manufacturing cost can be reduced.

  FIG. 3 shows a cross-sectional example of the semiconductor substrate 300. In the semiconductor substrate 100, the surface roughness is exemplified as an example in which the property of the second region 106 is different from that of the first region 104. In the semiconductor substrate 300, an example in which the plane orientation is different will be described as an example in which the first region 104 and the second region 106 have different properties.

  The first region 104 and the second region 106 of the semiconductor substrate 300 have different plane orientations. For example, the plane orientation of the first region 104 is a low-order plane orientation suitable for epitaxial growth, and the plane orientation of the second region 106 is a high-order plane orientation in which no single crystal is epitaxially grown. In such a case, a single crystal layer is formed in the first region 104, and a polycrystalline layer is formed in the second region 106. As a result, the first semiconductor 108 is formed in the first region 104. As a result, like the semiconductor substrate 100, the crystallinity of the first semiconductor 108 can be improved, and the manufacturing cost can be reduced even when AlN is used as the intermediate layer.

  FIG. 4 shows a cross-sectional example of the semiconductor substrate 400. In the semiconductor substrate 400, an example in which a groove is formed will be described as an example in which the properties of the first region 104 and the second region 106 are different.

  The substrate 102 of the semiconductor substrate 400 has a groove 403 surrounding the first region 104 on the surface. The second region 106 is a side wall surface of the groove 403. A fifth semiconductor 414 is formed on the bottom surface of the groove 403. The fifth semiconductor 414 is made of the same material as the first semiconductor 108 and is made of a single crystal. The fifth semiconductor 414 and the first semiconductor 108 are divided by the side wall of the groove 403 as a boundary.

  In such a case, the first semiconductor 108 formed in the first region 104 is divided from the fifth semiconductor 414, so that the first semiconductor 108 is formed by partitioning into the first region 104. As a result, like the semiconductor substrate 100, the crystallinity of the first semiconductor 108 can be improved, and the manufacturing cost can be reduced even when AlN is used as the intermediate layer. In addition, since the fifth semiconductor 414 and the first semiconductor 108 are separated from each other with the sidewall of the groove 403 as a boundary, the stress in the peripheral portion of the first semiconductor 108 is relieved and the generation of cracks is suppressed.

  Further, when an inhibitor is used as the structure surrounding the first region 104, the semiconductor raw material formed in the first region 104 is not consumed on the inhibitor, and the edge of the semiconductor formed in the first region 104 is not consumed. The semiconductor raw material is concentrated on the part. As a result, the end portion of the semiconductor formed in the first region 104 becomes thick. However, in the case of this embodiment in which an inhibitor is not used, the variation of the semiconductor material on the bottom surface of the first region 104 or the groove 403 is reduced, so that the first semiconductor formed on the bottom surface of the first region 104 or the groove 403 is used. The uniformity of the layer thickness of 108 and the fifth semiconductor 414 is improved.

  FIG. 5 shows a cross-sectional example of the semiconductor substrate 500. In the semiconductor substrate 500, as in the semiconductor substrate 400, an example in which a groove is formed will be described as an example in which the first region 104 and the second region 106 have different properties. However, in the semiconductor substrate 500, the first semiconductor 108 is formed at the bottom of the groove.

  The substrate 102 of the semiconductor substrate 500 has a groove 503 on the surface. The first region 104 is a bottom surface of the groove 503, and the second region 106 is a side wall surface of the groove 503. A sixth semiconductor 516 is formed on the surface of the substrate 102 at a place other than the groove 503. The sixth semiconductor 516 is made of the same material as the first semiconductor 108 and is made of a single crystal, and the sixth semiconductor 516 and the first semiconductor 108 are divided by the side wall of the groove 503 as a boundary.

  In such a case, the first semiconductor 108 formed in the first region 104 is divided from the sixth semiconductor 516, so that the first semiconductor 108 is formed by partitioning into the first region 104. As a result, like the semiconductor substrate 100, the crystallinity of the first semiconductor 108 can be improved, and the manufacturing cost can be reduced even when AlN is used as the intermediate layer. In addition, since the sixth semiconductor 516 and the first semiconductor 108 are separated from each other with the sidewall of the groove 503 as a boundary, the stress in the peripheral portion of the first semiconductor 108 is relieved and the generation of cracks is suppressed.

  Further, when an inhibitor is used as the structure surrounding the first region 104, the semiconductor raw material formed in the first region 104 is not consumed on the inhibitor, and the edge of the semiconductor formed in the first region 104 is not consumed. The semiconductor raw material is concentrated on the part. As a result, the end portion of the semiconductor formed in the first region 104 becomes thick. However, in the case of this embodiment in which an inhibitor is not used, the variation of the semiconductor raw material at the bottom surface of the groove 503 or the portion other than the groove 503 which is the first region 104 is reduced. The uniformity of the layer thickness of the first semiconductor 108 and the sixth semiconductor 516 formed in the place is improved.

  Note that the second region 106 in the semiconductor substrate 100 may be surrounded by an inhibitor as shown in FIGS. 6 and 7. FIG. 6 shows a cross-sectional example of the semiconductor substrate 600. FIG. 7 shows a plan example of the semiconductor substrate 600. The substrate 102 has a third region 602 that surrounds the second region 106. An inhibitor 604 is formed on the third region 602. The inhibitor 604 inhibits crystal growth of the first semiconductor 108 and the second semiconductor 110. The crystal layer can be epitaxially grown only in the intended region by the inhibitor 604. Since an extra epitaxial growth layer is not formed on the inhibitor 604, generation of particles or the like that would occur due to peeling or the like can be suppressed if an extra epitaxial growth layer is formed. Further, if the inhibitor 604 is formed of an insulator such as silicon oxide, it can be used as a region for forming a wiring or the like. The inhibitor 604 is not applied as a structure surrounding the first region 104. Therefore, the problem described in the column of the problem to be solved by the invention does not occur. That is, the inhibitor 604 does not reduce the uniformity of the first semiconductor 108 formed in the first region 104.

Further, as shown in FIG. 8, an intermediate crystal may be formed between the substrate 102 and the first semiconductor 108. FIG. 8 shows a cross-sectional example of the semiconductor substrate 700. An intermediate crystal 702 is formed between the surface of the substrate 102 and the first semiconductor 108. Intermediate crystal 702, the composition is a _{B x Al y Ga z In 1} -x-y-z N (0 ≦ x <1,0 ≦ y ≦ 1,0 ≦ z ≦ 1, and 0 <x + y + z ≦ 1) . An example of the intermediate crystal 702 is AlN. The Si _x Ge _1-x and the intermediate crystal 702 are preferably lattice-matched or pseudo-lattice matched, and the intermediate crystal 702 and the first semiconductor 108 are preferably lattice-matched or pseudo-lattice matched. The intermediate crystal 702 facilitates crystal growth of the first semiconductor 108 on the substrate 102.

FIG. 9 shows a cross section of the semiconductor substrate 800. The semiconductor substrate 800 has a first region 104, a second region 106, and a fourth region 802 on the surface of the substrate 102. The second area 106 surrounds the first area 104, and the fourth area 802 surrounds the second area 106. A plurality of grooves 804 are formed on the surface of the fourth region 802, and the first semiconductor 108 is formed on the first region 104. A third semiconductor 806 is formed across the plurality of grooves 804. The surface of the substrate 102 is Si _x Ge _1-x (0 ≦ x ≦ 1), and the second region 106 and the first region 104 have different surface properties. The first semiconductor 108 is a single crystal, is a group 3-5 compound semiconductor containing a nitrogen atom, and lattice-matched or pseudo-lattice-matched with Si _x Ge _1-x . The third semiconductor 806 is a Group 3-5 compound semiconductor containing nitrogen atoms, and the interval between the plurality of grooves 804 is shorter than the width of the first region 104. It is preferable that the second semiconductor 110 is formed on the second region.

  That is, the semiconductor substrate 800 has a structure in which the structure of the semiconductor substrate 100 is surrounded by the groove 804 in the fourth region 802 and the third semiconductor 806. Since the groove 804 is provided in the fourth region 802, the third semiconductor 806 formed in the fourth region 802 is divided by the plurality of grooves 804, and the stress is relieved. For this reason, the third semiconductor 806 is difficult to peel off, and as a result, generation of particles due to layer peeling or the like can be suppressed. In the semiconductor substrate 800, the interval between the plurality of grooves 804 is shorter than the width of the first region 104, so that the third semiconductor 806 is formed more finely divided than the first semiconductor 108 and less stressed than the first semiconductor 108. . As a result, the third semiconductor 806 is formed less easily than the first semiconductor 108.

FIG. 10 shows a cross section of the semiconductor substrate 900. The semiconductor substrate 900 includes a first region 104, a second region 106, and a fifth region 902 on the surface of the substrate 102. The second region 106 surrounds the first region 104, and the fifth region 902 surrounds the second region 106. A plurality of grooves 904 are formed on the surface of the fifth region 902, and the first semiconductor 108 is formed on the first region 104. A fourth semiconductor 906 is formed across the plurality of grooves 904. The surface of the substrate 102 is Si _x Ge _1-x (0 ≦ x ≦ 1), and the second region 106 and the first region 104 have different surface properties. The first semiconductor 108 is a single crystal, is a group 3-5 compound semiconductor containing a nitrogen atom, and lattice-matched or pseudo-lattice-matched with Si _x Ge _1-x . The fourth semiconductor 906 is a group 3-5 compound semiconductor containing nitrogen atoms, and the interval between the plurality of grooves 904 is longer than the width of the first region 104. It is preferable that the second semiconductor 110 is formed on the second region.

  That is, the semiconductor substrate 900 has a structure in which the structure of the semiconductor substrate 100 is surrounded by the groove 904 of the fifth region 902 and the fourth semiconductor 906. Since the fifth region 902 includes the groove 904, the fourth semiconductor 906 formed in the fifth region 902 is divided by the plurality of grooves 904, and stress is relieved. For this reason, the fourth semiconductor 906 is unlikely to peel off, and as a result, generation of particles due to layer peeling or the like can be suppressed. In the semiconductor substrate 900, since the interval between the plurality of grooves 904 is longer than the width of the first region 104, the region of the fourth semiconductor 906 can be made larger. The surface of the fourth semiconductor 906 in a large region can be used as a formation region for wiring or the like.

  Note that an element using the first semiconductor 108 in the semiconductor substrate 700 as the active region can be formed from the semiconductor substrate 100 described above. Examples of such an element include a heterojunction bipolar transistor (HBT), a high electron mobility transistor (HEMT), a light emitting diode, a laser diode, an optical sensor, and a solar cell.

Further, the semiconductor substrate 700 to the semiconductor substrate 700 can be manufactured by the following method. That is, after the step (a) of forming the first region 104 and the second region 106 surrounding the first region 104 on the surface of the substrate 102, the first region 104 and the second region 106 contain nitrogen atoms. Step (b) of forming a Group 3-5 compound semiconductor is performed. Here, the surface of the substrate 102 is Si _x Ge _1-x (0 <x ≦ 1), and in the step (a), the property of the second region 106 is made different from the property of the first region 104, ( In step b), the semiconductor in the first region 104 is lattice-matched or pseudo-lattice-matched with Si _x Ge _1-x and formed into a single crystal, and the semiconductor in the second region 106 is formed into a polycrystal.

  Examples of the substrate 102 include Si, GaAs, sapphire, SiC, AlN, and GaN. When Si is used as the substrate 102 and a GaN-based crystal is epitaxially grown as the first semiconductor 108, it may be epitaxially grown on the (111) plane or the (110) plane of the substrate 102. An off angle may be given to the epitaxial growth surface of the substrate 102. The angle and direction of the off angle are arbitrary.

Plasma etching or wet etching can be used as a method of forming grooves in the substrate 102 to change the plane orientation or to form surface roughness. A mask using lithography can be used for patterning. Examples of the plasma etching source gas include fluorine-containing compounds such as SF ₆ and CF ₄ , inert gases such as Ar, oxygen, and combinations thereof. Examples of the wet etching solution include aqueous solutions of inorganic basic compounds such as hydrofluoric acid, NaOH, KOH, and CsOH, and aqueous solutions of organic basic compounds such as hydrazine, tetramethylammonium hydroxide, and ethylenediamine. The depth of the groove to be formed is not limited, but is preferably a depth at which a step that does not interfere with each other is formed so that the epitaxial crystal in the upper part of the groove and the epitaxial crystal in the lower part of the groove do not exert a strong stress. Examples of the groove depth include a range of 1 μm to 100 μm.

  The size of the first semiconductor 108 depends on the size of the device active portion formed therein, the property and thickness of the first semiconductor 108, the presence / absence of dislocation exclusion processing, and the like. When forming a large device, it is necessary to increase the area of the first semiconductor 108. When the first semiconductor 108 has a large lattice constant difference or a large thermal expansion coefficient difference with silicon, the difference therebetween is required. Therefore, it is necessary to reduce the area of the first semiconductor 108 in order to suppress the strain that causes the generation of cracks corresponding to the above. Further, since the strain increases as the thickness of the first semiconductor 108 increases, the area of the first semiconductor 108 is reduced in order to suppress the occurrence of cracks. When the intermediate layer 702 is formed between the first semiconductor 108 and the substrate 102 and a crystal layer that can eliminate dislocations out of the crystal by heat treatment such as Ge is applied as the intermediate layer 702, the dislocation is excluded. A suitable area of the first semiconductor 108 is selected. Examples of the size of the first semiconductor 108 include a length of a long side between 1 μm and 1000 μm, preferably 2 μm to 500 μm, and more preferably 3 μm to 200 μm. Examples of the epitaxial growth method of the first semiconductor 108 include an MBE method, an MOCVD method, and an HVPE method. Note that the second semiconductor 110, the fifth semiconductor 414, the sixth semiconductor 516, the third semiconductor 806, and the fourth semiconductor 906 are epitaxially grown simultaneously with the first semiconductor 108.

(Example)
A semiconductor substrate 400 was formed, and a GaN-HEMT was formed on the first semiconductor 108. As the substrate 102, a Si substrate having a thickness of 525 μm, an epitaxial surface (111), and no off-angle was used. A resist having a square opening with a side of 20 μm was formed as a mask by photolithography. SF ₆ and CF ₄ were allowed to act as reactive gases on the Si substrate surface exposed through the mask opening, and a groove 403 having a depth of 20 μm was formed by plasma etching. After removing the resist with acetone, the first semiconductor 108 was epitaxially grown on the Si substrate by MOCVD. The first semiconductor 108 was an AlN / AlGaN / GaN / AlGaN laminated body of AlN (thickness 100 nm), AlGaN (thickness 20 nm), GaN (thickness 6000 nm), and AlGaN (thickness 25 nm) in this order from the substrate 102 side. Note that a fifth semiconductor 414 having the same configuration was formed at the same time as the first semiconductor 108. Tetramethylgallium (TMG), tetramethylaluminum (TMA), and ammonia (NH ₃ ) were used as MOCVD source gases. Hydrogen was used as the carrier gas. The reactor pressure was 15 kPa. The substrate temperature was 900 ° C. to 1150 ° C. The supply amount of TMG / TMA / NH ₃ in each layer was as follows.
When forming AlN (100 nm): 0 μmol / 20 μmol / 7.
When forming AlGaN (20 nm): 20 μmol / 4 μmol / 7.
When forming GaN (6000 nm): 90 μmol / 0 μmol / 7.
When forming AlGaN (25 nm): 22 μmol / 4.5 μmol / 7 l.

AlGaN, which is the uppermost layer of the AlN / AlGaN / GaN / AlGaN stack, was mirror-grown to form a flat surface of AlGaN. Although the AlN / AlGaN / GaN / AlGaN laminate was a thick layer having a thickness of 6000 nm or more, no crack was generated on the flat surface. Compared with a conventional method using a selective growth mask such as SiO ₂ and performing a plurality of epitaxial growths to grow a thick layer, it is thicker without using a mask in the middle of one epitaxial growth. The layer could be grown.

  Next, a photosensitive negative polyimide resin was applied to the manufactured semiconductor substrate 400 by a spin coating method. The photosensitive polyimide other than the first semiconductor 108 was exposed. The photosensitive polyimide was developed with an alcohol-based developer to remove the photosensitive polyimide in the first semiconductor 108 portion. Curing was performed at 400 ° C. for 10 minutes in a nitrogen atmosphere to cure the polyimide resin. By repeating this series of operations a plurality of times, the step between the first semiconductor 108 and its surroundings was made ± 1 μm or less.

  A laminated metal film of Ti (thickness 20 nm) / Au (thickness 200 nm) was formed on the first semiconductor 108 by lithography and electron beam evaporation. The laminated metal film was annealed for 30 minutes in a nitrogen atmosphere at 400 ° C. to form an ohmic electrode. A metal laminated film of Ni (thickness 15 nm) / Au (thickness 200 nm) was formed by lithography and electron beam evaporation to form a gate electrode. As described above, a HEMT device was manufactured in the first semiconductor 108. The fabricated HEMT device had a source-drain spacing of 10 μm, a gate width of 30 μm, and a gate length of 2 μm.

  FIG. 11 shows drain current-drain voltage characteristics of the HEMT device formed in the first semiconductor 108. When the gate voltage was changed in the range of 0V to −5V, the drain current changed according to the gate voltage, and thus the modulation operation by the gate signal was shown. Appropriate pinch-off was also observed, and good transistor characteristics were obtained.

  The execution order of each process such as operations, procedures, steps, and stages in the apparatus, system, and method shown in the claims, the description, and the drawings is particularly “before”, “prior”, etc. It should be noted that it can be implemented in any order unless explicitly stated and the output of the previous process is used in the subsequent process. Regarding the operation flow in the claims, the description, and the drawings, even if it is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

DESCRIPTION OF SYMBOLS 100 Semiconductor substrate 102 Substrate 104 1st area | region 106 2nd area | region 108 1st semiconductor 110 2nd semiconductor 300 Semiconductor substrate 400 Semiconductor substrate 403 Groove 414 5th semiconductor 500 Semiconductor substrate 503 Groove 516 6th semiconductor 600 Semiconductor substrate 602 3rd area | region 604 Inhibitor 700 Semiconductor substrate 702 Intermediate crystal 802 Fourth region 804 Groove 806 Third semiconductor 902 Fifth region 904 Groove 906 Fourth semiconductor

Claims (14)

A substrate having a first region and a second region on the surface;
A first semiconductor formed above the first region;
A second semiconductor formed above the second region;
Including
The surface of the substrate is Si _x Ge _1-x (0 ≦ x ≦ 1);
The second region surrounds the first region, and has a different property from the first region,
The first semiconductor is a single crystal, a Group 3-5 compound semiconductor containing a nitrogen atom, and lattice-matched or pseudo-lattice-matched with the surface of the substrate;
The semiconductor substrate, wherein the second semiconductor is polycrystalline and is a group 3-5 compound semiconductor containing a nitrogen atom. The substrate further includes a third region surrounding the second region on the surface of the substrate;
Further comprising an inhibitor formed above the third region;
The semiconductor substrate according to claim 1, wherein the inhibitor inhibits crystal growth of the first semiconductor and the second semiconductor. A substrate having a first region, a second region surrounding the first region, and a fourth region surrounding the second region on the surface;
A plurality of grooves formed in the surface of the fourth region;
A first semiconductor formed above the first region;
A third semiconductor formed across the plurality of grooves;
Including
The surface of the substrate is Si _x Ge _1-x (0 ≦ x ≦ 1);
The second region is different in nature from the first region,
The first semiconductor is a single crystal, a Group 3-5 compound semiconductor containing a nitrogen atom, and lattice-matched or pseudo-lattice-matched with the Si _x Ge _1-x ,
The third semiconductor is a group 3-5 compound semiconductor containing a nitrogen atom;
A semiconductor substrate, wherein an interval between the plurality of grooves is shorter than a width of the first region. A substrate having a first region, a second region surrounding the first region, and a fifth region surrounding the second region on the surface;
A plurality of grooves formed in the surface of the fifth region;
A first semiconductor formed above the first region;
A fourth semiconductor formed across the plurality of grooves;
Including
The surface of the substrate is Si _x Ge _1-x (0 ≦ x ≦ 1);
The second region is different in nature from the first region,
The first semiconductor is a single crystal, a Group 3-5 compound semiconductor containing a nitrogen atom, and lattice-matched or pseudo-lattice-matched with the Si _x Ge _1-x ,
The fourth semiconductor is a group 3-5 compound semiconductor containing a nitrogen atom;
A semiconductor substrate, wherein a distance between the plurality of grooves is longer than a width of the first region. The semiconductor substrate according to claim 1, wherein the first region and the second region have different plane orientations. The semiconductor substrate according to any one of claims 1 to 4, wherein the first region and the second region have different surface roughness. The semiconductor substrate according to claim 1, wherein the first region and the second region have different impurity concentrations. The substrate has a groove on the surface surrounding the first region;
The semiconductor substrate according to claim 1, wherein the second region is a side wall surface of the groove. The substrate has grooves on the surface;
The first region is a bottom surface of the groove;
The semiconductor substrate according to claim 1, wherein the second region is a side wall surface of the groove. 10. The semiconductor according to claim 8, wherein the first semiconductor is formed on both the surface of the substrate other than the groove and the bottom surface of the groove, and is divided at a side wall of the groove. substrate. An intermediate crystal formed between the surface of the substrate and the first semiconductor;
The intermediate crystal composition be _{B x Al y Ga z In 1} -x-y-z N (0 ≦ x <1,0 ≦ y ≦ 1,0 ≦ z ≦ 1, and 0 <x + y + z ≦ 1) ,
The semiconductor substrate according to any one of claims 1 to 10, wherein the Si _x Ge _1-x and the intermediate crystal are pseudo-lattice matched, and the intermediate crystal and the first semiconductor are pseudo-lattice matched. The semiconductor substrate according to claim 1, wherein the first region has a substantially square planar shape, and a length of a long side of the square is 300 μm or less.   An electronic device having an element obtained by using the first semiconductor in the semiconductor substrate according to any one of claims 1 to 12 as an active region. (A) forming a first region and a second region surrounding the first region on the surface of the substrate;
(B) forming a group 3-5 compound semiconductor containing a nitrogen atom in the first region and the second region;
Including
The surface of the substrate is Si _x Ge _1-x (0 <x ≦ 1);
In the step (a), the property of the second region is different from the property of the first region,
In the step (b), the semiconductor in the first region is lattice-matched or pseudo-lattice-matched with the Si _x Ge _1-x and formed into a single crystal, and the semiconductor in the second region is formed into a polycrystal A method for manufacturing a semiconductor substrate.

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