JP2011192944A - Semiconductor device and method of operating semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make a threshold voltage of a transistor high. <P>SOLUTION: A floating electrode 110 is formed on a semiconductor layer 102 and an insulation layer is formed on the floating electrode 110. A bias electrode 134 is opposed to a part of the floating electrode 110 via the insulation layer to be capacitively coupled with the floating electrode 110 and is applied with a voltage with such a magnitude that the floating electrode 110 may not form a channel region in the semiconductor layer 102. A control electrode 132 is opposed to the other part of the floating electrode 110 via the insulation layer to be capacitively coupled with the floating electrode 110 and is applied with a control voltage to control on/off of the transistor. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for operating the semiconductor device.

  Nitride-based semiconductors such as GaN, AlGaN, and InGaN, SiC, and the like have a wider band gap than conventional semiconductors such as Si, and thus exhibit excellent characteristics as semiconductors for high-temperature, high-voltage devices. For nitride-based semiconductor (GaN-based semiconductor) materials, heterojunction field-effect transistors (HETero-junction FETs: HFETs) that use AlGaN / GaN heterojunctions, also known as HEMTs (High Electron Mobility Transistors) Is being actively developed.

  At the AlGaN / GaN heterojunction interface, positive charges are generated on the AlGaN side due to spontaneous polarization and the piezoelectric effect (piezo effect), and as a result, negative charges (electrons) accumulate on the GaN side. The accumulated electrons form a high-concentration two-dimensional electron gas without doping AlGaN, and the on-resistance of the HFET can be made much smaller than the on-resistance of an AlGaAs / GaAs HFET having no polarization.

  On the other hand, even when the gate voltage is 0 V, it cannot be turned off because a two-dimensional electron gas is formed in the channel due to spontaneous polarization and piezoelectric effect. That is, a general HFET is a normally-on type FET. In general, inverters and converters used for power control use so-called normally-off type FETs in which no current flows through the FET when 0 V is applied to the gate. In order to apply to a device, it is necessary to use a normally-off type (enhancement mode type). In order to achieve an enhancement mode type in an AlGaN / GaN HFET, as shown in Non-Patent Document 1, a method of reducing the polarization effect by thinning the AlGaN layer is disclosed.

T. Inoue et al., IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 55, No. 2, February 2008, pp. 483-488

  In a high voltage FET, a threshold voltage of 2 V or higher is desired. However, in the method of reducing the polarization effect by thinning the AlGaN layer in the AlGaN / GaN-based HFET, there is a limit in increasing the threshold value. For this reason, a high threshold voltage of, for example, 1 V or more has not been realized.

According to the present invention, a semiconductor layer;
A floating electrode formed on the semiconductor layer;
An insulating layer formed on the floating electrode;
A bias that is capacitively coupled to the floating electrode by facing a part of the floating electrode through the insulating layer and is applied with a constant voltage that does not form a channel region in the semiconductor layer. Electrodes,
A control electrode that is capacitively coupled to the floating electrode by facing the other part of the floating electrode through the insulating layer and receives a control voltage for controlling on / off of the transistor;
A semiconductor device is provided.

  According to the present invention, in order to turn on a transistor, a control voltage for controlling on / off of the transistor is input to the control electrode. A constant voltage is applied to the bias electrode so that the floating electrode does not form a channel region in the semiconductor layer. For this reason, the magnitude of the control voltage necessary for turning on the transistor can be changed by controlling the magnitude of the constant voltage input to the bias electrode. Therefore, the threshold voltage of the transistor can be increased by applying a constant voltage having an appropriate magnitude to the bias power.

According to the present invention, a semiconductor layer;
A floating electrode formed on the semiconductor layer;
An insulating layer formed on the floating electrode;
A bias electrode capacitively coupled to the floating electrode by facing a part of the floating electrode through the insulating layer;
A control electrode capacitively coupled to the floating electrode by facing the other part of the floating electrode through the insulating layer;
With
A semiconductor device is provided in which a capacitance formed between the control electrode and the floating electrode is larger than a capacitance formed between the bias electrode and the floating electrode.

According to the present invention, a semiconductor layer;
A floating electrode formed on the semiconductor layer;
An insulating layer formed on the floating electrode;
A bias electrode capacitively coupled to the floating electrode by facing a part of the floating electrode through the insulating layer;
A control electrode capacitively coupled to the floating electrode by facing the other part of the floating electrode through the insulating layer;
In a semiconductor device comprising a transistor having
The transistor is turned on / off by controlling the magnitude of the voltage applied to the control electrode while applying a constant voltage to the bias electrode such that the floating electrode does not form a channel region in the semiconductor layer. A method for operating a semiconductor device is provided.

  According to the present invention, the threshold voltage of a transistor can be increased.

1 is a plan view showing a configuration of a semiconductor device according to a first embodiment. It is AA 'sectional drawing of FIG. It is BB 'sectional drawing of FIG. It is an energy band figure for demonstrating operation | movement of HFET in embodiment. It is a figure which shows the equivalent circuit of the structure shown in FIG. It is a top view which shows the semiconductor device which concerns on 2nd Embodiment. It is AA 'sectional drawing of FIG. It is a top view which shows the modification of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  FIG. 1 is a plan view showing the configuration of the semiconductor device according to the first embodiment. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1, and FIG. 3 is a cross-sectional view taken along the line BB ′ of FIG. In addition to the configuration shown in FIGS. 1 to 3, the semiconductor device according to the present embodiment is provided with an interlayer insulating film, wiring for making electrical connection with other elements, and the like. However, illustration and description thereof are omitted. This semiconductor device has an HFET, and specifically includes semiconductor layers 100 and 102, a floating electrode 110, an insulating layer 120, a bias electrode 134, and a control electrode 132. The floating electrode 110 is formed on the semiconductor layer 102, and the insulating layer 120 is formed on the floating electrode 110. The bias electrode 134 is opposed to a part of the floating electrode 110 through the insulating layer 120, thereby capacitively coupling with the floating electrode 110, and having a size such that the floating electrode 110 does not form a channel region in the semiconductor layers 100 and 102. A voltage is applied. The control electrode 132 is opposed to the other part of the floating electrode 110 with the insulating layer 120 interposed therebetween, so that the control electrode 132 is capacitively coupled to the floating electrode 110 and receives a control voltage for controlling on / off of the transistor. That is, the control electrode 132 can be applied with a voltage large enough for the floating electrode 110 to form a channel region in the semiconductor layers 100 and 102. Details will be described below.

  The semiconductor layer 102 is an AlGaN layer, for example, and is formed on the semiconductor layer 100 made of, for example, a GaN layer. An element isolation film 101 is embedded in the semiconductor layers 100 and 102. The element isolation film 101 isolates the transistor formation region from other regions.

  A source electrode 106 and a drain electrode 104 are formed on the semiconductor layer 102 in addition to the floating electrode 110. The insulating layer 120 covers the element isolation film 101, the semiconductor layer 102, the source electrode 106, the drain electrode 104, and the floating electrode 110.

  As shown in FIG. 1, the planar shape of the transistor formation region, that is, the portion of the semiconductor layer 102 that is not covered with the element isolation film 101 is rectangular. The source electrode 106 overlaps one end of the rectangular short side, and the drain electrode 104 overlaps the other end. The control electrode 132 covers a portion of the floating electrode 110 overlapping the transistor formation region, and the bias electrode 134 covers a portion of the floating electrode 110 located on the element isolation film 101. The area of the control electrode 132 that faces the floating electrode 110 is larger than the area of the bias electrode 134 that faces the floating electrode 110. Therefore, the capacitance between the floating electrode 110 and the control electrode 132 is larger than the capacitance between the floating electrode 110 and the bias electrode 134.

  Next, the operation of the HFET of the semiconductor device shown in FIGS. 0 V is applied to the source electrode 106 and a positive voltage, for example, 600 V is applied to the drain electrode 104. When the potential of the floating electrode 110 becomes equal to or higher than a certain voltage, carriers are formed at the interface between the semiconductor layer 100 and the semiconductor layer 102, and current flows between the source electrode 106 and the drain electrode 104 (ON state). The potential of the floating electrode 110 is controlled by the voltage of the control electrode 132 and the bias electrode 134. When a zero voltage is applied to the control electrode 132 while a constant negative voltage is applied to the bias electrode 134, the HFET is turned off, and when a positive voltage is applied to the control electrode 132, the HFET is turned on. Become. In this embodiment, the voltage of the control electrode 132 in the on state is referred to as a threshold voltage.

Specifically, the potential of the floating electrode 110 includes a capacitance C ₁ between the floating electrode 110 and the control electrode 132, a capacitance C ₂ between the floating electrode 110 and the bias electrode 134, a voltage applied to the control electrode 132, and a bias It depends on the voltage applied to the electrode 134. Here, since a negative voltage is applied to the bias electrode 134, it is necessary to apply a higher voltage to the control electrode 132 in order to turn it on. That is, the threshold voltage can be increased. A threshold voltage of 2 V or higher can be obtained by setting the voltages applied to the capacitors C ₁ and C ₂ and the bias electrode 134. In addition, since the threshold voltage can be controlled by the voltage of the bias electrode 134, the influence of threshold variation in the device manufacturing process can be suppressed by this voltage.

  Note that the voltage input to the bias electrode 134 may be input from a constant voltage circuit provided inside the semiconductor device or may be input from the outside.

  Next, the effect of this embodiment will be described in detail. In a normal AlGaN / GaN-based HFET, due to spontaneous polarization and the piezoelectric effect, as shown in the energy band diagram of FIG. 4, the AlGaN layer in the gate electrode (floating electrode 110 in this embodiment) / AlGaN / GaN heterostructure A positive charge is formed on the GaN layer side, and a negative charge is formed on the gate electrode side. This amount of charge depends on the film thickness of the AlGaN layer, and the amount of charge formed increases as the film thickness increases. When the AlGaN layer becomes thicker than a certain value and the amount of charge formed in the AlGaN layer increases, a negative space charge of a two-dimensional electron gas is formed on the GaN layer side having a smaller band gap than the AlGaN layer, and on the gate electrode side. A positive charge is formed. The two-dimensional electron gas formed at the interface between the AlGaN layer and the GaN layer forms a channel, which is a depletion mode in which current flows even when the gate voltage is zero.

  In order to increase the threshold value, as described in the aforementioned Non-Patent Document 1, it is disclosed that a recess structure is formed by thinning an AlGaN layer only in a channel region. A thick AlGaN layer is formed between the gate, source electrode, and drain electrode to reduce resistance by a two-dimensional electron gas. Although depending on the Al composition, the AlGaN layer needs to be about 15 nm or less in order to be an enhancement mode type. Although the threshold voltage increases as the AlGaN layer is made thinner, in order to make the threshold voltage 1 V or more, it is necessary to make the AlGaN layer thinner to about 10 nm or less. Here, since the film thickness variation of the AlGaN layer becomes a threshold value variation, the AlGaN layer thickness needs to be formed with high accuracy. It is difficult to form a thin AlGaN layer as described above with good controllability. However, a method for forming a thin AlGaN layer only in the channel region with good controllability as described above is not disclosed.

  On the other hand, the semiconductor device according to the first embodiment does not require the channel to have a recessed structure, and the threshold voltage can be increased even if the AlGaN layer is formed thick from the source electrode to the drain electrode. . An equivalent circuit of the structure shown in FIG. 1 is shown in FIG. A positive voltage is applied to the control electrode 132 from zero, and a negative charge is formed from zero to the surface of the opposing floating electrode 110. When a negative constant voltage is applied to the bias electrode 134, a positive charge is formed on the opposing floating electrode 110. That is, since the charge in the direction that cancels the charge formed by the control electrode 132 is formed by the bias electrode 134, a higher voltage is applied to the control electrode 132 than in the case without the bias electrode 134 in order to make the channel potential the same. Must be applied. Accordingly, the threshold value is negative in the conventional structure, but in the present embodiment, the threshold value can be positive.

The above contents will be described with mathematical formulas. The potentials of the floating electrode 110, the control electrode 132, and the bias electrode 134 are V _F , V _C1 , and V _C2 , the capacitance between the floating electrode 110 and the control electrode 132 is C ₁ , and the capacitance between the floating electrode 110 and the bias electrode 134, respectively. Is C ₂ , and the capacitance between the floating electrode 110 and the semiconductor layer 100 is C ₀ , the potential of the floating electrode 110 is
V _F = (C ₁ V _C1 + C ₂ V _C2 ) / (C ₀ + C ₁ + C ₂ )
It can be expressed. By making the voltage V _C2 of the bias electrode 134 a negative voltage, the voltage V _F of the floating electrode 110 can be set to a negative voltage when the voltage V _C1 of the control electrode 132 is a positive voltage. V _F corresponds to the gate voltage of the conventional structure, and V _C1 corresponds to the gate voltage of the structure of the present embodiment. However, even if the threshold voltage is negative in the conventional structure, the threshold in the structure of the present embodiment. It can be seen that the value voltage can be made positive.

If the drain current is Id, the mutual conductance gm is
gm = ∂Id / ∂V _C1 = ∂Id / ∂V _F · ∂V _F / ∂V _C1 = ∂Id / ∂V _F · C1 / (C ₀ + C ₁ + C ₂ )
It can be expressed. When C ₁ >> C ₀ , C ₂ , it becomes ∂VF / ∂V _C1 ~ 1,
gm = ∂Id / ∂V _F
It becomes. ∂Id / ∂V _F is the mutual conductance in the conventional structure, and by making the capacitance between the floating electrode and the control electrode 132 larger than other capacitances, the mutual conductance gm can be designed to the same level as in the conventional structure. it can.

  Further, in the present embodiment, the case where charges are not accumulated in the floating electrode 110 has been described. However, a method for increasing the threshold voltage by accumulating negative charges in the floating electrode 110 can be appropriately combined. is there. As a method for accumulating negative charges, electron injection by the tunnel effect from the control electrode 132 or the bias electrode 134 can be used. Furthermore, in this embodiment, the control electrode 132 is formed on the transistor formation region. However, the control electrode 132 only needs to be capacitively coupled to the floating electrode 110. It may be placed on top.

  FIG. 6 is a plan view showing the semiconductor device according to the second embodiment. FIG. 7 is a cross-sectional view taken along the line AA ′ of FIG. In addition to the configuration shown in FIG. 6, the semiconductor device according to the present embodiment is provided with an interlayer insulating film, wiring for making electrical connection with other elements, and the like. However, illustration and description thereof are omitted. The semiconductor device according to the present embodiment has the same configuration as the semiconductor device shown in the first embodiment except for the following points.

  First, the floating electrode 110 is not the Schottky type but the MIS type, that is, the insulating film 103 is formed between the floating electrode 110 and the semiconductor layer 102. A plurality (for example, two) of control electrodes 132 are provided. A constant negative voltage is applied to the bias electrode 134, and a zero or positive voltage is applied to the control electrodes 132 and 133. This semiconductor device is designed to be turned on when a positive voltage is applied to both the control electrodes 132 and 133, and is an AND circuit having the control electrode 132 and the control electrode 133 as two inputs. Yes.

  According to this embodiment, the same effect as that of the first embodiment can be obtained. In addition, an AND circuit can be formed as described above.

  In FIG. 6, the control electrodes 132 and 133 are arranged side by side in the direction connecting the source electrode 106 and the drain electrode 104. However, as shown in FIG. May be arranged side by side in a vertical direction. As described above, the control electrodes 132 and 133 may be arranged arbitrarily as long as they are capacitively coupled to the floating electrode 110. Therefore, it may be formed in a field region on element isolation. In addition, a multi-input AND circuit can be formed by increasing the number of control electrodes 132 and 133.

  Further, in the present embodiment, the case where charges are not accumulated in the floating electrode 110 has been described. However, a method for increasing the threshold voltage by accumulating negative charges in the floating electrode 110 can be appropriately combined. is there. As a method for accumulating negative charges, electron injection by the tunnel effect from the control electrodes 132 and 133 and the bias electrode 134 can be used. Further, the gate insulating film 103 may have a stacked structure of oxide film / nitride film / oxide film, and a method of increasing the threshold voltage by accumulating negative charges in the nitride film may be appropriately combined. As a method for accumulating negative charges, electron injection from the semiconductor layer 102 by a tunnel effect or the like can be used. Furthermore, in this embodiment, the control electrodes 132 and 133 are formed on the transistor formation region. However, the control electrodes 132 and 133 need only be capacitively coupled to the floating electrode 110. You may arrange | position on the film | membrane 101. FIG.

  As mentioned above, although embodiment of this invention was described with reference to drawings, these are the illustrations of this invention, Various structures other than the above are also employable.

100 Semiconductor layer 101 Element isolation film 102 Semiconductor layer 103 Insulating film 104 Drain electrode 106 Source electrode 110 Floating electrode 120 Insulating layer 132 Control electrode 133 Control electrode 134 Bias electrode

Claims (8)

A semiconductor layer;
A floating electrode formed on the semiconductor layer;
An insulating layer formed on the floating electrode;
A bias that is capacitively coupled to the floating electrode by facing a part of the floating electrode through the insulating layer and is applied with a constant voltage that does not form a channel region in the semiconductor layer. Electrodes,
A control electrode that is capacitively coupled to the floating electrode by facing the other part of the floating electrode through the insulating layer and receives a control voltage for controlling on / off of the transistor;
A semiconductor device comprising: The semiconductor device according to claim 1,
The control electrode is a semiconductor device to which a voltage having a magnitude that allows the floating electrode to form a channel region in the semiconductor layer can be applied. The semiconductor device according to claim 1 or 2,
A semiconductor device in which a capacitance between the floating electrode and the control electrode is larger than a capacitance between the floating electrode and the bias electrode. The semiconductor device according to claim 3.
A semiconductor device in which an area of a portion of the control electrode facing the floating electrode is larger than an area of a portion of the bias electrode facing the floating electrode. In the semiconductor device according to any one of claims 1 to 4,
The floating electrode is a semiconductor device in which negative charges are accumulated. In the semiconductor device according to any one of claims 1 to 5,
A plurality of the control electrodes;
A semiconductor device in which a transistor is turned on when a control voltage for turning on the transistor is input to the plurality of control electrodes. A semiconductor layer;
A floating electrode formed on the semiconductor layer;
An insulating layer formed on the floating electrode;
A bias electrode capacitively coupled to the floating electrode by facing a part of the floating electrode through the insulating layer;
A control electrode capacitively coupled to the floating electrode by facing the other part of the floating electrode through the insulating layer;
With
A semiconductor device in which a capacitance formed between the control electrode and the floating electrode is larger than a capacitance formed between the bias electrode and the floating electrode. A semiconductor layer;
A floating electrode formed on the semiconductor layer;
An insulating layer formed on the floating electrode;
A bias electrode capacitively coupled to the floating electrode by facing a part of the floating electrode through the insulating layer;
A control electrode capacitively coupled to the floating electrode by facing the other part of the floating electrode through the insulating layer;
In a semiconductor device comprising a transistor having
On / off of the transistor is controlled by controlling the voltage applied to the control electrode while applying a voltage to the bias electrode such that the floating electrode does not form a channel region in the semiconductor layer. A method for operating a semiconductor device.

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