JP2010118495A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an element isolation structure capable of suppressing the generation of a leakage current between adjacent element regions while holding an element isolation region. <P>SOLUTION: The element isolation structure is composed of the element isolation region 41I formed on a semiconductor substrate 41 in a shallow trench isolation structure, first and second impurity diffusion regions 41N1 and 41N2 formed holding the element isolation region 41I and having a first conductivity type and a third impurity diffusion region 41PW formed under the element isolation region 41I and having a second conductivity type. The element isolation structure is further composed of a fourth impurity diffusion region 41DPW formed in a depth deeper than the depth of the third impurity diffusion region 41PW under the element isolation region 41I and containing a third impurity element of the second conductivity type and first and second impurity diffusion regions 41n1 and 41n2 formed in the depth shallower than the depth of the fourth impurity diffusion region DPW in the first and second impurity diffusion regions 41N1 and 41N2 and containing the third impurity element in addition to the first impurity element. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having an element isolation region and a method for manufacturing the same.

  In today's fine semiconductor devices, a large number of semiconductor elements such as transistors are electrically isolated from each other by an element isolation region and formed on a common semiconductor substrate.

For example, a p-channel MOS transistor is formed in an n-type well defined by an element isolation region in a silicon substrate, and an n-channel MOS transistor is formed in a p-well defined in the same silicon substrate by an element isolation region. Often. In today's fine semiconductor devices, such an element isolation region is generally formed in a so-called STI (shallow trench isolation) structure in which an element isolation trench is filled with an element isolation insulating film. By adopting the STI structure, the area occupied by the element isolation region on the semiconductor substrate can be reduced as compared with the element isolation region formed by the conventional LOCOS method.
JP 2004-235475 A JP 2004-64085 A JP 2006-310576 A

  In a conventional semiconductor device having such an STI structure, a pair of n-type wells are adjacent to each other through a p-type well therebetween, for example, a structure as shown in FIG. 1 is often formed in a silicon substrate. is there.

Referring to FIG. 1, the device isolation region 11I STI-type in the silicon substrate 11, a first n-type well 11N ₁ and second n-type well 11N ₂ is defined, also the n-type between the well 11N ₁ and n-type well 11N ₂ is, p-type well 11P is also being defined by a device isolation region 11I, intervening in a state of being in contact with the n-type well 11N ₁ and n-type well 11N ₂ is doing.

In this structure, the leakage current between said n-type well 11N ₁ and n-type well 11N ₂ is p-type well 11P is suppressed to interposed between each transistor is miniaturized, When the size of the n-type well 11N ₁ , 11N ₂ or p-type well 11P becomes 1 μm or less, for example, from the n-type well 11N ₁ to the n-type well 11N ₂ or vice versa, the p-type well 11P In some cases, a leak current flows along a deep current path.

Therefore, in Patent Document 1, in order to cut off the leakage current along such a deep current path, as shown in FIG. 1, below the wells 11N ₁ , 11P and 11N _{2 in} the silicon substrate 11, as shown in FIG. Alternatively, as shown in FIG. 2, it has been proposed to form a p-type deep well 11DPW at least below the p-type well 11P. However, in FIG. 1 and FIG. 2, the same reference numerals are given to the parts described above in FIG. Further, in FIG. 1, illustration of p-channel MOS transistors formed in the n-type wells 11N1 and 11N2 or n-channel MOS transistors formed in the p-type well 11P is omitted.

On the other hand, in a miniaturized semiconductor device today, 3A, as shown in FIG. 3B, the first n-type well 21N ₁ and a plurality of n-type comprising a second n-type well 21N ₂ in the silicon substrate 21 A structure in which wells are arranged separated by an STI type element isolation region 21I may be used. However, FIG. 3B is an enlarged cross-sectional view showing a portion surrounded by a broken line in FIG. 3A.

  In such a structure, in order to cut off a leakage current path that passes under the element isolation region 21I, it becomes an acceptor via the element isolation insulating film constituting the STI structure under the element isolation region 21I. An impurity element (hereinafter referred to as a p-type impurity element) is introduced by ion implantation to form a p-type channel stopper region 21PW.

  However, since such p-type channel stopper region 21PW is implanted with acceptor ions through the element isolation insulating film which is an amorphous phase, introduced acceptor ions, specifically boron ions (B +). Loses a lot of energy when passing through the element isolation insulating film, and as a result, the depth of the channel stopper region 21PW formed under the element isolation region 21I is inevitably reduced. .

  FIG. 3C is a diagram showing the depth distribution of the impurity element introduced into the silicon substrate by ion implantation.

Referring to FIG. 3C, the vertical axis represents the concentration of the introduced impurity element, and the horizontal axis represents the penetration depth in microns. In FIG. 3C, the curve indicated by “A” indicates the boron (B) depth distribution in the p-type channel stopper region 21PW formed immediately below the STI structure 21I, and the curve indicated by “B” indicates the silicon substrate. It shows the depth distribution that occurs when boron ions are implanted directly under the same conditions. The curve indicated by “C” indicates the depth distribution of phosphorus (P) implanted into the silicon substrate, and hence the depth distribution of phosphorus in the n-type wells 21N ₁ and 21N ₂ .

As can be seen from curve “B” or curve “C” in FIG. 3C, when ions are directly implanted into a silicon substrate having a crystal structure, boron ions and phosphorus ions are about 1 μm or more from the surface as a result of so-called channeling. It can be seen that the concentration is distributed up to a depth of 1 mm, whereas when implanted through the STI-type element isolation region 21I, the concentration rapidly decreases after a depth of about 0.5 μm. That is, the depth of the lower end portion of the p-type channel stopper region 21PW is located at a position that is substantially shallower than the lower end portions of the n-type wells 21N ₁ and 21N ₂ .

As a result, in the semiconductor device having the well having the structure shown in FIGS. 3A and 3B, as indicated by an arrow in FIG. 3B, the n-type wells 21N ₁ and 21N ₂ are located under the p-type channel stopper region 21PW. This causes a problem that leakage current is likely to occur.

  In order to solve this problem, the acceptor concentration in the portion of the silicon substrate 21 below the p-type channel stopper region 21PW may be increased to cut off the leakage current path. For this reason, the configuration of FIG. From this analogy, it can be considered that a p-type deep well 21DPW is formed in the silicon substrate 21 below the p-type channel stopper region 21PW as shown in FIG.

However, such a deep p-type well 21DPW is also formed below the n-type wells 21N ₁ and 21N ₂ where the impurity concentration is decreased. As a result, as shown in FIGS. 5 (A) and 5 (B). Thus, regions 21p ₁ and 21p ₂ that have changed to p-type corresponding to the deep p-type well 21DPW appear below the n-type wells 21N ₁ and 21N ₂ , and are indicated by broken lines in FIG. wherein among the n-type well _21N 1, _{21N 2,} problems such p-type region _21p 1, deeper than 21p ₂ will be isolated in a n-type island _21n 1, 21n ₂ occurs. 5A shows the concentration distribution of the acceptor in the cross section of FIG. 4, and FIG. 5B shows the depth of phosphorus in the n-type well 21N ₁ or 21N ₂ , that is, donor and boron, that is, the depth of acceptor. The density distribution along the line AA ′ in FIG. 4 in the vertical direction is shown. 5 from (B), the slightly shallower than the lower end portion of the n-type well 21N ₁ or 21N _2, the concentration of boron exceeds the concentration of phosphorus in the portion surrounded by a broken line in FIG. 4, the conductivity type changes to the p-type I can see that In FIG. 5A, “NW” corresponds to the n-type wells 21N1, 21N2, “PW” corresponds to the p-type channel stopper region 21PW, and “DPW” corresponds to the deep p-type well 21DPW. .

  Such an n-type island forms a pn junction at the interface with the adjacent deep p-type well 21DPW, and further at the interface with the p-type region of the silicon substrate, which is generally doped p-type. In addition, the charge trapped in the pn junction causes unstable operation of the semiconductor device.

Further, in the configuration of FIG. 4 as described above, the depth of the n-type wells 21N ₁ and 21N ₂ is reduced from the initial depth due to the formation of the deep p-type well 21DPW. As a result, the sheet resistance is reduced. When the CMOS element is formed on such a substrate that increases, a latch-up problem also occurs.

  According to one aspect, a semiconductor device is formed with a semiconductor substrate, an element isolation region formed in the semiconductor substrate, and the semiconductor substrate sandwiching the element isolation region, and having a first conductivity type first. First and second impurity diffusion regions having the first conductivity type, and the first conductivity type opposite to the first conductivity type formed below the element isolation region in the semiconductor substrate. A third impurity diffusion region containing the second impurity element of the second conductivity type and having the second conductivity type; and formed in the semiconductor substrate under the third impurity diffusion region, A fourth impurity diffusion region containing a third impurity element of conductivity type, and the first and second impurity diffusion regions are formed to be shallower than a depth of the fourth impurity diffusion region; A first and a third impurity element in addition to the element; And having a second impurity diffusion region portion.

  According to another aspect, a method for manufacturing a semiconductor device includes a step of forming a groove on a semiconductor substrate, and introducing a first impurity element of a first conductivity type over the entire surface of the semiconductor substrate on which the groove is formed. And forming a first impurity diffusion region including the first impurity element and having the first conductivity type at a position deeper than the groove below the groove, and at the same time, in the semiconductor substrate, The first and second impurity diffusion region portions containing the first impurity element are shallower than the first impurity diffusion region on the first side and the second side opposite to the first side. Forming at a position; embedding an insulating film in the groove to form the element isolation region; forming a first mask pattern exposing the element isolation region on the semiconductor substrate; First mask pattern forming step Then, using the first mask pattern as a mask, a second impurity element of the first conductivity type is introduced into the semiconductor substrate by an ion implantation method, and includes the second impurity element and includes the first conductivity type. After the step of forming a second impurity diffusion region having, a step of forming a second mask pattern covering the element isolation region on the semiconductor substrate, and a step of forming the second mask pattern. Using the mask pattern of 2 as a mask, a third impurity element having a second conductivity type opposite to the first conductivity type is introduced into the semiconductor substrate by an ion implantation method, and the element isolation region is formed in the semiconductor substrate. The first and second impurity diffusion regions containing the third impurity element and having the second conductivity type on the first side and the second side are referred to as the first impurity diffusion region, respectively. Part and second failure And having a step of forming superimposed on objects diffusion region portion.

  According to another aspect, a method for manufacturing a semiconductor device includes: forming a resist pattern having an opening corresponding to an element isolation region on a semiconductor substrate; and forming the resist pattern after the resist pattern forming step. A first impurity element of a first conductivity type is introduced to the entire surface of the semiconductor substrate through the resist pattern, and the first conductivity type includes the first impurity element below the opening. A first impurity diffusion region having the first impurity element on the first side of the trench and the second side opposite to the first side in the semiconductor substrate. Forming the first and second impurity diffusion regions at a position shallower than the first impurity diffusion region, forming a groove corresponding to the opening in the semiconductor substrate, and forming the groove in the groove Insulation film And after the step of forming the element isolation region, the step of forming a first mask pattern exposing the element isolation region on the semiconductor substrate, and the step of forming the first mask pattern, Using the first mask pattern as a mask, a second impurity element of the first conductivity type is introduced into the semiconductor substrate by an ion implantation method, and includes the second impurity element and the first conductivity type. The second mask pattern after the step of forming the second impurity diffusion region, the step of forming the second mask pattern covering the element isolation region on the semiconductor substrate, and the step of forming the second mask pattern. As a mask, a third impurity element of the second conductivity type opposite to the first conductivity type is introduced into the semiconductor substrate by ion implantation, and the first side of the element isolation region in the semiconductor substrate is introduced. , And forming a third impurity diffusion region containing the third impurity element and having the second conductivity type on the second side opposite to the first side. It is characterized by.

  According to the present invention, the occurrence of a leakage current between a pair of diffusion regions of one conductivity type adjacent to each other with the element isolation region interposed therebetween can be caused in a shallow current path immediately below the element isolation region and also between the pair of diffusion regions. It is possible to effectively suppress a deep current path connecting the lower end portions and a current path having a depth intermediate between the shallow region and the deep region.

[First Embodiment]
6A and 6B are cross-sectional views illustrating the configuration of the semiconductor device according to the first embodiment. However, FIG. 6B is an enlarged cross-sectional view of a portion surrounded by a broken line in FIG. 6A.

Referring to FIG 6A, during p- type silicon substrate 41, n-type well including a first n-type well 41N ₁ the second n-type well 41N _2, that is, n-type diffusion region 41N, STI As shown in the enlarged view of FIG. 6B, a channel stopper region 41PW made of a p-type diffusion region is formed immediately below the device isolation region 41I. .

Further, in the structure of FIG. 6B, a deep region formed by another p-type diffusion region in the vicinity of the lower ends of the n-type wells 41N ₁ and 41N2 below the p-type channel stopper region 41PW when viewed from the surface of the silicon substrate 41. A p-type well 41DPW is formed so that the lower end thereof substantially coincides with the lower ends of the n-type wells 41N ₁ and 41N ₂ , and the n-type wells 41N1 and 41N2 are seen from the surface of the silicon substrate 41. As a result, by implanting acceptor ions such as boron ions into the intermediate depth between the p-type channel stopper region 41PW and the deep p-type well 41DPW, the n − -type regions 41n ₁ and 41n ₂ having reduced electron concentration are formed. Is formed.

FIG. 7A shows the concentration distribution of B in the cross-sectional structure of FIG. 6B. FIG. 7B shows the boron concentration along the lines BB ′ and CC ′ in FIG. The distribution profile extracted by the phosphorus simulation is shown.

Referring to FIG. 7A, boron ions are ion-implanted so that a concentration peak appears in the p-type channel stopper region 41PW and a deep p-well 41DPW below the p-type channel stopper region 41PW, and the n − -type region 41n. ₁ and 41n ₂ are also ion-implanted so that a peak appears.

  Referring to FIG. 7B, when viewed in the BB ′ cross section, the boron concentration peak is vertically separated in the p-type channel stopper region 41PW and the deep p-type well 41DPW immediately below the element isolation region 41I. You can see that it has appeared.

On the other hand, from FIG. 7B, when viewed in the CC ′ cross section, a phosphorus concentration peak occurs at a depth substantially coincident with the depth of the p-type channel stopper region 41PW. Although it decreases as the depth from the surface of the silicon substrate 41 increases, it can be seen that peaks of boron concentration occur corresponding to the n − -type regions 41n ₁ and 41n ₂ in FIG. 6B. However, in the n − -type regions 41n ₁ and 41n ₂ , the boron concentration does not exceed the phosphorus concentration, and the n-type wells 41N ₁ and 41N ₂ maintain the n-type throughout the entire depth direction. is doing.

7B, the portions of the n-type wells 41N ₁ and 41N ₂ that are in contact with the upper ends of the n − -type regions 41n ₁ and 41n ₂ are located at the positions indicated by the line I in FIG. 7B. While having an electron concentration of 1.5 × 10 ¹⁷ cm ⁻³ to 4.0 × 10 ¹⁷ cm ⁻³ , typically about 2.5 × 10 ¹⁷ cm ⁻³ , the n -In the portions in the mold regions 41n ₁ and 41n ₂ are smaller, 2.0 × 10 ¹⁶ cm ⁻³ to 6.0 × 10 ¹⁶ cm ⁻³ , typically 4.5 × 10 ¹⁶ cm ^−3. It can be seen that the electron concentration is realized.

  FIG. 8 is a diagram showing the horizontal distribution of boron and phosphorus along line D-D ′ in FIG. 7A.

Referring to FIG. 8, conventionally, boron has not been introduced into the n − -type regions 41n ₁ and 41n ₂ , so the concentration distribution of boron in the horizontal direction is from the portion immediately below the element isolation region 41I. In contrast to the sudden decrease when it is removed (“Prior Art” in the figure), in this embodiment, even if the element is separated from the portion immediately below the element isolation region 41I in the horizontal direction, a relatively high concentration of boron is maintained. I understand that

6A and 6B, the phosphorus distribution along the line DD ′ is the same as the conventional one. 6A and 6B, the electron concentration expressed as the difference between the donor concentration and the acceptor concentration is higher in the n − -type regions 41n ₁ and 41n ₂ than in the prior art. As a result, the resistance values in the n − -type regions 41n ₁ and 41n ₂ are increased as compared with the prior art.

As a result, as schematically shown in FIG. 9, the leakage current between the n-type wells 41N ₁ and 41N ₂ along the current path A immediately below the element isolation region 41I is blocked by the p-type channel stopper region 41PW. Further, the leakage current flowing between the lower ends of the n wells 41N ₁ and 41N ₂ along the deep current path B is blocked by the deep p-type well 41DPW, and further along the current path C at an intermediate depth. The flowing leakage current is suppressed by the increase in resistance of the n − -type regions 41n ₁ and 41n ₂ .

In such a configuration, the lower ends of the n-type wells 41N ₁ and 41N ₂ do not form an isolated island, so that the problem that the operation of the semiconductor device becomes unstable due to the trapped charges does not occur. Further, since the n-type wells 41N ₁ and 41N ₂ maintain the n-type up to the lower end portions thereof, there is no problem that the sheet resistance increases.

  10A to 10F are views showing a method of forming the structure shown in FIGS. 6 (A) and 6 (B).

Referring to FIG. 10A, a SiN polishing stopper film 41 sn having a thickness of 112 nm is formed on the surface of the silicon substrate 41 via a pad oxide film 41 ox made of a thermal oxide film having a thickness of 10 nm. on SiN polishing stopper film 41Sn, wherein in the silicon substrate 41 surface, the resist film R ₁ having an opening R1A exposing a formation region of the isolation region 41I is formed.

Then the resist pattern the SiN polishing stopper film _{R 1} as a mask 41sn and the pad oxide film 41ox thereunder in the step of FIG. 10B is patterned, the SiN polishing stopper film 41sn and the pad oxide film 41ox thereunder, Corresponding to the resist opening R1A, an opening 41SNO is formed to expose a region where the element isolation region 41I is to be formed in the surface of the silicon substrate 41.

  Further, in the step of FIG. 10C, the silicon substrate 41 is dry-etched to a depth of 280 nm, for example, with a width of 0.4 μm by the RIE method using the SiN polishing stopper film 41 sn as a mask, and the openings are formed in the silicon substrate 41. An element isolation trench 41T is formed corresponding to 41SNO.

Next, in the step of FIG. 10D, the boron concentration peak is below the element isolation trench 41T, for example, at a depth of 1.1 to 1.4 μm from the surface of the silicon substrate 41 through the SiN film 41sn and the pad oxide film 41ox. So that boron is ion-implanted into the entire surface of the silicon substrate 41 under an acceleration voltage of 250 keV, for example, at a dose of 2 × 10 ¹² cm ⁻² and a tilt angle of 0 °, the p-type deep well 41DPW is formed. Form. In this case, the peak concentration of boron in the p-type deep well 41DPW is, for example, about 3.3 × 10 ¹⁶ cm ⁻³ .

At the same time, by the process of FIG. 10D, boron is also introduced into the formation regions of the n-type wells 41NW ₁ and 41NW ₂ on both sides of the element isolation region 41I. As a result, the concentration peak of the p-type deep well 41DPW Boron introduction regions 41B ₁ and 41B ₂ having a peak concentration of, for example, 4.5 × 10 ¹⁶ cm ⁻³ at a depth of 0.4 μm, for example, from the surface of the silicon substrate 41, which is shallower than the depth at which n appears, Formed corresponding to the mold regions 41n ₁ and 41n ₂ .

  Next, in the step of FIG. 10E, the element isolation trench 41T is filled with a silicon oxide film, and an extra silicon oxide film on the silicon substrate 41 is further subjected to chemical mechanical polishing (CMP) using the SiN polishing stopper film 41sn as a stopper. Then, the SiN polishing stopper film 41 sn and the pad oxide film 41 ox therebelow are removed. As a result, an element isolation region 41I having a shallow trench isolation structure in which the element isolation trench 41T is filled with an element isolation oxide film is formed. In the structure of FIG. 10E, the element isolation oxide film filling the element isolation trench 41T slightly protrudes above the silicon substrate 41, but the protrusion is not shown in FIG. 10E.

Next, in the step of FIG. 10F, the resist film R ₂ having the resist opening R _2A exposing the device isolation region 41I is formed on the silicon substrate 41, the boron the resist film R ₂ as a mask, the element For example, under an acceleration voltage of 150 keV, a dose of 3 × 10 ¹³ cm ⁻² and a tilt so that a boron concentration peak appears at a depth of about 0.5 μm from the surface of the silicon substrate 41 immediately below the isolation region 41I. By ion implantation at an angle of 0 °, the p-type channel stopper region 41PW is formed immediately below the element isolation region 41I. In this case, the peak concentration of boron in the p-type channel stopper region 41PW is, for example, about 1.5 × 10 ¹⁸ cm ⁻³ .

Furthermore after the Figure 10F step, protected by the resist pattern _{R 3} the device isolation region 41I in the step of FIG. 10G, under the acceleration voltage of the phosphorous ions example 360 keV, a dose amount of 3 × 10 ¹³ cm ^-2, tilt angle By implanting ions at 0 °, both sides of the element isolation region 41I in the silicon substrate 41 are doped n-type, and accordingly, the boron introduction regions 41B ₁ and 41B ₂ are n-type conductivity type. To change. In this case, the phosphorus concentration peak in the n-type wells 41NW1 and 41NW2 appears at a depth of 0.5 μm from the surface of the silicon substrate 41, and the peak concentration of phosphorus at that time is 6 × 10 ¹⁷ cm ^−3. It will be about.

FIG. 11 is a diagram showing a leakage current generated between the n-type wells 41NW ₁ and 41NW ₂ in the structure of FIGS. 6A and 6B formed as described above.

In FIG. 11, the curve indicated by “technology of the present embodiment” indicates that the potential of the silicon substrate 41 is maintained at 0V in the structure of FIGS. 6A and 6B, and 0 V is applied to the n-type well 41 NW ₁ . the voltage is applied, when a voltage applied to the n-type well 41NW ₂ was varied in the range of 0 to 10V, showing the leakage current between the n-type well 41NW ₁ and n-type well 41NW ₂ . However, the leak current is for the case where a p-type silicon substrate having a specific resistance of 10 Ωcm is used as the silicon substrate 41. In the experiment of FIG. 11, the width of the element isolation trench 41T is 0.4 μm at the bottom and 0.68 μm at the top.

FIG. 11 shows, as another comparative example, a leakage current measurement result (“Comparative Example 1”) for a structure in which the p-type deep well 21DPW is formed in the silicon substrate 21 described above with reference to FIG. As shown in FIG. 12, the measurement result of leak current (“Comparative Example 2”) is shown for the structure in which the formation of the p-type deep well 21DPW is limited to just below the element isolation region 21I in the configuration of FIG. Yes. In Comparative Example 1, however, boron ions are implanted into the silicon substrate 21 under an acceleration voltage of 500 keV at a dose of 2 × 10 ¹² cm ⁻² and a tilt angle of 0 °, and the p-type deep well 21DPW is formed. Forming. In Comparative Example 2, after the formation of the element isolation groove in the element isolation region 21I, boron ions are applied only to the portion immediately below the element isolation groove under an acceleration voltage of 250 keV and a dose amount of 2 × 10 ¹² cm ⁻² . The ions are implanted at a tilt angle of 0 °.

Other conditions are common to the “technology of the present embodiment”, “Comparative Example 1”, and “Comparative Example 2”. For example, a p-type silicon substrate having a specific resistance of 10Ω is used as the silicon substrates 21 and 41. In the element isolation region 21I or 41I, an element isolation groove is formed to a depth of 280 nm, and a p-type channel stopper region is formed. 21PW or 41PW is formed by implanting boron ions with an acceleration voltage of 150 keV and a dose of 3 × 10 ¹³ cm ⁻² at a tilt angle of 0 °, and n-type wells 21NW ₁ , 21NW ₂ , and n The mold wells 41NW ₁ and 41NW ₂ are formed by implanting phosphorus ions at an acceleration voltage of 360 keV or a dose of 3 × 10 ¹³ cm ⁻² and a tilt angle of 0 °. Also, other process conditions such as heat treatment are the same.

Referring to FIG. 11, according to the “present embodiment technique”, when the applied voltage to the n-type well 21 NW ₂ or 41 NW ₂ is at least in the range of 0.00 V to 3.50 V, the “prior art 1”, “ It can be seen that the leakage current can be reduced more than any of the “prior art 2”.

  13A and 13B show a modification of the present embodiment.

In this modified example, as shown in FIG. 13A, after forming the element isolation trench 41T in the silicon substrate 41 corresponding to the step of FIG. 10C, the SiN film 41sn is removed as shown in FIG. 13B. Then, boron ions are ion-implanted only through the pad oxide film 41ox to form the other deep well 41DPW and boron introduction regions 41B ₁ and 41B ₂ for the p-type. The subsequent steps are the same as those in the embodiment of FIGS. 10E to 10G. In this modification, the boron introduction regions 41B ₁ and 41B ₂ are formed slightly deeper than in the process of FIG. 10D because the SiN film 41sn does not exist, and the boron concentration peak is from the surface of the silicon substrate 41. It is formed to a depth of about 0.7 μm.

Returning to FIG. 10G again, the n-type wells 41N ₁ and 41N ₂ formed in this way constitute an element region of a p-channel MOS transistor formed on the silicon substrate 41.

Therefore, after the step of FIG. 10G, as shown in FIG. 10H, arsenic ions are applied to the surfaces of the n-type wells 41N ₁ and 41N ₂ under an acceleration voltage of 60 keV and a dose amount of 2 × 10 ¹³ cm ⁻² and a tilt angle of 7 ° in ions are implanted to form the n-type well _41N 1, the surface of 41N ₂ doped channel region 41CH _1, 41CH ₂ respectively. In this case, for example, as shown in FIG. 14, an arsenic concentration peak appears at a depth of about 30 nm from the surface of the n-type wells 41N ₁ and 41N ₂ at a peak concentration of 4.3 × 10 ¹⁸ cm ^−3. . However, the present invention is not limited to such a specific arsenic concentration distribution.

  Further, in the step of FIG. 10H, although not shown, the entire silicon substrate 41 is rapidly heat-treated (RTA) for 10 seconds at a temperature of 1000 ° C. to activate the impurity element introduced into the silicon substrate 41.

Further, as shown in FIG. 10I, a dielectric film 42 serving as a gate insulating film is formed on the surface of the n-type wells 41N ₁ and 41N ₂ by thermal oxidation or plasma oxidation to a thickness of 1.6 nm, for example. A polysilicon film 43 serving as a gate electrode is deposited on the dielectric film 42 by a CVD method at 600 ° C. to a film thickness of, for example, 105 nm.

Furthermore patterned by the polysilicon film 43 using the resist process, the n-type well 41NW polysilicon gate electrode 43G ₁ on the surface of the _1, and simultaneously the n-type well 41NW ₂ surface as shown in FIG. 10J , polysilicon gate electrode 43G ₂ are formed through the dielectric film 42.

Further, in the step of FIG. 10J, the entire silicon substrate 41 is rapidly heat-treated at a temperature of 950 ° C. for 5 seconds, and then arsenic is used in the n-type wells 41NW1 and 41NW2 using the polysilicon gate electrodes 43G ₁ and 43G ₂ as a mask. Ions are pocket-implanted under an acceleration voltage of 60 keV at a dose of 5 × 10 ¹² cm ⁻² and a tilt angle of 28 °, and in the n-type well 41N ₁ , the n-type pocket implantation region 41pk ₁ is formed as the gate electrode 413G. ₁ and on the n-type well 41N ₂ , n-type pocket implantation regions 41pk ₂ are formed on both sides of the gate electrode 413G ₂ .

Further, a silicon oxide film is formed on the structure of FIG. 10J so as to cover the polysilicon gate electrodes 43G ₁ and 43G ₂ by a plasma CVD method at a substrate temperature of 520 °, for example, to a thickness of 15 nm. etched back in a direction substantially perpendicular to the plane, as shown in FIG. 10K, the both sides walls of the gate electrodes 43G _1, the film thickness is thin sidewall oxide films 43 w ₁ of approximately 12 nm, also both sidewall surfaces of the gate electrode 43G ₂ the film thickness to form a sidewall oxide film 43 w ₂ thin about 12 nm.

Further, in the step of FIG. 10K, boron ions are used in the silicon substrate 41 with an acceleration voltage of 0.6 keV, for example, 3 × 10 4 using the gate electrodes 43G ₁ and 43G ₂ and the sidewall oxide films 43w ₁ and 43w ₂ as a mask. dose of ¹⁴ cm ^-2, and ion implantation with a tilt angle of 0 °, in the n-type well 41N _1, the outer sides of the sidewall insulating film 43 w ₁ with respect to the channel region right underneath the gate electrode 43G _1, p-type A source extension region 41a and a drain extension region 41b are formed. Similarly, in the n-type well 41N _2, outer sides of the sidewall insulating film 43 w ₂ with respect to the channel region right underneath the gate electrode 43G _2, p-type source extension region 41c and a drain extension region 41d are respectively formed .

Further, in the step of FIG. 10L, the silicon oxide film is formed by a plasma CVD method at 520 ° so as to cover the polysilicon gate electrodes 43G ₁ and 43G ₂ via the side wall oxide films 43w ₁ and 43w ₂ on the structure of FIG. after forming at the substrate temperature for example to a thickness of 70nm, and which is etched back in a direction substantially perpendicular to the substrate surface, as shown in FIG. 10L, to respective sidewalls of the gate electrode 43G _1, wherein the side wall oxide film 43w a thick sidewall oxide films 43W ₁ film thickness of approximately 68nm through _1, also on both sidewall surfaces of the gate electrode 43G _2, film thickness to form a sidewall oxide film 43W ₂ thick about 68nm.

Further, in the step of FIG. 10L, boron ions are first masked with an acceleration voltage of 8 keV, a dose of 1 × 10 ¹³ cm ⁻² , and tilt using the gate electrodes 43G ₁ and 43G ₂ and the sidewall oxide films 43W ₁ and 43W ₂ as a mask. angle 0 is ion-implanted in °, further under the acceleration voltage of 4 keV, the dose amount of 6 × 10 ¹⁵ cm ^-2, and ion implantation with a tilt angle of 0 °, right underneath the gate electrode 43G ₁ in the n-type well 41N ₁ outside the viewed from the channel region sidewall oxide films 41W _1, the p-type source region 41e and the drain region 41f, are formed respectively. Similarly, in the n-type well 41N ₂ on the outside of the sidewall oxide films 41W ₂ as viewed from the channel region right underneath the gate electrode 43G _2, a p-type source region 41g and the drain region 41h, are formed respectively.

  Further, in the step of FIG. 10L, after the ion implantation step, the silicon substrate 41 is rapidly heat-treated at a temperature of 1025 ° C. for 1 second, thereby activating the introduced boron.

  Next, in the step of FIG. 10M, for example, a cobalt silicide film 44 is formed on the surfaces of the gate electrodes 43G1 and 43G2, the source region 41e and the drain region 41f, and the source region 41g and the drain region 41h by the salicide method. In the process of 10N, the SiN film 45 is formed as a contact stopper on the structure of FIG. 10M by a plasma CVD method to a film thickness of about 80 nm, for example, at a temperature of 600 ° C. Further, in the process of FIG. 10O, the structure of FIG. An insulating film 46 having a structure in which an undoped silica glass film and a TEOS oxide film are stacked is formed on the insulating film 46, and an opening exposing the source region 41 e, drain region 41 f, source region 41 g and drain region 41 h is formed in the insulating film 46. The part is formed in each opening. Abbreviated Although Ti / tungsten plug 46A~46D via an adhesion layer of TiN multilayer structure is formed by each of the silicide layers 44 and the contact.

  In the semiconductor device having such a configuration, as described above with reference to FIG. 11, even if a potential difference is generated between the n-type wells 41N1 and 41N2 which are element regions of the respective p-channel MOS transistors during the operation of the semiconductor device, Generation of leakage current is effectively suppressed.

  In the above description, the width of the element isolation region 41I is 0.4 μm. However, the present invention is effective even when the width of the element isolation region 41I is further reduced to reach 0.3 μm.

In the present embodiment, the example in which phosphorus is used as the donor impurity element in the n-type wells 41N ₁ and 41N ₂ has been described, but arsenic (As) or antimony (Sb) can be used instead of phosphorus. In this embodiment, the p-type and n-type can be inverted.

[Second Embodiment]
FIG. 15A to FIG. 15E are views showing a method for manufacturing a semiconductor device according to the second embodiment. However, in the figure, the same reference numerals are assigned to portions corresponding to the portions described above, and description thereof is omitted.

Referring to FIG. 15A, in this embodiment, a resist film R1 having an opening R1A corresponding to the element isolation region 41I to be formed is formed on the silicon substrate 41. In the step of FIG. 15B, the resist film R1 As a mask, boron ions are introduced into the silicon substrate 41 by ion implantation. In one example, the boron ion implantation is performed under an acceleration voltage of 500 keV with a dose of 2 × 10 ¹² cm ⁻² and a tilt angle of 0 °. As a result, in the element isolation region 41I where the resist film R1 is not present. Boron ions penetrate deeply in the region to be formed and, for example, a boron concentration peak occurs at a depth of 1.1 to 1.4 μm from the surface of the silicon substrate 41 at a concentration of about 2.8 × 10 ¹⁶ cm ^−3. The p-type deep well 41DPW is formed.

In contrast, the boron ions that have passed through the resist film R1 lose their energy when passing through the resist film R1, and as a result, the peak of the boron concentration is at a depth of about 0.7 μm from the surface of the silicon substrate 41. Appear at a concentration of about 3.5 × 10 ¹⁶ cm ⁻³ . Thereby, boron introduction regions 41B ₁ and 41B ₂ are formed under the resist film R1 at a position shallower than the p-type deep well 41DPW, as shown in FIG. 15B.

  Next, in the step of FIG. 15C, the resist film R1 is removed, and further, a pad oxide film 41ox and a SiN polishing stopper film 41sn are formed on the surface of the silicon substrate 41 by thermal oxidation and CVD, and further the SiN polishing stopper film Similar to the resist film R1, a resist film R1 ′ having an opening R1A ′ that exposes a region where the element isolation region 41I is to be formed is formed on 41sn.

  Further, in the step of FIG. 15D, the SiN film 41sn is patterned using the resist film R1 ′ as a mask, and the silicon substrate 41 is dry-etched by the RIE method using the SiN film 41sn as a mask, thereby forming the element isolation region 41I. An element isolation trench 41T is formed in the planned formation region.

  Further, in the step of FIG. 15E, the resist film R1 'is removed and the element isolation trench 41T is filled with a silicon oxide film, thereby forming an element isolation region 41I.

  Thereafter, by performing the steps of FIGS. 10G to 10O, a semiconductor device in which a desired leakage current is suppressed can be obtained.

As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.
(Appendix 1)
A semiconductor substrate;
An element isolation region formed in the semiconductor substrate;
First and second impurity diffusion regions formed in the semiconductor substrate with the element isolation region interposed therebetween and including the first impurity element of the first conductivity type and having the first conductivity type;
A third impurity having a second conductivity type, which is formed under the element isolation region in the semiconductor substrate and includes a second impurity element of a second conductivity type opposite to the first conductivity type; A diffusion region;
A fourth impurity diffusion region formed under the third impurity diffusion region in the semiconductor substrate and containing a third impurity element of the second conductivity type;
First and second impurities that are formed shallower than the fourth impurity diffusion region in the first and second impurity diffusion regions and include the third impurity element in addition to the first impurity element. A diffusion region portion;
A semiconductor device comprising:
(Appendix 2)
The semiconductor device according to appendix 1, wherein the first and second impurity diffusion region portions are formed deeper than the third impurity diffusion region.
(Appendix 3)
The first impurity diffusion region includes the first impurity diffusion region portion and has the first conductivity type, and the second impurity diffusion region includes the second impurity diffusion region portion, The semiconductor device according to appendix 1 or 2, wherein the semiconductor device has the first conductivity type.
(Appendix 4)
In the first and second impurity diffusion regions, the concentration of the first impurity element is higher than the concentration of the second impurity element across the entire depth direction from the surface of the silicon substrate. The semiconductor device according to any one of appendices 1 to 3.
(Appendix 5)
5. The semiconductor device according to claim 1, wherein the first and second impurity diffusion region portions are formed shallower than the fourth impurity diffusion region.
(Appendix 6)
First and second active elements are respectively formed in the first and second impurity diffusion regions, and the first and second impurity diffusion regions differ from each other during the operation of the semiconductor device. The semiconductor device according to claim 1, wherein a potential is applied.
(Appendix 7)
The first and second impurity diffusion regions are 2.0 × 10 ¹⁶ cm ^{−3 to} 5.5 × 10 ¹⁷ cm ⁻³ in the portions in contact with the first and second impurity diffusion regions, respectively. 1 in the first and second impurity diffusion region portions, the first carrier density is 1.5 × 10 ¹⁵ cm ^{−3 to} 4.5 × 10 ¹⁶ cm ^−3. The semiconductor device according to claim 1, wherein the semiconductor device has a low second carrier density.
(Appendix 8)
8. The semiconductor device according to claim 1, wherein the second impurity element and the third impurity element are the same impurity element.
(Appendix 9)
Forming a groove on the semiconductor substrate;
A first impurity element of a first conductivity type is introduced into the entire surface of the semiconductor substrate in which the groove is formed, and the first impurity element is contained below the groove and deeper than the groove. Forming a first impurity diffusion region having one conductivity type, and simultaneously forming the first impurity on the first side of the trench and the second side opposite to the first side in the semiconductor substrate; Forming first and second impurity diffusion region portions containing an element at a position shallower than the first impurity diffusion region;
Embedding an insulating film in the groove and forming the element isolation region;
Forming a first mask pattern exposing the element isolation region on the semiconductor substrate;
After the step of forming the first mask pattern, using the first mask pattern as a mask, the second impurity element of the first conductivity type is introduced into the semiconductor substrate by an ion implantation method, and the second mask pattern is formed. Forming a second impurity diffusion region containing an impurity element and having the first conductivity type;
Forming a second mask pattern covering the element isolation region on the semiconductor substrate;
After the step of forming the second mask pattern, ion implantation of a third impurity element having a second conductivity type opposite to the first conductivity type into the semiconductor substrate using the second mask pattern as a mask. In the semiconductor substrate, the third and fourth elements containing the third impurity element on the first side and the second side of the element isolation region and having the second conductivity type are included. Forming the impurity diffusion regions of the first impurity diffusion region portion and the second impurity diffusion region portion, respectively,
A method for manufacturing a semiconductor device, comprising:
(Appendix 10)
The method of manufacturing a semiconductor device according to appendix 9, wherein the step of introducing the first impurity element is performed through an oxide film.
(Appendix 11)
Forming a resist pattern having an opening corresponding to an element isolation region on a semiconductor substrate;
After the resist pattern forming step, a first impurity element of a first conductivity type is introduced into the entire surface of the semiconductor substrate on which the resist pattern is formed via the resist pattern, and below the opening, A first impurity diffusion region containing the first impurity element and having the first conductivity type is formed, and at the same time, a first side of the groove portion and a first side of the groove portion facing the first side are formed in the semiconductor substrate. Forming a first and second impurity diffusion region portion containing the first impurity element at a position shallower than the first impurity diffusion region on the second side;
Forming a groove corresponding to the opening in the semiconductor substrate;
Embedding an insulating film in the groove and forming the element isolation region;
Forming a first mask pattern exposing the element isolation region on the semiconductor substrate;
After the step of forming the first mask pattern, using the first mask pattern as a mask, the second impurity element of the first conductivity type is introduced into the semiconductor substrate by an ion implantation method, and the second mask pattern is formed. Forming a second impurity diffusion region containing an impurity element and having the first conductivity type;
Forming a second mask pattern covering the element isolation region on the semiconductor substrate;
After the second mask pattern forming step, a third impurity element having a second conductivity type opposite to the first conductivity type is ion-implanted into the semiconductor substrate using the second mask pattern as a mask. And introducing the third impurity element on the first side of the element isolation region and the second side opposite to the first side in the semiconductor substrate and having the second conductivity type. Forming third and fourth impurity diffusion regions;
A method for manufacturing a semiconductor device, comprising:
(Appendix 12)
The method of manufacturing a semiconductor device according to any one of appendices 9 to 11, wherein the second impurity diffusion region is formed at a position shallower than the first impurity diffusion region.
(Appendix 13)
In the third and fourth impurity diffusion regions, the concentration of the third impurity element is higher than the concentration of the first impurity element over the entire depth direction. The manufacturing method of the semiconductor device as described in any one of these.
(Appendix 14)
In the step of forming the second impurity diffusion region, the peak of the concentration distribution of the second impurity element in the depth direction is that of the first impurity element in the first and second impurity diffusion region portions. 13. The method for manufacturing a semiconductor device according to any one of appendices 9 to 12, wherein the method is performed so as to be formed at a position shallower than a concentration peak in a depth direction.

It is a figure which shows the example of the conventional semiconductor device. It is a figure which shows another example of the conventional semiconductor device. It is a figure explaining a subject. It is another figure explaining a subject. It is another figure explaining a subject. It is another figure explaining a subject. It is another figure explaining a subject. 1 is a diagram illustrating a semiconductor device according to a first embodiment. It is a figure which expands and shows a part of FIG. 6A. It is a figure which shows the distribution to the perpendicular direction of the impurity element in a silicon substrate. It is a figure which shows the distribution to the horizontal direction of the impurity element in a silicon substrate. It is a figure explaining the effect of 1st Embodiment. FIG. 6 is a diagram (part 1) for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a diagram (part 2) for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 6 is a view (No. 3) for describing a manufacturing step of the semiconductor device according to the first embodiment; FIG. 8 is a diagram (part 4) for explaining a manufacturing process of the semiconductor device according to the first embodiment; FIG. 8 is a diagram (No. 5) for describing a manufacturing step of the semiconductor device according to the first embodiment; FIG. 6 is a view (No. 6) for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 7 is a view (No. 7) for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 8 is a view (No. 8) for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 9 is a view (No. 9) for explaining a manufacturing step of the semiconductor device according to the first embodiment; FIG. 10 is a view (No. 10) for explaining a manufacturing step of the semiconductor device according to the first embodiment; It is FIG. (11) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is FIG. (12) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is FIG. (13) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is FIG. (14) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is FIG. (15) explaining the manufacturing process of the semiconductor device by 1st Embodiment. It is a figure which shows the leakage current characteristic in 1st Embodiment compared with a comparative example. It is a figure which shows one structure of the comparative example in FIG. It is a figure (the 1) which shows the modification of 1st Embodiment. It is FIG. (2) which shows the modification of 1st Embodiment. It is a figure which shows the density | concentration distribution of the impurity element to the perpendicular direction which arises in the silicon substrate in 1st Embodiment. It is FIG. (1) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is FIG. (2) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is FIG. (3) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is FIG. (4) explaining the manufacturing process of the semiconductor device by 2nd Embodiment. It is FIG. (5) explaining the manufacturing process of the semiconductor device by 2nd Embodiment.

Explanation of symbols

21 and 41 a silicon substrate 21DPW, 41DPW p-type deep well 21I, 41I isolation region 21PW, 41PW p-type channel stopper region 21p _1, 21p ₂ p-type region 21n _1, 21n ₂ n-type island 41a, 41c source extension region 41b , 41d drain extension region 41Ch ₁ , 41Ch ₂ channel doped region 41e, 41g source region 41f, 41h drain region 41B1, 41B2 B introduction region 41pk ₁ , 41pk ₂ pocket injection region 41N, 41N ₁ , 41N ₂ n-type well 41n ₁ , 41n ₂ n− type region 41T element isolation trench 42 gate insulating film 43 polysilicon film 43G ₁ , 43G ₂ polysilicon gate electrode 44 silicide layer 45 contact stopper layer 46 insulation Membrane 46A-46D Contact plug

Claims (7)

A semiconductor substrate;
An element isolation region formed in the semiconductor substrate;
First and second impurity diffusion regions formed in the semiconductor substrate with the element isolation region interposed therebetween and including the first impurity element of the first conductivity type and having the first conductivity type;
A third impurity having a second conductivity type, which is formed under the element isolation region in the semiconductor substrate and includes a second impurity element of a second conductivity type opposite to the first conductivity type; A diffusion region;
A fourth impurity diffusion region formed under the third impurity diffusion region in the semiconductor substrate and containing a third impurity element of the second conductivity type;
First and second impurities that are formed shallower than the fourth impurity diffusion region in the first and second impurity diffusion regions and include the third impurity element in addition to the first impurity element. A diffusion region portion;
A semiconductor device comprising:   2. The semiconductor device according to claim 1, wherein the first and second impurity diffusion region portions are formed deeper than the third impurity diffusion region.   The first impurity diffusion region includes the first impurity diffusion region portion and has the first conductivity type, and the second impurity diffusion region includes the second impurity diffusion region portion, The semiconductor device according to claim 1, wherein the semiconductor device has the first conductivity type.   4. The semiconductor device according to claim 1, wherein the first and second impurity diffusion region portions are formed shallower than the fourth impurity diffusion region. Forming a groove on the semiconductor substrate;
A first impurity element of a first conductivity type is introduced into the entire surface of the semiconductor substrate in which the groove is formed, and the first impurity element is contained below the groove and deeper than the groove. Forming a first impurity diffusion region having one conductivity type, and simultaneously forming the first impurity on the first side of the trench and the second side opposite to the first side in the semiconductor substrate; Forming first and second impurity diffusion region portions containing an element at a position shallower than the first impurity diffusion region;
Embedding an insulating film in the groove and forming the element isolation region;
Forming a first mask pattern exposing the element isolation region on the semiconductor substrate;
After the step of forming the first mask pattern, using the first mask pattern as a mask, the second impurity element of the first conductivity type is introduced into the semiconductor substrate by an ion implantation method, and the second mask pattern is formed. Forming a second impurity diffusion region containing an impurity element and having the first conductivity type;
Forming a second mask pattern covering the element isolation region on the semiconductor substrate;
After the step of forming the second mask pattern, ion implantation of a third impurity element having a second conductivity type opposite to the first conductivity type into the semiconductor substrate using the second mask pattern as a mask. In the semiconductor substrate, the third and fourth elements containing the third impurity element on the first side and the second side of the element isolation region and having the second conductivity type are included. Forming the impurity diffusion regions of the first impurity diffusion region portion and the second impurity diffusion region portion, respectively,
A method for manufacturing a semiconductor device, comprising: Forming a resist pattern having an opening corresponding to an element isolation region on a semiconductor substrate;
After the resist pattern forming step, a first impurity element of a first conductivity type is introduced into the entire surface of the semiconductor substrate on which the resist pattern is formed via the resist pattern, and below the opening, A first impurity diffusion region containing the first impurity element and having the first conductivity type is formed, and at the same time, a first side of the groove portion and a first side of the groove portion facing the first side are formed in the semiconductor substrate. Forming a first and second impurity diffusion region portion containing the first impurity element at a position shallower than the first impurity diffusion region on the second side;
Forming a groove corresponding to the opening in the semiconductor substrate;
Embedding an insulating film in the groove and forming the element isolation region;
Forming a first mask pattern exposing the element isolation region on the semiconductor substrate;
After the step of forming the first mask pattern, using the first mask pattern as a mask, the second impurity element of the first conductivity type is introduced into the semiconductor substrate by an ion implantation method, and the second mask pattern is formed. Forming a second impurity diffusion region containing an impurity element and having the first conductivity type;
Forming a second mask pattern covering the element isolation region on the semiconductor substrate;
After the second mask pattern forming step, a third impurity element having a second conductivity type opposite to the first conductivity type is ion-implanted into the semiconductor substrate using the second mask pattern as a mask. And introducing the third impurity element on the first side of the element isolation region and the second side opposite to the first side in the semiconductor substrate and having the second conductivity type. Forming third and fourth impurity diffusion regions;
A method for manufacturing a semiconductor device, comprising:   6. The third and fourth impurity diffusion regions, wherein the concentration of the third impurity element is higher than the concentration of the first impurity element over the entire depth direction. 6. A method for manufacturing a semiconductor device according to 6.