JP2010034895A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus which accelerates a read speed in performing addition and perform high-quality image capturing wherein generation of moire or the like is suppressed. <P>SOLUTION: The present invention relates to a solid-state imaging apparatus including: color filters for a plurality of colors in the Bayer array; a plurality of photoelectric conversion sections (2-1 to 2-4) provided correspondingly to the colors of the color filters; a first common amplifier (5-2) for adding charges of two photoelectric conversion sections of a first color being neighboring via a photoelectric conversion section of a different color in a vertical direction; and a second amplifier (5-3) for amplifying, without performing addition of the charge of a photoelectric conversion section of a second color, which is neighboring to any one of the two photoelectric conversion sections for addition and is not disposed between the two photoelectric conversion sections for addition. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  In recent years, an increasing number of video cameras are equipped with a CMOS sensor excellent in high-speed signal reading. Particularly, HD (High Definition) standard video sensors are becoming mainstream capable of realizing high image quality and high resolution.

  On the other hand, an increase in the number of pixels is required for the still image function of a video camera. In order to realize the HD moving image and the still image with one sensor, it is conceivable to add the number of pixels of the still image and perform compression or thinning operation to convert it into the HD standard pixel number. In general, moire or the like occurs in the thinning-out operation, so the addition operation is superior in image quality. Therefore, CMOS sensors are required to perform addition and read at high speed.

  Patent Document 1 discloses a configuration in which addition is performed by selecting pixels so that the centroids of the signals after addition become equal pitches between the signals. Further, Patent Document 2 discloses a configuration in which each photoelectric charge from a photodiode corresponding to a plurality of pixels of the same color is simultaneously connected to an output circuit and added.

Japanese Patent Laying-Open No. 2005-0866657 Japanese Patent Laid-Open No. 2005-244995

  In the configuration according to Patent Document 1, addition is performed in the capacitor section of the column readout circuit as a specific addition circuit, and the reading speed is not sufficiently increased.

  In the configuration according to Patent Literature 2, there is no idea of adjusting the barycentric pitch of the signal after addition, and there is a possibility that moire or the like occurs.

  In view of the above problems, an object of the present invention is to provide a solid-state imaging device that enables high-quality imaging in which the reading speed is increased and generation of moire or the like is suppressed when performing addition.

  The solid-state imaging device of the present invention is adjacent to a plurality of color filters in a Bayer array and a plurality of photoelectric conversion units provided corresponding to each color of the color filters via photoelectric conversion units of different colors in the vertical direction. Two common photoelectric conversion units that are adjacent to one of the two photoelectric conversion units that perform the addition and the common first amplification unit that adds the charges of the two photoelectric conversion units of the first color and that perform the addition And a second amplifying unit that amplifies without adding the charges of the photoelectric conversion units of the second color that are not arranged between the units.

  The solid-state imaging device according to the present invention includes a plurality of colors of Bayer array color filters, a plurality of photoelectric conversion units provided corresponding to the colors of the color filters, and a second color photoelectric conversion unit in the vertical direction. A common first amplifying unit for adding charges of three photoelectric conversion units adjacent to each other via the first color, and the second color adjacent to each other in the vertical direction via the photoelectric conversion unit for the first color A common second amplifying unit that adds the charges of the three photoelectric conversion units, and the two photoelectric components of the second color sandwiched between the three photoelectric conversion units of the first color that perform the addition The conversion units are added in groups of three photoelectric conversion units having different second colors by different second amplification units.

  When performing addition, it is possible to increase the readout speed and to perform high-quality imaging in which the occurrence of moire or the like is suppressed.

(First embodiment)
A solid-state imaging device according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows an example of a method of reading out the number of pixels compressed in half in the vertical direction when the color filter array is a Bayer array. Reference numerals 1-1 to 1-8 schematically show pixels, and color filters are Bayer arrayed on the respective pixels. The R pixels 1-1 and 1-3 have a red filter (R), the G pixels 1-2, 1-4, 1-5 and 1-7 have a green filter (G), and the B pixels 1-6, 1- A blue filter (B) is arranged at 8. There may be a convex microlens on the color filter.

  In such a pixel arrangement, in order to read out the compressed data by 1/2 in the vertical direction, first, the charges of the R pixels 1-1 and 1-3 are added, and then the charges of the G pixel 1-4 are read as they are. The charge of the pixel 1-2 is not read out. Similarly, the charges of the G pixels 1-5 and 1-7 are added, the charge of the B pixel 1-8 is read as it is, and the charge of the B pixel 1-6 is not read. When such readout is performed, the number of pixels can be compressed by half in the vertical direction while maintaining the color centroid.

  FIG. 2 is an equivalent circuit diagram of the solid-state imaging device according to the first embodiment of the present invention. Reference numerals 2-1 to 2-8 denote photodiodes which are photoelectric conversion units, and correspond to pixels. Reference numerals 3-1 to 3-8 denote transfer transistors as transfer means for transferring the charges generated in the photodiodes 2-1 to 2-8 to the gates of the amplification transistors 5-1 to 5-6. Reference numerals 4-1 to 4-6 denote reset transistors for resetting the gates of the amplification transistors 5-1 to 5-6, and 5-1 to 5-6 amplify the gate charges to generate the vertical signal lines 6. It is an amplifying transistor that is an amplifying unit that outputs to −1, 6-2. The photodiodes 2-1 and 2-3 of the R pixel, which are the same color pixels, and the photodiodes 2-5 and 2-7 of the G pixel are connected to a common floating diffusion region (floating diffusion: FD). Hereinafter, the floating diffusion region is referred to as FD. The FD is provided in the source region of the transfer transistors 3-1 to 3-8. The transfer transistors 3-1 to 3-8 have drains connected to the cathodes of the photodiodes 2-1 to 2-8, and sources (FD) connected to the gates of the amplification transistors 5-1 to 5-6. FD is a charge accumulation region. By simultaneously turning on the transfer transistors 3-1, 3-3 (or 3-5, 3-7), charges can be added in the FD. Compared with the case where the reading time is not added, the time is exactly the same except that the number of turning on the transfer transistors 3-1 and 3-3 is different. Therefore, the reading time does not change even if addition is performed. The G pixel photodiode 2-4 and the B pixel photodiode 2-8 are read as they are, and the G pixel photodiode 2-2 and the B pixel photodiode 2-6 are not read, so that the color center of gravity is maintained. The number of pixels can be reduced to ½ in the vertical direction.

  FIG. 3 is a timing chart for explaining the driving method of the solid-state imaging device according to the first embodiment of the present invention. The same reference numerals as those in FIG. 2 denote pulses input to the gates of the respective transistors. First, the power supply voltage VDD is lowered to turn on the reset transistors 4-2 and 4-3, and then the power supply voltage VDD is raised to turn on the reset transistor 4-1. By this operation, the potential of the FD to which the photodiodes 2-1 and 2-3 are connected is increased, so that the photodiodes 2-1 and 2-3 in the first and third rows are selected. By simultaneously turning on the transfer transistors 3-1 and 3-3, the charges of the respective photodiodes 2-1 and 2-3 are transferred to the common FD. The addition of the charges 2-1 and 2-3 is completed. The amplification transistor 5-2 outputs a voltage to the vertical signal line 6-1 according to the voltage of the FD connected to the gate.

  Next, the power supply voltage VDD is lowered to turn on the reset transistors 4-1 and 4-2, and then the power supply voltage VDD is raised to turn on the reset transistor 4-3. By this operation, only the FD connected to the photodiode 2-4 is set to a high potential, and the transfer transistor 3-4 is turned on, whereby the charge of the photodiode 2-4 is transferred to the FD. The amplification transistor 5-3 outputs a voltage to the vertical signal line 6-1 according to the voltage of the FD connected to the gate.

  It can be seen that the reading can be performed in the same time when the charges of the photodiodes 2-1 and 2-3 are added and when only the charge of the photodiode 2-4 is read.

  As described above, by applying this embodiment, it is possible to perform vertical addition without increasing the pixel readout time and without increasing the parasitic capacitance of the FD. Although the CMOS type solid-state imaging device has been described in the present embodiment, the same effect can be obtained with a MOS type, a JFET type, a CMD, and a VMIS.

(Second Embodiment)
A solid-state imaging device according to a second embodiment of the present invention will be described. Description will be made using a readout method for compressing the number of pixels in the vertical direction to ½ as shown in FIG.

  FIG. 4 is an equivalent circuit diagram of the solid-state imaging device according to the second embodiment of the present invention. Reference numerals 7-1 to 7-8 denote photodiodes which are photoelectric conversion units, and correspond to pixels. Reference numerals 8-1 to 8-8 denote transfer transistors as transfer means for transferring charges generated in the photodiodes to the gates of the amplification transistors 10-1 to 10-4. Reference numerals 9-1 to 9-4 denote reset transistors for resetting the gates of the amplifying transistors 10-1 to 10-4, and 10-1 to 10-4 amplify the gate charges to generate the vertical signal line 11. It is an amplifying transistor which is an amplifying part which outputs to −1 and 11-2. R pixel photodiodes 7-1 and 7-3, G pixel photodiodes 7-2 and 7-4, G pixel photodiodes 7-5 and 7-7, and B pixel photodiodes 7- 6 and 7-8 are connected to a common FD. By simultaneously turning on the transfer transistors 8-1 and 8-3 (or 8-5 and 8-7), the charges of the photodiodes 7-1 and 7-3 (or 7-5 and 7-7) are shared. It can be added in the FD. In addition, the G pixel photodiode 7-4 and the B pixel photodiode 7-8 are read as they are, and the G pixel photodiode 7-2 and the B pixel photodiode 7-6 are not read, so that the color centroid is maintained. The number of pixels can be reduced to ½ in the vertical direction.

  FIG. 5 is a timing chart for explaining a driving method of the solid-state imaging device according to the second embodiment of the present invention. The same reference numerals as those in FIG. 4 denote pulses input to the gates of the respective transistors. First, the power supply voltage VDD is lowered to turn on the reset transistor 9-2, and then the power supply voltage VDD is raised to turn on the reset transistor 9-1. By this operation, the potential of the FD connected to the photodiodes 7-1 and 7-3 is increased, so that the photodiodes 7-1 and 7-3 in the first and third rows are selected. Since the charges of the photodiodes 7-1 and 7-3 are transferred to the common FD by simultaneously turning on the transfer transistors 8-1 and 8-3, the photodiodes 7- in the first and third rows are transferred. Addition of charges 1,7-3 is completed. The amplification transistor 10-1 outputs a voltage to the vertical signal line 11-1 according to the voltage of the FD connected to the gate.

  Next, the power supply voltage VDD is first lowered to turn on the reset transistor 9-1, and then the power supply voltage VDD is raised to turn on the reset transistor 9-2. By this operation, only the FD connected to the photodiodes 7-2 and 7-4 is set to a high potential, and only the transfer transistor 8-4 is turned on, whereby the charge of the photodiode 7-4 is transferred to the FD. The amplification transistor 10-2 outputs a voltage to the vertical signal line 11-1 according to the voltage of the FD connected to the gate.

  It can be seen that reading can be performed in the same time when the charges of the photodiodes 7-1 and 7-3 are added and when only the charge of the photodiode 7-4 is read. In the method described in the first embodiment, when all the pixels are read out without adding, the capacitance of the FD connected to each photodiode is different, so that there is a problem that the charge conversion gain is different for each pixel. However, the problem is solved by using the method of the second embodiment.

  As described above, the same effects as those of the first embodiment can be obtained by applying this embodiment.

(Third embodiment)
A solid-state imaging device according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 6 shows an example of a method for reading out by compressing the number of pixels to 1/3 in the vertical direction. Reference numerals 12-1 to 12-16 schematically show pixels, and color filters are Bayer arrayed on the respective pixels. A red filter (R) is disposed in each of the R pixels 12-1, 12-3, 12-5, and 12-7. In addition, green filters (G) are arranged in the G pixels 12-2, 12-4, 12-6, 12-8, 12-9, 12-11, 12-13, and 12-15. Also, blue filters (B) are arranged in the B pixels 12-10, 12-12, 12-14, and 12-16. There may be a convex microlens on the color filter. In order to read out such compressed pixels by 1/3 in the vertical direction, first, the charges of the R pixels 12-1, 12-3, 12-5 are added, and then the G pixels 12-4, 12-6. , 12-8 are added and read. Similarly, the charges of the G pixels 12-9, 12-11, and 12-13 are added, and the charges of the B pixels 12-12, 12-14, and 12-16 are added and read. When such readout is performed, the number of pixels can be read by being compressed by 1/3 in the vertical direction while maintaining the color centroid position.

  FIG. 7 is an equivalent circuit diagram of the solid-state imaging device according to the third embodiment of the present invention, and shows an equivalent circuit for performing the readout method as shown in FIG. Reference numerals 13-1 to 13-16 denote photodiodes that are photoelectric conversion units, which correspond to pixels. Reference numerals 14-1 to 14-16 denote transfer transistors as transfer means for transferring the charges generated in the photodiodes 13-1 to 13-16 to the gates of the amplification transistors 16-1 to 16-6. Reference numerals 15-1 to 15-6 denote reset transistors for resetting the gates of the amplification transistors 16-1 to 16-6. Reference numerals 16-1 to 16-6 amplify the charges on the gates so as to amplify the vertical signal line 17. It is an amplifying transistor that is an amplifying unit that outputs to −1 and 17-2. Photodiodes 13-1, 13-3, and 13-5 of R pixels that are the same color pixels are connected to a common FD. Further, photodiodes 13-4, 13-6 and 13-8 of G pixels which are the same color pixels are connected to a common FD. In addition, photodiodes 13-9, 13-11, and 13-13 of G pixels that are the same color pixels are connected to a common FD. Further, photodiodes 13-12, 13-14, and 13-16 of B pixels that are the same color pixels are connected to a common FD.

  FIG. 8 is a timing chart for explaining a driving method of the solid-state imaging device according to the third embodiment of the present invention. Those given the same numbers as those in FIG. 6 are pulses inputted to the gates of the respective transistors. First, the power supply voltage VDD is lowered to turn on the reset transistor 15-2, and then the power supply voltage VDD is raised to turn on the reset transistor 15-1. By this operation, the potential of the FD to which the photodiodes 13-1, 13-3, and 13-5 are connected increases, and thus the photodiodes 13-1, 13-3, and 13-5 in the first, third, and fifth rows. Is selected. By simultaneously turning on the transfer transistors 14-1, 14-3, and 14-5, the charges of the photodiodes 13-1, 13-3, and 13-5 are transferred to the common FD. Thereby, the addition of the charges of the photodiodes 13-1, 13-3, 13-5 in the first, third, and fifth rows is completed. The amplification transistor 16-1 outputs a voltage to the vertical signal line 17-1 in accordance with the voltage of the FD connected to the gate.

  Next, the power supply voltage VDD is first lowered to turn on the reset transistor 15-1, and then the power supply voltage VDD is raised to turn on the reset transistor 15-2. By this operation, only the FD to which the photodiodes 13-4, 13-6, and 13-8 are connected is set to a high potential, and the transfer transistors 14-4, 14-6, and 14-8 are simultaneously turned on, so that the photodiode 13 is turned on. Charges of −4, 13-6, and 13-8 are transferred to the FD and added. The amplification transistor 16-2 outputs a voltage to the vertical signal line 17-1 according to the voltage of the FD connected to the gate.

  Even when compared with the first embodiment, it can be seen that the time to read out pixels is the same even when the number of vertical pixels added is increased. Further, according to the method of the present embodiment, as in the second embodiment, even when all the pixels are read out without addition, reading can be performed with the same charge conversion gain for each pixel.

  As described above, in the present embodiment, addition in the vertical direction can be performed without increasing the pixel readout time and without increasing the parasitic capacitance of the FD.

(Fourth embodiment)
A solid-state imaging device according to a fourth embodiment of the present invention will be described with reference to FIGS. FIG. 9 is a diagram showing a configuration in which three pixels of the same color pixel signal are added in the horizontal and vertical directions. Reference numerals 20-1 to 20-16 schematically indicate pixels, and color filters are arranged in a Bayer array on each pixel. A red filter (R) is disposed in each of the R pixels 20-1, 20-3, 20-5, and 20-7. In addition, green filters (G) are arranged in the G pixels 20-2, 20-4, 20-6, 20-8, 20-9, 20-11, 20-13, and 20-15. Further, blue filters (B) are arranged in the B pixels 20-10, 20-12, 20-14, and 20-16. There may be a convex microlens on the color filter. In the horizontal addition operation, first, the charges of the R pixels 20-1, 20-3, and 20-5 are added, and then the charges of the G pixels 20-4, 20-6, and 20-8 are added and read. Similarly, the charges of the G pixels 20-9, 20-11, and 20-13 are added, and the charges of the B pixels 20-12, 20-14, and 20-16 are added and read. The centers for each color after the addition are kept at regular intervals. The vertical addition method is the same as in the third embodiment. By combining vertical addition and horizontal addition on the floating diffusion (FD), the amount of output signal data is compressed to 1/3 while keeping the center of each color after the addition in the vertical and horizontal directions at equal intervals. Can be read.

  FIG. 10 is an equivalent circuit diagram of the solid-state imaging device according to the fourth embodiment of the present invention, and shows an equivalent circuit for reading out as shown in FIG. Reference numerals 21-1 to 21-8 denote clamp capacitors, and 22-1 to 22-8 denote switches for switching to the clamp power source Vclp. Reference numerals 24-1 to 24-8 denote sample and hold capacitors. Reference numerals 23-1 to 23-8 denote write switches for the sample and hold capacitors 24-1 to 24-8. Reference numerals 27-1 to 27-2 denote horizontal readout lines. Reference numerals 25-1 to 25-8 denote transfer switches to the horizontal readout lines 27-1 to 27-2. Reference numerals 26-1 to 26-6 denote switches (adders) for averaging (adding) the voltages written in the sample hold capacitors 24-1 to 24-8. Reference numerals 28-1 to 28-2 denote output amplifiers.

  FIG. 11 is a timing chart for explaining a driving method of the solid-state imaging device according to the fourth embodiment of the present invention. The same reference numerals as those in FIGS. 7 and 10 denote pulses input to the gates of the respective transistors. First, the power supply voltage VDD is first lowered to turn on the reset transistor 15-2, and then the power supply voltage VDD is raised to turn on the reset transistor 15-1. By this operation, the potential of the FD to which the photodiodes 13-1, 13-3, and 13-5 are connected increases, and thus the photodiodes 13-1, 13-3, and 13-5 in the first, third, and fifth rows. Is selected.

  Next, the switches 22-1 to 22-8 are turned on, and the noise levels of the clamp capacitors 21-1 to 21-8 are clamped to the clamp power supply Vclp to remove noise. Thereafter, by simultaneously turning on the transfer transistors 14-1, 14-3, and 14-5, the charges of the photodiodes 13-1, 13-3, and 13-5 are transferred to the common FD. Thereby, the addition of the charges of the photodiodes 13-1, 13-3, 13-5 in the first, third, and fifth rows is completed. The amplification transistor 16-1 outputs a voltage to the vertical signal line 17-1 in accordance with the voltage of the FD connected to the gate. The signals added by the FD are written in the sample hold capacitors 21-1 to 21-8 by turning on the switches 25-1 to 25-8. At this time, the horizontal direction addition shown in FIG. 9 can be performed by turning on the averaging switches 26-1, 26-3, 26-4, and 26-5. Finally, by sequentially turning on the switches 25-1 to 25-8, the signals can be read out to the horizontal output lines 27-1 and 27-2, and the added signals can be taken out through the output amplifiers 28-1 and 28-2. .

  As described above, the solid-state imaging devices according to the first to fourth embodiments include a plurality of color filters in a Bayer array and a plurality of photoelectric conversion units 2-1 to 2- provided corresponding to the colors of the color filters. 8 mag and so on.

  In the first and second embodiments, the amplification transistor 5-2 and the like include two photoelectric conversion units 2-1 of the first color adjacent to each other via photoelectric conversion units 2-2 and the like of different colors in the vertical direction. This is a common first amplifying unit that adds charges such as 2-3. The amplification transistor 5-3 and the like are adjacent to one of the two photoelectric conversion units 2-1 and 2-3 that perform addition, and the two photoelectric conversion units 2-1 and 2-3 that perform addition This is a second amplification unit that amplifies without adding the charges of the photoelectric conversion units 2-4 of the second color that are not arranged between them.

  In the first embodiment (FIG. 2), the two photoelectric conversion units 2-1 and 2-3 of the first color are the same via different first transfer transistors 3-1 and 3-3. To the first amplifying unit 5-2. Two photoelectric conversion units 2-2 and 2-4 of the second color adjacent to each other in the vertical direction via the photoelectric conversion unit 2-3 of the first color are different from each other in the second transfer transistor 3-3. And 3-4, etc., are connected to different second amplifying units 5-1, 5-3, etc. The floating diffusion regions such as the different first transfer transistors 3-1 and 3-3 are connected to each other by a metal wiring.

  In the second embodiment (FIG. 4), the two photoelectric conversion units 7-1 and 7-3 of the first color are the same via different first transfer transistors 8-1 and 8-3 and the like. To the first amplifying unit 10-1 and the like. Two photoelectric conversion units 7-2 and 7-4 of the second color adjacent to each other in the vertical direction via the photoelectric conversion unit 7-3 of the first color are different from each other in the second transfer transistor 8-2. And the same second amplifying unit 10-2 through 8-4 and the like. The floating diffusion regions such as the different first transfer transistors 8-1 and 8-3 are connected to each other by a metal wiring, and the floating diffusion regions such as the different second transfer transistors 8-2 and 8-4 are also connected to the metal wiring. Are connected to each other.

  In the third and fourth embodiments, the amplification transistor 16-1 or the like includes three photoelectric elements of the first color that are adjacent to each other in the vertical direction via the photoelectric conversion units 13-2 and 13-4 of the second color. This is a common first amplifying unit for adding charges such as the conversion units 13-1, 13-3, and 13-5. The amplification transistor 16-2 and the like include three photoelectric conversion units 13-4, 13-6, and 13- of the second color that are adjacent to each other in the vertical direction through the photoelectric conversion unit 13-5 of the first color. 8 is a common second amplifying unit that adds charges such as 8; The two photoelectric conversion units 13-2 and 13-4 of the second color sandwiched between the three photoelectric conversion units 13-1, 13-3, 13-5 of the first color performing the addition are as follows: These are added in a group of three photoelectric conversion units of different second colors by different second amplification units 16-2 and the like.

  In the fourth embodiment (FIGS. 9 and 10), the switches 26-1 and 26-3 and the like are adjacent to each other in the horizontal direction via the photoelectric conversion units 20-2 and 20-4 of the second color. This is a first addition unit that adds charges of the three photoelectric conversion units 20-1, 20-3, 20-5, and the like of one color. The switches 26-4 and 26-6, etc. are arranged in the horizontal direction so that the three photoelectric conversion units 20-4 of the second color adjacent to each other through the photoelectric conversion units 20-5, 20-7, etc. of the first color. , 20-6, 20-8, and the like.

  In the third and fourth embodiments, the three photoelectric conversion units 13-1, 13-3, 13-5 of the first color are different from each other in the first transfer transistors 14-1, 14-3, 14. It is connected to the same first amplifying unit 15-1 etc. via -5 etc. The three photoelectric conversion units 13-4, 13-6, 13-8, etc. of the second color are connected to the same second through different second transfer transistors 14-4, 14-6, 14-8, etc. Connected to the amplifying unit 16-2. The floating diffusion regions such as the different first transfer transistors 14-1, 14-3, and 14-5 are connected to each other by metal wiring, and the different second transfer transistors 14-4, 14-6, and 14-8. The floating diffusion regions such as are connected to each other by other metal wiring.

  As described above, according to the first to fourth embodiments, it is possible to perform high-quality imaging in which the reading speed is increased and generation of moire or the like is suppressed when performing addition.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed in a limited manner. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

It is the figure which showed an example of the pixel addition of a perpendicular direction. 1 is an equivalent circuit diagram of a solid-state imaging device according to a first embodiment. 3 is a timing chart for explaining a driving method of the solid-state imaging device according to the first embodiment. It is an equivalent circuit diagram of the solid-state imaging device according to the second embodiment. 10 is a timing chart for explaining a driving method of the solid-state imaging device according to the second embodiment. It is the figure which showed an example of the pixel addition of a perpendicular direction. It is an equivalent circuit diagram of the solid-state imaging device concerning a 3rd embodiment. 10 is a timing chart for explaining a driving method of the solid-state imaging device according to the third embodiment. It is a figure which shows the structure which adds 3 pixels of the signal of the same color pixel to a horizontal direction and a vertical direction. It is an equivalent circuit schematic of the solid-state imaging device concerning a 4th embodiment. 10 is a timing chart for explaining a driving method of the solid-state imaging device according to the fourth embodiment.

Explanation of symbols

1-1 to 1-8 Pixels 2-1 to 2-8 Photodiodes 3-1 to 3-8 Transfer transistors 4-1 to 4-6 Reset transistors 5-1 to 5-6 Amplifying transistors 6-1 to 6-6 2 Vertical output lines 7-1 to 7-8 Photodiodes 8-1 to 8-8 Transfer transistors 9-1 to 9-6 Reset transistors 10-1 to 10-6 Amplifying transistors 11-1 to 11-2 Vertical output lines 12-1 to 12-8 Pixels 13-1 to 13-8 Photodiodes 14-1 to 14-8 Transfer transistors 15-1 to 15-6 Reset transistors 16-1 to 16-6 Amplifying transistors 17-1 to 17- 2 Vertical output line

Claims (8)

A multi-color filter with a Bayer array;
A plurality of photoelectric conversion units provided corresponding to each color of the color filter;
A common first amplifying unit that adds the charges of two photoelectric conversion units adjacent to each other in the first color via photoelectric conversion units of different colors in the vertical direction;
Without adding the charge of the photoelectric conversion unit of the second color that is adjacent to one of the two photoelectric conversion units that perform the addition and that is not arranged between the two photoelectric conversion units that perform the addition A solid-state imaging device comprising: a second amplifying unit for amplifying. The two photoelectric conversion units of the first color are connected to the same first amplification unit via different first transfer transistors,
Two photoelectric conversion units of the second color that are adjacent in the vertical direction via the photoelectric conversion unit of the first color are connected to the different second amplification units via different second transfer transistors. The solid-state imaging device according to claim 1. The two photoelectric conversion units of the first color are connected to the same first amplification unit via different first transfer transistors,
Two photoelectric conversion units of the second color that are adjacent to each other in the vertical direction via the photoelectric conversion unit of the first color are connected to the same second amplification unit via different second transfer transistors. The solid-state imaging device according to claim 1.   4. The solid-state imaging device according to claim 2, wherein the floating diffusion regions of the different first transfer transistors are connected to each other by a metal wiring. A multi-color filter with a Bayer array;
A plurality of photoelectric conversion units provided corresponding to each color of the color filter;
A common first amplifying unit that adds the charges of three photoelectric conversion units of the first color adjacent in the vertical direction via the photoelectric conversion unit of the second color;
A common second amplifying unit that adds the charges of the three photoelectric conversion units adjacent to each other in the vertical direction via the photoelectric conversion unit of the first color;
The two photoelectric conversion units of the second color sandwiched between the three photoelectric conversion units of the first color that perform the addition are the three photoelectric conversions of the second color different from each other by different second amplification units. A solid-state imaging device characterized by being added in a group of parts. Furthermore, a first addition unit that adds the charges of three photoelectric conversion units of the first color adjacent in the horizontal direction via the photoelectric conversion unit of the second color;
6. The apparatus according to claim 5, further comprising a second addition unit that adds the charges of the three photoelectric conversion units adjacent to each other through the first color photoelectric conversion units in the horizontal direction. Solid-state imaging device. The three photoelectric conversion units of the first color are connected to the same first amplification unit via different first transfer transistors,
7. The solid-state imaging device according to claim 5, wherein the three photoelectric conversion units of the second color are connected to the same second amplification unit via different second transfer transistors. The floating diffusion regions of the different first transfer transistors are connected to each other by a metal wiring,
8. The solid-state imaging device according to claim 7, wherein the floating diffusion regions of the different second transfer transistors are connected to each other by another metal wiring.

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