JP2008270628A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for improving the analyzing precision of failure of a semiconductor device. <P>SOLUTION: A semiconductor chip 11 formed with a bump 12 on one main surface 11a is mounted on a substrate 20 by flip-chip connection, and a mounted structural body 100 in which an under-fill member 30 is arranged between the semiconductor chip 11 and the substrate 20 is inspected. Then, in a process for analyzing the failure of the mounted structural body 100 whose failure has been decided in the inspection process, the substrate 20 is ground from the face 20b side to the thickness direction, and the mounted structural body 100 is immersed in solution liquid for selectively solving the substrate 20 and the under-fill member 30, and the substrate 20 and the under-fill member 30 are removed. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique effective when applied to a failure analysis of a semiconductor device.

  Along with miniaturization and high functionality of various electronic devices in which semiconductor devices are mounted, there is a demand for miniaturization and high-density mounting in semiconductor devices. As a semiconductor chip mounting technology that meets the demand for miniaturization and higher density of semiconductor devices, there is a mounting technology called flip-chip connection or flip-chip mounting.

  In flip chip connection, a bump electrode called a bump is formed on an electrode formed on one main surface of a semiconductor chip, and the bump and the electrode terminal formed on the substrate are aligned and electrically connected. Technology.

  A semiconductor chip is mounted on a wiring board with the main surface on which bumps are formed facing the surface on which electrode terminals on the substrate are formed (referred to as face-down bonding). In an insulating material such as a resin called an underfill material is disposed.

  The underfill material generally functions as an adhesive for bonding a semiconductor chip to a substrate, and may have a function of protecting a circuit from moisture or the like, a function of preventing or suppressing the destruction of bumps, and the like.

  For example, Japanese Unexamined Patent Application Publication No. 2007-56070 (Patent Document 1) describes a package structure of a flip chip type semiconductor device in which an underfill material is disposed between a semiconductor element and a wiring board.

  Further, for example, Japanese Patent Laid-Open No. 9-289221 (Patent Document 2) describes a mounting structure in which a semiconductor chip is directly flip-chip connected to a mounting substrate called a printed circuit board (PCB). ing.

  In the manufacturing process of a semiconductor device, various inspections are performed to confirm that the semiconductor device has a predetermined specification. If it is determined in this inspection process that a defect has occurred, the cause of the defect is identified and fed back to the manufacturing process that caused the defect to perform a failure analysis.

For example, as described in Japanese Patent Application Laid-Open No. 10-74802 (Patent Document 3), a defect analysis of a semiconductor device includes a method of irradiating a semiconductor device with X-rays and evaluating a captured image.
JP 2007-56070 A JP-A-9-289221 JP-A-10-74802

  As a result of studying a failure analysis technique for semiconductor devices, the present inventor has found the following problems.

  In order to perform defect analysis, it is first necessary to identify a location where a defect that causes a defect has occurred. For example, it is necessary to specify whether the location where the failure occurred is the semiconductor chip itself, the substrate, or the bump that electrically connects the semiconductor chip and the substrate.

  The semiconductor chip and the substrate are inspected in each manufacturing process, and the location where the defect occurs is a bump that electrically connects the electrode formed on the main surface of the semiconductor chip and the electrode terminal formed on the substrate. Often around.

  For example, when the bump shape or the arrangement position deviates from the allowable range, it may cause a conduction failure or a characteristic failure. In particular, when the bump formed on the semiconductor chip is connected to the electrode terminal formed on the substrate, it is connected by heating, so that the shape of the bump is deformed and such a problem is likely to occur.

  As for the defective shape of the bump, if the appearance of the bump can be observed or the size of the bump can be measured, the presence or absence of a defect can be easily determined.

  However, since the semiconductor device to which the flip chip connection is applied is mounted with the surface of the semiconductor chip on which the bump is formed facing the wiring board, the appearance of the bump cannot be easily observed, or the size of the bump can be reduced. There is a problem that it cannot be measured.

  Further, when an underfill is filled between the semiconductor chip and the wiring board, there is a problem that the bump cannot be directly observed or the bump cannot be directly measured.

  As a method of observing the appearance of the bumps of the semiconductor chip mounted on the substrate by applying flip chip connection, there is a method of observing an image captured by irradiating the spot with X-rays. However, this method cannot observe a minute defect state such as a slight crack generated in the bump.

  A method of grasping the entire shape of the bump by polishing the semiconductor device from a certain direction by a mechanical polishing means and sequentially observing the polished cross section is also conceivable.

  However, this observation method has a problem that it is not possible to accurately observe a state where a defect occurs depending on a polishing place and a polishing direction. In addition, since the bumps to be observed are easily deformed by the pressure at the time of polishing, there is a problem that a fine defect phenomenon cannot be confirmed.

  As described above, when a defect is found in the electrical inspection process performed after the semiconductor chip is mounted on the substrate by flip-chip connection, there is a problem that it is extremely difficult to identify the defect portion.

  An object of the present invention is to provide a technique capable of improving the accuracy of failure analysis of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the defect of the mounting structure that is determined to be defective in the inspection process of the mounting structure in which the semiconductor chip is mounted on the substrate by flip chip connection, and an underfill material is disposed between the semiconductor chip and the substrate When performing the analysis, a part of the substrate is polished, and the mounting structure is immersed in a solution capable of selectively dissolving the substrate and the underfill material, and the substrate and the underfill material are immersed in the solution. Is to remove.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, according to the present invention, it is possible to improve the accuracy of failure analysis of a semiconductor device.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like.

  Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted in principle. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
First, the configuration of a mounting structure in which the semiconductor device according to the first embodiment is mounted on a printed circuit board by flip chip connection will be described with reference to FIGS. In the first embodiment, a semiconductor chip in which a plurality of flip chip connecting bumps are formed on one main surface is defined as a semiconductor device. Therefore, in the first embodiment, the underfill material and the printed circuit board are not included in the semiconductor device.

  FIG. 1 is an enlarged plan view of a mounting structure showing a state in which the semiconductor device according to the first embodiment is mounted on a printed circuit board, FIG. 2 is an enlarged cross-sectional view taken along line AA shown in FIG. It is a top view which shows the state of the main surface in which the bump of the semiconductor chip shown in FIG. 1 and FIG. 2 was formed.

  1 and 2, the mounting structure 100 according to the first embodiment includes a semiconductor device 10 including a semiconductor chip 11 and flip chip connection bumps 12 formed on one main surface 11a of the semiconductor chip 11. In FIG. And mounted on a substrate 20 which is a mounting substrate called a printed circuit board (hereinafter referred to as PCB).

  As shown in FIG. 2, a plurality of chip electrode pads 13 that are electrode terminals of the semiconductor chip 11 are formed on the main surface 11 a of the semiconductor chip 11. The chip electrode pad 13 functions as an external connection terminal of the semiconductor chip 11, and examples of the material include aluminum (Al), copper (Cu), gold (Au), and silver (Ag).

  As a detailed configuration of the semiconductor chip 11, for example, a semiconductor element is formed on the main surface of a semiconductor substrate made of silicon, and the semiconductor element and the chip electrode pad 13 are electrically connected via a wiring (wiring layer). ing.

  Bumps 12 for flip chip connection are formed on each of the chip electrode pads 13. The bump 12 has a function of electrically connecting the terminal 21 formed on the surface (first surface) 20a of the substrate 20 and the chip electrode pad 13 of the semiconductor chip 11, and is a ball-shaped solder called a solder ball. Can be used.

  As the solder, an alloy of tin (Sn) -lead (Pb) is generally used, but in recent years, an alloy of Sn and other metals may be used as a Pb-free solder. In some cases, bumps are formed using a material such as Au or Ag instead of solder.

  Since FIG. 2 is a cross-sectional view, the number of bumps 12 shown in FIG. 2 is two. However, as shown in FIG. 3, 18 bumps 12 are formed on the semiconductor chip 11. Accordingly, 18 chip electrode pads 13 shown in FIG. 2 are also formed on the main surface 11a correspondingly.

  Further, the number of the chip electrode pads 13 and the bumps 12 is not limited to this, and can be any number from several to several hundreds depending on the function required for the semiconductor chip 11.

  In the first embodiment, the chip electrode pads 13 and the bumps 12 are arranged in a line around the outer edge of the semiconductor chip 11. However, the arrangement of the chip electrode pads 13 and the bumps 12 is not limited to this.

  It can be arbitrarily set according to the plane area of the semiconductor chip 11 and the number of chip electrode pads 13 arranged. For example, it may be arranged in a row around the outer edge of the semiconductor chip 11. Alternatively, they may be arranged in a lattice pattern on the main surface 11a of the semiconductor chip.

  A substrate 20 shown in FIG. 2 is a mounting substrate called PCB (Printed Circuit Board) in which a glass fiber cloth (cloth) is overlapped with an epoxy resin. The substrate 20 has a structure in which insulating layers 22a and 22b are laminated in two layers. In the first embodiment, the substrate 20 is described as a substrate having a two-layer structure, but the number of stacked layers is not limited to this. It can be appropriately selected depending on the structure of the circuit formed on the substrate 20.

  For example, when the circuit formed on the substrate 20 is a very simple circuit, the layer structure of the substrate 20 may be a single layer structure (non-stacked structure). In addition, when it is necessary to form a complicated circuit, for example, a structure in which a plurality of insulating layers more than two layers such as a six-layer structure or an eight-layer structure are stacked may be used.

  The insulating layers 22a and 22b are bases for supporting circuit wiring formed on the substrate 20 and mounting components such as the semiconductor device 10 mounted on the substrate 20. For example, polyimide insulating resin or the like is desired. What was formed in the shape and hardened can be illustrated. Alternatively, the substrate 20 may be a ceramic substrate using a ceramic material such as glass ceramic for the insulating layers 22a and 22b.

  A surface wiring (conductive path) 23 is formed in a desired pattern on the surface of the uppermost insulating layer 22a. In addition, an internal wiring 24 that is a conductive path inside the substrate 20 is formed on the surface of the insulating layer 22b stacked in the lower layer.

  Further, the surface wiring 23 and the internal wiring 24 are electrically connected by vias 25 that are interlayer conductive paths, and these are arranged in a desired pattern to constitute an electric circuit.

  The material of the surface wiring 23, the internal wiring 24, and the via 25 is generally a large amount of Cu from the viewpoint of cost and workability, but is not limited thereto. For example, Au or Ag may be used. it can.

  The surface wiring 23 formed on the surface of the insulating layer 22a is covered with a solder resist layer 26 which is an insulating covering layer made of, for example, a polyimide resin. This solder resist layer 26 covers the entire surface of the insulating layer 22a except for the portion to be an external connection terminal of the substrate 20, such as the terminal 21 of the substrate 20.

  Further, a terminal 21 electrically connected to the chip electrode pad 13 is formed on a part of the surface wiring 23. The terminal 21 may be formed of Cu similarly to the surface wiring 23, the internal wiring 24, the via 25, etc., but Au or Ag can also be used. Alternatively, a thin film layer such as Au or Ag may be formed by plating on the surface of the terminal 21 made of Cu.

  In the first embodiment, the case where the terminal 21 is formed on a part of the surface wiring 23 is described. However, the bumps 12 of the semiconductor device 10 may be directly connected to the surface wiring 23 without forming the terminal 21. . In this case, the portion of the surface wiring 23 connected to the bump 12 is not covered with the solder resist layer 26.

  Next, an underfill material 30 that is an insulating resin material is filled between the semiconductor chip 11 and the substrate 20. In general, the underfill material 30 is required to have a function of protecting the circuit from moisture and the like, a function of preventing or suppressing the destruction of the bumps, in addition to functioning as an adhesive for bonding the semiconductor chip to the substrate.

  Various materials to be used as the underfill material 30 have been studied so far depending on the required functions, and resin materials in which various additives are added to the resin material as a base material have been proposed. A resin material based on an epoxy resin can be used.

  Next, a method for mounting the semiconductor device 10 will be described with reference to FIG.

  In FIG. 2, the semiconductor chip 11 included in the semiconductor device 10 is mounted with the main surface 11 a facing the surface 20 a of the substrate 20. Further, the chip electrode pad 13 of the semiconductor chip 11 is electrically connected to the terminal 21 formed on the surface of the substrate 20 via the bump 12. That is, no wire is used for electrical connection between the chip electrode pad 13 and the terminal 21.

  Such a connection method is called flip-chip connection and does not require a wire loop, so that the mounting efficiency can be improved and is a connection method suitable for high-density mounting.

  In the first embodiment, the semiconductor device 10 composed of the semiconductor chip 11 and the bumps 12 is directly mounted on the substrate 20 which is a mounting substrate. The method of directly mounting the semiconductor chip 11 on the substrate 20 as a mounting substrate is called bare chip mounting or DCA (Direct Chip Attach), and a semiconductor device having a package structure in which the semiconductor chip is sealed by a sealing body. Since it can be made thinner, it is a connection method suitable for high-density mounting.

  Next, a method for manufacturing the semiconductor device according to the first embodiment will be described.

  (A) First, the mounting structure 100 according to the first embodiment described with reference to FIGS. 1 to 3 is prepared.

  (B) Next, the mounting structure 100 is electrically inspected. In the manufacturing process of the semiconductor device 10, various inspections are performed at each stage of the manufacturing process. Even after the semiconductor device 10 is mounted on the substrate 20, which is a mounting substrate, and the mounting structure 100 is formed, the continuity confirmation test and the characteristic confirmation are performed. Electrical tests such as tests are performed.

  (C) Next, the mounting structure 100 determined to be defective in the above process is analyzed for defects. In this defect analysis step, it is first necessary to identify the location where the defect that caused the defect has occurred.

  Specifically, it is necessary to specify whether the occurrence of the defect is the semiconductor chip 11 itself, the substrate 20, or the bump 12 (including the connection state of the bump 12).

  The manufacturing method according to the first embodiment includes a step of removing the substrate 20 and the underfill material 30 from the mounting structure 100 as pre-processing in order to identify a location where a defect has occurred in the failure analysis step. By removing the substrate 20 and the underfill material 30 from the mounting structure 100, it is possible to observe the bumps 12 that are likely to be defective portions.

  Hereinafter, the results of the study by the present inventor regarding means for removing the substrate 20 and the underfill material 30 from the mounting structure 100 (hereinafter referred to as removal means) will be described with reference to FIGS. 2 and 4 to 6. FIG. 4 is a cross-sectional view showing an apparatus for immersing the mounting structure in a solution in the manufacturing method of the semiconductor device of the first embodiment, and FIG. 5 shows a state where the substrate of the mounting structure of the first embodiment is polished. FIG. 6 is a cross-sectional view showing the state of the semiconductor device after the substrate and underfill material of the mounting structure according to the first embodiment are selectively removed.

  First, the removal means studied by the present inventors will be described as a comparative example of the first embodiment.

  First, the inventor studied as a removing means is a method of dissolving the substrate 20 and the underfill material 30 shown in FIG. 2 with an acidic solvent. As the acidic solvent, fuming nitric acid and sulfuric acid which were available at a relatively low cost were studied.

  In order to dissolve the substrate 20 and the underfill material 30 with an acidic solvent, as shown in FIG. 4, the acid-resistant container 40 is filled with a fuming nitric acid or sulfuric acid solvent (dissolved solution) 42, and then the acid-resistant container 40 and the underfill material 30 are dissolved. The mounting structure 100 placed on the net 41 was immersed in the solvent 42. At this time, since the semiconductor chip is made of silicon, it cannot be dissolved unless a solvent having a higher acidity such as hydrofluoric acid is used.

  However, when fuming nitric acid is used as the solvent, the time required to dissolve the substrate 20 and the underfill material 30 shown in FIG. 2 is as long as about 3 minutes, so that the dissolution of the substrate 20 and the underfill material 30 is completed. In addition, the bumps 12 and part of the chip electrode pads 13 were dissolved, and the substrate 20 and the underfill material 30 could not be selectively dissolved.

  This is because the thickness of the substrate 20 is relatively thicker than the thickness of the semiconductor chip 11. More specifically, if the substrate 20 remains without being dissolved, the solvent is supplied only from between the semiconductor chip 11 and the substrate 20 in order to dissolve the underfill material 30. Therefore, if the underfill material 30 in the peripheral portion does not completely dissolve, the underfill material 30 formed near the center of the semiconductor chip 11 does not start to melt. In order to take out the semiconductor chip 11 from the substrate 20, it is necessary to completely dissolve the underfill material 30. Therefore, if the mounting structure 100 is immersed in a solvent for a long time until the underfill material 30 is completely dissolved. It has been found that even if a solvent that selectively dissolves only the substrate 20 and the underfill material 30 is used, the bumps 12 and the chip electrode pads 13 are also dissolved.

  When sulfuric acid was used as the solvent, the time required for dissolution was short, but since the oxidizing power was too strong, the bumps 12 and part of the chip electrode pads 13 were dissolved, and the substrate 20 and the underfill material 30 were selectively selected. Could not be dissolved.

  Then, even when the thickness of the substrate 20 is larger than the thickness of the semiconductor chip 11, the inventor does not dissolve the bumps 12 and the chip electrode pads 13 from the mounting structure 100 to the substrate 20 and the underfill material 30. We examined the means to remove

  That is, the substrate 20 and the underfill material 30 cannot be selectively dissolved by the method of simply immersing the mounting structure 100 in an acidic solvent as in this comparative example.

  Next, the removing means of the first embodiment will be described. In the first embodiment, before the mounting structure 100 is immersed in an acidic solvent, the substrate 20 shown in FIG. 2 is located on the side opposite to the surface (first surface) 20a on which the semiconductor chip 11 is mounted. (Second surface) A step of polishing in the thickness direction from 20b (hereinafter referred to as a polishing step) is included.

  As described in the comparative example, when fuming nitric acid having a lower oxidizing power than sulfuric acid is used as a solvent, it took about 3 minutes to dissolve the substrate 20 and the underfill material 30.

  However, in Embodiment 1, the time required to dissolve the substrate 20 and the underfill material 30 can be shortened by polishing the substrate 20 before the mounting structure 100 is immersed in an acidic solvent.

  Therefore, the substrate 20 and the underfill material 30 can be dissolved before the bumps 12 and part of the chip electrode pads 13 are dissolved. That is, the substrate 20 and the underfill material 30 can be selectively removed.

  The degree of polishing varies depending on the material of the substrate 20 and the material of the underfill material 30, but it is preferable to polish until the thickness of the insulating layer 22 a becomes thinner than the thickness of the underfill material 30 as shown in FIG. 5.

  When polished to this extent, the thickness of the substrate 20 is several tens of nm, which is thinner than the thickness of the semiconductor chip 11. When the insulating layer 22a is made of polyimide resin, the outline of the surface wiring 23 formed on the surface of the insulating layer 22a can be confirmed from the surface 20b side of the substrate 20.

  Thus, by polishing until the thickness of the insulating layer 22a becomes thinner than the thickness of the underfill material 30, the time required to dissolve the substrate 20 and the underfill material 30 is in the range of about 3 seconds to 10 seconds. Can fit in.

  Therefore, the substrate 20 and the underfill material 30 can be dissolved before the bumps 12 and part of the chip electrode pads 13 are dissolved. That is, the reliability of selectively removing the substrate 20 and the underfill material 30 can be improved.

  By the way, the case where the insulating layer 22a is made of ceramic such as glass ceramic (that is, the case where the substrate 20 is a ceramic substrate) will be described.

  In the case where the substrate 20 is a ceramic substrate, the insulating layer 22a is difficult to dissolve even if the insulating layer 22a is polished until the thickness of the insulating layer 22a is thinner than the thickness of the underfill material 30, so the substrate 20 and the underfill material 30 are dissolved. Before the process is completed, the bump 12 and part of the chip electrode pad 13 may be dissolved.

  Therefore, when the substrate 20 is a ceramic substrate, it is preferable to perform further polishing in the polishing step until the surface wiring 23 is partially exposed. By polishing until part of the surface wiring 23 is exposed, it is possible to remove the ceramic insulating layer 22a that is difficult to dissolve in the solvent.

  For this reason, even if the substrate 20 is a ceramic substrate, the accuracy of dissolving the substrate 20 and the underfill material 30 can be improved before the bumps 12 and part of the chip electrode pads 13 are dissolved. That is, the reliability of selectively removing the substrate 20 and the underfill material 30 can be improved.

  In addition, when the surface state of the substrate 20 is not flat, even if the substrate 20 is polished in the polishing step, a part of the substrate 20 (particularly, around the end portion) may be thick. When the substrate 20 is a ceramic substrate, the end of the substrate 20 may not be completely removed.

  However, if the substrate 20 in the region to which the bumps 12 are connected can be polished to a predetermined thickness, the substrate 20 and the underfill material 30 can be selectively removed.

  That is, even if the thickness of the periphery of the end portion of the substrate 20 is greater than a predetermined thickness, if the substrate 20 in the region to which the bump 12 is connected is dissolved, the substrate 20 remaining at the end portion is separated from the bump 12. As a result, it is possible to remove the substrate 20 from the bumps 12.

  Next, means for polishing in the polishing process will be described. As a means for polishing the substrate 20, a method of mechanically polishing through a polishing powder can also be used. However, as described above, the bump 12 may be deformed by the pressure during polishing. If the bump 12 is deformed by polishing, even if the bump 12 is observed to find a shape defect, it cannot be determined whether the shape defect has occurred during mounting or has occurred during polishing.

  Therefore, it is preferable to select chemical mechanical polishing called CMP (Chemical Mechanical Polishing) as a polishing means. In particular, when polishing until the thickness of the insulating layer 22a becomes thinner than the thickness of the underfill material 30, or when polishing until a part of the surface wiring 23 is exposed, the polishing is performed up to the vicinity of the bump 12, so the bump 12 Is susceptible to pressure during polishing.

  For this reason, even if mechanical polishing is performed in the initial stage of the polishing process, it is desirable to polish by chemical mechanical polishing in the final stage of setting the thickness of the substrate 20 to a predetermined thickness.

  In this polishing step, it is preferable to polish the surface as flat as possible along the surface 20 a of the substrate 20. By improving the flatness of the polished surface 20b, it is possible to improve the accuracy of selectively removing the substrate 20 and the underfill material 30 in the next dipping process. Here, when polishing is performed by chemical mechanical polishing, the flatness of the polished surface 20b can be improved as compared with the case of using mechanical polishing means.

  By using chemical mechanical polishing as the polishing means, it is possible to prevent or suppress the deformation of the bumps 12 due to the polishing process, so that the accuracy of failure analysis can be improved. In addition, since the flatness of the polished surface 20b can be improved, the accuracy of selectively removing the substrate 20 and the underfill material 30 in the next dipping process can be improved.

  Next, a process of immersing the mounting structure 100 with the substrate 20 polished as shown in FIG. 5 in a solvent to selectively dissolve the substrate 20 and the underfill material 30 (hereinafter referred to as an immersion process) will be described. In the description of the dipping process, each component constituting the mounting structure 100 will be described based on the structure shown in FIG.

  In the dipping process, for example, as shown in FIG. 4, the acid-resistant container 40 is filled with a solvent (dissolved solution) 42 that is a mixture of fuming nitric acid and sulfuric acid. Next, the mounting structure 100 obtained by polishing the substrate 20 in the polishing step is immersed in the solvent 42 for several seconds to 30 seconds in a state where the mounting structure 100 is placed on the acid-resistant net 41.

  Note that the apparatus shown in FIG. 4 shows an example of an apparatus used for the dipping process, and is not limited to the configuration shown in FIG. Other structures may be used as long as the mounting structure 100 is immersed in the solvent 42 which is a fuming nitric acid and sulfuric acid mixed solution and can be pulled up in a predetermined time.

  In this dipping process, dissolution starts from a part in contact with the solvent 42 among the components constituting the mounting structure 100. However, the semiconductor chip 11 is made of silicon (Si) or the like, and is more difficult to dissolve in the solvent 42 than the insulating layer 22a made of a resin material, the solder resist layer 26, and the underfill material 30.

  For this reason, the insulating layer 22 a and the solder resist layer 26 constituting the substrate 20 and the underfill material 30 are dissolved before the semiconductor chip 11.

  In addition, when the surface wiring 23 and the terminal 21 are made of Cu, the Cu is more resistant to the solvent 42 than the solder (Sn alloy), Au, Ag, or the like constituting the semiconductor chip 11 or the bump 12. Easy to dissolve.

  Further, even if the surface wiring 23 and the terminal 21 are made of, for example, Au or Ag instead of Cu, the surface wiring 23 and the terminal 21 come into contact with the solvent 42 before the bump 12, so that the bump 12 The surface wiring 23 and the terminal 21 can be dissolved before starting to dissolve in the solvent 42.

  That is, in this dipping process, the substrate 20 and the underfill material 30 are selectively dissolved by the correlation between the solubility of each component constituting the mounting structure 100 in the solvent 42 and the time in contact with the solvent 42. be able to.

  By the way, in the dipping process of the first embodiment, the time for dipping the mounting structure 100 in the solvent 42 is as short as several seconds to 30 seconds. By shortening the immersion time in this manner, it is possible to prevent the phenomenon in which the semiconductor chip 11 and the bumps 12 are dissolved in the solvent 42.

  Further, according to the first embodiment, the substrate 20 is polished in the polishing step. For this reason, even if the immersion time is shortened, the substrate 20 and the underfill material 30 can be selectively dissolved in the solvent 42.

  When the step of selectively dissolving the substrate 20 and the underfill material 30 of the mounting structure 100 in the solvent 42 is completed in this immersion step, the semiconductor chip 11 on which the bumps 12 are formed, that is, the semiconductor device 10 is left. .

  Next, a method for preparing the solvent 42 will be described. As described above, the solvent 42 shown in FIG. 4 is a mixed solution of fuming nitric acid and sulfuric acid. The mixing ratio of fuming nitric acid and sulfuric acid is selected as follows according to the material of the underfill material 30 to be dissolved, the material of the semiconductor chip 11 and the bump 12 to be analyzed, or the mounting structure of the mounting structure 100.

  In the first embodiment, the underfill material 30 is dissolved in a very short immersion time of about several seconds to 30 seconds. The oxidizing power of fuming nitric acid is lower than that of sulfuric acid. For this reason, in order to dissolve the underfill material 30 within a predetermined time, it is preferable to use a solvent in which a predetermined amount of sulfuric acid is mixed with fuming nitric acid.

  The solubility of the underfill material 30 in the solvent 42 differs depending on the material constituting the underfill material 30. For this reason, first, the time required to completely dissolve the underfill material 30 by immersing the underfill material 30 in the solvent 42 in which the mixing ratio of fuming nitric acid and sulfuric acid is a predetermined ratio (for example, 8: 2). (Underfill material dissolution time) is measured.

  Next, the semiconductor chip 11 in which the bumps 12 are formed in the solvent 42 in the same mixing ratio as the solvent 42 in which the underfill material 30 is immersed is immersed for the same time as the above-described underfill material dissolution time. Check for the dissolution of.

  If part of the semiconductor chip 11 or the bump 12 is dissolved in this time, the mixing ratio of the solvent 42 is changed, and the optimal mixing ratio is confirmed in the same step.

  At this time, it is preferable to investigate in advance the dissolution time of the semiconductor chip 11 and the bump 12 according to the mixing ratio of the solvent 42. By previously investigating the dissolution time of the semiconductor chip 11 and the bumps 12 according to the mixing ratio of the solvent 42, the mixing ratio determination time of the solvent 42 can be shortened.

  When the present inventor examined various mounting structures 100 using the method for preparing the solvent 42 described above, the mixing ratio of fuming nitric acid and sulfuric acid in the solvent 42 was 20% of the total ratio of the solvent 42. It has been found that the following is preferable.

  Further, depending on the material of the underfill material 30, the underfill material 30 may be dissolved within 30 seconds even when the solvent 42 is prepared by using only fuming nitric acid without mixing sulfuric acid. I also understood.

  Therefore, the solvent 42 of the first embodiment is preferably a mixture of fuming nitric acid and sulfuric acid, but is not limited thereto, and may be a solvent 42 containing only fuming nitric acid.

  Next, the semiconductor device 10 after removing the substrate 20 and the underfill material 30 by the dipping process is washed with a neutralizing solution (hereinafter referred to as a washing process). If the semiconductor device 10 is left in a state where the solvent 42 is attached, oxidation proceeds and, for example, a part of the bumps 12 and the like are dissolved.

  Therefore, it is necessary to completely remove the solvent 42. In this cleaning step, it is sufficient that the solvent 42 attached to the semiconductor device 10 can be removed, and the cleaning means can be appropriately selected. For example, a method of immersing the semiconductor device 10 in a neutralizing solution can be used.

  FIG. 6 shows the structure of the semiconductor device 10 after the solvent 42 is removed in the cleaning process. 6, the semiconductor device 10 has the substrate 20 and the underfill material 30 of the mounting structure 100 shown in FIG. 2 selectively removed.

  Further, the bumps 12 shown in FIG. 6 are exposed while maintaining the shape of the state of being electrically connected to the terminals 21 shown in FIG.

  As described above, according to the method of manufacturing the semiconductor device 10 of the first embodiment, the substrate 20 of the mounting structure 100 is polished from the surface 20b of the substrate 20 in the thickness direction in the step of analyzing the failure of the mounting structure 100. The substrate 20 and the underfill material 30 can be selectively removed by providing the step of immersing the mounting structure 100 in a solution that selectively dissolves the substrate 20 and the underfill material 30.

  For this reason, the main surface 11a side where the bump 12 of the semiconductor chip 11 is formed can be enlarged and observed using, for example, a microscope. Also, the dimensions such as the height and width of the bump 12 can be measured.

  If the location where the defect that caused the failure in the step (b) has occurred is a bump 12, the location of the failure can be easily identified by observing the bump 12 or measuring the dimensions. It becomes possible to do.

  Further, as shown in FIG. 6, the semiconductor device 10 after the cleaning process is completed maintains the shape in which the bumps 12 are electrically connected to the terminals 21 shown in FIG. For this reason, when the location where the defect that has been determined to be defective in the step (b) is a connection failure between the bump 12 and the terminal 21 shown in FIG. 2, the bump 12 is observed, or By measuring the dimensions, it is possible to easily identify the location of the defect.

  Further, as shown in FIG. 6, the bump 12 is exposed in the semiconductor device 10 after the cleaning process is completed. For this reason, the electrical inspection of the semiconductor chip 11 can be performed again by bringing a probe for electrical inspection into contact with the bump 12, for example.

  If the location where the failure that has been determined to be defective in the step (b) is an electrical failure of the semiconductor chip 11, the electrical inspection of the semiconductor chip 11 can be performed again to easily perform the failure. Can be specified.

  Moreover, if the abnormal part is not found by the above-described observation of the bump 12, the measurement of dimensions, or the electrical inspection of the semiconductor chip 11, there is a problem that causes the determination of a defect in the step (b). It can be estimated that the location is on the substrate 20.

  In this case, it is preferable to remount the semiconductor device 10 on another substrate and confirm that it operates normally. The underfill material 30 is not attached to the semiconductor device 10 shown in FIG. For this reason, the semiconductor device 10 can be remounted on a substrate different from the substrate 20 shown in FIG. 2 in the same process as the process of mounting the newly manufactured semiconductor device 10.

  Further, in this re-mounting process, the bump 12 formed on the main surface 11a of the semiconductor chip 11 is temporarily removed, a new bump 12 is formed, and then the semiconductor device 10 is a substrate different from the substrate 20 shown in FIG. Can also be re-implemented.

  In this manner, the bump 12 formed on the main surface 11a of the semiconductor chip 11 is temporarily removed, and a new bump 12 is formed. Thus, the semiconductor chip is manufactured in the same process as the process of mounting the newly manufactured semiconductor chip 11. 11 can be re-mounted on a substrate different from the substrate 20 shown in FIG.

  If the above-described remounting means is used, the semiconductor device 10 mounted on the mounting structure 100 determined to be defective in the step (b) can be reused.

  As described above, according to the first embodiment, it is possible to identify a defect occurrence location by selectively removing the substrate 20 and the underfill material 30 in the failure analysis step. For this reason, the precision of defect analysis can be improved.

(Embodiment 2)
In the first embodiment, a semiconductor chip having a plurality of flip chip connection bumps formed on one main surface is mounted on a printed circuit board by flip chip connection. The embodiment to which the analysis technique is applied has been described.

  In the second embodiment, a semiconductor chip in which a plurality of flip chip connection bumps are formed on one main surface is mounted on a wiring board by flip chip connection and sealed by a sealing body. An embodiment applied to a semiconductor device will be described.

  In the second embodiment, the entire package in which a semiconductor chip having a plurality of flip chip connecting bumps formed on one main surface is mounted on a wiring board and sealed by a sealing body is defined as a semiconductor device. To explain. Therefore, in the second embodiment, the underfill material and the wiring board are included in the semiconductor device.

  First, the configuration of a semiconductor device in which a semiconductor chip in which a plurality of flip chip connection bumps are formed on one main surface is mounted on a wiring board by flip chip connection will be described with reference to FIGS.

  Note that, in the semiconductor device 200 described in the second embodiment, components having the same reference numerals as those of the mounting structure 100 described in the first embodiment are components having the same function, and thus repeated description. Is omitted. Moreover, when it is necessary to explain the detailed structure of each component, it will be described with reference to FIGS. 1 to 6 described in the first embodiment as necessary.

  7 is an enlarged cross-sectional view showing the structure of the semiconductor device of the second embodiment, FIG. 8 is an enlarged plan view showing the back surface structure of the semiconductor device of the second embodiment, and FIG. 9 is provided in the semiconductor device shown in FIG. It is an enlarged plan view which shows the state by which the semiconductor chip was mounted in the wiring board.

  In the semiconductor device 200 of the second embodiment, the semiconductor chip 11 is sealed with a sealing resin 31 in FIG. For the sealing resin 31, for example, a resin material based on an epoxy resin is used. In addition, the sealing resin 31 and the underfill material 30 are made of the same material, and when the semiconductor chip 11 is sealed, the sealing resin 31 also wraps under the main surface 11a of the semiconductor chip 11 and collects them. Some structures are sealed.

  In addition, the semiconductor device 200 includes a wiring board 50. The difference between the wiring board 50 of the second embodiment shown in FIG. 7 and the board 20 (FIG. 2) described in the first embodiment is that the wiring board 50 includes the external connection terminals 51 of the semiconductor device 200. It is a point.

  The wiring substrate 50 is a part of the semiconductor device 200, and the semiconductor device 200 is formed by stacking the semiconductor device 200 through, for example, glass fiber cloth (cross) through the external connection terminals 51 formed on the wiring substrate 50. The printed circuit board is electrically connected to a mounting board called PCB (Printed Circuit Board) impregnated with an epoxy resin.

  Each external connection terminal 51 is provided with an electrode 52 that is a protruding conductive material. The electrode 52 has a function of electrically connecting the external connection terminal 51 and a mounting substrate on which the semiconductor device 200 is mounted. For example, ball-shaped solder called a solder ball can be used.

  In the second embodiment, the structure in which the electrode 52 is formed on the external connection terminal 51 is shown as a configuration example of the semiconductor device 200. However, the electrode 52 is not formed and the external connection terminal 51 is exposed. It is good also as a structure.

  The external connection terminals 51 and the electrodes 52 are formed on the surface 20b side of the wiring board 50. As shown in FIG. 8, the electrodes 52 are arranged in a grid pattern. The package having such a structure is called a BGA (Ball Grid Array) package, and is widely used as a package structure suitable for high-density mounting.

  A structure in which the electrodes 52 are not formed and the external connection terminals 51 are arranged in a lattice shape is called an LGA (Land Grid Array) package, and this structure is also suitable for high-density mounting.

  Further, the surface 20b of the wiring substrate 50 is covered with a solder resist layer 53 which is an insulating covering layer made of, for example, a polyimide resin. The solder resist layer 53 has a function of preventing a phenomenon in which adjacent electrodes 52 come into contact with each other and are electrically short-circuited when the semiconductor device 200 is mounted on a mounting substrate.

  In the second embodiment, the structure in which the surface 20b of the wiring board 50 is covered with the solder resist layer 53 is shown, but a structure in which the solder resist layer 53 is not formed may be used.

  Next, as shown in FIGS. 7 and 9, the semiconductor chip 11 is mounted on the surface 20 a (see FIG. 7) side of the wiring board 50 in the same manner as the mounting structure 100 described in the first embodiment. Yes. An underfill material 30 that is an insulating resin material is filled between the semiconductor chip 11 and the substrate 50.

  Next, a method for manufacturing the semiconductor device according to the second embodiment will be described.

  (A) First, the semiconductor device 200 according to the second embodiment described with reference to FIGS. 7 to 9 is prepared.

  (B) Next, the semiconductor device 200 is electrically inspected. In the manufacturing process of the semiconductor device 200, various inspections are performed at each stage of the manufacturing process. Even after the semiconductor device 200 is mounted on the wiring substrate 50 and sealed with the sealing resin 31, the conduction confirmation test and the characteristic confirmation test are performed. Electrical tests are performed.

  (C) Next, the semiconductor device 200 determined to be defective in the above process is analyzed for defects. In this defect analysis step, the wiring board 50 and the underfill material 30 are selectively removed from the semiconductor device 200 in order to identify the location where the defect that caused the defect has occurred.

  The difference between the semiconductor device 200 of the second embodiment and the mounting structure 100 described in the first embodiment is the presence or absence of the sealing resin 31. Therefore, in the second embodiment, it is preferable to remove the sealing resin 31 from the semiconductor device 200 in addition to the wiring substrate 50 and the underfill material 30.

  By the way, as described above, for example, a resin material having an epoxy resin as a base material is used as the sealing resin 31. For this reason, the sealing resin 31 is dissolved before the semiconductor chip 11.

  Therefore, also in the method for manufacturing the semiconductor device 200 according to the second embodiment, as a means for selectively removing the wiring substrate 50 and the underfill material 30, the substrate 20 and the underlayer are removed from the mounting structure 100 described in the first embodiment. A method similar to the means for removing the fill material 30 can be used.

  Of the means described in the first embodiment, only representative means are as follows.

  That is, in the step of analyzing the failure of the semiconductor device 200, the step of polishing the substrate 50 of the semiconductor device 200 in the thickness direction from the surface 20b of the substrate 50 and the solution for selectively dissolving the substrate 50 and the underfill material 30 are used. The semiconductor device 200 includes a step of immersing it.

  With such a configuration, the substrate 50, the underfill material 30, and the sealing resin 31 can be selectively removed from the semiconductor device 200.

  By selectively removing the substrate 50, the underfill material 30 and the sealing resin 31 from the semiconductor device 200, the structure as shown in FIG. 6, that is, the semiconductor chip 11 and the terminal 21 shown in FIG. A structure including the exposed bumps 12 while maintaining the connected shape can be obtained.

  Further, according to the second embodiment, the location of the defect can be easily identified by observing the shape of the bump 12 after being mounted on the wiring substrate 50 or measuring the dimensions.

  Further, for example, by bringing a probe for electrical inspection into contact with the bump 12 and performing electrical inspection of the semiconductor chip 11 again, the location of the defect can be easily identified.

  Further, by observing the shape of the bump 12, measuring the dimensions, or performing the electrical inspection of the semiconductor chip 11 again, the accuracy of the failure analysis can be improved.

  Further, by removing the bumps 12 formed on the main surface 11a of the semiconductor chip 11 and forming new bumps 12 in the same process as the process of mounting the newly manufactured semiconductor chip 11, the semiconductor chip 11 Can be re-mounted on a board different from the wiring board 50 shown in FIG.

  If this re-mounting means is used, the semiconductor chip 11 mounted on the semiconductor device 200 determined to be defective in the step (b) can be reused.

  The invention made by the present inventor has been specifically described based on the embodiment of the present invention. However, the present invention is not limited to the embodiment of the invention, and various modifications can be made without departing from the scope of the invention. Is possible.

  The present invention can be applied to a manufacturing technique of a semiconductor device, particularly a semiconductor device in which a semiconductor chip is flip-chip connected to a substrate.

1 is an enlarged plan view of a mounting structure showing a state in which a semiconductor device according to a first embodiment of the present invention is mounted on a printed circuit board. It is an expanded sectional view along the AA line shown in FIG. It is a top view which shows the state of the main surface in which the bump of the semiconductor chip shown in FIG. 1 and FIG. 2 was formed. In the manufacturing method of the semiconductor device of Embodiment 1 of this invention, it is sectional drawing which shows the structural example of the apparatus which immerses a mounting structure in a solution. It is sectional drawing which shows the state which grind | polished the board | substrate of the mounting structure of Embodiment 1 of this invention. It is sectional drawing which shows the state of the semiconductor device after selectively removing the board | substrate and underfill material of the mounting structure of Embodiment 1 of this invention. It is an expanded sectional view which shows the structure of the semiconductor device of Embodiment 2 of this invention. FIG. 8 is an enlarged plan view showing a back surface structure of the semiconductor device shown in FIG. 7. FIG. 8 is an enlarged plan view showing a state in which a semiconductor chip is mounted on a wiring board included in the semiconductor device shown in FIG. 7.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Semiconductor chip 11a Main surface 12 Bump 13 Chip electrode pad 20 Board | substrate 20a surface (1st surface)
20b surface (second surface)
21 Terminal 22a, 22b Insulating layer 23 Surface wiring (conductive path)
24 Internal wiring 25 Via 26 Solder resist layer 30 Underfill material 31 Sealing resin 40 Container 41 Net 42 Solvent (solution)
50 Wiring board (board)
51 External Connection Terminal 52 Electrode 53 Solder Resist Layer 100 Mounting Structure 200 Semiconductor Device

Claims (5)

(A) Mounting in which a semiconductor chip having a plurality of flip chip connecting bumps formed on one main surface is flip-chip connected to a substrate, and an underfill material is filled between the semiconductor chip and the substrate Preparing the structure;
(B) electrically inspecting the mounting structure;
(C) including a step of performing failure analysis on the mounting structure determined to be defective in the step (b),
In the step (c),
Polishing the substrate of the mounting structure in a thickness direction from a second surface located on the opposite side of the first surface on which the semiconductor chip of the substrate is mounted;
After the step of polishing the substrate, a step of immersing the mounting structure in a solution that selectively dissolves the substrate and the underfill material to remove the substrate and the underfill material is included. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the solution is a mixture of fuming nitric acid and sulfuric acid. In the manufacturing method of the semiconductor device according to claim 1,
The substrate includes an insulating layer and a conductive path formed on a surface of the insulating layer,
In the step of polishing the substrate of the mounting structure, the method of manufacturing a semiconductor device is characterized in that the insulating layer is polished so that the thickness of the insulating layer is thinner than the thickness of the underfill material. In the manufacturing method of the semiconductor device according to claim 3,
In the step of polishing the substrate of the mounting structure, polishing is performed until the conductive path is exposed on the polished surface of the substrate. (A) A semiconductor chip in which a plurality of flip chip connecting bumps are formed on one main surface and flip-chip connected to a substrate, and an underfill material is filled between the semiconductor chip and the substrate. Preparing the device;
(B) electrically inspecting the semiconductor device;
(C) including a step of performing failure analysis on the semiconductor device determined to be defective in the inspection step,
In the step (c),
Polishing the substrate of the semiconductor device in a thickness direction from a second surface located on the opposite side of the first surface on which the semiconductor chip of the substrate is mounted;
After the step of polishing the substrate, the method includes a step of immersing the semiconductor device in a solution that selectively dissolves the substrate and the underfill material, and removing the substrate and the underfill material. A method for manufacturing a semiconductor device.

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