JP2008258299A - Field-effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field-effect transistor reducing a current collapse, having high breakdown-strength characteristics and allowing low-cost manufacture. <P>SOLUTION: In the gallium nitride field-effect transistor 1, an electron transit layer 103 composed of a gallium nitride and an electron supply layer 104 configured of an indium-aluminum nitride shown in structural formula In<SB>x</SB>AI<SB>1-x</SB>N (0.13≤x≤0.22) are formed. The electrol supply layer comprises a gate recess structure 105 for storing an electrode and a drain recess structure 106 and has a thickness of 50 nm or more. In the field-effect transistor 1, at least a part of a gate electrode 108 or a drain electrode 109 is formed on the base of the corresponding recess structure. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a gallium nitride field effect transistor.

  A gallium nitride heterojunction field effect transistor (GaN-HFET) is a device that operates using a two-dimensional electron gas generated at a heterointerface as an electron transit layer. Development as a high-output high-frequency device has been promoted because of its high saturation electron velocity and high electron density.

  One problem with GaN-HFETs is device breakdown. When high power is applied to the device to obtain a large output, an excessive electric field concentrates on the semiconductor crystal near the drain side end of the gate electrode, and the device is destroyed.

One technique for improving the breakdown voltage is a field plate structure. The field plate structure is a structure in which a metal plate connected to a gate electrode or the like extends in an eave shape between the gate electrode and the drain electrode. Usually, an insulating dielectric such as silicon oxide is disposed between the protruding metal plate and the semiconductor crystal. With this structure, a part of the electric field concentrated on the semiconductor crystal near the drain end of the gate electrode is distributed to the insulating dielectric below the metal plate and the semiconductor crystal below it. Since the electric field applied to the crystal layer is reduced, the breakdown voltage of the element is improved. For example, Non-Patent Document 1 can be referred to as such a technique.
JP 2004-200248 A W. Saito, Y. Takada, M. Kuraguchi, K, Tsuda, I. Omura, T. Ogura, Jpn. J. Appl, Phys, Vol. 43, 2239 (2004) X. Hu, A. Koudymov, G. Simin, J. Yang, MA Khan, A. Tarakji, MS Shur, R. Gaska, Appl. Phys. Lett., Vol. 79, 2832 (2001)

  The field plate structure for improving the breakdown voltage of the element has a certain effect. However, new problems arise. That is the generation of current collapse. Current collapse is a phenomenon in which, when a voltage is applied to an electrode, negative charges are accumulated on the surface of the semiconductor crystal layer, and the accumulated charges act on electrons traveling through the channel to cause fluctuations in current value. For this phenomenon, Non-Patent Document 2, for example, can be referred to. Generally, the insulating film used in the field plate structure is an oxide material such as alumina or silicon oxide. When such a material is formed on the surface of the gallium nitride crystal, a high-density surface level is likely to be generated at the interface between the insulating material and the semiconductor crystal. Such a surface state accumulates electric charges in response to input of a gate signal and fluctuation of drain voltage, and causes current collapse.

  In order to avoid this problem, for example, Patent Document 1 discloses a technique for reducing the current collapse by reducing the sites where negative charges are accumulated by disposing a silicon nitride passivation film at the interface between the oxide insulating layer and the semiconductor layer. However, such a process using a multilayer dielectric film is expensive, and in addition, the control parameters for the threshold value and the like are increased.

  An object of the present invention is to provide a field effect transistor that can solve the above-mentioned problems in the prior art.

  An object of the present invention is to provide a GaN-HFET that has a high breakdown voltage, has a small current collapse, and can be manufactured at a relatively low cost.

  The field effect transistor according to the present invention is characterized in that an indium aluminum nitride layer formed thicker than an electron supply layer used in a general GaN-HFET is used as an electron supply layer. The most common material for the electron supply layer and the electron transit layer of the GaN-HFET is a combination in which the former is aluminum gallium nitride and the latter is gallium nitride. However, in the case of this combination, aluminum gallium nitride has a lattice mismatch with gallium nitride, so there is a limit to increasing the film thickness, and it is usually used in the range of 8 nm to 50 nm. By reducing the composition of aluminum, the degree of mismatch can be reduced as much as possible. However, the polarization of the electron transit layer is reduced, and at the same time, the potential well to be formed at the interface cannot be formed, and the two-dimensional electron gas is reduced. Not formed. Accordingly, the electron supply layer cannot be formed thick in the conventional system described above.

  In a system using indium aluminum nitride for the electron supply layer, it is theoretically possible to form a two-dimensional electron gas by lattice-matching the crystals of the electron supply layer and the electron transit layer. However, there is no example in which the electron supply layer is deposited thicker than 50 nm. According to the present invention, since the electron supply layer can be made thicker, the distance between the semiconductor crystal surface and the electron transit layer can be increased, and even if charges accumulate on the crystal surface of the electron supply layer, the transit electron Can be reduced, and current collapse can be suppressed.

  The field effect transistor according to the present invention has a recess structure (recess) in a thick indium aluminum nitride layer formed as an electron supply layer, and at least a part of the gate electrode is formed on the bottom surface of the recess structure, and The second feature is that the drain side end of the gate electrode is formed on the electron supply layer other than the bottom surface of the recess. With this feature, a field plate structure can be formed without forming an insulating dielectric film such as an oxide. This is because, in this structure, by forming a thick semiconductor crystal layer, an electric field can be effectively dispersed in the semiconductor crystal layer immediately below the field plate edge, as in the case of forming an oxide film. . With these effects, it is possible to realize a field effect transistor having a small current collapse and a high gate breakdown voltage.

  The field effect transistor according to the present invention has a recess structure in an indium aluminum nitride layer formed thicker than usual as an electron supply layer, and at least a part of the drain electrode is formed on the bottom surface of the recess structure, and the drain A third feature is that the gate end of the electrode is formed on an unrecessed electron supply layer. With this feature, a field plate structure can be formed near the drain electrode without forming an insulating dielectric film such as an oxide film, and the drain breakdown voltage can be further increased.

  Furthermore, since the proposed field effect transistor does not require the formation of an insulating dielectric such as an oxide film, the device manufacturing process can be simplified as compared with a GaN-HFET having a general field plate structure. It can be manufactured at low cost.

According to the first aspect of the present invention, in the gallium nitride field effect transistor, an electron transit layer composed of gallium nitride and a structural formula In _x AI _1-x N (0.13 ≦ x ≦ 0.22) And an electron supply layer having a thickness greater than 50 nm and having a recess for accommodating the electrode, and at least a part of the gate electrode or the drain electrode is formed in the recess. A field effect transistor characterized by being formed on the bottom surface is proposed.

  According to a second aspect of the invention, there is proposed a field effect transistor according to the first aspect of the invention, wherein the drain side end of the gate electrode is formed on an electron supply layer other than the bottom surface of the recess.

  According to a third aspect of the invention, in the first aspect of the invention, the field effect according to the first aspect, wherein the drain side end of the gate electrode is formed on the electron supply layer other than the recess. A transistor is proposed.

  According to a fourth aspect of the present invention, there is proposed a field effect transistor according to the first aspect, wherein a gate side end of the drain electrode is formed on an electron supply layer other than the bottom surface of the recess.

  According to a fifth aspect of the present invention, there is proposed a field effect transistor according to the first aspect of the present invention, wherein a gate side end portion of the drain electrode is formed on a portion other than the concave portion of the electron supply layer.

  According to the present invention, it is possible to manufacture a high-performance field effect transistor having a small current collapse and a high breakdown voltage characteristic at low cost.

  Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a schematic cross-sectional view for explaining an example of an embodiment of a field effect transistor according to the present invention. The field effect transistor 1 shown in FIG. 1 is a gallium nitride-based heterojunction field effect transistor. Here, the field effect transistor 1 is formed on a substrate in which a buffer layer 102 is formed on a base substrate 101.

  As the base substrate 101, a single or little difference in lattice multiplier between the epitaxial layer formed on the base substrate 101, such as a silicon carbide substrate, a sapphire substrate, a silicon substrate, a gallium nitride substrate, or a gallium arsenide substrate, is provided. A crystal substrate can be used. The base substrate 101 is preferably semi-insulating, but even if it is conductive, it cannot be used. A commercially available base substrate 101 can be used.

  The buffer layer 102 provided on the base substrate 101 reduces strain caused by a difference in lattice constant between the various semiconductor crystal layers provided on the base substrate 101 and the base substrate 101, and the base substrate 101. It has been introduced for the purpose of preventing the influence of impurities contained in. As the material of the buffer layer 102, aluminum nitride, aluminum gallium nitride, gallium nitride, or the like can be used. The buffer layer 102 can be formed by the MOVPE method, the MBE method, the HVPE method, or the like. As the raw material to be used, since a raw material suitable for each growth method is commercially available, it is preferable to use this. Although there is no restriction | limiting in particular in the thickness of the buffer layer 102, Usually, it is the range of 300 nm-3000 nm.

  An electron transit layer 103 is formed on the buffer layer 102. Gallium nitride can be used as the material of the electron transit layer 103. As the formation method, MOVPE method, MBE method, and HVPE method can be used. Since the raw material used for forming the electron transit layer 103 is commercially available for each growth method, it is preferable to use this. Although there is no restriction | limiting in particular in the thickness of the electron transit layer 103, Usually, it is the range of 500 nm to 5000 nm, More preferably, it is the range of 1000 nm to 3000 nm, More preferably, it is the range of 1200 nm to 2500 nm. When the electron transit layer 103 is formed, doping is not usually performed, but a small amount of silicon may be doped for the purpose of increasing channel carriers. As each raw material used for forming the electron transit layer 103, a raw material suitable for each growth method is commercially available.

  An electron supply layer 104 is formed on the electron transit layer 103. The electron supply layer 104 is formed as an indium aluminum nitride layer. As the formation method, MOVPE method, MBE method, and HVPE method can be used. As the raw material to be used, since a raw material suitable for each growth method is commercially available, it is preferable to use this.

  The thickness of the electron supply layer 104 is set in a range thicker than 50 nm. If the thickness is less than 50 nm, the influence of current collapse is large, and the effect of the field plate formed on the electron transit layer 103 is insufficient, so that the breakdown voltage cannot be improved. The upper limit of the thickness of the electron supply layer 104 is not particularly limited, but the thickness of the electron supply layer 104 is generally 2000 nm or less from the viewpoint of ease of processing and industrial production efficiency. The thickness of the electron supply layer 104 is determined within the above-described range, and also in a range where the crystal lattice is relaxed in balance with the indium composition, that is, a range that is thinner than the critical thickness.

The indium composition of indium aluminum nitride lattice-matched to gallium nitride is x = 0.18 in the structural formula In _x AI _1-x N (0.13 ≦ x ≦ 0.22). It can be formed infinitely thick. When the indium composition of indium aluminum nitride is higher or lower than this, tensile strain or compressive strain is generated in the electron supply layer 104, respectively, and the limit of the laminated film thickness occurs. The critical film thickness decreases as the difference between the set composition and x = 0.18 increases.

  According to the study by the present inventors, this critical film thickness is about 1000 nm when the composition x = 0.17 and about 400 nm when the composition x = 0.16 in the composition on the side where tensile strain occurs. Yes, about 200 nm when the composition x = 0.15, about 80 nm when the composition x = 0.14, and about 50 nm when the composition x = 0.13. On the side where compressive strain occurs, when x = 0.19, it is approximately 800 nm, when composition x = 0.20, it is approximately 300 nm, when composition x = 0.21, it is approximately 150 nm, and composition x = 0. .22, approximately 50 nm.

  Further, within this range, the film thickness may be selected in consideration of the breakdown voltage and the current collapse. From the viewpoint of reducing current collapse, the electron supply layer 104 is preferably as thick as possible. On the other hand, it is preferable that there is an appropriate thickness in order to improve the breakdown voltage. The mechanism for improving the breakdown voltage by using the field plate structure is to disperse the electric field concentrated on the semiconductor crystal layer under the electrode end in the crystal layer under the field plate, so that the semiconductor crystal layer under the field plate is too thick The electric field is mostly applied to the semiconductor crystal layer under the gate electrode, so that the effect of dispersion cannot be obtained and the breakdown voltage cannot be improved. On the other hand, if it is too thin, the electric field is excessively distributed to the crystal layer under the field plate, and this portion of the crystal layer is destroyed, so that the breakdown voltage cannot be improved. From a comprehensive viewpoint including this viewpoint, the thickness of the electron supply layer 104 is preferably 50 nm to 2000 nm, more preferably 100 nm to 1000 nm, and most preferably 200 nm to 800 nm.

  The composition of indium is determined in the range of 0.13 to 0.22. If it deviates from this range, there is a problem that the crystal relaxes as described above, so that the film thickness of indium aluminum nitride cannot be set sufficiently thick, and the effect of suppressing current collapse cannot be expected.

  The indium composition is related to the amount of free carriers generated in the channel. That is, if the composition is lower than the lattice-matching composition 0.18, tensile strain occurs in the electron supply layer, and a piezo electric field having the same polarity as the spontaneous polarization existing in the electron supply layer 104 is generated. And the free carriers in the electron transit layer 103 increase. On the other hand, if the composition is higher than 0.18, a piezo electric field that cancels the spontaneous polarization is generated in the electron supply layer 104, and the electrons in the electron transit layer are reduced or depleted. From these viewpoints, the indium composition can be appropriately selected according to the operation mode of the transistor to be manufactured and a desired current value, but is generally 0.13 to 0.22, preferably 0.15 to 0.20, More preferably, it is 0.17 to 0.19, Most preferably, it is 0.175 to 0.185.

  A gate recess structure 105 is formed in the electron supply layer 104. The gate recess structure 105 is a recess for accommodating all or part of the electrode. Here, the gate recess structure 105 is formed as a groove extending in a direction perpendicular to the paper surface in FIG. The recess depth of the gate recess structure 105 is set based on a balance between a desired mutual conductance and a current value. That is, if the indium aluminum nitride layer in the recess portion where the gate recess structure 105 is formed is thinned, the transconductance of the transistor is increased, and the gain is increased. On the other hand, if the thickness is reduced, the polarization of the electron supply layer is reduced, so that the channel resistance increases and the current value decreases. From such a viewpoint, the thickness of the electron supply layer of the gate recess structure 105 is usually determined in the range of 5 nm to 200 nm, preferably 8 nm to 100 nm, more preferably 10 nm to 70 nm, and most preferably 12 nm to 50 nm. The recess processing for forming the gate recess structure 105 can be performed using a reactive gas such as a reactive ion etching (RIE) using a photoresist or the like as a mask. After the processing, the processed substrate may be annealed in the range of 200 ° C. to 600 ° C. in a nitrogen atmosphere for the purpose of recovering damage to the crystal surface caused by etching.

  A drain recess structure 106 is also formed in the electron supply layer 104. Similarly to the gate recess structure 105, the drain recess structure 106 is a recess for accommodating all or part of the electrode. The drain recess structure 106 is for reducing the contact resistance of the drain electrode 109 and for further improving the breakdown voltage of the element by forming a field plate structure in the drain electrode 109. The recess depth is set so that the thickness of the indium aluminum nitride is 10 nm to 50 nm. This processing can be performed by RIE etching in the same manner as the gate recess structure 105.

  A source recess structure 107 is further formed in the electron supply layer 104. Similarly to the gate recess structure 105, the source recess structure 107 is a recess for accommodating all or part of the electrode. The source recess structure 107 is provided to reduce the contact resistance of the source electrode 110. The recess depth of the source recess structure 107 is set so that the thickness of the indium aluminum nitride is 10 nm to 50 nm. The processing for forming the source recess structure 107 can be performed by RIE etching similarly to the gate recess structure 105.

  A gate electrode 108 is formed in the gate recess structure 105. As a material of the gate electrode 108, for example, a laminated structure of Ni and gold can be used. For example, a vapor deposition method can be used as the formation method, and the gate electrode 108 is formed so that at least a part thereof is in contact with the bottom surface of the gate recess structure 105. The drain side end of the gate electrode 108 is positioned so as to protrude from the surface of the electron supply layer 104 so that the gate electrode 108 forms a field plate structure. With such an arrangement, electric lines of force extending so as to concentrate toward the drain end of the gate electrode 108 from the positive fixed charge existing at the electron supply layer side interface between the electron supply layer 104 and the electron transit layer 103. Since a part thereof is dispersed at the drain side end of the field plate, the gate breakdown voltage can be improved and the breakdown breakdown voltage of the element can be improved.

  In FIG. 1, the sidewall of each recess structure is formed vertically, but this vertical portion may be formed in a step shape. Since such a configuration can reduce the height per step, it is effective in preventing disconnection of the metal constituting the field plate. In FIG. 1, the drain side end of the gate electrode 108 is positioned on the surface of the electron supply layer 104. In the example shown in the figure, the field plate metal and the electron supply layer 104 are in direct contact with each other, but a dielectric may be sandwiched therebetween.

  A drain electrode 109 is provided in the drain recess structure 106 so as to accommodate a part thereof. As a material of the drain electrode 109, for example, a laminated structure of titanium and gold can be used. The drain electrode 109 is formed so that at least a part of the electrode is in contact with the bottom surface of the drain recess structure 106. Further, the gate side end portion of the drain electrode 109 is positioned so as to protrude from the surface of the electron supply layer 104 so that a part of the drain electrode 109 forms a field plate structure. With the gate field plate structure of the drain electrode 109 formed by such a structure, the drain breakdown voltage can be improved for the same reason as described above, and the breakdown breakdown voltage of the element can be improved.

  In FIG. 1, the side wall of the drain recess structure 106 is formed vertically, but this portion may be formed in a step shape to form an inclined wall surface. This is the same reason as described above. In FIG. 1, the gate end of the drain electrode 109 is located on the surface of the electron supply layer 104, but it may be arranged on the step of the side wall formed in a step shape.

  A source electrode 110 is formed on the electron supply layer 104. As an electrode material of the source electrode 110, for example, a laminated structure of Ti and gold can be used. For example, a vapor deposition method can be used as the formation method.

  What is indicated by reference numeral 113 is an insulating portion for element isolation. By providing such a portion, it is possible to prevent elements from electrically interfering with each other when a plurality of field effect transistors having the above-described layer structure are arranged on a substrate. Such an insulating portion can be manufactured by forming a separation groove by nitrogen ion implantation or RIE.

  In the above, the present invention has been described based on an example of the embodiment. However, the embodiment of the present invention disclosed above is merely an example, and the technical scope of the present invention is limited to these embodiments. It is not limited.

  Hereinafter, the present invention will be described in more detail with reference to examples. However, the examples of the present invention described below are merely examples, and the present invention is not limited thereto.

(Example)
A gallium nitride field effect transistor 2 having the structure shown in FIG. 2 was produced as follows.

  First, a silicon carbide base substrate 201 having a growth surface of (0001) plane and an off angle of 0.5 ° is set in a growth furnace, and an aluminum nitride buffer layer 202 is formed on the surface of the base substrate 201 by an MOCVD method at 2000 nm. Growing to the thickness of. Subsequently, the source gas was switched, and the gallium nitride crystal layer 203 was grown to a thickness of 2000 nm to form the electron transit layer 203. Subsequently, the source gas was switched, the substrate temperature was changed, and indium aluminum nitride having an indium composition of 0.177 was grown to a thickness of 430 nm, whereby the electron supply layer 204 was formed. Thus, an epitaxial crystal substrate for a gallium nitride field effect transistor was obtained.

  Then, a predetermined resist opening was formed in the epitaxial crystal substrate by lithography, and then an element isolation groove 213 was formed to a depth of 600 nm by RIE using chlorine gas. Thereafter, resist openings were formed in the shape of the source electrode 209 and the drain electrode 210 by a lithography method in the same manner. After the opening was formed, the electron transit layer (indium aluminum nitride layer) 204 was etched to a depth of 400 nm by RIE to form the drain recess structure 206 and the source recess structure 207. Thereafter, a Ti / Al / Ni / Au metal film was formed to a thickness of 20 nm / 200 nm / 25 nm / 500 nm by a vapor deposition method, and then processed into a predetermined shape by a lift-off method. Thereafter, the substrate was heated in a nitrogen atmosphere at 820 ° C. for 30 seconds to form the source electrode 209 and the drain electrode 210.

  Next, the gate recess structure 205 was formed as follows. First, after the surface of the electron supply layer 204 and a predetermined resist opening were similarly formed by lithography, the electron supply layer (indium aluminum nitride layer) 204 was etched to a depth of 100 nm by RIE to form an etching layer. . Next, a resist opening was formed at the bottom of the etching groove by the same lithography method, and the indium aluminum nitride of the electron supply layer 204 was etched to a depth of 100 nm by RIE. This lithography and RIE are repeated two more times, and a stepped recess side surface having a thickness of the indium aluminum nitride layer at the recess bottom portion of 30 nm, a step height of the step portion of 100 nm, and a step width of 500 nm is obtained. A gate recess structure 205 is formed in the electron supply layer 204. Subsequently, the substrate was annealed at 500 ° C. for 20 minutes in a nitrogen atmosphere.

  Next, an opening is formed in a predetermined shape in the electron supply layer 204 by a lithography method, a Ni / Au metal film is formed by a vapor deposition method to a thickness of 25 nm / 150 nm, and then processed into a predetermined shape by a lift-off method did. Thus, the field effect transistor 2 having the structure shown in FIG. 2 was obtained. The distance between the source electrode 210 and the gate electrode 208 of the fabricated field effect transistor 2 is 3 μm. The distance between the gate electrode 208 and the drain electrode 209 is 7 μm. The gate length is 1.0 μm. The gate width is 30 μm. The drain side end of the gate electrode 208 is located at a position of 3 μm from the drain electrode.

(Comparative example)
As a comparative example, a gallium nitride field effect transistor 3 shown in FIG. 3 was produced in the same manner as in the production of the above example. The field effect transistor 3 has the same configuration and manufacturing method as those of the transistors described in the embodiments except that the electron supply layer 303 has a thickness of 30 nm and the electron supply layer 303 does not have a recess structure. Of the parts in FIG. 3, the parts corresponding to the parts in FIG.

  The off breakdown voltages of the field effect transistors 2 and 3 of the example and comparative example thus fabricated were evaluated. The source electrode is grounded, −13 V, which is a voltage equal to or lower than the threshold voltage (−9.5 V in the fabricated device), is applied to the gate electrode, the drain voltage is applied in the positive direction, and the current value is 1 mA / mm. Was defined as the breakdown voltage of the device, the breakdown voltage of the device of the example showed an extremely high value of 240V. On the other hand, the breakdown voltage of the comparative device was 160V.

  Next, each current collapse of the field effect transistors 2 and 3 of Examples and Comparative Examples was evaluated. When the source electrode is installed and the drain electrode voltage is switched from 20 V to 1 V with -3 V applied to the gate electrode, the difference between the current value after 100 ms and the current value after 2000 ms is the current collapse. It was defined as quantity and evaluated. As a result, in the comparative transistor, the current collapse amount was 16 mA / mm, whereas in the example transistor, the current collapse amount was 2 mA / mm. From the above results, it was found that the GaN-HFET according to the present invention has excellent characteristics.

The typical sectional view showing an example of the embodiment of the invention. The typical sectional view of the example of the present invention. The typical sectional view of a comparative example.

Explanation of symbols

101, 201, 301 Underlying substrate 102, 202, 302 Buffer layer 103, 203, 303 Electron traveling layer 104, 204, 304 Electron supply layer 105, 205 Gate recess structure 106, 206 Drain recess structure 107, 207 Source recess structure 108, 208, 308 Gate electrodes 109, 209, 309 Drain electrodes 110, 210, 310 Source electrodes 113, 213, 313 Device isolation

Claims (5)

In gallium nitride field effect transistors,
An electron transit layer composed of gallium nitride;
Electron supply made of indium aluminum nitride represented by the structural formula In _x AI _1-x N (0.13 ≦ x ≦ 0.22) and having a recess for accommodating an electrode, the thickness being greater than 50 nm Comprising a layer,
A field effect transistor, wherein at least a part of a gate electrode or a drain electrode is formed on a bottom surface of the recess.   The field effect transistor according to claim 1, wherein a drain side end portion of the gate electrode is formed on an electron supply layer other than a bottom surface of the recess.   The field effect transistor according to claim 1, wherein a drain side end portion of the gate electrode is formed on the electron supply layer other than the concave portion.   The field effect transistor according to claim 1, wherein a gate side end of the drain electrode is formed on an electron supply layer other than the bottom surface of the recess.   The field effect transistor according to claim 1, wherein a gate side end portion of the drain electrode is formed on a portion other than the concave portion of the electron supply layer.

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