JP2008251620A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for shortening a time required for manufacturing a semiconductor device having reduced on-voltage. <P>SOLUTION: The manufacturing method is provided with a step of forming dummy trenches 35 (second trenches) each having a bottom surface 37, positioned inside a body region 50 between adjacent trenches 30 (first trenches) from the surface of the body region 50; a step of covering the surface of the body region 50, with a mask opened on the dummy trenches 35; and a step of injecting an n-type (first conductivity-type) impurity into the inside of the dummy trench 35 over the mask to form an n-type carrier mobility suppressing region 70 around the bottom surface 37 of each of the dummy trenches 35. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device with reduced on-voltage and a method for manufacturing the same. In particular, the present invention relates to a semiconductor device capable of reducing the time required for manufacturing and a manufacturing method thereof.

  A technique for reducing the on-voltage or on-resistance of a semiconductor device has been studied. As an example, Patent Document 1 discloses an IGBT that can reduce the on-voltage. As shown in FIG. 10 attached to the present specification, the IGBT 100 includes a gate electrode G that controls ON / OFF of a current flowing between the emitter electrode E and the collector electrode C.

Here, the operation of the IGBT 100 in the on state will be described. In order to turn on the IGBT 100, the emitter electrode E is grounded, a positive voltage is applied to the collector electrode C, and a gate voltage higher than the threshold is applied to the trench gate electrode 134 via the gate electrode G. As a result, a portion of the p-type body region 150 facing the trench gate electrode 134 via the gate insulating film 132 is inverted to the n-type, and a channel region is formed. Majority carriers (electrons) emitted from the n-type emitter region 160 are injected into the n ⁻ -type drift region 120 through the channel region and accumulated in the n ⁺ -type buffer region 140. When majority carriers accumulate in the buffer region 140, the contact potential difference between the buffer region 140 and the p ⁺ -type collector region 142 decreases, and minority carriers (holes) are injected from the collector region 142 into the buffer region 140 and the drift region 120. As a result, a conductivity modulation phenomenon occurs in the buffer region 140 and the drift region 120, and the IGBT 100 is turned on at a low on voltage. Minority carriers injected from the collector region 142 are recombined with the majority carriers and disappear, or are discharged to the grounded emitter electrode E via the body region 150 and the body contact region (not shown). Is done. The body contact region is formed at any position in the depth direction of the cross section of the IGBT 100 shown in FIG. The body contact region is formed facing the surface 111 a of the semiconductor substrate 111 and is connected to the emitter electrode E together with the emitter region 160.

  In the case of the IGBT 100, a carrier movement suppression region 170 is formed between the body region 150 and the drift region 120. The carrier movement suppression region 170 has a lower concentration than the emitter region 160 and contains an n-type impurity at a higher concentration than the drift region 120. Due to the potential barrier formed at the interface between the carrier movement suppression region 170 and the body region 150, minority carriers discharged to the emitter electrode E are likely to accumulate in the drift region 120. Thereby, in the IGBT 100, the minority carrier concentration between the emitter electrode E and the collector electrode C is increased, and the on-voltage is reduced.

The manufacturing method of IGBT100 is demonstrated with reference to FIGS.
In order to manufacture the IGBT 100, first, an n ⁻ type semiconductor substrate 111 is prepared.
As shown in FIG. 11, a mask A is selectively formed on the surface 111 a of the semiconductor substrate 111. Then, n-type impurities are implanted through the mask. In FIG. 11, the implanted n-type impurity is schematically indicated by cross marks.
Next, as shown in FIG. 12, the semiconductor substrate is heat-treated to diffuse the implanted impurities from the surface 111a to a deep position. As a result, an n-type impurity diffusion region N11 is formed.
Next, as shown in FIG. 13, a p-type body region 150 is formed by injecting and diffusing p-type impurities from the surface 111a. At this time, the body region 150 is formed so that a part of the n-type diffusion region N11 remains below the body region 150.
Thereafter, formation of the trench 130, formation of the gate insulating film 132, formation of the trench gate electrode 134, formation of the emitter region 160, and the like are performed by a general method to manufacture the IGBT 100.

FIG. 14 shows the impurity concentration M corresponding to the depth D from the surface 111 a of the IGBT 100. In FIG. 14, the solid line indicates the concentration of the n-type impurity. Further, the concentration of the p-type impurity is indicated by a one-dot chain line.
Here, in a semiconductor region containing both p-type impurities and n-type impurities, it can be considered that impurities of the same concentration are substantially offset. The semiconductor region becomes a semiconductor region having the same conductivity type as the impurity having a higher concentration.
Therefore, as shown in FIG. 14, in a region shallow from the surface 111a, a p-type semiconductor region is formed by the diffusion region P11 of the p-type impurity. This region becomes the body region 150. Under the body region 150, an n-type semiconductor region is formed by an n-type impurity diffusion region N11. This area becomes the carrier movement suppression area 170.
In FIG. 14, since the concentration of the n-type impurity contained in the semiconductor substrate 111 is thin, it is omitted.

JP 2005-347289 A

In the conventional technique, as shown in FIGS. 11 and 12, an n-type impurity diffusion region N <b> 11 is formed in order to form the carrier movement suppression region 170. In the step of forming the diffusion region N11, n-type impurities are implanted into the surface 111a, and the implanted impurities are diffused from the surface 111a to a deep position by performing heat treatment. Therefore, it is necessary to perform the heat treatment for a long time.
The present invention has been devised to solve the above problems. That is, the present invention provides a technique for shortening the time required for manufacturing a semiconductor device that reduces the on-voltage.

  According to the method of manufacturing a semiconductor device of the present invention, a second conductivity type impurity is implanted from the surface of the first conductivity type semiconductor layer, and a second conductivity type body region is formed in a region from the surface of the semiconductor layer to a predetermined depth. A step of forming a plurality of first trenches whose bottom surfaces protrude from the surface of the body region to the first conductivity type semiconductor layer, and a surface of the body region between adjacent first trenches. A step of forming a second trench whose bottom surface is located in the body region; a step of covering the surface of the body region with a mask opened in the second trench; A step of forming a first conductivity type carrier movement suppression region around the bottom surface of the second trench, a step of removing the mask, and facing the surface of the body region and in contact with the first trench. In circumference, the first conductivity type impurity is implanted, and a step of forming an emitter region of the first conductivity type. A gate insulating layer and a trench gate electrode are formed in the first trench by a known method.

The order in which the above steps are performed is not limited to the order described above.
The step of forming the first trench and the step of forming the second trench may be performed simultaneously or separately.
“Inside the body region” where the bottom surface of the second trench is located includes the case where the bottom surface of the second trench coincides with the interface between the body region and the first conductivity type semiconductor layer.
One second trench may be formed between adjacent first trenches, or a plurality of second trenches may be formed.
The depths of the bottom surfaces of the plurality of second trenches may be all located at the same depth. Alternatively, a plurality of types of second trenches having different bottom depths may be included in the plurality of second trenches. For example, when forming both the second trench whose bottom surface is located at the first depth in the body region and the second trench whose bottom surface is located at the second depth in the body region, impurities are implanted into the inner surfaces thereof. Thus, the carrier movement suppression region to be formed can be formed in both the first depth region and the second depth region.
Further, the carrier movement suppression region may be continuous between adjacent first trenches or may not be continuous.

The semiconductor device of the prior art also includes a carrier movement suppression region in order to suppress the movement of minority carriers (holes in the case of an n-channel IGBT) and easily accumulate carriers in the drift region. In the conventional semiconductor device, the first conductivity type diffusion region for forming the carrier movement suppression region is formed by implanting the first conductivity type impurity into the surface of the semiconductor layer. Then, the implanted impurities are diffused from the surface to a deep position by performing heat treatment. For this reason, the time required for heat treatment was long.
In the method for manufacturing a semiconductor device disclosed in this specification, a second trench is formed from the surface of the semiconductor layer, the bottom surface of which is located in the body region. A carrier movement suppression region is formed by implanting a first conductivity type impurity toward the inner surface of the second trench. Impurities are directly implanted into the deep region from the surface in the body region using the second trench. Therefore, the heat treatment time required for diffusion of the implanted impurities can be shortened.

The present invention realizes a novel semiconductor device.
The semiconductor device includes a plurality of first conductivity type emitter regions, a second conductivity type body region, a first conductivity type drift region, a first conductivity type carrier movement suppression region, a first trench, A gate insulating layer, a trench gate electrode, and a second trench. The emitter region is formed facing a part of the surface of the semiconductor layer. The body region surrounds the emitter region and is formed in a region from the surface of the semiconductor layer to a predetermined depth. The drift region is formed below the body region, and is separated from the emitter region by the body region. The carrier movement suppression region is formed in an intermediate depth region in the body region and / or a region sandwiched between the body region and the drift region, and is separated from the emitter region by the body region. The first trench extends from the surface of each emitter region through the body region, and its bottom surface projects into the drift region. The gate insulating layer covers the inner surface of the first trench. The trench gate electrode is accommodated in the first trench in a state surrounded by the gate insulating layer. The second trench is formed between the adjacent first trenches, and extends from the surface of the body region to the carrier movement suppression region.
According to the semiconductor device described above, by implanting impurities toward the inner surface of the second trench, the first conductivity type impurity diffusion region for forming the carrier movement suppression region can be easily formed in a short time.

The carrier movement suppression region may include a first conductivity type impurity, and the concentration of the impurity may be higher as it approaches the second trench.
The carrier movement suppression region preferably extends continuously between adjacent first trenches.
By providing the carrier movement suppression region having the above configuration, it is possible to sufficiently suppress the movement of minority carriers to the emitter electrode connected to the emitter region. Therefore, sufficient minority carriers can be accumulated in the drift region.

Further, the insulating layer covering the inner surface of the second trench, the conductive member enclosed in the second trench in a state surrounded by the insulating layer, the trench gate electrode, and the conductive member are connected. A gate electrode may be provided.
An insulating layer covering the inner surface of the second trench; a conductive member enclosed in the second trench in a state surrounded by the insulating layer; a gate electrode connected to the trench gate electrode; and an emitter An emitter electrode connected to the region and the conductive member may be provided.
Note that the second trench may be filled with an insulating layer. According to this configuration, the gate capacitance of the semiconductor device can be reduced.

  According to the present invention, a semiconductor device having a low on-voltage can be manufactured in a short time.

The main features of the embodiments described below are listed.
(First Feature) The semiconductor device is a vertical IGBT having a trench gate electrode.
(Second Feature) The carrier movement suppression region 70 is formed in an intermediate depth region of the body region 50 (FIG. 1).
(3rd characteristic) The carrier movement suppression area | region 70a is formed in the area | region pinched | interposed into the body area | region 50 and the drift area | region 20 (FIG. 8).
(4th characteristic) The bottom face of several 2nd trench is located in the same depth in a body area | region.
(Fifth feature) A second trench having a bottom surface located at a first depth in the body region and a second trench having a bottom surface located at a second depth in the body region are provided (FIG. 9).
(Sixth feature) The opening of the trench 30 is larger than the opening of the dummy trench 35 (second trench).
(Seventh feature) The trench 30 and the dummy trench 35 (second trench) are formed simultaneously.
(Eighth Feature) An n-type impurity is implanted into the bottom surface 37 of the dummy trench 35 (second trench) to form an n-type impurity diffusion region for the carrier movement suppression region 70.
(Ninth Feature) An n-type impurity is implanted obliquely into the side surface in the vicinity of the bottom surface 37 of the dummy trench 35 (second trench) to form an n-type impurity diffusion region for the carrier movement suppression region 70.

(First embodiment)
Embodiments of a semiconductor device embodying the present invention and a manufacturing method thereof will be described with reference to FIGS. In this embodiment, the present invention is applied to a trench gate type vertical IGBT. A feature of the semiconductor device 10 of this embodiment is that a carrier movement suppression region 70 is formed in an intermediate depth region of the body region 50 as shown in FIG. Further, a dummy trench 35 (an example of the second trench) extending from the surface 11a of the semiconductor substrate 11 into the carrier movement suppression region 70 is formed. The carrier movement suppression region 70 is formed by implanting n-type impurities toward the inner surface of the dummy trench 35.

The configuration of the semiconductor device 10 will be described with reference to the cross-sectional view of FIG.
The semiconductor device 10 includes an emitter electrode E connected to the surface 11 a of the semiconductor substrate 11. The semiconductor device 10 includes a plurality of n ⁺ -type emitter regions 60 facing the surface 11 a of the semiconductor substrate 11 and connected to the emitter electrode E. Further, the semiconductor device 10 includes a p ⁺ type body contact region (not shown). The body contact region is formed at a position in the depth direction of the cross section of FIG. 1 and faces the surface 11 a of the semiconductor substrate 11. The body contact region is connected to the emitter electrode E together with the emitter region 60. Further, the semiconductor device 10 includes a p-type body region 50 that surrounds the emitter region 60 and the body contact region and is continuously formed in a region from the surface 11a to a predetermined depth. An n ⁻ type drift region 20 separated from the emitter region 60 by the body region 50 is formed below the body region 50.

  In the intermediate depth region 53 in the body region 50, an n-type carrier movement suppression region 70 is formed. The carrier movement suppression region 70 is formed continuously between adjacent trenches 30 (first trench example). The concentration of the n-type impurity in the carrier movement suppression region 70 is lower than that of the emitter region 60 and higher than that of the drift region 20. The carrier movement suppression region 70 is separated from the emitter region 60 and the drift region 20 by the body region 50. Here, the body region 50 disposed on the carrier movement suppression region 70 is referred to as an upper body region 51. The body region 50 disposed below the carrier movement suppression region 70 is referred to as a lower body region 52.

  The trench 30 (an example of the first trench) extends from the surface of the emitter region 60 in the depth direction of the semiconductor substrate 11 (downward in FIG. 1). The trench 30 penetrates through the body region 50 and its bottom surface 31 protrudes into the drift region 20. Further, the trench 30 extends long in the depth direction of the drawing. The inner surface of the trench 30 is covered with a gate insulating film 32. The inside is filled with polysilicon. The polysilicon constitutes the trench gate electrode 34. The trench gate electrode 34 is accommodated in the trench 30 while being surrounded by the gate insulating film 32. The trench gate electrode 34 faces the body region 50 with the gate insulating film 32 interposed therebetween. The trench gate electrode 34 is connected to the gate electrode G and insulated from the emitter electrode E.

  The semiconductor device 10 further includes a dummy trench 35 (an example of a second trench). A plurality of dummy trenches 35 are formed between adjacent trenches 30. The dummy trench 35 is. It extends from the surface of the body region 50 to the inside of the carrier movement suppression region 70. In FIG. 1, three dummy trenches 35 are schematically illustrated between adjacent trenches 30, but more dummy trenches 35 are actually formed between adjacent trenches 30. . The inner surface of the dummy trench 35 is covered with an insulating film 36. The inside is filled with polysilicon (conductive member 38). The conductive member 38 is accommodated in the dummy trench 35 while being surrounded by the insulating film 36.

Further, the semiconductor device 10 includes an n ⁺ -type buffer region 40 in contact with the drift region 20 on the back surface side of the drift region 20. The semiconductor device 10 further includes a p ⁺ -type collector region 42 that is in contact with the buffer region 40. The collector region 42 is connected to the collector electrode C formed on the back surface 11 b of the semiconductor substrate 11.

A method for manufacturing the semiconductor device 10 will be described with reference to FIGS. FIG. 7 shows the impurity concentration M corresponding to the depth D from the surface 11 a of the semiconductor substrate 11 of the semiconductor device 10. In FIG. 7, the concentration of the n-type impurity diffusion region N1 is shown by a solid line graph. Further, the concentration of the diffusion region P1 of the p-type impurity is shown by a one-dot chain line graph.
In order to manufacture the semiconductor device 10, an n ⁻ type semiconductor substrate 11 is prepared.
First, as shown in FIG. 2, p-type impurities are implanted from the surface 11 a of the semiconductor substrate 11. Thereafter, heat treatment is performed to form a p-type impurity diffusion region P1 having a concentration profile shown in FIG. The diffusion region P1 is formed to a depth of about 4.5 μm from the surface 11a.

Next, a mask for simultaneously forming the trench 30 and the dummy trench 35 is formed on the surface 11a. In the mask, openings are respectively formed at positions where the trench 30 and the dummy trench 35 are formed. The opening width H2 for the dummy trench 35 of the mask R is about ¼ of the opening width H1 for the trench 30 of the mask R. In this state, the trench 30 and the dummy trench 35 are simultaneously formed by anisotropic etching. Further, the opening width H <b> 2 of the dummy trench 35 is narrower than the opening width H <b> 1 of the trench 30. For this reason, even if the trench 30 and the dummy trench 35 are formed at the same time, the bottom surface 37 of the dummy trench 35 is formed at a shallower position from the surface 11 a than the bottom surface 31 of the trench 30. As a result, as shown in FIG. 3, a trench 30 that penetrates the body region 50 from the surface 11 a and protrudes into the drift region 20 and a dummy trench 35 in which the bottom surface 31 stays in the drift region 20 are formed.
By the above process, the trench 30 is formed to have a depth of about 5.5 μm. The opening width of the trench 30 is formed to be about 2 μm. The dummy trench 35 is formed to have a depth of about 2.5 μm. The opening width of the dummy trench 35 is formed to be about 0.5 μm. The dummy trenches 35 are formed between adjacent trenches 30 so that the pitch is about 1 μm.

  Next, as shown in FIG. 4, the mask R is removed, and a thermal oxide film of about 0.1 μm is formed on the inner surfaces of the trench 30 and the dummy trench 35. The thermal oxide film formed on the surface 11a is removed. The thermal oxide film formed on the inner surface of the trench 30 becomes the gate insulating film 32.

Next, as shown in FIG. 5, a stencil mask L that opens at a location corresponding to the dummy trench 35 is disposed on the surface 11 a. Then, an n-type impurity is implanted through the stencil mask L toward the inner surface of the dummy trench 35. As shown in FIG. 5, the n-type impurity is implanted in an oblique direction and introduced into the bottom surface 37 of the dummy trench 35 and the semiconductor layer on the side surface in the vicinity of the bottom surface 37.
Then, heat treatment is performed to form an n-type impurity diffusion region N1 as shown in FIG. In this embodiment, since the n ⁻ type semiconductor substrate 11 is used, the semiconductor substrate 11 originally contains a small amount of n type impurities. For this reason, FIG. 7 shows a graph in which the concentration of the n-type impurity in the diffusion region N1 and the concentration of the n-type impurity originally contained in the semiconductor substrate 11 are continuous.

Here, in a semiconductor region containing both p-type impurities and n-type impurities, it can be considered that impurities of the same concentration are substantially offset. The semiconductor region becomes a semiconductor region having the same conductivity type as the impurity having a higher concentration.
The graph of the impurity concentration of the diffusion region N1 and the impurity concentration of the diffusion region P1 in FIG. 7 intersects at the depth x1. The p-type impurity concentration is higher on the surface side than the depth x1, and this region becomes a p-type semiconductor region. This p-type semiconductor region becomes the upper body region 51.
Further, the graph of the impurity concentration of the diffusion region N1 and the impurity concentration of the diffusion region P1 intersect at a depth x2. The n-type impurity concentration is higher on the deeper side than the depth x1 and on the surface side than the depth x2, and this region becomes an n-type semiconductor region. This n-type semiconductor region becomes the carrier movement suppression region 70.
Further, at the depth x3, the n-type impurity concentration originally included in the semiconductor substrate 11 is around the p-type impurity concentration of the diffusion region P1. The p-type impurity concentration is higher on the deeper side than the depth x2 and on the surface side of the depth x3, and this region becomes a p-type semiconductor region. This p-type semiconductor region becomes the lower body region 52.
The n ⁻ type semiconductor region deeper than the depth x 3 becomes the drift region 20.
Thereby, the carrier movement suppression region 70 is formed in the region 53 (refer to FIG. 5 together) having an intermediate depth of the body region 50.
FIG. 7 shows the impurity concentration in the cross section shown in FIG. 1 and divided at a predetermined position in the horizontal direction shown in FIG. When the concentration of the n-type impurity in the diffusion region N1 (and the carrier movement suppression region 70 formed by the diffusion region N1) is observed (not shown) in the lateral direction shown in FIG. The concentration is high. This is because n-type impurities are implanted toward the inner surface of the dummy trench 35.

Next, as shown in FIG. 6, polysilicon is deposited in the trench 30 and the dummy trench 35. The polysilicon deposited on the surface 11a is removed, and an interlayer insulating film 80 is formed on the surface 11a. The interlayer insulating film 80 is formed with a contact hole that exposes the surface of the emitter region 60 in the cross section shown in FIG. Further, a contact hole that exposes the surface of the body contact region is formed in any cross section in the depth direction of FIG. An emitter electrode E connected to the emitter region 60 and the body contact region through these contact holes is formed. Further, the interlayer insulating film 80 is formed with a contact hole exposing the surface of the trench gate electrode 34 and the conductive member 38 accommodated in the dummy trench 35 in any cross section in the depth direction of FIG. Yes. A gate electrode G connected to the trench gate electrode 34 and the conductive member 38 through these contact holes is formed.
Further, the semiconductor substrate 11 is shaved from the back surface to a desired thickness, and each impurity is implanted from the back surface 11b to form an n-type buffer region 40 and a p-type collector region 42. Then, a collector electrode C connected to the collector region 42 is formed.
The order in which the steps are performed is not limited to the order described above. In addition, the heat treatment after the impurity implantation may be performed at least partially. Further, the heat treatment for forming the thermal oxide film may also serve as the heat treatment after the impurity implantation.

The semiconductor device 10 turns on / off the gate voltage applied to the trench gate electrode 34 in a state where the emitter electrode E is grounded and a positive voltage of about several hundred V to 1000 V is applied to the collector electrode C. Thereby, the current flowing between the emitter electrode E and the collector electrode C is turned on / off.
Hereinafter, an operation when the semiconductor device 10 is in the on state will be described.
When a gate voltage equal to or higher than the threshold value is applied to the trench gate electrode 34, the p-type body region 50 facing the trench gate electrode 34 via the gate insulating film 32 is inverted to n-type, and a channel region is formed. As a result, electrons that have flowed out of the n ⁺ -type emitter region 60 are injected into the drift region 20 through the channel region. Further, holes move from the p ⁺ -type collector region 42 toward the drift region 20. Electrons and holes are injected into the drift region 20 to cause a conductivity modulation phenomenon, and the semiconductor device 10 is turned on at a low on voltage. The holes are recombined with electrons and disappear, or discharged to the emitter electrode E through the body region 50 and the body contact region described above.

  In the semiconductor device 10, an n-type carrier movement suppression region 70 that is sandwiched between the upper body region 51 and the lower body region 52 and that is separated from both the emitter region 60 and the drift region 20 is formed. Due to the potential barrier formed at the interface between the carrier movement suppression region 70 and the upper body region 51, minority carriers discharged to the emitter electrode E are likely to accumulate in the drift region 20. This increases the minority carrier concentration between the emitter and collector electrodes and reduces the on-voltage.

Also in the conventional semiconductor device, as shown in FIGS. 12 to 14, in order to suppress the movement of holes and easily accumulate the holes in the drift region 120, the carrier movement suppression region 170 by the n-type impurity diffusion region N <b> 11 is formed. I have. However, in the conventional technique, in order to form the carrier movement suppression region 170, an n-type impurity is implanted into the surface of the semiconductor layer, and the n-type impurity is diffused from the surface 111a to a deep position. Therefore, it takes a long time to perform the heat treatment for impurity diffusion.
In the semiconductor device 10 of the present embodiment, as shown in FIG. 1, a dummy trench 35 having a bottom surface 37 positioned in the body region 50 is formed from the surface 11 a of the semiconductor substrate 11. In order to form the carrier movement suppression region 70, an n-type impurity is implanted toward the inner surface of the dummy trench 35 to form an n-type diffusion region. Impurities can be directly implanted from the surface 11 a into a deep position in the body region 50 using the dummy trench 35. Therefore, it is not necessary to heat and diffuse the implanted impurities for a long time, and the time for performing the heat treatment can be shortened.

In the conventional technique, since the implanted n-type impurity is diffused from the surface 111a to a deep position, the concentration profile of the carrier movement suppression region 70 varies depending on the heat treatment conditions for diffusion and individual differences. It is likely to occur. In the conventional technique, since n-type impurities are implanted into the surface 111a of the semiconductor substrate 111 and diffused from the surface to a deep position, the diffusion region N11 is a diffusion region having the highest concentration on the surface 111a. Can only be formed.
In the manufacturing method of the semiconductor device 10 disclosed in the present invention, since the impurity is directly implanted into the region 53 at the intermediate depth of the body region 50 that forms the carrier movement suppression region 70, the desired range can be easily obtained. In addition, the carrier movement suppression region 70 having a desired concentration profile can be formed. In addition, there is little variation in the impurity concentration distribution of the carrier movement suppression region 70 formed in this way.

Conventionally, a high energy implant technique for injecting impurities into a semiconductor layer with high energy is known. When a high energy implant is performed, crystal defects are likely to occur in the semiconductor layer. This crystal defect increases the leakage current between the collector and the emitter.
In the method for manufacturing the semiconductor device 10 disclosed in the present invention, an n-type impurity is implanted deep from the surface 11a into the body region 50 without performing a high energy implant. Therefore, crystal defects are not increased. When the semiconductor device 10 of this embodiment is used, leakage current can be suppressed.

  In the semiconductor device 10 of the present embodiment, the case where the carrier movement suppression region 70 is continuous between the adjacent trenches 30 has been described, but the carrier movement suppression region 70 is not continuous between the trenches 30. Also good. The carrier movement suppression region 70 may be formed in a shape that enhances the hole accumulation effect of the drift region 20.

In the semiconductor device 10 of the present embodiment, the case where the conductive member 38 accommodated in the dummy trench 35 is connected to the gate electrode G has been described. However, the conductive member 38 is connected to the emitter electrode E. May be.
In the semiconductor device 10 of the present embodiment, the case where the conductive member 38 is disposed in the dummy trench 35 has been described. However, the dummy trench 35 may be filled with an insulating film. According to this configuration, the gate capacitance of the semiconductor device can be reduced.

(Second embodiment)
A second embodiment of the semiconductor device embodying the present invention will be described with reference to FIG. In addition, about the structure substantially the same as the semiconductor device 10 of FIG. 1, the same number is attached | subjected and the description is abbreviate | omitted.
As a feature of the semiconductor device 10a of the second embodiment, a carrier movement suppression region 70a is formed between the body region 50 and the drift region 20 as shown in the cross-sectional view of the main part in FIG. For this purpose, in the step of forming the dummy trench 35a, the dummy trench 35a is formed so that the bottom surface thereof is disposed at the interface between the body region 50 and the drift region 20.

(Third embodiment)
A third embodiment of the semiconductor device embodying the present invention will be described with reference to FIG. In addition, about the structure substantially the same as the semiconductor device 10 of FIG. 1, the same number is attached | subjected and the description is abbreviate | omitted.
As a feature of the semiconductor device 10a of the third embodiment, a dummy trench 35 and a dummy trench 35b having a depth different from that of the dummy trench 35 are provided as shown in the sectional view of the main part in FIG. The bottom surface 37b of the dummy trench 35b exists deeper from the surface 11a than the bottom surface 37 of the dummy trench 35. Therefore, the carrier movement suppression region 70b formed by injecting impurities toward the inner surfaces of both the dummy trench 35 and the dummy trench 35b is not formed with a uniform depth between the adjacent trenches 30. FIG. It is curved in the vertical direction.

  In the present embodiment, the case where the carrier movement suppression region 70b is curved has been described. For example, when the dummy trenches 35 having the bottom surface 37 at the first depth and the dummy trenches 35b having the bottom surface 37b at the second depth are alternately formed and the dummy trenches 35 and the dummy trenches 35b are formed densely, A first carrier movement suppression region continuous around one depth and a second carrier movement suppression region continuous around the second depth can be formed.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology illustrated in the present specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

2 is a cross-sectional view of a main part of the semiconductor device 10. The manufacturing process of the semiconductor device 10 is shown. The manufacturing process of the semiconductor device 10 is shown. The manufacturing process of the semiconductor device 10 is shown. The manufacturing process of the semiconductor device 10 is shown. The manufacturing process of the semiconductor device 10 is shown. The impurity concentration M corresponding to the depth D from the surface 11a of the semiconductor device 10 is shown. It is principal part sectional drawing of the semiconductor device 10a. It is principal part sectional drawing of the semiconductor device 10b. It is principal part sectional drawing of the conventional IGBT100. The manufacturing process of conventional IGBT100 is shown. The manufacturing process of conventional IGBT100 is shown. The manufacturing process of conventional IGBT100 is shown. The impurity concentration M corresponding to the depth D from the surface 111a of the conventional IGBT 100 is shown.

Explanation of symbols

10: Semiconductor device 11: Semiconductor substrate 11a: Front surface 11b: Back surface 20: Drift region 30: Trench 31: Bottom surface 32: Gate insulating film 34: Trench gate electrode 35: Dummy trench 36: Insulating film 37: Bottom surface 38: Conductive member 40: buffer region 42: collector region 50: body region 51: upper body region 52: lower body region 60: emitter region 70: carrier movement suppression region 80: interlayer insulating film C: collector electrode E: emitter electrode G: gate electrode H1 , H2: opening width L: stencil mask N1: diffusion region P1: diffusion region R: mask

Claims (6)

Injecting a second conductivity type impurity from the surface of the first conductivity type semiconductor layer to form a second conductivity type body region in a region from the surface of the semiconductor layer to a predetermined depth;
Forming a plurality of first trenches whose bottom surfaces protrude from the surface of the body region to the first conductivity type semiconductor layer;
Forming a second trench having a bottom surface located in the body region from the surface of the body region between the adjacent first trenches;
Covering the surface of the body region with a mask opened in the second trench;
Implanting a first conductivity type impurity through the mask toward the inner surface of the second trench, and forming a first conductivity type carrier movement suppression region around the bottom surface of the second trench;
Removing the mask;
A step of implanting a first conductivity type impurity in a range facing the surface of the body region and in contact with the first trench to form a first conductivity type emitter region;
A method for manufacturing a semiconductor device, comprising: A plurality of first conductivity type emitter regions formed facing a part of the surface of the semiconductor layer;
A second conductivity type body region surrounding the emitter region and formed in a region from the surface of the semiconductor layer to a predetermined depth;
A drift region of a first conductivity type formed under the body region and separated from the emitter region by the body region;
An intermediate depth region in the body region and / or a region sandwiched between the body region and the drift region and separated from the emitter region by the body region;
A first trench extending from the surface of each emitter region through the body region and having a bottom surface protruding into the drift region;
A gate insulating layer covering the inner surface of the first trench;
A trench gate electrode housed in the first trench in a state surrounded by a gate insulating layer;
A second trench formed between the adjacent first trenches and extending from the surface of the body region to the carrier movement suppression region;
A semiconductor device comprising:   3. The semiconductor device according to claim 2, wherein the carrier movement suppression region includes an impurity of a first conductivity type, and the concentration of the impurity is higher as it approaches the second trench.   4. The semiconductor device according to claim 2, wherein the carrier movement suppression region extends continuously between adjacent first trenches. An insulating layer covering an inner surface of the second trench;
A conductive member housed in the second trench in a state surrounded by an insulating layer;
A gate electrode connected to the trench gate electrode and the conductive member;
The semiconductor device according to claim 2, further comprising: An insulating layer covering an inner surface of the second trench;
A conductive member housed in the second trench in a state surrounded by an insulating layer;
A gate electrode connected to the trench gate electrode;
An emitter electrode connected to the emitter region and the conductive member;
The semiconductor device according to claim 2, further comprising:

Images