JP2008122734A - Method for driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve image display quality of even a panel having high luminance and high definition by stably generating an initialization discharge and increasing a contrast ratio. <P>SOLUTION: A plurality of sub-fields each having a write period wherein a discharge cell to be discharged is selected and a sustain period wherein a sustain discharge is generated by the discharge cell selected in the write period a number of times corresponding to luminance weight are provided in a one-field period. In a sustain period of a predetermined sub-field among the plurality of sub-fields, a voltage for generating a final sustain discharge is applied to one of a pair of display electrodes and then a voltage which drops down to a predetermined potential with a gradient is applied, where a positive voltage is applied to a data electrode in the middle of the application of the dropping voltage after the application of the voltage for generating the final sustain discharge to the one of the display electrode pair. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for driving a plasma display panel used in a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon in a partial pressure ratio is sealed in the internal discharge space. Has been. Here, a discharge cell is formed at a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of red, green, and blue colors are excited and emitted by the ultraviolet light to perform color display.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields is generally used.

  Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, wall charges necessary for the subsequent address operation are formed on each electrode, and priming particles for stably generating the address discharge (priming agent for discharge = excited particles) ). In the address period, an address pulse voltage is selectively applied to the discharge cells to be displayed to generate an address discharge to form wall charges (hereinafter, this operation is also referred to as “address”). In the sustain period, a sustain pulse is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell in which the address discharge is generated, and the phosphor layer of the corresponding discharge cell is caused to emit light. The image is displayed.

  In addition, among the subfield methods, initializing discharge is performed using a slowly changing voltage waveform, and further, initializing discharge is selectively performed on discharge cells that have undergone sustain discharge. A driving method is disclosed in which light emission that is not generated is reduced as much as possible to improve the contrast ratio.

  In this driving method, for example, among the plurality of subfields, an initialization operation (hereinafter referred to as “all-cell initialization operation”) in which initialization discharge is generated in all discharge cells in the initialization period of one subfield. In the initializing period of the other subfield, an initializing operation (hereinafter abbreviated as “selective initializing operation”) for generating an initializing discharge only in the discharge cells in which the sustain discharge has been performed is performed. By driving in this way, the light emission not related to the image display is only the light emission due to the discharge of the all-cell initialization operation, and the luminance of the black display area (hereinafter abbreviated as “black luminance”) is the initial value of all cells. Only weak light emission in the digitizing operation is possible, and high-contrast image display is possible (for example, see Patent Document 1).

In the above-mentioned Patent Document 1, the pulse width of the last sustain pulse in the sustain period is made shorter than the pulse widths of the other sustain pulses, and so-called narrow erasure is performed to alleviate the potential difference due to wall charges between the display electrode pairs. It also describes the discharge. By stably generating this narrow erase discharge, a reliable address operation can be performed in the address period of the subsequent subfield, and a plasma display device with a high contrast ratio can be realized.
JP 2000-242224 A

  In recent years, with the increase in size, brightness, and definition of panels, further improvement in display quality in plasma display devices is desired.

  The present invention has been made in order to meet such a demand. Even in a panel with high brightness and high definition, the initialization discharge is stably generated and the contrast ratio is increased to improve the image display quality. It is an object of the present invention to provide a panel driving method that can be performed.

  In order to solve such a problem, the present invention provides a method for driving a panel having a plurality of discharge cells each having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, the discharge cell being discharged A plurality of subfields each having an address period to be selected and a sustain period for generating sustain discharges corresponding to the luminance weight in the discharge cells selected in the address period are provided in one field period. In the sustain period of the predetermined subfield, after applying a voltage for generating the last sustain discharge to one of the display electrode pairs, a voltage that is inclined down to a predetermined potential is applied, and the display electrode described above is applied. A positive voltage is applied to the data electrode during the application of the decreasing voltage after the voltage for generating the last sustain discharge is applied to one of the pair. It is characterized in that form.

  With this method, even in a panel with high brightness and high definition, it is possible to stably generate initializing discharge and improve the image display quality by increasing the contrast ratio.

  Further, in the panel driving method of the present invention, the plurality of subfields described above include an all-cell initializing subfield that generates initializing discharge in all discharge cells and a discharge that generates sustaining discharge in the immediately preceding subfield. A selective initializing subfield for generating an initializing discharge only in the cell, and the predetermined subfield includes a subfield immediately before the all-cell initializing subfield. By this method, it is possible to stably generate the all-cell initialization operation.

  In the panel driving method of the present invention, the predetermined subfield includes a subfield having the smallest luminance weight.

  According to the present invention, there is provided a panel driving method capable of stably generating an initializing discharge and improving a contrast ratio and improving image display quality even in a panel with high brightness and high definition. Is possible.

  Hereinafter, an embodiment of a plasma display device driven by a panel driving method of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is an exploded perspective view showing a structure of panel 10 according to the embodiment of the present invention. On the glass front plate 21, a plurality of display electrode pairs 24 composed of scan electrodes 22 and sustain electrodes 23 are formed. A dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.

  This protective layer 26 has been used as a panel material in order to lower the discharge starting voltage in the discharge cell. When neon (Ne) and xenon (Xe) gas is sealed, the secondary layer 26 has a large secondary electron emission coefficient and is durable. It is made of a material mainly composed of MgO.

  A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer peripheral portion thereof is sealed with a sealing material such as glass frit. is doing. In the discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells are discharged and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 in accordance with the exemplary embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. m data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is placed in the discharge space. M × n are formed. As shown in FIG. 1 and FIG. 2, scan electrode SCi and sustain electrode SUi are formed in parallel with each other, and therefore, between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. There is an interelectrode capacitance Cp.

  FIG. 3 is a diagram illustrating an example of a circuit block of the plasma display device 1 according to the embodiment of the present invention. In FIG. 3, the plasma display device 1 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and each circuit. A power supply circuit (not shown) for supplying power necessary for the block is provided.

  The image signal processing circuit 41 described above converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The timing generation circuit 45 described above generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the respective circuit blocks. Based on the timing signal, scan electrode drive circuit 43 described above generates a ramp waveform voltage in the initialization period, generates a scan pulse in the address period, and generates a sustain pulse in the sustain period, thereby generating each scan electrode SC1. ... SCn is driven. Sustain electrode driving circuit 44 described above generates sustain pulses in the sustain period based on the timing signal to drive sustain electrodes SU1 to SUn. The data electrode driving circuit 42 described above generates an address pulse in the address period based on the timing signal to drive the data electrodes D1 to Dm.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described with reference to FIG. FIG. 4 is a drive voltage waveform diagram of the plasma display device in accordance with the exemplary embodiment of the present invention.

  First, in the plasma display device 1 in the present embodiment, the subfield method is used as a method for driving the panel 10. This is a driving method for performing gradation display by dividing one field period into a plurality of subfields and controlling light emission and non-light emission of each discharge cell in each subfield. Each subfield has an initialization period, an address period, and a sustain period.

  In the initializing period, initializing discharge is performed in the discharge cells, and wall charges necessary for the subsequent address operation are formed. Further, priming particles are generated for reducing the discharge delay when the address discharge is generated and for stably generating the address discharge. The initializing operation at this time includes all-cell initializing operation in which initializing discharge is generated in all discharge cells, and selective initializing operation in which initializing discharge is generated in the discharge cells that have undergone sustain discharge in the immediately preceding subfield. There is.

  In the address period, in order to select a discharge cell to be discharged, a scan pulse is sequentially applied to scan electrodes SC1 to SCn, and an address pulse corresponding to an image signal to be displayed is applied to data electrodes D1 to Dm. To selectively form wall charges. In the subsequent sustain period, a predetermined number of sustain pulses corresponding to the display luminance to be emitted are applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and a discharge cell in which wall charges are formed by address discharge is selected. Discharge and emit light.

  In this embodiment, one field is divided into eleven subfields (first SF, second SF,..., Eleventh SF), and each subfield is, for example, (0.5, 1, 2, 3). , 6, 11, 18, 30, 44, 60, 80). In the present embodiment, the sustain discharge generated by applying a positive voltage to scan electrodes SC1 to SCn and the sustain discharge generated by applying a positive voltage to sustain electrodes SU1 to SUn are maintained twice. The discharge is paired, and the luminance weight 0.5 of the first SF represents that a sustain discharge is generated only once by applying a positive voltage to scan electrodes SC1 to SCn. As a result, the luminance involved in the image display of the first SF can be made lower than in the case of generating a pair of sustain discharges, so that finer gradation display is possible and a smooth image can be displayed. Further, in the initialization period of the second SF, the all-cell initialization operation is performed (hereinafter, the subfield in which the all-cell initialization operation is performed is abbreviated as “all-cell initialization subfield”), and the first SF, the third SF to the eleventh SF. In this initialization period, a selective initialization operation is performed (hereinafter, a subfield in which the selective initialization operation is performed is abbreviated as “selective initialization subfield”). FIG. 4 shows drive voltage waveforms in two subfields, ie, a first SF that is a selective initialization subfield and a second SF that is an all-cell initialization subfield. However, in the present embodiment, the number of subfields and the luminance weight of each subfield are not limited to the above values, and the subfield configuration may be switched based on an image signal or the like.

  First, at the end of the sustain period of the last subfield (11th SF) of one field period, as shown in FIG. 4, the data electrodes D1 to Dm are held at 0 (V), and the last sustain discharge is performed. After applying a positive voltage Vs for generating the width erasing discharge to the scan electrodes SC1 to SCn, a positive voltage Ve1 for reducing the potential difference between the electrodes of the display electrode pair 24 is applied to the sustain electrodes SU1 to SUn. . Thus, a narrow pulse-like voltage difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn to generate a narrow erase discharge, leaving the positive wall voltage on data electrode Dk, and the scan electrode. The wall voltage on SCi and sustain electrode SUi is erased (scan electrode SCi, sustain electrode SUi, and data electrode Dk represent the electrodes selected based on the image data from the respective electrodes).

  The first SF in the subsequent field is a subfield for performing a selective initialization operation. In the initialization period in which selective initialization is performed, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn while data electrodes D1 to Dm are held at 0 (V), and sustain electrodes are applied to scan electrodes SC1 to SCn. A ramp waveform voltage (hereinafter, referred to as “ramp waveform voltage”) that gently decreases from voltage Vi3 ′ that is equal to or lower than the discharge start voltage to voltage Vi4 that exceeds the discharge start voltage is applied to SU1 to SUn. Then, in the discharge cell in which a sustain discharge has occurred in the sustain period of the immediately preceding subfield, a weak initializing discharge occurs between scan electrode SCi and sustain electrode SUi and between scan electrode SCi and data electrode Dk. The negative wall voltage above scan electrode SCi and the positive wall voltage above sustain electrode SUi are weakened. For the data electrode Dk, an excessive portion of the positive wall voltage on the data electrode Dk accumulated by the immediately previous sustain discharge is discharged by the initialization discharge, whereby the positive wall above the data electrode Dk is discharged. The voltage is adjusted to a wall voltage suitable for the subsequent write operation. On the other hand, the discharge cells that did not cause the sustain discharge in the previous subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained as they are. The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the subsequent address period, positive voltage Ve2 is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn.

  First, a negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and a positive address pulse voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. To do. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 due to the difference in externally applied voltage (Vd−Va). It becomes the sum and exceeds the discharge start voltage. Then, address discharge occurs between data electrode Dk and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1, positive wall voltage is accumulated on scan electrode SC1, and negative wall is applied on sustain electrode SU1. A voltage is accumulated, and a negative wall voltage is also accumulated on the data electrode Dk.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, since the luminance weight of the first SF is set to 0.5 as described above, a sustain discharge is generated only once by applying a positive voltage to one of the display electrode pairs 24, that is, the scan electrode SCi. Let Specifically, after sustain electrodes SU1 to SUn are once returned to 0 (V), positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn. Then, in the discharge cell that has caused the address discharge, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. As a result of addition, the discharge start voltage is exceeded and a sustain discharge occurs between scan electrode SCi and sustain electrode SUi. Then, the phosphor layer 35 emits light due to the ultraviolet rays generated at this time, a negative wall voltage is accumulated on the scan electrode SCi, a positive wall voltage is accumulated on the sustain electrode SUi, and also on the data electrode Dk. A positive wall voltage is accumulated. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Note that this sustain discharge is the last sustain discharge in the sustain period of the first SF, thereby realizing a luminance weight of 0.5. In the present embodiment, the first SF is thus set to the luminance weight 0.5 smaller than the luminance weight 1, and the luminance involved in the image display of the first SF is lowered to enable fine gradation display.

  On the other hand, in the discharge cell in which the last sustain discharge has occurred, as described above, a negative wall voltage is present above scan electrode SCi, a positive wall voltage is present above sustain electrode SUi, and a positive wall voltage is present above data electrode Dk. Although wall voltages are formed, these wall voltages strongly generate initializing discharge in the following subfields to cause unnecessary light emission, which may cause deterioration in contrast ratio due to an increase in black luminance.

  Therefore, in the present embodiment, a discharge for relaxing this unnecessary wall charge is generated. Specifically, after applying the positive sustain pulse voltage Vs to one of the display electrode pairs 24, that is, scan electrodes SC1 to SCn to generate the last sustain discharge in the first SF, the scan electrodes SC1 to SCn are subjected to a predetermined amount. A ramp waveform voltage that gradually falls from a voltage Vi3 ′ that is equal to or lower than the discharge start voltage to the voltage Vi4 that exceeds the discharge start voltage is applied to the sustain electrodes SU1 to SUn. . In addition, the positive sustain pulse voltage Vs, which is a voltage for generating the last sustain discharge, is applied to the scan electrodes SC1 to SCn, which is one of the display electrode pairs 24, and then the ramp waveform voltage that is decreasing is being applied. In the meantime, a positive voltage Vd, which is a positive voltage, is applied to the data electrodes D1 to Dm, and a positive voltage Ve1 is applied to the sustain electrodes SU1 to SUn. As a result, in the discharge cell in which the last sustain discharge has occurred, a weak discharge occurs between scan electrode SCi and sustain electrode SUi and between scan electrode SCi and data electrode Dk. Is alleviated. Therefore, the weak discharge generated by the ramp voltage of the ramp acts as an erasing discharge for relaxing the wall voltage on each electrode.

  Further, in the present embodiment, the positive voltage applied to the data electrodes D1 to Dm is applied during the application of the ramp waveform voltage to the scan electrodes SC1 to SCn so that the light emission due to the erasing discharge does not increase the black luminance. The application of Vd is terminated, and the potentials of the data electrodes D1 to Dm are returned to 0 (V). In the present embodiment, by performing such driving, the discharge intensity of the erasing discharge is controlled and the light emission generated by the erasing discharge is reduced, so that the image display quality in the plasma display device 1 is improved. Details of the erasing discharge will be described later.

  The subsequent second SF is a subfield for performing the all-cell initialization operation. In the first half of the initialization period, first, 0 (V) is applied to sustain electrodes SU1 to SUn, positive voltage Vd is applied to data electrodes D1 to Dm, and sustain electrodes are applied to scan electrodes SC1 to SCn. A ramp waveform voltage that gradually rises from a voltage Vi1 that is equal to or lower than the discharge start voltage to a voltage Vi2 that exceeds the discharge start voltage is applied to SU1 to SUn.

  While this ramp waveform voltage rises, weak initializing discharges occur between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, respectively. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn.

  Subsequently, in the latter half of the initialization period, the data electrodes D1 to Dm are set to 0 (V), the positive voltage Ve1 is applied to the sustain electrodes SU1 to SUn, and the sustain electrodes SU1 to SUn are applied to the scan electrodes SC1 to SCn. A ramp waveform voltage that gently decreases from voltage Vi3 that is equal to or lower than the discharge start voltage to voltage Vi4 that exceeds the discharge start voltage is applied to SUn. During this time, weak initializing discharges occur between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, respectively. Then, the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SU1 to SUn are weakened, and the positive wall voltage above data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed. In the present embodiment, since the wall voltage in the discharge cell is sufficiently relaxed by the immediately preceding erasing discharge, a weak initializing discharge can be obtained compared to the case where it is not. Thereby, unnecessary light emission generated at the time of initializing discharge can be suppressed, and an increase in black luminance can be suppressed.

  The operation during the subsequent writing period is the same as the operation during the writing period of the first SF, and thus description thereof is omitted.

  In the subsequent sustain period, the first sustain discharge is generated by the same operation as the sustain period of the first SF, a negative wall voltage is accumulated on the scan electrode SCi, and the positive voltage is accumulated on the sustain electrode SUi and the data electrode Dk. The wall voltage is accumulated. Subsequently, 0 (V) is applied to scan electrodes SC1 to SCn, and positive sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the first sustain discharge has occurred, the voltage difference between sustain electrode SUi and scan electrode SCi exceeds the discharge start voltage, so the second sustain is performed between sustain electrode SUi and scan electrode SCi. Discharge occurs. Then, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, in the same manner, sustain discharge is applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn alternately by the number of sustain pulses obtained by multiplying the luminance weight by the luminance magnification, thereby sustain discharge in the discharge cells that have caused address discharge in the address period. Will continue. However, a sustain discharge does not occur in a discharge cell in which no address discharge has occurred in the address period, and the wall voltage at the end of the initialization period is maintained.

  At the end of the sustain period, a so-called narrow pulse voltage difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn to generate a narrow erase discharge, and scan electrodes SCi and sustain electrodes SUi The wall voltage is weakened. Thus, the sustain operation in the sustain period of the second SF ends. The narrow erase discharge in the second SF and the narrow erase discharge in the eleventh SF described above have the same function. The subsequent subfield operations are substantially the same except that the number of sustain pulses is different from that of the second SF.

  Next, the erase discharge generated immediately after the last sustain discharge of the first SF described above will be described.

  As described above, in the discharge cell in which the last sustain discharge has occurred in the sustain period of the first SF, a negative wall voltage is present above scan electrode SCi, and a positive wall voltage is present above sustain electrode SUi and data electrode Dk. It is formed. Since the strength of the initializing discharge generated in the subsequent second SF depends on the strength of the wall voltage formed in the discharge cell, the initializing discharge of the subsequent subfield is generated in the discharge cell in which those wall voltages are formed. May occur strongly.

  If the subsequent initializing discharge is strongly generated, the luminance of light emission not related to the image display caused by the initializing discharge increases, and the black luminance increases and the contrast ratio is deteriorated. Therefore, it is desirable to generate the subsequent initializing discharge as a weak discharge that does not substantially deteriorate the black luminance, and for this purpose, the wall voltage in the discharge cell is set so that the discharge intensity of the initializing discharge is weakened. You can relax in advance.

  Therefore, in the present embodiment, after the last sustain discharge in the first SF is generated, the erasing discharge for relaxing the wall voltage on each electrode is generated by the drive voltage waveform described above. That is, after applying sustain pulse voltage Vs for generating the last sustain discharge to scan electrodes SC1 to SCn, which are one of display electrode pairs 24, a ramp waveform voltage that ramps down to a predetermined potential is applied. In addition, the positive sustain pulse voltage Vs for generating the last sustain discharge is applied to the scan electrodes SC1 to SCn, and the data electrodes D1 to Dm are positively applied during the application of the ramp waveform voltage that falls. A positive voltage Vd, which is a negative voltage, is applied, and a positive voltage Ve1 is applied to the sustain electrodes SU1 to SUn. Thus, in the discharge cell in which the last sustain discharge has occurred, erase discharge is generated between the scan electrode SCi, the sustain electrode SUi, and the data electrode Dk, respectively, and the wall voltage on each electrode is relaxed.

  At this time, if the discharge intensity of the erasing discharge is insufficient, the wall voltage in the discharge cell cannot be sufficiently relaxed, and the subsequent initializing discharge cannot be made weak.

  Further, this erasing discharge also has a function of generating priming particles necessary for promptly generating the subsequent initializing discharge. If this priming particle is insufficient, the discharge does not occur promptly during the subsequent initialization operation, and as a result, a strong discharge is induced, and unnecessary wall charges may be formed in the discharge cells. The unnecessary wall charge due to the strong discharge generates a discharge cell (hereinafter referred to as “initialization bright spot”) that emits light due to a sustain discharge even though no address is written. Therefore, this erasing discharge must generate enough priming particles to promptly generate a subsequent initializing discharge.

  On the other hand, the erase discharge generated by applying the ramp waveform voltage to the scan electrodes SC1 to SCn is different from the strong discharge that occurs instantaneously such as the sustain discharge and the address discharge in the application time of the ramp waveform voltage. This discharge is generated continuously for a corresponding period. The discharge intensity and duration of the erasing discharge are related to the black luminance. If an erasing discharge with increased discharge intensity is generated for a long time, the black luminance is affected and the contrast ratio is deteriorated. There is a fear. This tendency becomes prominent in a panel with high luminous efficiency and high luminance.

  Here, in this embodiment, when the ramp waveform voltage that falls is applied to scan electrodes SC1 to SCn, positive voltage Vd is applied to data electrodes D1 to Dm. The voltage difference with respect to Dk can be increased by applying the positive voltage Vd. Accordingly, it is possible to generate an erasing discharge as much as that to make the discharge intensity of the erasing discharge sufficient. Further, in the present embodiment, the duration of the erase discharge with the increased discharge intensity is controlled by controlling the application period of the positive voltage Vd applied to the data electrodes D1 to Dm in order to increase the erase discharge. To do. Specifically, the application of the positive voltage Vd is finished while the ramp waveform voltage is applied and the voltages of the scan electrodes SC1 to SCn are decreasing, and the potentials of the data electrodes D1 to Dm are set to 0 (V Return to). At this time, the application of the positive voltage Vd ends at a timing at which the wall voltage in the discharge cell is sufficiently relaxed, sufficient priming particles are generated, and substantially no increase in black luminance occurs. As a result, the duration of the erasing discharge with increased discharge intensity can be controlled, and an erasing discharge can be realized without increasing the discharge intensity and substantially affecting the black luminance.

  Note that the structure in this embodiment is particularly effective in a panel with high brightness and high definition, in which discharge tends to become unstable.

  In the present embodiment, the duration of the ramp voltage waveform applied to the scan electrodes SC1 to SCn is about 110 μsec, and the application period of the positive voltage Vd to the data electrodes D1 to Dm is about 60 μsec. These are merely examples, and may be set to optimum values within a range where the above-described effects can be obtained according to the characteristics of the panel, the specifications of the plasma display device, and the like.

  Next, the configuration and operation of scan electrode drive circuit 43 will be described. FIG. 5 is a circuit diagram of scan electrode driving circuit 43 according to the embodiment of the present invention. Scan electrode driving circuit 43 includes sustain pulse generating circuit 50 for generating a sustain pulse, initialization waveform generating circuit 53 for generating an initialization waveform, and scan pulse generating circuit 54 for generating a scan pulse.

  Sustain pulse generation circuit 50 includes a power recovery circuit 51 and a clamp circuit 52. The power recovery circuit 51 includes a power recovery capacitor C1, switching elements Q1 and Q2, backflow prevention diodes D1 and D2, and a resonance inductor L1. The power recovery capacitor C1 has a sufficiently large capacity compared to the interelectrode capacity Cp, and is charged to about Vs / 2, which is half the voltage value Vs, so as to serve as a power source for the power recovery circuit 51. Clamp circuit 52 includes switching element Q3 for clamping scan electrodes SC1 to SCn to voltage Vs, and switching element Q4 for clamping scan electrodes SC1 to SCn to 0 (V). Then, sustain pulse voltage Vs is generated based on the timing signal output from timing generation circuit 45.

  For example, when the sustain pulse waveform is raised, the switching element Q1 is turned on to cause the interelectrode capacitance Cp and the inductor L1 to resonate, and the power recovery capacitor C1 passes through the switching element Q1, the diode D1, and the inductor L1 to scan electrodes. Power is supplied to SC1 to SCn. Then, when the voltage of scan electrodes SC1 to SCn approaches Vs, switching element Q3 is turned on, and scan electrodes SC1 to SCn are clamped to voltage Vs.

  On the contrary, when the sustain pulse waveform is lowered, the switching element Q2 is turned on to resonate the interelectrode capacitance Cp and the inductor L1, and the interelectrode capacitance Cp is used for power recovery through the inductor L1, the diode D2, and the switching element Q2. The power is recovered in the capacitor C1. Then, when the voltage of scan electrodes SC1 to SCn approaches 0 (V), switching element Q4 is turned on, and scan electrodes SC1 to SCn are clamped to 0 (V).

  The initialization waveform generation circuit 53 includes a switching element Q11, a capacitor C10, and a resistor R10. The initialization waveform generation circuit 53 generates a rising ramp waveform voltage that gradually rises in a ramp shape up to a predetermined initialization voltage Vi2, and a switching element Q14. A Miller integration circuit that has a capacitor C12 and a resistor R11 and generates a ramp-down waveform voltage that gradually falls in a ramp shape to a voltage Vi4, a separation circuit using the switching element Q12, and a separation circuit using the switching element Q13 are provided. Yes. Then, the initialization waveform described above is generated based on the timing signal output from the timing generation circuit 45. In FIG. 5, the input terminals of the Miller integrating circuit are shown as an input terminal INa and an input terminal INb.

  For example, when generating an upward ramp waveform voltage in the initialization waveform, a predetermined voltage (for example, 15 (V)) is applied to the input terminal INa to set the input terminal INa to “Hi”. Then, a constant current flows from the resistor R10 toward the capacitor C10, the source voltage of the switching element Q11 increases in a ramp shape, and the output voltage of the scan electrode drive circuit 43 starts to increase in a ramp shape.

  Further, when generating a ramp voltage waveform in the initialization waveform or a ramp waveform voltage for the above-described erasing discharge, a predetermined voltage (for example, 15 (V)) is applied to the input terminal INb. The input terminal INb is set to “Hi”. Then, a constant current flows from the resistor R11 toward the capacitor C12, the drain voltage of the switching element Q14 decreases in a ramp shape, and the output voltage of the scan electrode driving circuit 43 starts to decrease in a ramp shape.

  Scan pulse generation circuit 54 includes switch circuits OUT1 to OUTn that output scan pulse voltages to scan electrodes SC1 to SCn, switching element Q21 for clamping the low voltage side of switch circuits OUT1 to OUTn to voltage Va, A diode D21 and a capacitor C21 are provided for applying a voltage Vc obtained by superimposing the voltage Vscn on the voltage Va to the high voltage side of the switch circuits OUT1 to OUTn. Each of the switch circuits OUT1 to OUTn includes switching elements QH1 to QHn for outputting the voltage Vc and switching elements QL1 to QLn for outputting the voltage Va. Based on the timing signal output from the timing generation circuit 45, the scan pulse voltage Va to be applied to the scan electrodes SC1 to SCn in the address period is sequentially generated.

  In this embodiment, the initialization waveform generating circuit 53 employs a Miller integrating circuit using a practical and relatively simple FET. However, the present invention is not limited to this configuration. Any circuit can be used as long as it can generate an up-ramp waveform voltage and a down-ramp waveform voltage.

  Although not shown, the sustain pulse generation circuit of sustain electrode drive circuit 44 has the same configuration as sustain pulse generation circuit 50, and collects and reuses power when driving sustain electrodes SU1 to SUn. A timing recovery circuit 45, a switching element for clamping sustain electrodes SU1 to SUn to voltage Vs, and a switching element for clamping sustain electrodes SU1 to SUn to 0 (V). Sustain pulse voltage Vs is generated based on the timing signal output from.

  Next, the configuration and operation of the data electrode driving circuit 42 will be described.

  FIG. 6 is a circuit diagram of the data electrode driving circuit 42 according to the embodiment of the present invention. As shown in FIG. 6, the data electrode drive circuit 42 includes an address pulse generation circuit 55 and an address pulse output circuit 58.

  The write pulse generation circuit 55 includes a power recovery circuit 56 and a clamp circuit 57. The power recovery circuit 56 includes a power recovery capacitor C31, switching elements Q31 and Q32, and backflow prevention diodes D31 and D32. The clamp circuit 57 includes switching elements Q33 and Q34. Then, the electrode capacitance of the data electrode and the inductor for resonance L31 are resonated to recover the power supplied to the data electrode to the power recovery capacitor C31 to generate a write pulse, and the generated write pulse is written. Output to the pulse output circuit 58. The operation of the write pulse generation circuit 55 is the same as that of the sustain pulse generation circuit 50, and thus the description thereof is omitted.

  The address pulse output circuit 58 includes switch units OUT1 to OUTm that output address pulses to the data electrodes D1 to Dm, respectively. Each of the switch sections OUT1 to OUTm includes switching elements QH1 to QHm for outputting the write pulse output from the write pulse generating circuit 55 to the data electrodes D1 to Dm, and a switching element for grounding the data electrodes D1 to Dm. QL1 to QLm. Then, the switching elements are switched based on the timing signal output from the timing generation circuit 45 and the image data output from the image signal processing circuit 41, and the data electrode to which the write pulse output from the write pulse generation circuit 55 is to be applied. Output to Dk.

  As described above, in the present embodiment, in the subfield immediately before the subfield where all cells are initialized, one of the display electrode pairs 24, that is, the last sustain discharge is generated in scan electrodes SC1 to SCn. After the sustain pulse voltage Vs is applied, a ramp waveform voltage that ramps down from a voltage Vi3 ′ that is equal to or lower than the discharge start voltage to the sustain electrodes SU1 to SUn to a predetermined potential, that is, a voltage Vi4 that exceeds the discharge start voltage. And applying the sustain pulse voltage Vs for generating the last sustain discharge to the scan electrodes SC1 to SCn, which is one of the display electrode pairs 24, during the application of the ramp waveform voltage descending as described above. A positive voltage Vd that is a positive voltage is applied to the data electrodes D1 to Dm.

  With such a configuration, the discharge intensity of the erasing discharge for relaxing the wall voltage on each electrode can be adjusted and generated, so the wall voltage on each electrode is sufficiently relaxed during the subsequent initialization operation. It is possible to prevent a strong discharge from occurring, and it is possible to suppress an unnecessary light emission associated with the initializing discharge and suppress an increase in black luminance. Furthermore, since the priming particles necessary for the initialization discharge can be sufficiently generated, the subsequent initialization discharge can be generated promptly and stably, and a stable address discharge can be realized in the subsequent address period. it can. Furthermore, by controlling the duration of the erase discharge with increased discharge intensity, it is possible to achieve an erase discharge that does not substantially affect the black luminance. In this way, it is possible to realize a plasma display device having a stable contrast ratio with a good initialization operation and a high image display quality.

  In the present embodiment, after the last sustain discharge of the first SF occurs, the application of the positive voltage Vd to the data electrodes D1 to Dm and the application of the positive voltage Ve1 to the sustain electrodes SU1 to SUn are performed almost simultaneously. Although the configuration has been described, the application timing does not have to be the same, and a difference within a range in which the intended effect of the present invention can be obtained is allowed.

  In the present embodiment, the luminance weight of the first SF is set to 0.5 and the second SF is described as the all-cell initialization subfield. However, this is merely an example, and the configuration is limited to this subfield configuration. It is not a thing. The present embodiment can obtain the above-mentioned effect by being applied to the erase discharge immediately before the all-cell initializing operation, and may be set as appropriate according to the subfield configuration.

  In the present embodiment, in the erase discharge immediately before the all-cell initialization operation, the duration of the downward ramp waveform voltage applied to scan electrodes SC1 to SCn is about 110 μsec, and the positive voltage to data electrodes D1 to Dm is set. Although the application period of Vd has been described as about 60 μsec, these numerical values are only examples, and the wall voltage in the discharge cell is sufficiently relaxed according to the panel characteristics, the specifications of the plasma display device, etc. What is necessary is just to set to an optimal value in the period when a priming particle | grain generate | occur | produces and a black brightness raise does not generate | occur | produce substantially.

  Further, the voltage applied to the data electrodes D1 to Dm when the erasing discharge is generated does not necessarily need to be Vd, and may be set to an optimum voltage value in accordance with the panel characteristics, the specifications of the plasma display device, and the like. .

  Further, the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the values appropriately according to the characteristics of the panel, the specifications of the plasma display device, and the like.

  INDUSTRIAL APPLICABILITY The present invention is useful as a panel driving method because it can stably generate an initializing discharge and improve a contrast ratio and improve image display quality even in a panel with high brightness and high definition. .

The disassembled perspective view which shows the structure of the panel in embodiment of this invention Electrode arrangement of the panel The figure which shows an example of the circuit block of the plasma display apparatus in one embodiment of this invention Driving voltage waveform diagram of the plasma display device 1 is a circuit diagram of a scan electrode driving circuit according to an embodiment of the present invention. The circuit diagram of the data electrode drive circuit in one embodiment of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front plate (made of glass) 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 25, 33 Dielectric layer 26 Protective layer 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 41 Image signal processing circuit 42 data electrode drive circuit 43 scan electrode drive circuit 44 sustain electrode drive circuit 45 timing generation circuit 50 sustain pulse generation circuit 51, 56 power recovery circuit 52, 57 clamp circuit 53 initialization waveform generation circuit 54 scan pulse generation circuit 55 write pulse generation Circuit 58 Write pulse output circuit

Claims (3)

A method for driving a plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode,
A plurality of subfields having an address period for selecting discharge cells to be discharged and a sustain period for generating sustain discharges corresponding to the luminance weight in the discharge cells selected in the address period are provided in one field period,
In the sustain period of a predetermined subfield of the plurality of subfields, a voltage that is ramped down to a predetermined potential is applied after a voltage for generating the last sustain discharge is applied to one of the display electrode pairs. And applying a voltage in the positive direction to the data electrode during application of the decreasing voltage after applying the voltage for generating the last sustain discharge to one of the display electrode pairs. A driving method of a plasma display panel characterized by comprising. The plurality of subfields include selective initialization for generating initializing discharge only in all cell initializing subfields in which initializing discharge is generated in all discharge cells, and only in discharge cells having generated sustaining discharge in the immediately preceding subfield. The method of claim 1, wherein the predetermined subfield includes a subfield immediately before the all-cell initialization subfield. 3. The method of driving a plasma display panel according to claim 1, wherein the predetermined subfield includes a subfield having the smallest luminance weight.

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