JP2008170842A - Electrooptical device, driving circuit, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To compatibly achieve prevention against a decrease in display quality and reduction in power consumption. <P>SOLUTION: In a driving circuit of an electrooptical device, switches 260 are provided corresponding to respective data lines 211 and each have one end connected to a data line and the other end connected to a feeder 281 in common. A ramp signal generating circuit 10 generates a ramp signal Vrp which monotonously varies in voltage for an application period of a selection voltage, and a buffer circuit 20 supplies a ramp signal Vout, generated by buffering the voltage of the ramp signal Vrp, to the feeder 281. In the application period of the selection voltage, a switch 260 is turned on for a period corresponding to a grayscale of a pixel corresponding to an intersection of a scan line applied with the selection voltage and a data line connected to one end of the switch, and then controlled into an off state after the period by a data line driving circuit 250. The buffer circuit 20 switches driving capability of the ramp signal Vout in the application period of the selection voltage according to display contents of one line of pixels disposed on the scan line applied with the selection voltage. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a technique for reducing power consumption and preventing deterioration of display quality in an active matrix electro-optical device.

An electro-optical device that performs display by electro-optical change such as a liquid crystal is applied to a pixel by applying a voltage corresponding to a gradation to a pixel electrode through a data line during a period in which a selection voltage is applied to the scanning line. There is a configuration in which the effective voltage value to be applied is controlled, and thereby gradation display is performed.
However, in such a configuration, it is necessary to individually generate voltages corresponding to gradations with both positive and negative polarities, so that there is a problem that a circuit for generating voltages becomes complicated.
Therefore, while the selection voltage is applied to the scanning line, for example, while maintaining the common electrode at a constant voltage, a signal whose voltage monotonously changes is applied to the pixel electrode via the ON switch and the data line. A technique has been proposed in which the switch is turned off when a time corresponding to the gradation has elapsed, thereby holding the voltage difference between the pixel electrode and the common electrode (see Patent Document 1).
Japanese Patent No. 3367808

However, in the above technique, if the signal whose voltage changes monotonously does not change as expected for some reason, the voltage difference between the pixel electrode and the common electrode does not become a value corresponding to the target gradation. It has been pointed out that the gradation cannot be obtained and the display quality is deteriorated.
Here, the reason why the signal whose voltage changes monotonously does not change as expected is mainly because the load capacity of the signal line that supplies the signal changes, so that the signal has a sufficiently high driving capability. However, with such a configuration, it becomes impossible to achieve low power consumption.
The present invention has been made in view of such circumstances, and an object of the present invention is to provide an electro-optical device, a driving circuit, and an electro-optical device that achieve both low power consumption and prevention of deterioration in display quality in the electro-optical device. To provide electronic equipment.

In order to achieve the above object, the present invention includes a pair of a pixel electrode and a switching element provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, and the switching element includes the data A drive circuit of an electro-optical device including a plurality of pixels that are in a conductive state when a selection voltage is applied to the scanning line between the line and the pixel electrode. A scanning line driving circuit for selecting and applying the selection voltage in order, and provided corresponding to each of the plurality of data lines, one end being connected to the data line and the other end being common to the power supply line A plurality of connected data-side switches, a ramp signal generating circuit that generates a ramp signal whose voltage monotonously changes over a period in which the selection voltage is applied to one scanning line, and buffering the ramp signal A buffer circuit for supplying either the power supply line or the common electrode facing the pixel electrode; and the data side switch in a period in which a selection voltage is applied to one of the plurality of scanning lines. Then, the data side switch is turned on only for a period corresponding to the gradation of the pixel corresponding to the intersection of the scanning line to which the selection voltage is applied and the data line connected to one end of the data side switch. A data line driving circuit that controls the off-state, and the buffer circuit displays the display content of one row of pixels located on the scanning line to which the selection voltage is applied during the period in which the selection voltage is applied. The driving capability of the ramp signal is switched accordingly. According to the present invention, since the driving capability of the ramp signal is switched according to the display content of one row of the pixels located on the scanning line to which the selection voltage is applied, the power consumption can be reduced when the driving capability is low. I can expect.

In the present invention, during the period when the selection voltage is applied, one of the feeder line and the common electrode is kept at a predetermined voltage, and the voltage of the ramp signal changes in a direction away from the predetermined voltage. The buffer circuit preferably has a configuration in which the driving capability of the ramp signal decreases as the number of columns in which the data-side switch is turned on decreases. In this configuration, the buffer circuit includes a plurality of operational amplifiers connected in parallel to each other, and the plurality of operational amplifiers according to the number of columns in which the data-side switch is on during the period in which the selection voltage is applied. It is good also as a structure containing the load determination circuit which determines the combination of the buffer which performs buffer operation | movement.
Note that the present invention can be conceptualized not only as a drive circuit for an electro-optical device, but also as an electro-optical device itself and an electronic device including the electronic device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention.
As shown in this figure, the electro-optical device 1 has a display area 100. In this display area 100, 320 scanning lines 311 are provided so as to extend in the row (X) direction, while 240 data lines 211 are provided so as to extend in the column (Y) direction. Pixel 12
0 is arranged corresponding to the intersection of 320 scanning lines 311 and 240 columns of data lines 211. Therefore, in the present embodiment, the pixels 120 are arranged in a matrix of 320 vertical rows × 240 horizontal columns, but the present invention is not limited to this arrangement.

Here, a detailed configuration of the pixel 120 will be described. FIG. 2 is a diagram illustrating a configuration of the pixel 120, i rows and (i + 1) rows adjacent thereto, j columns and (j + 1) adjacent thereto.
A configuration of a total of 4 pixels of 2 × 2 corresponding to the intersections with the columns is shown.
Note that i and (i + 1) are symbols for generally indicating a row in which the pixels 120 are arranged, and are integers of 1 to 320, and j and (j + 1) are columns in which the pixels 120 are arranged. It is a symbol in the general case, and is an integer from 1 to 240.

As shown in FIG. 2, each pixel 120 includes a liquid crystal capacitor (liquid crystal element) 130 and an n-channel thin film transistor (hereinafter simply referred to as “TFT”) 241 that functions as a switching element. . Since each pixel 120 has the same configuration, the pixel 120 in the i-th row and j-th column will be described as a representative example. In the pixel 120 in the i-th row and j-th column, the gate electrode of the TFT 241 is connected to the i-th scanning line 311. On the other hand, the source electrode is connected to the data line 211 in the j-th column, and the drain electrode is connected to the pixel electrode 231 that is one end of the liquid crystal capacitor 130.
The other end of the liquid crystal capacitor 130 is connected to the common electrode 110. This common electrode 1
In this embodiment, 10 is common to all the pixels 120 as shown in FIG. 1, and is kept constant at the voltage Vcom in this embodiment.

In the liquid crystal capacitor 130, the voltage difference between the pixel electrode 231 and the common electrode 110 is held, and the amount of light transmitted (or reflected) through the liquid crystal capacitor 130 changes according to the effective value of the hold voltage. .
Although it is considered that such a configuration does not need to be described in detail, a method in which the liquid crystal is sandwiched between the pixel electrode and the common electrode and the electric field direction applied to the liquid crystal is the substrate surface vertical direction, the pixel electrode, Examples include a method in which an insulating layer and a common electrode are stacked so that the direction of the electric field applied to the liquid crystal is the horizontal direction of the substrate surface.
In the present embodiment, for convenience, when the effective voltage value held in the liquid crystal capacitor 130 is close to zero, the light transmittance is maximized to display white, while the amount of light transmitted as the effective voltage value increases. This will be described as a normally white mode that decreases and finally becomes a black display with the minimum transmittance.

In the display area 100, 320 rows of scanning lines 311 and 240 columns of data lines 211 are thus obtained.
In addition, a pixel 120 is provided at each of these intersections. Therefore, next, the ramp signal generation circuit 10, the buffer circuit 20, the data line driving circuit 250, the switch 260, the scanning line driving circuit 350, and the control circuit 400, which are circuits for driving the scanning lines 311 and the data lines 211, will be described. To do.
The control circuit 400 controls the data line driving circuit 250 by supplying the control signal CntX and the reset signal Res, and controls vertical scanning of the display area 100 by the scanning line driving circuit 350 by supplying the control signal CntY. In addition, the control circuit 400 includes a polarity instruction signal Pol,
The reset signal Res and the clock signal Clk are supplied to the ramp signal generation circuit 10.

When the reset signal Res is supplied at the beginning of the horizontal scanning period (1H) in which the selection voltage is applied to a certain scanning line 311, the ramp signal generation circuit 10 determines the voltage of the output signal Vrp as
The voltage is reset to the voltage Vcom, which is the voltage applied to the common electrode 110, and the clock signal Cl
Each time k is supplied for one period, the voltage is increased or decreased by ΔV. In detail,
The ramp signal generation circuit 10 increases the signal Vrp by the voltage ΔV every time the clock signal Clk is supplied if the polarity instruction signal Pol is H level, while the clock signal Clk is clocked if the polarity instruction signal Pol is L level. Every time the signal Clk is supplied, the voltage ΔV is lowered.
If the clock signal Clk is constant at a sufficiently high frequency with respect to the horizontal scanning period (1H) and the voltage ΔV is also sufficiently small, the signal Vrp from the ramp signal generation circuit 10 is as shown in FIG.
If the polarity instruction signal Pol is at H level, the voltage V
If it rises linearly from com and the polarity indicating signal Pol is at L level, it can be regarded as a ramp signal that falls linearly from voltage Vcom in the horizontal scanning period.
The ramp signal Vrp is equal to the horizontal scanning period (1H) if the polarity instruction signal Pol is at the H level.
) When the voltage Vp is reached and the polarity instruction signal Pol is at L level, the horizontal scanning period (1
It is assumed that the voltage Vm has been reached at the end of H).

The buffer circuit 20 buffers the voltage of the ramp signal Vrp from the ramp signal generation circuit 10, that is, amplifies the voltage with a voltage amplification factor “1”, and supplies it as the ramp signal Vout to the feeder line 28.
The details will be described later.

The scanning line driving circuit 350 sequentially selects the scanning lines 311 in the first, second, third,..., 320th rows in each horizontal scanning period (1H) according to the control signal CntY, and also selects the selected scanning line 311. The scanning signal corresponding to is the selection voltage Vdd corresponding to the H level over the horizontal scanning period (1H), and the other scanning signals corresponding to the scanning line 311 are the non-selection voltage Vss corresponding to the L level (= voltage zero = Gnd). Where 1, 2, 3, ...
Scan signals supplied to the scanning line 311 of the 320th row are respectively Y1, Y2, Y3,.
When expressed as 320, these scanning signals are represented in the horizontal scanning period (1H as shown in FIG.
) Are sequentially shifted.
Note that Yi is used when generally describing the scanning signal without specifying a particular row. In this embodiment, the period from when the first scanning signal Y1 changes to the H level to when the final scanning signal Y320 changes to the L level is defined as the vertical scanning period (1F).

Next, the data line driving circuit 250 outputs switch control signals X1, X2, X3,..., X240 corresponding to the data lines 211 in the 1, 2, 3,.
More specifically, the data line driving circuit 250 has storage areas (not shown) corresponding to a matrix arrangement of 320 rows × 240 columns, and each storage area stores the gradation data Da of the corresponding pixel 120. Remember. The gradation data Da is data that designates the gradation value (brightness) of the pixel 120. The gradation data Da is supplied from a host device (not shown) and is stored in a corresponding storage area when the display content is changed. The gradation data Da is rewritten. Here, when one scanning line 311 is selected by the scanning line driving circuit 350, the data line driving circuit 250 generates one row of the gradation data Da of the pixel located on the scanning line in accordance with the control signal CntX. Read in advance, and switch control signals X1, X2, X3,... According to one row of the gradation data Da.
, X240 is output.
Further, the data line driving circuit 250 has switch control signals X1, X2, X3,.
Among them, the data Nx indicating the number of H levels is supplied to the buffer circuit 20.
In order to notify the start timing of the horizontal scanning period (1H), the data line driving circuit 2
A reset signal Res is supplied to 50.
Here, when the switch control signals X1, X2, X3,..., X240 are generally expressed as Xj when they are generally described without specifying a column, the switch control signal Xj is the start end of the horizontal scanning period (1H). To the rear side of the time axis from the scanning line 31 selected in the horizontal scanning period.
Only the period corresponding to the gradation value specified by the gradation data Da of the pixel corresponding to the intersection of the 1st and jth data lines 211 is set to the H level, and the remaining period is set to the L level.

On the other hand, the switch 260 is a data side switch provided corresponding to each of the data lines 211 in the 1st to 240th columns. In each switch 260, one terminal is connected to the data line 211 corresponding to itself, and the other terminal is commonly connected to the power supply line 281. These switches 260 are, for example, switches 260 corresponding to the data line 211 in the j-th column.
Is conductive between one terminal and the other terminal when the switch control signal Xj is at H level (
On-state, on the other hand, it becomes non-conducting (off) state at the L level.
Here, for convenience, the voltage of the data line 211 in the 240th column is set to S1, S2,
Indicated as S3,..., S240, and in general description without specifying a column, it is expressed as Sj.

Note that the writing polarity with respect to the liquid crystal capacitor 130 is positive when the potential of the pixel electrode 231 is high with respect to the voltage Vcom, and negative when the potential of the pixel electrode 231 is low. In this embodiment, as will be described in detail later, the ramp signal Vout that changes in voltage from the voltage Vcom passes along the path of the power supply line 281 → (on state) switch 260 → data line 211 → (on state) TFT 241. Since the common electrode 110 is kept constant at the voltage Vcom while being applied to the pixel electrode 231, the writing polarity with respect to the liquid crystal capacitor 130 becomes positive when the ramp signal changes in the upward direction from the voltage Vcom. When changing from Vcom in the downward direction, the negative polarity is obtained. For this reason, the polarity instruction signal Pol that specifies the voltage change direction of the ramp signal also specifies the writing polarity to the liquid crystal capacitor 130.
As shown in FIG. 5, the polarity instructing signal Pol is inverted every horizontal scanning period (1H) within the vertical scanning period (1F) and the same horizontal in the adjacent vertical scanning periods (1F). Even if attention is paid to the scanning period, the polarity is reversed. For this reason, in this embodiment,
Although the scanning line inversion (row inversion) in which the writing polarity is inverted for each scanning line is performed, the present invention is not limited to this. The reason why the polarity is inverted in this way is to prevent deterioration due to application of a direct current component to the liquid crystal.

Next, the detailed configuration of the buffer circuit 20 will be described. FIG. 3 is a block diagram showing a configuration of the buffer circuit 20.
As shown in this figure, the buffer circuit 20 includes a load determination circuit 22 and a switch 201.
, 202, 203 and voltage buffers 221, 222, 223.
The ramp signal Vrp from the ramp signal generation circuit 10 is commonly supplied to one end of each of the switches 201, 202, and 203. The other end of the switch 201 is connected to the input end of the voltage buffer 221, and similarly, the other ends of the switches 202 and 203 are connected to the input ends of the voltage buffers 222 and 223, respectively. The output terminals of the voltage buffers 221, 222, and 223 are connected to the feeder line 2
81 is commonly connected.
Therefore, the series connection of the switch 201 and the voltage buffer 221, the series connection of the switch 202 and the voltage buffer 222, and the series connection of the switch 203 and the voltage buffer 223 are connected in parallel to each other.
Here, the switch 201 is turned on when the switch control signal d1 is at the H level, and is turned off when the switch control signal d1 is at the L level. Similarly, the switches 202 and 203 are turned on when the switch control signals d2 and d3 are at the H level, and are turned off when the switch control signals d2 and d3 are at the L level.
Each of the voltage buffers 221, 222, and 223 is composed of an operational amplifier, and buffers the voltage at the input end and outputs it to the output end. In this embodiment, the drive capacity is 1: 2 respectively. : The ratio is set to 4.

The load determination circuit 22 controls the data Nx according to the number of switch control signals X1 to X240 that are at the H level, that is, the number of switches 260 that are turned on among the switches 260 corresponding to the columns 1 to 240. It defines the logic levels of the signals d1, d2, and d3. Specifically, as shown in FIG. 4, as the number of turned on decreases (as the number that changes to the off state increases), the driving capability by the combination of the voltage buffers 221, 222, and 223 decreases. Further, the logic levels of the switch control signals d1, d2, and d3 are set.

Next, writing in the electro-optical device 1 having such a configuration will be described.
As already shown in FIG. 5, in the vertical scanning period (1F), the scanning signals Y1 to Y320 sequentially become the H level, but here, the scanning signal Yi in the i-th row and the following (i + 1).
A case where the scanning signal Y (i + 1) in the row becomes the H level will be described. FIG. 6 shows i row j
It is a figure which shows the writing of the pixel of a column, and the writing of the pixel of the (i + 1) row j column adjacent one row below this in relation to the scanning signals Yi and Y (i + 1).
When the pixel in i row and j column is set to an intermediate gradation between white of the highest gradation and black of the lowest gradation, and the polarity instruction signal Pol is H level, the scanning signal Yi is H level. Scanning period (
In 1H), switch control signal Xj from the beginning of the horizontal scanning period (1H), the period T ₁ H level only in accordance with the halftone. When the switch control signal Xj becomes H level, the switch 260 in the j-th column is turned on, so that the data line 211 in the j-th column is connected to the power supply line 281. Therefore, the data line 211 in the j-th column has the horizontal scanning period (1H
), A ramp signal Vout that gradually rises from the voltage Vcom is applied. Here, when the scanning signal Yi becomes H level, the pixels 12 for one row located on the i-th scanning line 311.
At 0, the TFT 241 is turned on.
Therefore, the pixel electrode 231 in the pixel 120 in the i row and the j column has the data line 2 in the j column.
11 is applied through the TFT 241 in the on state.
Since the common electrode 110 is maintained at the voltage Vcom, in the liquid crystal capacitor 130 in the pixel in the i-th row and j-th column, the switch 260 in the j-th column is turned on when the TFT 241 is in the on-state. Writing with 231 as the high-order side is started.

Next, when the elapse of time T ₁ from the start of the horizontal scanning period, the data signal Xj is changed from H level to L level. For this reason, since the switch 260 is turned off, the data line 211 in the j-th column is in a high impedance state where the voltage is uncertain.
At this time, if the TFT 241 is in an on state, the pixel electrode 231 is also in a high impedance state. However, since the liquid crystal capacitor 130 holds a difference voltage between the ramp signal Vout immediately before that, that is, immediately before the switch 260 changes to the OFF state, and the voltage Vcom of the common electrode 110, the data line in the j-th column The voltage Sj and the voltage of the pixel electrode 231 are maintained at the voltage of the ramp signal Vout in the immediately preceding state.
Therefore, the write voltage for the liquid crystal capacitor 130 in the i row and the j column is determined at the moment when the switch 260 in the j column is turned off during the period in which the scanning signal Yi is at the H level, and the polarity instruction signal Pol is at the H level. If there is a difference voltage (voltage indicated by ↑ in FIG. 6) between the voltage Vout and the voltage Vcom at the moment when the switch 260 in the j-th column is turned off, even after the switch 260 is turned off with the pixel electrode 231 at the higher side. Will be retained.
This holding state is similarly maintained even when the TFT 241 is turned off at the end of the horizontal scanning period. In addition, here, the operation has been described by representatively assuming that the pixel located in the j-th column among the pixels in the i-th row, but in the period when the scanning signal Yi is at the H level, 1 to 2 located in the i-th row.
Writing for the j-th column is performed in parallel for all the 40-column pixel rows.

In the next horizontal scanning period (1H), the scanning signal Y (i + 1) is at the H level.
Writing is performed in the same manner for pixels for one row located in the (i + 1) th row. However,
In this embodiment, since the writing polarity is inverted for each scanning line, as a result of the polarity instruction signal Pol being inverted to the L level, the ramp signal Vout falls from the voltage Vcom in the horizontal scanning period.
Therefore, the write voltage for the liquid crystal capacitor 130 in (i + 1) rows and j columns is equal to the scanning signal Y (
i + 1) is determined at the moment when the switch 260 in the j-th column is turned off during the period when the switch 260 in the j-th column is turned off, and the voltage difference between the voltage Vout and the voltage Vcom at the moment when the switch 260 in the j-th column is turned off (in FIG. 6) The voltage indicated by ↓) is the switch 2 with the pixel electrode 231 at the lower side.
Even after the TFT 60 is turned off, the TFT 241 is held even if the TFT 241 is turned off.

Here, the writing of the i and (i + 1) th rows adjacent to each other is described.
Such writing is executed for each horizontal scanning period in the order of rows 1, 2, 3,..., 320 in the vertical scanning period (1F), and an image of one frame is displayed. Also,
In the next vertical scanning period (1F), the writing polarity is reversed in each row, and similar writing is executed.

In the electro-optical device according to the present embodiment, regardless of the logic level of the polarity instruction signal Pol, all the switches 260 are in the on state at the start of each horizontal scanning period, and then selected in the horizontal scanning period. The switch 260 that is in the on state gradually changes to the off state in accordance with the display content for one row of pixels located on the scanning line. Specifically, since the normally white mode is used in this embodiment, if there are many pixels that should be dark tones in one row located in the scanning line selected in the horizontal scanning period, the time is delayed. On the other hand, the number of switches 260 that are turned off at a certain timing increases, while the number of switches 260 that turn off at a timing that is earlier in time increases when there are many pixels that should have a bright gradation.

The large number of switches 260 that are in the on state in a certain horizontal scanning period means that the number of data lines 211 and pixel electrodes 231 to which the signal Vout is to be supplied is large.
That is, the load is large), which means that the load capacity of the feeder line 281 is large. For this reason, the buffer circuit 20 that outputs the ramp signal Vout is required to have a higher driving capability.
If the driving capability of the buffer circuit 20 is low with respect to the size of the load, the ramp signal Vout
Since it becomes impossible to follow the voltage change of the ramp signal Vrp as an input, it becomes impossible to hold the voltage according to the gradation in the liquid crystal capacitor 130 and the display quality deteriorates.

Here, if the driving capability of the circuit that buffers the ramp signal Vrp is constant, the driving capability is the highest (that is, all the switches 260 in the 1st to 240th columns are in the on state).
Therefore, the power consumed by the circuit becomes large.
In contrast, in the buffer circuit 20 according to the present embodiment, when all the switches 260 are in the on state at the start of the horizontal scanning period, the switch control signals d1, d2, and d3 are set to H as shown in FIG. Therefore, the switches 201, 202, and 203 are turned on to output the ramp signal Vout with the maximum driving capability. Thereafter, as the number of switches 260 that continue to be turned on decreases (changes to the off state). As the number of switches 260 increases), the ramp signal Vout is output with a gradually reduced driving capability. As described above, in the present embodiment, the ramp signal Vout having a gradually reduced driving capability is output in accordance with the decrease in load, so that the power consumed by the buffer circuit 20 can be suppressed while maintaining high display quality. Can do it.

In the embodiment described above, the load determination circuit 22 defines the logic levels of the control signals d1, d2, and d3 according to the number of switch control signals X1 to X240 that are at the H level. As the basis, any element that reflects the load capacity of the power supply line 281 to which the ramp signal Vout is supplied may be used.
For example, the switch control signals X1 to X240 are based on the gradation data for one row corresponding to the position of the scanning line to be selected among the gradation data Da stored in the storage area of the data line driving circuit 250. The logic levels of the control signals d1, d2, and d3 in the horizontal scanning period may be defined based on the result of calculating the gradation data for one row.

When the switches 201, 202, 203 are turned off, the voltage buffers 221, 22 are used.
If the power supply to the power sources 2 and 223 is interrupted, the power consumption can be further reduced.
In the buffer circuit 20, three voltage buffers having different driving capabilities are used. However, for example, four buffers such as 1: 2: 4: 8 may be used, and switching may be performed in 16 stages. It may be possible to switch with finer accuracy.
In addition, while operating all voltage buffers of the same drive capability at the beginning of the horizontal scan period,
A configuration may be adopted in which the number of voltage buffers to be operated is gradually reduced as the load decreases.

In the electro-optical device 1 shown in FIG. 1, the ramp signal Vout is supplied to the power supply line 281 that commonly connects the other ends of the switches 260, and the voltage Vcom is applied to the common electrode 110. FIG. As described above, the ramp signal Vout is applied to the common electrode 110 and the power supply line 281 is applied.
Alternatively, the voltage Vcom may be applied. In such a configuration, the load capacity of the common electrode 110 decreases as the number of switches 260 turned off increases, and the driving capability of the ramp signal Vout is also reduced by the buffer circuit 20 with this decrease.
In this configuration, when the switch 260 is turned off, as shown in FIG. 8, the voltage of the pixel electrode 231 (the voltage Sj of the data line in the j-th column) maintains the difference voltage held immediately before. It changes at the same rate as the ramp signal Vout.

The rate of increase or decrease of the ramp signal Vrp does not have to be constant, and may be monotonously increasing or decreasing. For example, a so-called gamma curve with a bow may be used.
Further, the ramp signal Vrp (Vout) is raised from the voltage Vcom to the voltage Vp if the positive polarity writing is designated, and is lowered from the voltage Vcom to the voltage Vm if the negative polarity writing is designated. However, for example, if positive polarity writing is specified, the voltage Vcom is increased from the voltage Vp. If negative polarity writing is specified, the voltage applied to the common electrode 110 is switched from the voltage Vcom to the voltage Vp. The ramp signal Vrp (Vout) may be lowered from the voltage Vp to the voltage Vcom. As described above, in the configuration in which the voltage applied to the common electrode 110 is switched between the two values, the voltage change range of the ramp signal Vrp (Vout) can be halved. Therefore, the scanning line driving circuit 350, the data line driving circuit 250, and the voltage buffer 221 are used. , 222, and 223, the voltage withstand voltage can be reduced, and the configuration can be simplified correspondingly.

Further, although the liquid crystal capacitor 130 is in the normally white mode, it may be in a normally black mode in which the liquid crystal capacitor 130 becomes dark when no voltage is applied. Furthermore, R (red), G (green),
Color display may be performed by configuring one dot with three B (blue) pixels, and another one color (for example, cyan (C)) is added, and one dot is formed with these four color pixels. To improve color reproducibility.

<Electronic equipment>
Next, an electronic apparatus in which the electro-optical device 1 according to the above-described embodiment is applied to a display device will be described. FIG. 9 is a diagram illustrating a configuration of a mobile phone 1200 using the electro-optical device 1 according to the embodiment.
As shown in this figure, a cellular phone 1200 includes the electro-optical device 1 described above, together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206.
Note that components of the electro-optical device 1 other than the portion corresponding to the display region 100 do not appear as an appearance.
As an electronic apparatus to which the electro-optical device 1 is applied, in addition to the mobile phone shown in FIG. 9, a digital still camera, a notebook computer, a liquid crystal television, a viewfinder type (or a monitor direct view type) video recorder. , Car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, devices equipped with touch panels, and the like. Needless to say, the above-described electro-optical device 1 is applicable as a display device of these various electronic devices.

1 is a diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. It is a figure which shows the structure of the buffer circuit in the same electro-optical apparatus. It is a figure which prescribes | regulates the switch control signal in the buffer circuit. FIG. 6 is a diagram for explaining an operation in the electro-optical device. FIG. 6 is a diagram for explaining an operation in the electro-optical device. It is a figure which shows the structure of the modification in the same electro-optical apparatus. It is a figure which shows operation | movement of the modification. It is a figure which shows the structure of the mobile telephone to which the electro-optical apparatus which concerns on embodiment is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electro-optical device, 10 ... Lamp signal generation circuit, 20 ... Buffer circuit, 22 ... Load determination circuit, 110 ... Common electrode, 120 ... Pixel, 201-203 ... Switch, 221-223
DESCRIPTION OF SYMBOLS ... Voltage buffer, 211 ... Data line, 231 ... Pixel electrode, 241 ... TFT, 250 ... Data line drive circuit, 281 ... Feed line, 311 ... Scan line, 350 ... Scan line drive circuit, 400 ... Control circuit

Claims (5)

Including a pair of a pixel electrode and a switching element provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, the switching element between the data line and the pixel electrode,
A drive circuit of an electro-optical device including a plurality of pixels that become conductive when a selection voltage is applied to the scanning line,
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order and applying the selection voltage;
A plurality of data-side switches provided corresponding to each of the plurality of data lines and having one end connected to the data line and the other end commonly connected to a power supply line;
A ramp signal generation circuit for generating a ramp signal whose voltage monotonously changes over a period in which the selection voltage is applied to one scanning line;
A buffer circuit for buffering the ramp signal and supplying the buffer signal to either the power supply line or the common electrode facing the pixel electrode;
Among the plurality of scanning lines, in a period in which a selection voltage is applied to one scanning line, the data side switch is connected to the scanning line to which the selection voltage is applied and a data line connected to one end of the data side switch. It is turned on only for a period corresponding to the gradation of the pixel corresponding to the intersection with
A data line driving circuit for controlling the data side switch to an off state;
With
The buffer circuit switches the driving ability of the ramp signal in accordance with display contents of one row of pixels located on a scanning line to which the selection voltage is applied during a period in which the selection voltage is applied. A driving circuit for the electro-optical device. In the period when the selection voltage is applied,
Either the power supply line or the common electrode is kept at a predetermined voltage,
The voltage of the ramp signal changes in a direction away from the predetermined voltage,
2. The drive circuit for an electro-optical device according to claim 1, wherein the buffer circuit reduces the drive capability of the ramp signal as the number of columns in which the data-side switch is turned on decreases. The buffer circuit is
A plurality of operational amplifiers connected in parallel to each other;
A load determination circuit that determines a combination of buffers that perform a buffer operation among the plurality of operational amplifiers according to the number of columns in which the data-side switch is turned on in a period in which the selection voltage is applied;
The drive circuit of the electro-optical device according to claim 2, wherein Including a pair of a pixel electrode and a switching element provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, the switching element between the data line and the pixel electrode,
A plurality of pixels that become conductive when a selection voltage is applied to the scan line;
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order and applying the selection voltage;
A plurality of data-side switches provided corresponding to each of the plurality of data lines and having one end connected to the data line and the other end commonly connected to a power supply line;
A ramp signal generation circuit for generating a ramp signal whose voltage monotonously changes over a period in which the selection voltage is applied to one scanning line;
A buffer circuit for buffering the ramp signal and supplying the buffer signal to either the power supply line or the common electrode facing the pixel electrode;
Among the plurality of scanning lines, in a period in which a selection voltage is applied to one scanning line, the data side switch is connected to the scanning line to which the selection voltage is applied and a data line connected to one end of the data side switch. It is turned on only for a period corresponding to the gradation of the pixel corresponding to the intersection with
A data line driving circuit for controlling the data side switch to an off state;
With
The buffer circuit switches the driving ability of the ramp signal in accordance with display contents of one row of pixels located on a scanning line to which the selection voltage is applied during a period in which the selection voltage is applied. An electro-optical device.   An electronic apparatus comprising the electro-optical device according to claim 4.

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