JP2008026774A - Electro-optical device, method for manufacturing same, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve performance of a TFT for pixel switching and to enhance light shielding property in an electro-optical device. <P>SOLUTION: The electro-optical device includes, on a substrate 10: data lines 6a; scanning lines 11a; pixel electrodes 9a provided in accordance with intersections of the data lines and scanning lines; and transistors 30 each having a semiconductor layer 1a including a first LDD (lightly doped drain) region 1b formed between a channel region 1a' and a source region 1d and a second LDD region 1c formed between the channel region and a drain region 1e, and a gate electrode 3a overlapping the channel region. Further, the device includes a first light shielding section 11a disposed in a layer different from the gate electrode over an insulating film 41a, at least partially overlapping the first and the second LDD regions, and electrically connected to the gate electrode. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electro-optical device such as a liquid crystal device and a manufacturing method thereof, and a technical field of an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  A liquid crystal device which is an example of this type of electro-optical device is frequently used not only as a direct-view display but also as a light modulation means (light valve) of, for example, a projection display device. In particular, in the case of a projection display device, strong light from a light source is incident on a liquid crystal light valve, and this thin film transistor (TFT: Thin Film Transistor) in the liquid crystal light valve does not cause an increase in leakage current or malfunction. As described above, a light shielding film as a light shielding means for blocking incident light is built in the liquid crystal light valve. However, in a TFT in which an LDD (Lightly Doped Drain) region is formed in a semiconductor layer for the purpose of reducing off-state current (that is, a TFT having an LDD structure), light emitted to the LDD region is irradiated to the LDD region. There is a problem that leakage current occurs. Thus, for example, Patent Document 1 proposes a technique for reducing the light leakage current by covering the LDD region of the TFT with a gate electrode.

  On the other hand, in the field of semiconductors, a TFT having a so-called GOLD (Gate drain OverLapped Device) structure is known (see, for example, Patent Document 2). In the TFT having the GOLD structure, the gate electrode is formed so as to overlap with the source / drain regions, and this makes it possible to increase the channel current during the operation of the TFT.

JP 2001-1119027 A Japanese Patent Laid-Open No. 2-116137

  However, according to the technique disclosed in Patent Document 1 described above, the TFT may not be sufficiently shielded from light when the above-described light shielding film is formed thin in order to improve the aperture ratio or downsize the device. There is a technical problem. In addition, the TFT having the GOLD structure described above has a technical problem that the channel current may increase during non-operation.

  The present invention has been made in view of the above-described problems, for example, and improves the performance of a transistor for pixel switching and has improved light shielding properties, and an electro-optical device capable of displaying a high-quality image, and the same It is an object to provide a manufacturing method and an electronic apparatus including the electro-optical device.

  In order to solve the above problems, a first electro-optical device according to the present invention has a plurality of data lines and a plurality of scanning lines intersecting each other on a substrate, and the intersection of the plurality of data lines and the plurality of scanning lines. And a pixel electrode formed in each of a plurality of pixels constituting the display region on the substrate, and electrically connected to the pixel electrode, and between the channel region and the source region A semiconductor layer having a formed first LDD region and a second LDD region formed between the channel region and the drain region; a transistor having a gate electrode overlapping the channel region; and the gate electrode Are disposed in different layers with an insulating film interposed therebetween, and are formed so as to overlap at least partially with the first and second LDD regions when viewed in plan on the substrate and And a over gate electrode and the first light-shielding portion that is electrically connected.

  According to the first electro-optical device of the present invention, for example, an image signal is controlled from a data line to a pixel electrode, and an image display by a so-called active matrix method is possible. The image signal is supplied to the pixel electrode at a predetermined timing, for example, when a transistor described later is turned on / off. The pixel electrode is a transparent electrode made of a transparent conductive material such as ITO (Indium Tin Oxide), for example, and a plurality of pixel electrodes are provided in a matrix form in a region to be a display region on the substrate corresponding to the intersection of the data line and the scanning line. It is done.

  The transistor includes a semiconductor layer including a channel region and a gate electrode overlapping with the channel region. The semiconductor layer has a first LDD region formed between the channel region and the source region, and a second LDD region formed between the channel region and the drain region. That is, the transistor has an LDD structure.

  Each of the “first LDD region” and the “second LDD region” is an impurity region formed by implanting impurities into the semiconductor layer by impurity implantation such as ion implantation. Such impurity regions are formed in mirror symmetry on both sides of the channel region along the channel length in the semiconductor layer, and reduce off-current flowing in the source region and the drain region when the transistor is not operating. It is possible to suppress a decrease in on-current flowing during the operation.

  The gate electrode is formed so as to overlap the channel region. The gate electrode may be formed as a portion of the scanning line that overlaps the channel region, or may be a conductive film provided separately from the scanning line. Such a conductive film is electrically connected to the scanning line through connection means such as a contact hole.

  In the present invention, in particular, the gate electrode of the transistor and the insulating layer are disposed in different layers, and are formed so as to at least partially overlap the first and second LDD regions when viewed in plan on the substrate. A first light shielding portion. That is, the first light-shielding portion has a light-shielding property so as to cover at least partially the first and second LDD regions when viewed in plan on the substrate, for example, on the upper layer side of the gate electrode through the insulating film. Are formed by laminating these conductive films. Therefore, the light irradiated to the first and second LDD regions can be reduced. In other words, the light traveling toward the first and second LDD regions is shielded by the first light shielding portion formed so as to at least partially overlap the first and second LDD regions. Therefore, it can be suppressed that light leakage current is generated in the first and second LDD regions by irradiating the first and second LDD regions with light. As a result, display defects such as flicker caused by the occurrence of light leakage current can be reduced.

  Here, “at least partially overlaps the first and second LDD regions” according to the present invention includes not only the case where the first and second LDD regions overlap partially or completely, but also the first This also includes a case where it partially or completely overlaps only with the LDD region, and a case where it partially or completely overlaps only with the second LDD region. From the viewpoint of improving the light blocking property of blocking the light reaching the first and second LDD regions, it is preferable that the first light blocking portion overlaps both the first and second LDD regions.

  Further, in the present invention, in particular, the first light-shielding portion is electrically connected to the gate electrode via a connection means such as a contact hole opened in an insulating film laminated between the first light-shielding portion and the gate electrode. Connected. Accordingly, an electric field can be applied at least partially to the first and second LDD regions in addition to the channel region during the operation of the transistor. Accordingly, the on-current that flows during the operation of the transistor can be increased. In addition, since the first light-shielding portion is disposed in different layers with the gate electrode and the insulating film interposed therebetween, an increase in off-current that flows when the transistor is not in operation can be suppressed. In other words, by adjusting the thickness of the insulating film positioned between the first light-shielding portion and the gate electrode, it is possible to increase the on-current that flows during the operation of the transistor while suppressing the off-current during the non-operation. .

  As described above, according to the first electro-optical device according to the present invention, the first light-shielding portion that at least partially overlaps the first and second LDD regions of the transistor electrically connected to the pixel electrode, Generation of light leakage current in the first and second LDD regions can be suppressed, and an on-current that flows during the operation of the transistor can be increased. This makes it possible to display a high-quality image with reduced display defects such as flicker.

  In one aspect of the first electro-optical device according to the present invention, the first light shielding portion is formed as a part of the scanning line.

  According to this aspect, the first light-shielding portion is a direction in which, for example, the data line extends from a part of the scanning line, that is, the main line portion along the direction in which the scanning line extends (that is, the X direction). In other words, it is formed as an extended portion that extends in the Y direction. Accordingly, a part of the scanning line can function as the first light shielding portion, so that the light shielding property of the first and second LDD regions is improved and the transistor is hardly caused without causing the complicated laminated structure on the substrate. The on-state current can be increased. The first light shielding part may be formed as a part of the main line part, or may be formed as a part of the main line part and the extending part.

  In another aspect of the first electro-optical device according to the invention, the first portion is formed in a layer different from the transistor, and extends along the first direction in the display region, and the first direction A second portion extending along the intersecting second direction, and a first region extending along the first direction among the non-opening regions separating the opening regions of the plurality of pixels from each other, and the first of the non-opening regions. In a crossing region where a second region extending in two directions crosses each other, the first part and the second part include a second light-shielding part having a crossing part where they cross each other. The data line is electrically connected to the drain region, the data line is electrically connected to the source region, and at least a part of the second LDD region overlaps the intersection.

  According to this aspect, the second light-shielding portion has the second LDD region overlapped with the intersecting portion, so that the second LDD region does not overlap with the intersecting portion. Light irradiated to the LDD region can be reduced.

  Further, the inventor of the present application provides a source electrically connected to the data line in the second LDD region formed between the drain region and the channel region electrically connected to the pixel electrode during the operation of the transistor. It is presumed that the light leakage current is relatively likely to occur as compared with the first LDD region formed between the region and the channel region.

  Therefore, according to this aspect, since at least a part of the second LDD region overlaps the intersection, the LDD region where the light leakage current is likely to be generated can be shielded, and the light leakage current flowing through the transistor is effectively reduced. it can.

  The “first region” according to the present invention is a region extending in the first direction of the display region among the non-opening regions extending in a lattice pattern in the display region so as to separate the adjacent opening regions from each other. More specifically, for example, the row direction of a plurality of pixels defined in a matrix on the substrate, that is, the arrangement direction in which a plurality of scanning lines are arranged. The data lines intersecting the plurality of scanning lines are formed in the first region, and the scanning lines are formed in the second region described later. An “opening region” according to the present invention is a region in a pixel through which light is substantially transmitted, for example, a region in which a pixel electrode is formed, and an electro-optic such as a liquid crystal according to a change in transmittance. This is a region where the gradation of the emitted light that has passed through the substance can be changed. In other words, the “opening region” is a light shielding body such as a wiring, a light shielding film, and various elements in which the light collected on the pixel does not transmit the light or the light transmittance is relatively smaller than that of the transparent electrode. An area that is not obstructed. The “non-opening region” according to the present invention means a region where light contributing to display is not transmitted, for example, a region where a non-transparent wiring or electrode, or a light-shielding body such as various elements is arranged in a pixel. Means. The “aperture ratio” according to the present invention means the ratio of the aperture area in the pixel size including the aperture area and the non-aperture area, and the display performance of the electro-optical device according to the present invention improves as the aperture ratio increases. .

  A second electro-optical device according to the present invention is defined on a substrate in correspondence with a plurality of data lines and a plurality of scanning lines intersecting each other, and the intersection of the plurality of data lines and the plurality of scanning lines. A pixel electrode formed in each of a plurality of pixels constituting the display region on the substrate, and a first electrode formed between the first channel region and the source region and electrically connected to the pixel electrode. And a first semiconductor layer having a second LDD region formed between the first channel region and the drain region, and overlapping the first channel region and the first and second layers. And a first transistor having a first gate electrode that at least partially overlaps the LDD region.

  According to the second electro-optical device according to the present invention, image display is performed in substantially the same manner as the above-described first electro-optical device according to the present invention.

  In the present invention, the first semiconductor layer included in the first transistor electrically connected to the pixel electrode includes the first LDD region formed between the first channel region and the source region, and the first transistor A second LDD region is formed between the channel region and the drain region.

  Each of the “first LDD region” and the “second LDD region” is an impurity region formed by implanting impurities into the first semiconductor layer by impurity implantation such as ion implantation. Such impurity regions are formed in mirror symmetry on both sides of the first channel region along the channel length in the first semiconductor layer, and flow into the source region and the drain region when the first transistor is not operating. The off-state current can be reduced, and the decrease in the on-state current that flows during the operation of the first transistor can be suppressed.

  Particularly in the present invention, the first gate electrode constituting the first transistor overlaps the first channel region of the first semiconductor layer and at least partially overlaps the first and second LDD regions. That is, the first transistor has a so-called GOLD structure. Therefore, the light irradiated to the first and second LDD regions can be reduced. In other words, the light traveling toward the first and second LDD regions is shielded by the gate electrode formed so as to at least partially overlap the first and second LDD regions. Therefore, it can be suppressed that light leakage current is generated in the first and second LDD regions by irradiating the first and second LDD regions with light. As a result, display defects such as flicker caused by the occurrence of light leakage current can be reduced.

  The first gate electrode may be formed as a portion of the scanning line that overlaps the first channel region and the first and second LDD regions, or may be a conductive film provided separately from the scanning line. Such a conductive film is electrically connected to the scanning line through connection means such as a contact hole. From the viewpoint of improving the light shielding property of blocking the light reaching the first and second LDD regions, it is preferable that the first gate electrode overlaps both the first and second LDD regions.

  Further, the first gate electrode overlaps the first channel region of the first semiconductor layer and at least partially overlaps the first and second LDD regions, so that the first channel region is operated during the operation of the first transistor. In addition, an electric field can be applied at least partially to the first and second LDD regions. Therefore, the on-state current that flows during the operation of the first transistor can be increased.

  As described above, according to the second electro-optical device of the present invention, in addition to the first channel region of the first semiconductor layer, the gate electrode at least partially overlaps with the first and second LDD regions. In addition, it is possible to suppress the occurrence of light leakage current in the first and second LDD regions, and to increase the on-current that flows during the operation of the first transistor. This makes it possible to display a high-quality image with reduced display defects such as flicker.

  In an aspect of the second electro-optical device according to the invention, the first gate electrode is formed as a part of the scanning line.

  According to this aspect, the first gate electrode is formed as a part of the scanning line. More specifically, the first gate electrode covers, for example, a part of the main line part along the direction in which the scanning line extends (that is, the X direction) and the first and second LDD regions from the part. It is formed as an extension part extended in the. Therefore, a part of the scanning line functions as the first gate electrode that overlaps the first and second LDD regions in addition to the first channel region. In addition, the light shielding property of the second LDD region can be improved and the on-current of the first transistor can be increased.

In another aspect of the second electro-optical device according to the invention, the first portion is formed in a different layer from the first transistor, and extends along the first direction in the display region. A second portion extending along a second direction intersecting with one direction, and a first region extending along the first direction and a non-opening region among the non-opening regions separating the opening regions of the plurality of pixels from each other. Among these, in a crossing region where the second region extending along the second direction intersects with each other, the pixel electrode includes a light-shielding part having a crossing part where the first part and the second part cross each other. Electrically connected to the drain region, the data line is electrically connected to the source region;
At least a part of the second LDD region overlaps the intersection.

  According to this aspect, the light-shielding portion formed in a different layer from the first transistor has the second LDD region where at least part of the light-shielding portion overlaps the intersecting portion, so that the light leakage current is likely to occur. The LDD region can be shielded from light, and the light leakage current flowing through the transistor can be effectively reduced.

  In another aspect of the second electro-optical device according to the invention, the second electro-optical device is disposed in a peripheral region located around the display region, and is provided on each of both sides of the second channel region for driving the pixel electrode. A driving circuit including a second semiconductor layer having a third LDD region provided and a second transistor having a second gate electrode which overlaps with the second channel region and does not overlap with the third LDD region; .

  According to this aspect, a drive circuit such as a data line drive circuit, a sampling circuit, or a scan line drive circuit for driving the pixel electrode is provided in the peripheral region, and the drive circuit is connected to the third LDD. A second transistor having a second semiconductor layer in which the region is formed and a second gate electrode is included. In this embodiment, in particular, the second gate electrode is formed so as to overlap the second channel region and not the third LDD region in the second semiconductor layer, that is, the second transistor has an LDD structure. Therefore, when the second transistor included in the driver circuit is not in operation, off current flowing in the source region and the drain region can be reduced, and reduction in on current flowing in the operation of the transistor can be suppressed.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described first or second electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic apparatus of the present invention, since it includes the first or second electro-optical device according to the present invention described above, a projection display device, a television, Various electronic devices such as a cellular phone, an electronic notebook, a word processor, a viewfinder type or a monitor direct-view type video tape recorder, a workstation, a video phone, a POS terminal, and a touch panel can be realized. In addition, as an electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper, an electron emission device (Field Emission Display and Conduction Electron-Emitter Display), and a display device using these electrophoretic device and electron emission device are realized. Is also possible.

  In order to solve the above problems, a first electro-optical device manufacturing method according to the present invention includes a first doping step of doping a semiconductor layer formed in a display region on a substrate with a first conductivity type impurity, After the first doping step, a gate electrode is formed in a region to be a channel region of the semiconductor layer, and the semiconductor layer is doped with an impurity of a second conductivity type different from the first conductivity type using the gate electrode as a mask. Forming a channel region and forming the second conductivity type impurity region on both sides of the channel region; and after the second doping step, on the semiconductor layer and the gate electrode. A first insulating film stacking step of stacking a first insulating film on the first insulating film, a region on the first insulating film, a region to be a first LDD region between the channel region and the source region, and a front surface A light shielding portion forming step of forming a light shielding portion from a light shielding conductive material so as to cover a region to be a second LDD region between the channel region and the drain region and to be electrically connected to the gate electrode. And a third doping step of forming the source region, the drain region, and the first and second LDD regions by doping the semiconductor layer with the second conductive type impurity using the light shielding portion as a mask. A wiring forming step for forming a plurality of data lines and a plurality of scanning lines intersecting each other on the substrate, and a line forming step defined on the substrate and corresponding to the intersection of the plurality of data lines and the plurality of scanning lines. A pixel electrode forming step of forming a pixel electrode in each of a plurality of pixels constituting the display region.

  According to the manufacturing method of the first electro-optical device according to the present invention, the first electro-optical device according to the present invention described above can be manufactured. Here, in particular, since the light shielding portion is formed by the light shielding portion forming step so as to overlap with the channel region of the transistor formed in the display region and the first and second LDD regions, in the first and second LDD regions. The generation of light leakage current can be suppressed and the on-current that flows during operation of the transistor can be increased. Therefore, an electro-optical device that can display a high-quality image can be manufactured.

  In another aspect of the method of manufacturing the first electro-optical device according to the invention, the light shielding part forming step forms the light shielding part as a part of the scanning line.

  According to this aspect, since the light shielding portion is formed as a part of the scanning line, the manufacturing process can be simplified.

  In order to solve the above problems, a second electro-optical device manufacturing method according to the present invention includes a first doping step of doping a semiconductor layer formed in a display region on a substrate with a first conductivity type impurity, After the first doping step, a resist film is formed in a region to be a channel region of the semiconductor layer, and the semiconductor layer is doped with an impurity of a second conductivity type different from the first conductivity type using the resist film as a mask. A second doping step of forming the channel region and forming the impurity region of the second conductivity type on both sides of the channel region; and after the second doping step, the channel region of the semiconductor layer. , So as to overlap a region to be the first LDD region between the channel region and the source region and a region to be the second LDD region between the channel region and the drain region, Forming a gate electrode from a light-shielding conductive material, and doping the semiconductor layer with the second conductivity type impurity using the gate electrode as a mask, the source region, the drain region, and A third doping step for forming the first and second LDD regions; a wiring forming step for forming a plurality of data lines and a plurality of scanning lines intersecting each other on the substrate; And a pixel electrode forming step of forming a pixel electrode on each of the plurality of pixels that are defined corresponding to the intersection of the plurality of scanning lines and that constitute the display region.

  According to the second electro-optical device manufacturing method of the present invention, the above-described second electro-optical device of the present invention can be manufactured. Here, in particular, since the gate electrode is formed so as to overlap the channel region of the transistor formed in the display region and the first and second LDD regions by the gate electrode forming step, the gate electrode in the first and second LDD regions is formed. The generation of light leakage current can be suppressed and the on-current that flows during the operation of the transistor can be increased. Therefore, an electro-optical device that can display a high-quality image can be manufactured.

  A first doping step of doping a semiconductor layer formed in a display region on a substrate with a first conductivity type impurity; and a first resist in a region to be a channel region of the semiconductor layer after the first doping step. Forming a channel, and doping the semiconductor layer with an impurity of a second conductivity type different from the first conductivity type using the first resist film as a mask, thereby forming the channel region and both sides of the channel region A second doping step for forming the impurity region of the second conductivity type, and after the second doping step, the channel region, the first LDD region between the channel region and the source region of the semiconductor layer, A gate electrode formed from a light-shielding conductive material so as to partially overlap a region to be formed and a region to be a second LDD region between the channel region and the drain region Forming a second resist film on the semiconductor layer and the light shielding film so as to cover the channel region, the region to be the first LDD region, and the region to be the second LDD region; A resist film forming step to be formed; and the semiconductor layer is doped with an impurity of the second conductivity type using the second resist film as a mask, whereby the source region, the drain region, and the first and second regions A third doping step for forming the LDD region, a wiring formation step for forming a plurality of data lines and a plurality of scanning lines intersecting each other on the substrate, and an intersection of the plurality of data lines and the plurality of scanning lines. And a pixel electrode forming step of forming a pixel electrode in each of a plurality of pixels that define the display region.

  According to the third electro-optical device manufacturing method according to the present invention, the second electro-optical device according to the present invention is substantially the same as the above-described second electro-optical device manufacturing method according to the present invention. Can be manufactured. That is, according to the present invention, the gate electrode is formed so as to overlap with the channel region of the transistor electrically connected to the pixel electrode and partially overlap with the first and second LDD regions in the gate electrode formation step. In addition, generation of light leakage current in the first and second LDD regions can be suppressed, and an on-current that flows during the operation of the transistor can be increased.

  In the present invention, in particular, the gate electrode is formed so as to partially overlap the first and second LDD regions by the gate electrode formation step. More specifically, in the gate electrode formation step, the gate electrode is moved from the boundary between the source region and the first LDD region to the channel region side, and from the boundary between the drain region and the second LDD region to the channel region side. A region where the gate electrode is not formed (that is, an offset) is provided, and is formed so as to overlap the channel region and partially overlap the first and second LDD regions. Therefore, it is possible to reduce or prevent the electric field from the gate electrode from being applied to the boundary between the source region and the first LDD region, and to each of the drain region and the second LDD region. Accordingly, it is possible to suppress an increase in off-state current due to a decrease in breakdown voltage of the transistor.

  In order to solve the above problems, a fourth electro-optical device manufacturing method according to the present invention is formed in a first semiconductor layer formed in a display region on a substrate and a peripheral region positioned around the display region. A first doping step of doping the second semiconductor layer with an impurity of the first conductivity type, and a region to be the first channel region of the first semiconductor layer after the first doping step; A first resist film is formed on the entire surface of the semiconductor layer, and the first and second semiconductor layers are doped with an impurity of a second conductivity type different from the first conductivity type using the first resist film as a mask. A second doping step of forming the first channel region and forming the first impurity region of the second conductivity type on both sides of the first channel region; and after the second doping step, the first semiconductor The first channel region of the layer , Overlapping a region to be a first LDD region between the first channel region and the first source region and a region to be a second LDD region between the first channel region and the first drain region. Forming a first gate electrode and forming a second gate electrode in a region to be a second channel region of the second semiconductor layer, and the first gate electrode and the first gate electrode. A second resist film is formed so as to cover the semiconductor layer, and a second conductivity different from the first conductivity type is formed in the first and second semiconductor layers using the second resist film and the second gate electrode as a mask. A third doping step of forming the second channel region and forming the second conductivity type second impurity region on both sides of the second channel region by doping a type impurity; and Resist And forming a third resist film so as to overlap with the second channel region of the second semiconductor layer and the regions to be the third LDD regions on both sides of the second channel region, The first source region in the first semiconductor layer by doping the first and second semiconductor layers with the second conductivity type impurity using the first gate electrode and the third resist film as a mask, Forming the first drain region, the first and second LDD regions, and forming the second source region and the second drain region and the third LDD region in the second semiconductor layer; Corresponding to a doping process, a wiring forming process for forming a plurality of data lines and a plurality of scanning lines intersecting each other on the substrate, and a plurality of the data lines and the plurality of scanning lines intersecting each other. And a pixel electrode forming step of forming a pixel electrode in each of the plurality of pixels that are defined and constitute the display area.

  According to the fourth electro-optical device manufacturing method of the present invention, the second electric device of the present invention described above is substantially similar to the second and third electro-optical device manufacturing methods of the present invention described above. An optical device can be manufactured. That is, according to the present invention, the first gate electrode is formed to overlap the first channel region, the first and second LDD regions of the transistor electrically connected to the pixel electrode by the gate electrode formation step. Therefore, it is possible to suppress the occurrence of light leakage current in the first and second LDD regions and increase the on-current that flows during the operation of the transistor.

  Furthermore, in the present invention, in particular, transistors having different structures in the display region and the peripheral region can be formed in the same process. That is, by the same manufacturing process, a transistor having a GOLD structure can be formed in the display region and a transistor having an LDD structure can be formed in the peripheral region. Therefore, by forming the transistor to be formed in the display region where light is incident as a GOLD structure, the light leakage is reduced while improving the light shielding property, and should be formed in the peripheral region where little or no light is incident. By forming the transistor included in the driver circuit as an LDD structure, off-state current in the transistor can be suppressed.

  The operation and other advantages of the present invention will become apparent from the best mode for carrying out the invention described below.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, a driving circuit built-in type TFT active matrix driving type liquid crystal device, which is an example of the electro-optical device of the present invention, is taken as an example.
<First Embodiment>
The liquid crystal device and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

  First, the overall configuration of the liquid crystal device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the overall configuration of the liquid crystal device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.

  1 and 2, in the liquid crystal device 1 according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are disposed to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are around the image display region 10 a as an example of the “display region” according to the present invention. They are bonded to each other by a sealing material 52 provided in a sealing region located in the area.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. In the sealing material 52, a gap material such as glass fiber or glass beads for dispersing the distance between the TFT array substrate 10 and the counter substrate 20 (inter-substrate gap) to a predetermined value is dispersed. The liquid crystal device 1 of this embodiment is small and suitable for performing enlarged display for a light valve of a projector.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The sampling circuit 7 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. The scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. Further, in order to connect the two scanning line driving circuits 104 provided on both sides of the image display area 10 a in this way, a plurality of the pixel lines are covered along the remaining side of the TFT array substrate 10 and covered with the frame light shielding film 53. Wiring 105 is provided. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  In FIG. 2, on the TFT array substrate 10, a laminated structure in which wiring for TFTs for pixel switching, scanning lines, data lines and the like is formed is formed. In the image display area 10a, pixel electrodes 9a are provided in a matrix on the upper layer of wiring such as pixel switching TFTs, scanning lines, and data lines. An alignment film is formed on the pixel electrode 9a. On the other hand, a light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. The light shielding film 23 is formed of, for example, a light shielding metal film or the like, and is patterned, for example, in a lattice shape in the image display region 10a on the counter substrate 20. On the light shielding film 23, a counter electrode 21 made of a transparent material such as ITO is formed on almost the entire surface so as to face the plurality of pixel electrodes 9a. An alignment film is formed on the counter electrode 21. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, in addition to the data line driving circuit 101 and the scanning line driving circuit 104, the TFT array substrate 10 is used for inspecting the quality, defects, and the like of the liquid crystal device during manufacturing or at the time of shipment. An inspection circuit, an inspection pattern, or the like may be formed.

  Next, a main configuration of the liquid crystal device will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of the main part of the liquid crystal device according to this embodiment.

  3, the liquid crystal device according to the present embodiment includes a scanning line driving circuit 104, a data line driving circuit 101, a sampling circuit 7 and the like in a peripheral region located around the image display region 10a on the TFT array substrate 10. The drive circuit is formed. Each of these drive circuits includes a plurality of TFTs.

  As shown in FIG. 3, the scanning line driving circuit 104 receives various control signals such as a Y clock signal CLY (and an inverted Y clock signal CLY ′) and a Y start pulse signal from an external circuit via the external circuit connection terminal 102. Is supplied. Based on these signals, the scanning line driving circuit 104 sequentially generates scanning signals G1,..., Gm in this order and outputs them to the scanning line 11a. Further, the power supply VDDY and VSSY for driving the scanning line driving circuit 104 and various control signals are supplied to the scanning line driving circuit 104 via the external circuit connection terminal 102.

  In FIG. 3, an X clock signal and an X start pulse are supplied to the data line driving circuit 101 from an external circuit via the external circuit connection terminal 102. When the X start pulse is input, the data line driving circuit 101 sequentially generates and outputs sampling signals S1,..., Sn at a timing based on the X clock signal. The data line driving circuit 101 is supplied with power supplies VDDX and VSSX and various control signals for driving the data line driving circuit 101 via the external circuit connection terminal 102.

  The sampling circuit 7 is provided with a plurality of sampling switches 7 s composed of P-channel or N-channel single-channel TFTs. The sampling switch 7s may be composed of a complementary TFT.

  In FIG. 3, the liquid crystal device according to the present embodiment is further provided with a plurality of pixel portions 700 arranged in a matrix in the image display region 10a occupying the center of the TFT array substrate.

  Here, the configuration of the pixel portion of the liquid crystal device according to the present embodiment will be described with reference to FIG. 4 in addition to FIG. FIG. 4 is an equivalent circuit diagram of various elements, wirings, etc. in a plurality of pixel portions of the liquid crystal device according to this embodiment.

  4, a plurality of pixel portions 700 are each formed with a pixel electrode 9a and a TFT 30 for controlling the switching of the pixel electrode 9a, and data lines to which image signals VS1, VS2,. 6 a is electrically connected to the source of the TFT 30. As will be described later, the TFT 30 has a semiconductor layer made of a polysilicon film.

  Further, the scanning line 11a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 11a in a pulse-sequential manner in this order at a predetermined timing. It is configured. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal VS1, VS2,..., VSn supplied from the data line 6a is obtained by closing the switch of the TFT 30 as a switching element for a certain period. Write at a predetermined timing.

  Image signals VS1, VS2,..., VSn written to the liquid crystal via the pixel electrode 9a are held for a certain period with the counter electrode 21 formed on the counter substrate. The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly depending on the applied voltage level. In the normally white mode, the transmittance for incident light is reduced according to the voltage applied in units of each pixel, and in the normally black mode, the light is incident according to the voltage applied in units of each pixel. The light transmittance is increased, and light having a contrast corresponding to an image signal is emitted from the liquid crystal device as a whole.

  In order to prevent the image signal held here from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode 21 (see FIGS. 1 and 2). The storage capacitor 70 is provided side by side with the scanning line 11a, and includes a capacitor line 300 including a fixed potential side capacitor electrode and a predetermined potential. The storage capacitor 70 improves the charge retention characteristics of each pixel electrode. Note that the potential of the capacitor line 300 may be constantly fixed to one voltage value, or may be fixed while being swung to a plurality of voltage values at a predetermined period.

  Since the pixel portions 700 as described above are arranged in a matrix in the image display region 10a, active matrix driving is possible.

  As shown in FIG. 3 again, the image signals are supplied for each group to the set of six data lines 6a corresponding to each of the image signals VID1 to VID6 that are serially and parallelly developed in six phases. It is configured as follows. Note that the number of phase development of the image signal (that is, the number of series of image signals that are serial-parallel-developed) is not limited to six phases, and may be, for example, a plurality of phases such as nine phases, twelve phases, and twenty-four phases. The developed image signal may be supplied to a set of data lines 6a in which the number corresponding to the number of development is set as one set. Alternatively, the data lines 6a may be supplied line-sequentially without being serial-parallel developed.

  Next, a specific configuration of the pixel portion of the liquid crystal device according to the present embodiment will be described with reference to FIGS. FIG. 5 is a plan view of a plurality of adjacent pixels on the TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed. FIG. 6 is an enlarged plan view showing an enlarged configuration of one of the plurality of pixels shown in FIG. 7 is a cross-sectional view taken along the line AA ′ of FIG. In FIGS. 5 to 7, the scales of the respective layers and members are different from each other in order to make each layer and each member recognizable on the drawing. In FIG. 7, for convenience of explanation, illustration of a portion located above the pixel electrode 9a is omitted.

  5 to 7, the liquid crystal device 1 includes a TFT array substrate 10, a plurality of transparent pixel electrodes 9a in a matrix with respect to the X direction and the Y direction, and a plurality of pixels extending along vertical and horizontal boundaries of the pixel electrodes 9a, respectively. A data line 6a, a plurality of scanning lines 11a, a TFT 30, and a storage capacitor 70 are provided.

  5 and 6, the image display area 10a on the TFT array substrate 10 is composed of a plurality of pixels each provided with a pixel electrode 9a. A gate electrode 3a is disposed so as to face the channel region 1a ′ of the semiconductor layer 1a of the TFT 30. A pixel switching TFT 30 is provided at each of the points where the scanning line 11a and the data line 6a intersect each other.

  The TFT 30 includes a semiconductor layer 1a and a gate electrode 3a. The semiconductor layer 1a is made of polysilicon, for example, and extends along the Y direction in the first region D1 extending along the Y direction, which is an example of the “first direction” according to the present invention. The channel region 1a ′ of the semiconductor layer 1a has a channel length along the Y direction. The gate electrode 3a is made of, for example, conductive polysilicon. In the present embodiment, the thickness of the gate electrode 3a is about 100 nm.

  The scanning line 11a, the data line 6a, the storage capacitor 70, the lower light shielding film 19, the relay layer 93, and the TFT 30 are viewed on the TFT array substrate 10 in plan view, that is, an opening area of each pixel corresponding to the pixel electrode 9a (that is, In each pixel, the pixel is disposed in a non-opening region surrounding a region where light that actually contributes to display is transmitted or reflected. That is, the scanning line 11a, the storage capacitor 70a, the data line 9a, the lower light shielding film 19, and the TFT 30 are arranged not in the opening area of each pixel but in the non-opening area so as not to hinder display.

  In FIG. 7, the TFT 30 includes a channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by an electric field from the gate electrode 3a, and two insulating films 2a and 2b that insulate the gate electrode 3a and the semiconductor layer 1a. And a gate insulating film 2 included.

  5 and 6, the gate electrode 3a includes a second region D2 and a first region D1 extending along the X direction which is an example of the “second direction” of the present invention in the non-opening region. It is formed at a position shifted from the intersection region along the Y direction (that is, in the first region D1).

  The semiconductor layer 1a has a source region composed of a low concentration source region 1b and a high concentration source region 1d, and a drain region composed of a low concentration drain region 1c and a high concentration drain region 1e. The low concentration source region 1b is a “first LDD region” according to the present invention, and the low concentration drain region 1c is an example of a “second LDD region” according to the present invention. The high concentration source region 1d is an example of the “source region” according to the present invention, and the high concentration drain region 1e is an example of the “drain region” according to the present invention. The TFT 30 has an LDD structure in which a low-concentration source region 1b, a low-concentration drain region 1c, a high-concentration source region 1d, and a high-concentration drain region 1e are formed in mirror symmetry on both sides of the channel region 1a ′.

  The low-concentration source region 1b, the low-concentration drain region 1c, the high-concentration source region 1d, and the high-concentration drain region 1e are impurity regions formed by implanting impurities into the semiconductor layer 1a by impurity implantation such as an ion implantation method. According to such an impurity region, when the TFT 30 is not operating, it is possible to reduce the off current flowing in the source region and the drain region, and to suppress the decrease in the on current flowing when the TFT 30 is operating.

  As will be described later, the TFT 30 is disposed so that the low-concentration drain region 1c overlaps the intersecting region where the first region D1 and the second region D2 intersect each other.

  6 and 7, the scanning line 11a is formed on the upper layer side of the TFT 30 via the interlayer insulating film 41a, and extends along the X direction from the main line portion 11ax along the X direction and along the Y direction from the main line portion 11ax. It is comprised from the extending part 11ay which extends. The scanning line 11a is composed of a two-layer film in which conductive polysilicon and tungsten (W) are stacked. The scanning line 11a is electrically connected to the gate electrode 3a in the extending portion 11ay via a contact hole 86 opened in the interlayer insulating film 41a.

  In the present embodiment, the conductive polysilicon layer has a thickness of about 50 nm, and the tungsten layer has a thickness of about 150 nm. The film thickness of the interlayer insulating film 41a is about 50 nm.

  The scanning line 11a may be formed of a conductive polysilicon film, or may be made of a refractory metal such as titanium (Ti), chromium (Cr), tungsten (W), tantalum (Ta), molybdenum (Mo). You may form by the metal single-piece | unit containing at least one of them, an alloy, metal silicide, polysilicide, or these laminated bodies.

  As shown in FIGS. 5 to 7, in the present embodiment, in particular, the scanning line 11 a has the extending portion 11 ay described above, and the low concentration source region 1 b as viewed in plan on the TFT array substrate 10. And is formed so as to overlap the low-concentration drain region 1c. The scanning line 11a is an example of the “first light shielding portion” according to the present invention. More specifically, the scanning line 11a and the TFT 30 have a positional relationship such that the main line portion 11ax and the low-concentration drain region 1c at least partially overlap each other, and the extension portion 11ay and the low-concentration source region 1b overlap each other. Is arranged in. Therefore, the light irradiated to the low concentration source region 1b and the low concentration drain region 1c can be reduced. In other words, of the incident light incident on the image display region 10a from the upper layer side, the light directed toward the low concentration source region 1b and the low concentration drain region 1c overlaps with the low concentration source region 1b and the low concentration drain region 1c. The scanning line 11a is shielded from light. Therefore, it can be suppressed that light leakage current is generated in the lightly doped source region 1b and the lightly doped drain region 1c by irradiating light to the lightly doped source region 1b and the lightly doped drain region 1c. As a result, display defects such as flicker caused by the occurrence of light leakage current can be reduced.

  Further, the scanning line 11a overlaps with the low concentration source region 1b and the low concentration drain region 1c when viewed in plan on the TFT array substrate 10, and is electrically connected to the gate electrode 3a. Sometimes, an electric field can be applied to the low concentration source region 1b and the low concentration drain region 1c. Accordingly, the on-current that flows during the operation of the transistor can be increased.

  In addition, since the scanning lines 11a are arranged in different layers with the gate electrode 3a and the interlayer insulating film 41a interposed therebetween, an increase in off-current that flows when the TFT 30 is not operating can be suppressed. That is, by adjusting the film thickness of the interlayer insulating film 41a disposed between the scanning line 11a and the gate electrode 3a, the on-current flowing during the operation of the TFT 30 is increased while suppressing the off-current during the non-operation. be able to. In other words, the electric current is applied from the scanning line 11a to the low-concentration source region 1b and the low-concentration drain region 1c during operation to increase the on-current of the TFT 30, and during non-operation, the low concentration from the scanning line 11a. When an electric field of a certain value or more is applied to the source region 1b and the low-concentration drain region 1c, an off current is generated in the TFT 30, and an interlayer insulating film 41a is formed between the scanning line 11a and the semiconductor layer 1a. It can reduce or prevent by interposing.

  5 to 7, the storage capacitor 70 is formed on the upper layer side than the scanning line 11a via the interlayer insulating film 41b. The storage capacitor 70 is formed by arranging an upper capacitor electrode 300 a and a lower capacitor electrode 71 so as to face each other with a dielectric film 75 therebetween.

  In the present embodiment, the interlayer insulating film 41b has a thickness of about 400 nm.

  The upper capacitor electrode 300a is a fixed potential side capacitor electrode configured as a part of the capacitor line 300 (see FIG. 4). The upper capacitor electrode 300a (in other words, the capacitor line 300) is a non-transparent metal film provided on the TFT 30 including, for example, a metal or an alloy. The upper capacitor electrode 300a also functions as an upper light shielding film (built-in light shielding film) that shields the TFT 30 from light. The upper capacitor electrode 300a is formed to contain a metal such as Al (aluminum) or Ag (silver). The upper capacitor electrode 300 includes at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum), and Pd (palladium). Further, it may be composed of a simple metal, an alloy, a metal silicide, a polysilicide, or a laminate of these.

  The lower capacitor electrode 71 is a pixel potential side capacitor electrode that is electrically connected to the high-concentration drain region 1 e of the TFT 30 through the contact hole 83. The lower capacitor electrode 71 is made of a semiconductor such as polysilicon. Accordingly, the storage capacitor 70 has a so-called MIS (Metal-Insulator-Semiconductor) structure. The lower capacitor electrode 71 has a function as a light absorption layer or a light shielding film disposed between the upper capacitor electrode 300 as an upper light shielding film and the TFT 30 in addition to a function as a pixel potential side capacitance electrode.

  The dielectric film 75 has a single layer structure or a multilayer structure composed of a silicon oxide film such as an HTO (High Temperature Oxide) film, an LTO (Low Temperature Oxide) film, or a silicon nitride film.

  As shown in FIG. 6, the storage capacitor 70 includes a first portion Py extending along the Y direction from an intersection region where the first region D1 and the second region D2 intersect each other, and an X direction from the intersection region. The extending second portion Px and the intersecting portion Cd where the first portion Py and the second portion Px intersect each other in the intersecting region.

  The first portion Py includes a lower capacitance electrode Y-side extension portion 71y extending along the Y direction in the lower capacitance electrode 71 and an upper capacitance electrode Y-side extension portion 300y extending along the Y direction in the upper capacitance electrode 300a. And a portion of the dielectric film 75 extending between the lower capacitor electrode Y side extending portion 71y and the upper capacitor electrode Y side extending portion 300y. The second portion Px includes a lower capacitor electrode X side extending portion 71x extending along the X direction in the lower capacitor electrode 71 and an upper capacitor electrode X side extending portion 300x extending along the X direction in the upper capacitor electrode 300a. And a portion of the dielectric film 75 extending between the lower capacitive electrode X side extending portion 71x and the upper capacitive electrode X side extending portion 300x.

  As shown in FIGS. 5 and 6, in the present embodiment, the TFT 30 is particularly arranged so that the low-concentration drain region 1 c partially overlaps the intersection Cd. Therefore, compared with the case where the low concentration drain region 1c does not overlap the intersection Cd, the light irradiated to the low concentration drain region 1a can be more reliably reduced by the storage capacitor 70 functioning as the upper light shielding film. More specifically, light incident obliquely on the low-concentration drain region 1c along the X direction is blocked by the second portion Px extending along the X direction. Light incident obliquely on the low-concentration drain region 1c along the Y direction is blocked by the first portion Py extending along the Y direction. Therefore, when the low-concentration drain region 1c overlaps the intersection Cd, it is possible to block most of the light incident obliquely on the low-concentration drain region 1c from the upper layer side. In particular, in the present embodiment, the inventor of the present application speculates that a light leakage current is more likely to occur in the lightly doped drain region 1c than in the lightly doped source region 1d. Therefore, by providing the low-concentration drain region 1c so as to overlap the intersection Cd, the light reaching the low-concentration drain region 1c can be reduced, and the generation of light leakage current can be effectively reduced.

  In FIG. 5, the data line 6 a is formed on the upper layer side of the storage capacitor 70 through the interlayer insulating film 42, and penetrates the interlayer insulating films 41 a, 41 b, 61 and 42 in the high concentration source region 1 d of the TFT 30. The contact holes 81 are opened and electrically connected. The data line 6a and the inside of the contact hole 81 are made of, for example, an Al (aluminum) -containing material such as Al—Si—Cu or Al—Cu, Al alone, or a multilayer film including an Al layer and a TiN layer. The data line 6a also has a function of shielding the TFT 30 from light.

  5 to 7, the lower light shielding film 19 is provided in a lattice shape below the TFT 30 with the base insulating film 12 interposed therebetween. The lower light-shielding film 19 shields the channel region 1a ′ of the TFT 30 and its periphery from the return light that enters the device from the TFT array substrate 10 side. The lower light-shielding film 19 includes, for example, a metal simple substance, an alloy, a metal silicide, a polysilicide, or a laminate of at least one of refractory metals such as Ti, Cr, W, Ta, Mo, and Pd. Etc.

  The base insulating layer 12 is formed on the entire surface of the TFT array substrate 10 in addition to the function of insulating the TFT 30 from the lower light-shielding film 19, so that it remains after polishing the surface of the TFT array substrate 10 or after cleaning. It has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to dirt or the like.

  The pixel electrode 9a is electrically connected to the high-concentration drain region 1e in the semiconductor layer 1a through the upper capacitor electrode 300a, the contact holes 83, 84 and 85, and the relay layer 93. The contact hole 85 is formed by depositing a conductive material constituting the pixel electrode 9a such as ITO on the inner wall of a hole formed so as to penetrate the interlayer insulating layer 43.

  On the TFT 30, an interlayer insulating film 41a is formed in which a contact hole 86 leading to the gate electrode 3a, a contact hole 81 leading to the high concentration source region 1d, and a contact hole 83 leading to the high concentration drain region 1e are opened. . On the scanning line 11a, an interlayer insulating film 41b in which a contact hole 81 and a contact hole 83 are respectively formed is formed. A lower capacitor electrode 71 and an upper capacitor electrode 300a are formed on the interlayer insulating film 41b, and an interlayer insulating film having a contact hole 81 and a contact hole 84 leading to the lower capacitor electrode 71 formed thereon, respectively. 42 is formed. An insulating film 61 is partially interposed between the first interlayer insulating film 41 and the second interlayer insulating film 42. An interlayer insulating film 43 in which contact holes 85 are formed is formed so as to cover the entire surface of the interlayer insulating film 42 and the relay layer 93 from above the data line 6a. The pixel electrode 9 a and an alignment film (not shown) are provided on the upper surface of the interlayer insulating film 43.

  The relay layer 93 is formed in the same layer as the data line 6 a on the interlayer insulating film 42. For the data line 6a and the relay layer 93, a thin film made of a conductive material such as a metal film is formed on the interlayer insulating film 42 using a thin film forming method, and the thin film is partially removed, that is, patterned. Thus, they are formed apart from each other. Accordingly, since the data line 6a and the relay layer 93 can be formed in the same process, the manufacturing process of the liquid crystal device 1 can be simplified.

  As described above, according to the liquid crystal device 1 according to the present embodiment, the low-concentration source region 1b and the low-concentration source region 1b and the low-concentration source region 1b of the pixel switching TFT 30 have the portions overlapping the low-concentration source region 1b and the low-concentration drain region 1c. The generation of light leakage current in the low concentration drain region 1c can be suppressed, and the on-current that flows during the operation of the TFT 30 can be increased. This makes it possible to display a high-quality image with reduced display defects such as flicker. Further, since the low concentration drain region 1c is arranged at the intersection Cd of the storage capacitor 70 functioning as the upper light shielding film, the light reaching the low concentration drain region 1c electrically connected to the pixel electrode 9a is reduced. And generation of light leakage current can be effectively reduced.

  Next, the TFT for the drive circuit of the liquid crystal device according to this embodiment will be described with reference to FIG. FIG. 8 is a cross-sectional view of a TFT for a drive circuit of the liquid crystal device according to this embodiment.

  As described above with reference to FIG. 3, drive circuits such as the data line drive circuit 101, the scan line drive circuit 104, and the sampling circuit 7 are provided in the peripheral area located around the image display area 10 a on the TFT array substrate 10. Is formed. These drive circuits include, for example, TFTs for drive circuits such as switching elements.

  As shown in FIG. 8, the driving circuit TFT 200 is formed on the base insulating film 12 in the peripheral region.

  The driving circuit TFT 200 includes a semiconductor layer 200a, a gate electrode 203a, and a gate insulating film 2 (specifically, two insulating films 2a and 2b).

  The semiconductor layer 200a is made of, for example, polysilicon. The semiconductor layer 200a has a channel region 200a ′, a source region composed of a low concentration source region 200b and a high concentration source region 200d, and a drain region composed of a low concentration drain region 200c and a high concentration drain region 200e. The low concentration source region 200b and the low concentration drain region 200c are examples of the “third LDD region” according to the present invention. The TFT 200 has an LDD structure in which a low-concentration source region 200b, a low-concentration drain region 200c, a high-concentration source region 200d, and a high-concentration drain region 200e are formed in mirror symmetry on both sides of the channel region 200a ′.

  The low-concentration source region 200b, the low-concentration drain region 200c, the high-concentration source region 200d, and the high-concentration drain region 200e are impurity regions obtained by implanting impurities into the semiconductor layer 200a by impurity implantation such as ion implantation. According to such an impurity region, when the TFT 200 is not operating, the off-current flowing through the source region and the drain region can be reduced, and the decrease in the on-current flowing when the TFT 200 is operating can be suppressed.

  The gate electrode 203a is made of the same film as the gate electrode 3a in the pixel switching TFT 30 (that is, a conductive polysilicon film) (see FIG. 7).

  Further, interlayer insulating films 41 a, 41 b, 61 and 42 are disposed so as to cover the gate electrode 203 a, and a source electrode 251 and a drain electrode 252 are disposed on the interlayer insulating film 42.

  The source electrode 251 and the drain electrode 252 are made of the same film as the data line 6a (that is, a metal film such as an aluminum film) (see FIG. 7).

  The source electrode 251 is electrically connected to the high-concentration source region 200 c through a contact hole 281 opened through the interlayer insulating films 42, 61, 41 b and 41 a and the gate insulating film 2.

  The drain electrode 252 is electrically connected to the high-concentration drain region 200e through the interlayer insulating films 42, 61, 41b and 41a and the contact hole 282 opened through the insulating film 2.

  An interlayer insulating film 43 is stacked on the interlayer insulating film 42 including the source electrode 251 and the drain electrode 252.

  As described above, since the TFT 200 for the drive circuit has an LDD structure, it is possible to reduce the off-current that flows in the source region and the drain region when not operating, and to suppress the decrease in the on-current that flows when the TFT 200 operates. .

  Next, a manufacturing method of the liquid crystal device for manufacturing the above-described liquid crystal device according to the present embodiment will be described with reference to FIGS. 9 to 11 in addition to FIGS. FIG. 9 to FIG. 11 are process diagrams sequentially showing the laminated structure of the liquid crystal device according to the first embodiment in each process of the manufacturing process. In FIGS. 9 to 11, the scales of the respective layers and members are different from each other in order to make each layer and each member recognizable on the drawing.

  9 to 11, a process of forming the pixel switching TFT 30 and the scanning line 11a and the driving circuit TFT 200, which are characteristic parts of the liquid crystal device 1, will be mainly described. In the following, the case where the TFT 30 and the TFT 200 are formed as N-channel transistors (that is, NPN transistors) will be described.

  First, in the step shown in FIG. 9A, a TFT array substrate 10 made of, for example, a quartz substrate or a glass substrate is prepared. Here, the annealing treatment is preferably performed in an inert gas atmosphere such as N 2 (nitrogen) and at a high temperature of about 850 to 1300 ° C., more preferably 1000 ° C., and distortion generated in the TFT array substrate 10 in a high-temperature process to be performed later is small. It pre-processes so that it may become. That is, the TFT array substrate 10 may be heat-treated in advance at the same temperature or higher according to the temperature at which the high temperature treatment is performed at the maximum temperature in the manufacturing process.

  Next, in the image display region 10a, a metal alloy film such as a metal such as Ti, Cr, W, Ta, Mo and Pb or a metal silicide is sputtered on the TFT array substrate 10 to a thickness of about 100 to 500 nm. Here, after forming a light-shielding film having a thickness of about 200 nm, the lower light-shielding film 19 is formed by patterning by etching.

  Next, on the entire surface of the TFT array substrate 10 (that is, the image display region 10a and the peripheral region), for example, TEOS (tetraethylorthosilicate) gas, TEB (tetraethylethylsilicate) gas is formed by atmospheric pressure or low pressure CVD. A base insulating film 12 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like using a (boat rate) gas, TMOP (tetra-methyl-oxy-phosphate) gas, or the like. Form. The film thickness of the base insulating film 12 is, for example, about 400 to 1200 nm. Here, it is about 1100 nm.

  Next, the surface of the base insulating film 12 is globally polished and planarized. As a planarization method by polishing, for example, a CMP (Chemical Mechanical Polishing) method can be used. Thereby, the film thickness of the base insulating film 12 is set to about 450 nm.

  Next, a polysilicon film is formed on the base insulating layer 12 by a low pressure CVD method or the like. Next, the polysilicon film is subjected to, for example, a photolithography method and an etching process to form semiconductor layers 1a and 200a having predetermined patterns in the image display region 10a and the peripheral region, respectively. Further, the gate insulating film 2 is formed by thermal oxidation or the like, and thereafter, the semiconductor layers 1a and 200a are doped with P-type impurity ions such as boron (B) ions. The P-type impurity ion is an example of the “first conductivity type impurity” according to the present invention.

  Next, in the step shown in FIG. 9B, a polysilicon film is deposited to a thickness of about 100 to 500 nm by a low pressure CVD method or the like, and phosphorus (P) is further thermally diffused to make the polysilicon film conductive. Turn into. Thereafter, gate electrodes 3a and 203a having a predetermined pattern are formed by, for example, performing a photolithography method and an etching process on the conductive polysilicon film. At this time, the gate electrode 3a is formed so as to overlap with the region to be the channel region 1a ′ of the semiconductor layer 1a, and the gate electrode 203a is formed so as to overlap with the region of the semiconductor layer 200a that is to become the channel region 200a ′. . Here, the film thickness of the gate electrodes 3a and 203a is about 100 nm.

  Next, the semiconductor layers 1a and 200a are doped with N-type impurity ions such as phosphorus (P) ions at a low concentration. The N-type impurity ion is an example of the “second conductivity type impurity” according to the present invention. At this time, the gate electrode 3a serves as a mask in the semiconductor layer 1a, while the gate electrode 200a serves as a mask in the semiconductor layer 200a. Thus, the channel region 1a ′, the low concentration source region 1b, and the low concentration drain region 1c of the semiconductor layer 1a are formed in the image display region 10a. On the other hand, in the peripheral region, the channel region 200a ′, the low concentration source region 200b, and the low concentration drain region 200c of the semiconductor layer 200a are formed.

  Next, in the step shown in FIG. 10A, after a resist film 501 is formed in a predetermined pattern on each of the semiconductor layers 1a and 200a, N-type impurity ions are doped at a high concentration. More specifically, the image display region 10a has a shape that overlaps with the gate electrode 3a and is wider than the gate electrode 3a, and in the peripheral region, the image display region 10a overlaps with the gate electrode 203a and is wider than the gate electrode 203a. The resist film 501 is formed so as to have a wide shape. Thereafter, the semiconductor layers 1a and 200a are doped with N-type impurity ions at a high concentration using the resist film 501 as a mask. Thereby, the low concentration source region 1b, the low concentration drain region 1c, the high concentration source region 1d and the high concentration drain region 1e are formed in the semiconductor layer 1a, and the low concentration source region 200b and the low concentration drain region 200c are formed in the semiconductor layer 200a. Then, a high concentration source region 200d and a high concentration drain region 200e are formed. That is, TFTs 30 and 200 each having an LDD structure are formed.

  Next, in the process shown in FIG. 10B, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film or an oxide film is formed on the entire surface of the TFT array substrate 10 by, for example, atmospheric pressure or low pressure CVD. An interlayer insulating film 41a made of a silicon film or the like is formed. The film thickness of the interlayer insulating film 41a is, for example, about 40 nm to 100 nm. Here, the film thickness of the interlayer insulating film 41a is about 50 nm.

  Next, in the image display region 10a, a contact hole 86 for electrically connecting the scanning line 11a (see FIG. 7) and the gate electrode 3a is formed by an interlayer insulating film by, for example, a dry etching method, a wet etching method, or a combination thereof. 41a is opened.

  Next, in the step shown in FIG. 11, after depositing a polysilicon film to a thickness of about 100 to 500 nm by a low pressure CVD method or the like and further thermally diffusing phosphorus (P) to make this polysilicon film conductive. Then, the scanning line 11a having a predetermined pattern is formed by photolithography and etching. Here, the film thickness of the scanning line 11a is about 50 nm.

  At this time, particularly in the present embodiment, the scanning line 11a is formed in a pattern that covers the lightly doped source region 1b and the lightly doped drain region 1c. That is, the scanning line 11a is formed so as to have the main line portion 11ax and the extending portion 11ay described above with reference to FIGS. Therefore, the scanning line 11a can function as a light-shielding film for light traveling from the upper layer side toward the lightly doped source region 1b and the lightly doped drain region 1c, and light is irradiated to the lightly doped source region 1b and the lightly doped drain region 1c. As a result, it is possible to suppress the occurrence of light leakage current in the TFT 30.

  Next, an interlayer insulating film 41b is formed on the entire surface of the TFT array substrate 10 in the same manner as the interlayer insulating film 41a. The thickness of the interlayer insulating film 41b is, for example, about 200 nm to 600 nm. Here, the film thickness of the interlayer insulating film 41b is about 400 nm.

  Thereafter, in the image display region 10a, a contact hole 83 (see FIG. 7) for electrically connecting the lower capacitor electrode 71 (see FIG. 7) and the high concentration drain region 1e of the TFT 30 is formed in the same manner as the contact hole 86. Then, the interlayer insulating films 41b and 41a and the gate insulating film 2 are penetrated. Subsequently, the interlayer insulating film 61, the dielectric film 75, and the capacitor line 300 are laminated in a predetermined pattern to form the storage capacitor 70 (see FIG. 7). Subsequently, an interlayer insulating film 42 (see FIG. 7) is formed on the entire surface of the TFT array substrate 10 in the same manner as the interlayer insulating film 41a. Subsequently, in the image display region 10a, a contact hole 81 (see FIG. 7) for electrically connecting the data line 6a (see FIG. 7) and the high concentration source region 1d of the TFT 30 is formed in the same manner as the contact hole 86. Then, the interlayer insulating films 42, 61, 41b, 41a and the gate insulating film 2 are penetrated. Further, a contact hole 84 for electrically connecting the relay layer 93 (see FIG. 7) and the lower capacitor electrode 71 is opened through the interlayer insulating films 42 and 61 in the same manner as the contact hole 83. On the other hand, in the peripheral region, a contact hole 281 (see FIG. 8) and a drain electrode (see FIG. 8) for electrically connecting the source electrode 251 (see FIG. 8) and the high concentration source region 200d of the TFT 200 to the TFT 200 Similar to the contact hole 86, contact holes 282 (see FIG. 8) for electrically connecting the high concentration drain region 200e penetrate the interlayer insulating films 42, 61, 41b, 41a and the gate insulating film 2, respectively. Open the hole.

  Thereafter, a low resistance metal such as aluminum (Al) or a metal film such as metal silicide is deposited on the interlayer insulating film 42 by sputtering or the like to a thickness of about 100 to 700 nm, preferably about 350 nm. Subsequently, the metal film is patterned by, for example, a photolithography process and an etching process, and the data line 6a and the relay wiring 93 (see FIG. 7) in the image display area 10a, and the source electrode 251 and the drain electrode 252 (FIG. 8) in the peripheral area. Each).

  Subsequently, the interlayer insulating film 43 (FIG. 7) is formed on the entire surface of the TFT array substrate, that is, on the interlayer insulating film 42 including the data line 6a, the relay wiring 93, the source electrode 251 and the drain electrode 252, similarly to the interlayer insulating film 41a. And FIG. 8). The film thickness of the interlayer insulating film 43 is preferably about 500 to 1500 nm, and more preferably 800 nm.

  Subsequently, in the image display region 10 a, a contact hole 85 (see FIG. 7) for electrically connecting the pixel electrode 9 a and the relay layer 93 is opened in the interlayer insulating film 43 in the same manner as the contact hole 86.

  Subsequently, in the image display region 10a, a transparent conductive thin film such as an ITO film is deposited on the interlayer insulating film 43 by sputtering or the like to a thickness of about 50 to 200 nm, and then the pixel electrode 9a is etched or the like. (See FIG. 7).

  Subsequently, a polyimide alignment film coating solution is applied onto the pixel electrode 9a, and then an alignment film (not shown) is formed by performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle.

  On the other hand, for the counter substrate 20 shown in FIG. 2, a glass substrate or the like is first prepared as the counter substrate 20. On the counter substrate 20, for example, metal chromium is sputtered, and then a matrix-shaped light shielding film 23 is formed through a photolithography process and an etching process. The light shielding film 23 may be formed of a metal material such as Cr, Ni, or Al, or a material such as resin black in which carbon or Ti is dispersed in a photoresist.

  Finally, the TFT array substrate 10 on which the respective layers are formed as described above and the counter substrate 20 are bonded together with a sealing material (see FIGS. 1 and 2) so that the pixel electrode 9a and the counter electrode 23 face each other. By vacuum suction or the like, for example, liquid crystal formed by mixing a plurality of types of nematic liquid crystals is sucked into the space between both substrates to form the liquid crystal layer 50 having a predetermined thickness.

  When the liquid crystal device is manufactured as described above, the scanning line 11a is electrically connected to the gate electrode 3a of the pixel switching TFT 30, and is formed so as to cover the low concentration source region 1d and the low concentration drain region 1c. Therefore, it is possible to suppress the occurrence of light leakage current in the low concentration source region 1d and the low concentration drain region 1c, and to increase the on-current that flows during the operation of the TFT 30. Further, when the interlayer insulating film 41a is formed on the TFT 30, the scanning line 11a and the semiconductor layer 1a (more specifically, the low concentration source region 1b and the low concentration are adjusted by adjusting the film thickness of the interlayer insulating film 41a. The interlayer distance to the drain region 1c) can be adjusted. Therefore, for example, by increasing the film thickness of the interlayer insulating film 41a, it is possible to suppress off-state current during non-operation.

  Next, a modified example of the above-described liquid crystal device manufacturing method will be described with reference to FIGS. FIG. 12 is a process diagram having the same concept as in FIG. 10 in the first modification. FIG. 13 is a process diagram having the same concept as in FIG. 12A in the second modified example.

  In the manufacturing method of the liquid crystal device according to the first embodiment described above, the step shown as the first modification in FIG. 12 may be performed after the step shown in FIG. 9B is performed.

  That is, in the step shown in FIG. 12A, after performing the step shown in FIG. 9B, NSG, PSG, BSG, An interlayer insulating film 41a made of a silicate glass film such as BPSG, a silicon nitride film or a silicon oxide film is formed.

  Next, in the image display region 10a, a contact hole 86 for electrically connecting the scanning line 11a (see FIG. 7) and the gate electrode 3a is formed by an interlayer insulating film by, for example, a dry etching method, a wet etching method, or a combination thereof. 41a is opened.

Next, in the process shown in FIG. 12B, a polysilicon film is deposited to a thickness of about 100 to 500 nm by a low pressure CVD method or the like, and phosphorus (P) is further thermally diffused to make the polysilicon film conductive. Then, the scanning line 11a having a predetermined pattern is formed by a photolithography method and an etching process. At this time, the scanning line 11a is formed in a pattern overlapping the low concentration source region 1b and the low concentration drain region 1c. Next, a resist film 502 is formed in a predetermined pattern on the semiconductor layer 200a. More specifically, the resist film 502 is formed in the peripheral region so as to overlap with the gate electrode 203a and have a shape wider than the gate electrode 203a.
Thereafter, the semiconductor layers 1a and 200a are doped with N-type impurity ions at a high concentration using the scanning line 11a and the resist film 502 as a mask. Thereby, the low concentration source region 1b, the low concentration drain region 1c, the high concentration source region 1d, and the high concentration drain region 1e are formed in the semiconductor layer 1a, and the low concentration source region 200b and the low concentration drain region 200c are formed in the semiconductor layer 200a. Then, a high concentration source region 200d and a high concentration drain region 200e are formed. That is, TFTs 30 and 200 each having an LDD structure are formed. Next, after removing the resist film 502, a process substantially similar to the process after the process described above with reference to FIG. 11 is performed.

  According to the method of manufacturing the liquid crystal device according to the first modification, as described with reference to FIG. 12B, the N-type impurity ions are doped at a high concentration using the scanning line 11a as a mask. The low concentration source region 1b and the low concentration drain region 1c can be formed in a region overlapping with the scanning line 11a. In other words, the scanning line 11a can be formed so as to surely overlap the low concentration source region 1b and the low concentration drain region 1c. Therefore, it is possible to suppress the occurrence of light leakage current in the low concentration source region 1b and the low concentration drain region 1c and to increase the on-current that flows during the operation of the TFT 30.

  Alternatively, in the method of manufacturing the liquid crystal device according to the first modification described above, a process shown as a second modification in FIG. 13 may be performed instead of the process shown in FIG.

  That is, in the step shown in FIG. 13, after performing the step shown in FIG. 12A, a polysilicon film is deposited to a thickness of about 100 to 500 nm by a low pressure CVD method or the like, and phosphorus (P) is further thermally diffused. Then, after making the polysilicon film conductive, the scanning line 11a having a predetermined pattern is formed by photolithography and etching. At this time, particularly in this modification, the scanning line 11a is moved from the boundary between the region to be the high concentration source region 1d and the region to be the low concentration source region 1b to the channel region 1a ′ side and the high concentration drain region 1e. A region where the scanning line 11a is not formed (that is, the offset d1) is provided on each side of the channel region 1a ′ from the boundary between the region to be formed and the region to be the low concentration drain region 1c, and overlaps with the channel region 1a ′ and has a low concentration. The source region 1b and the lightly doped drain region 1c are formed so as to partially overlap.

  Next, after forming a resist film 503 in a predetermined pattern on each of the semiconductor layers 1a and 200a, N-type impurity ions are doped at a high concentration. More specifically, the image display region 10a has a shape that overlaps with the portion of the scanning line 11a covering the gate electrode 3a and is wider than the portion (in other words, the channel region 1a ′ in the semiconductor layer 1a). And the region to be the low-concentration source region 1b and the low-concentration drain region 1c), and the peripheral region has a shape that overlaps with the gate electrode 203a and is wider than the gate electrode 203a (in other words, For example, the resist film 503 is formed so as to cover the channel region 200a ′ and the regions to be the low concentration source region 200b and the low concentration drain region 200c in the semiconductor layer 200a. Thereafter, the semiconductor layers 1a and 200a are doped with N-type impurity ions at a high concentration using the resist film 503 as a mask. Thereby, the low concentration source region 1b, the low concentration drain region 1c, the high concentration source region 1d and the high concentration drain region 1e are formed in the semiconductor layer 1a, and the low concentration source region 200b and the low concentration drain region 200c are formed in the semiconductor layer 200a. Then, a high concentration source region 200d and a high concentration drain region 200e are formed. That is, TFTs 30 and 200 each having an LDD structure are formed. Next, after removing the resist film 503, a process substantially similar to the process after the process described above with reference to FIG. 11 is performed.

According to the method of manufacturing the liquid crystal device according to the second modification, near the boundary between the high concentration source region 1d and the low concentration source region 1b and the boundary between the high concentration drain region 1e and the low concentration drain region 1c, Since the scanning line 11a is not formed, the electric field from the scanning line 11a is applied to the boundary between the high concentration source region 1d and the low concentration source region 1b and the boundary between the high concentration drain region 1e and the low concentration drain region 1c. This can be reduced or prevented. Therefore, it can be suppressed that the breakdown voltage of the TFT 30 is lowered and the off-current is increased.
<Second Embodiment>
A liquid crystal device according to a second embodiment and a manufacturing method thereof will be described with reference to FIGS.

  First, the configuration of the liquid crystal device according to the second embodiment will be described with reference to FIG. FIG. 14 is a sectional view having the same concept as in FIG. 7 in the second embodiment. In FIG. 14, the same reference numerals are given to the same components as the components according to the first embodiment shown in FIGS. 1 to 11, and description thereof will be omitted as appropriate.

  In FIG. 14, the liquid crystal device according to the second embodiment differs from the liquid crystal device according to the first embodiment described above in that the liquid crystal device according to the second embodiment includes a TFT 32 instead of the TFT 30 of the liquid crystal device according to the first embodiment described above. In terms of points, the liquid crystal device according to the first embodiment is configured in substantially the same manner.

  In FIG. 14, the liquid crystal device according to the second embodiment includes a TFT 32 for pixel switching. The TFT 32 includes a semiconductor layer 1a, a gate electrode 32a, and a gate insulating film 2 (specifically, two insulating films 2a and 2b).

  The semiconductor layer 1a is made of, for example, polysilicon. In the semiconductor layer 1a ′, a channel region 1a ′ in which a channel is formed by an electric field from the gate electrode 32a is formed. A low concentration source region 1b, a low concentration drain region 1c, a high concentration drain region 1c are formed on both sides of the channel region 1a ′. The concentration source region 1d and the high concentration drain region 1e are formed in mirror symmetry.

  The gate electrode 32a is formed as a part of the scanning line 11a made of, for example, conductive polysilicon.

  Particularly in the present embodiment, the gate electrode 32a constituting the TFT 32 is formed so as to overlap the channel region 1a ′ of the semiconductor layer 1a and at least partially overlap the lightly doped source region 1b and the lightly doped drain region 1c. That is, the TFT 32 has a so-called GOLD structure. Therefore, the light irradiated to the low concentration source region 1b and the low concentration drain region 1c can be reduced. In other words, light traveling toward the low concentration source region 1b and the low concentration drain region 1c is shielded by the gate electrode 32a formed so as to at least partially overlap the low concentration source region 1b and the low concentration drain region 1c. Therefore, it can be suppressed that light leakage current is generated in the lightly doped source region 1b and the lightly doped drain region 1c by irradiating light to the lightly doped source region 1b and the lightly doped drain region 1c. As a result, display defects such as flicker caused by the occurrence of light leakage current can be reduced.

  In this embodiment, the gate electrode 32a is configured as a part of the scanning line 11a. However, the gate electrode 32a may be configured from a conductive film provided in a layer different from the scanning line 11a. Further, from the viewpoint of improving the light blocking property of blocking light reaching the low concentration source region 1b and the low concentration drain region 1c, it is preferable that the gate electrode 32a overlaps both the low concentration source region 1b and the low concentration drain region 1c. .

  Further, the gate electrode 32a overlaps the channel region 1a ′ of the semiconductor layer 1a and at least partially overlaps the lightly doped source region 1b and the lightly doped drain region 1c, so that the TFT 32 operates in addition to the channel region 1a ′. An electric field can be applied at least partially to the low concentration source region 1b and the low concentration drain region 1c. Therefore, the on-current that flows during the operation of the TFT 32 can be increased.

  As described above, according to the liquid crystal device according to the second embodiment, in addition to the channel region 1a ′ of the semiconductor layer 1a, the gate electrode 32a at least partially overlaps the lightly doped source region 1b and the lightly doped drain region 1c. In addition, the occurrence of light leakage current in the low concentration source region 1b and the low concentration drain region 1c can be suppressed, and the on-current that flows during the operation of the TFT 32 can be increased. This makes it possible to display a high-quality image with reduced display defects such as flicker.

  Next, a method for manufacturing a liquid crystal device for manufacturing the liquid crystal device according to the second embodiment will be described with reference to FIGS. FIG. 15 to FIG. 17 are process diagrams sequentially showing the laminated structure of the liquid crystal device according to the second embodiment in each process of the manufacturing process. In FIGS. 15 to 17, the scales of the layers and members are different from each other in order to make the layers and members recognizable on the drawings. 15 to 17, the same reference numerals are given to the same components as those according to the first embodiment illustrated in FIGS. 9 to 11, and description thereof will be omitted as appropriate.

  15 to 17, the process of forming the pixel switching TFT 32 and the driving circuit TFT 200 which are characteristic parts of the liquid crystal device according to the second embodiment will be mainly described.

  First, in the step shown in FIG. 15A, a TFT array substrate 10 made of, for example, a quartz substrate or a glass substrate is prepared. In the image display region 10a, a lower side containing a metal such as Ti on the TFT array substrate 10 is prepared. A light shielding film 19 is formed. Subsequently, the base insulating film 12 is formed on the entire surface of the TFT array substrate 10 (that is, the image display region 10a and the peripheral region), and the surface of the base insulating film 12 is planarized by, for example, CMP.

  Next, the semiconductor layers 1a and 200a having a predetermined pattern in the image display region 10a and the peripheral region are formed on the base insulating layer 12 from a polysilicon film, respectively. Further, the gate insulating film 2 is formed by thermal oxidation or the like, and thereafter, the semiconductor layers 1a and 200a are doped with P-type impurity ions such as boron (B) ions.

  Next, in the step shown in FIG. 15B, the image display region 10a overlaps with the region to be the channel region 1a ′ of the semiconductor layer 1a, and the peripheral region covers the entire semiconductor layer 200a. Next, a resist film 504 is formed. After that, the semiconductor layers 1a and 200a are doped with N-type impurity ions such as phosphorus (P) ions at a low concentration using the resist film 504 as a mask. Thus, the channel region 1a ′, the low concentration source region 1b, and the low concentration drain region 1c of the semiconductor layer 1a are formed in the image display region 10a. At this time, in the peripheral region, since the semiconductor layer 200a is covered with the resist film 504, the N-type impurity is not doped. Thereafter, the resist film 504 is removed.

  Next, in the step shown in FIG. 16A, gate electrodes 32a and 203a having a predetermined pattern are formed on the semiconductor layers 1a and 200a, respectively, from conductive polysilicon. At this time, the gate electrode 3a is overlapped with the region to be the channel region 1a ′ of the semiconductor layer 1a and has a shape wider than the region, and the gate electrode 203a is formed with the channel region 200a of the semiconductor layer 200a. It forms so that it may overlap with the area | region which should become '.

  Next, in the step shown in FIG. 16B, a resist film 505 is formed so as to cover the entire semiconductor layer 1a in the image display region 10a. Thereafter, the semiconductor layers 1a and 200a are doped with N-type impurity ions at a low concentration using the resist film 505 and the gate electrode 203a as a mask. Thus, the channel region 200a ′, the low concentration source region 200b, and the low concentration drain region 200c of the semiconductor layer 200a are formed in the peripheral region. At this time, in the image display region 10a, the semiconductor layer 1a is covered with the resist film 505, so that N-type impurities are not doped. Thereafter, the resist film 505 is removed.

  Next, in the step shown in FIG. 17A, a resist film 506 is formed in the peripheral region so as to overlap with the gate electrode 203a and to have a shape wider than the gate electrode 203a. Thereafter, the semiconductor layers 1a and 200a are doped with N-type impurity ions at a high concentration using the gate electrode 32a and the resist film 506 as a mask. Thereby, the low concentration source region 1b, the low concentration drain region 1c, the high concentration source region 1d and the high concentration drain region 1e are formed in the semiconductor layer 1a, and the low concentration source region 200b and the low concentration drain region 200c are formed in the semiconductor layer 200a. Then, a high concentration source region 200d and a high concentration drain region 200e are formed. That is, TFTs 32 and 200 each having an LDD structure are formed. Here, in particular, the gate electrode 32a of the TFT 32 is formed so as to overlap the low concentration source region 1b and the low concentration drain region 1c. That is, the TFT 32 has a so-called GOLD structure. Therefore, it is possible to suppress the occurrence of light leakage current in the low concentration source region 1b and the low concentration drain region 1c, and to increase the on-current that flows during the operation of the TFT 32. Thereafter, the resist film 506 is removed.

  Next, in a step shown in FIG. 17B, an interlayer insulating film 41 is formed on the entire surface of the TFT array substrate 10. Thereafter, the components of the storage capacitor 70, the data line 6a, the relay layer 93, the pixel electrode 9a, and the like (see FIG. 14) are formed in substantially the same manner as in the liquid crystal device manufacturing method according to the first embodiment described above.

  According to the manufacturing method of the liquid crystal device according to the present embodiment described above, the gate electrode 32a is formed so as to overlap the channel region 1a ′, the low concentration source region 1b, and the low concentration drain region 1c of the TFT 32 for pixel switching. Therefore, it is possible to suppress the occurrence of light leakage current in the low concentration source region 1b and the low concentration drain region 1c, and to increase the on-current that flows during the operation of the TFT 32.

  Further, in this embodiment, in particular, the pixel switching TFT 32 and the driving circuit TFT 200 having different structures can be formed in the same process. That is, by the same manufacturing process, the TFT 32 having the GOLD structure can be formed in the image display region 10a and the TFT 30 having the LDD structure can be formed in the peripheral region. Therefore, by forming the pixel switching TFT 32 to be formed in the image display region 10a on which light is incident as a GOLD structure, the peripheral region where light is hardly incident or not at all is improved while improving the light shielding property and reducing the light leakage current. By forming the TFT 200 for a driver circuit to be formed as an LDD structure, off current in the TFT 200 can be suppressed.

  Next, a modification of the method for manufacturing the liquid crystal device according to the second embodiment will be described with reference to FIG. FIG. 18 is a process diagram having the same concept as FIG. 17A in the modification of the second embodiment.

  In the method of manufacturing the liquid crystal device according to the second embodiment described above, after performing the process shown in FIG. 16B, the process shown in FIG. 18 as a modification is performed instead of the process shown in FIG. May be.

That is, in the process shown in FIG. 18, after performing the process shown in FIG. 16B, the image display region 10a has a shape that overlaps the gate electrode 32a and is wider than the gate electrode 32a, and In the peripheral region, a resist film 507 is formed so as to overlap with the gate electrode 203a and have a shape wider than the gate electrode 203a. Thereafter, the semiconductor layers 1a and 200a are doped with N-type impurity ions at a high concentration using the resist film 507 as a mask. Thereby, the low concentration source region 1b, the low concentration drain region 1c, the high concentration source region 1d and the high concentration drain region 1e are formed in the semiconductor layer 1a, and the low concentration source region 200b and the low concentration drain region 200c are formed in the semiconductor layer 200a. Then, a high concentration source region 200d and a high concentration drain region 200e are formed. In particular, in the image display region 10a, the gate electrode 32a is connected to the channel region 1a 'side from the boundary between the high concentration source region 1d and the low concentration source region 1b, and between the high concentration drain region 1e and the low concentration drain region 1c. A region where the gate electrode 32a is not formed on each side of the channel region 1a ′ from the boundary, that is, an offset d2 is provided so as to overlap the channel region 1a ′ and partially overlap the lightly doped source region 1b and the lightly doped drain region 1c. Formed. Therefore, it is possible to reduce or prevent the electric field from the gate electrode 32a from being applied to the boundary between the high concentration source region 1d and the low concentration source region 1b and the boundary between the high concentration drain region 1e and the low concentration drain region 1c. . Therefore, it can be suppressed that the withstand voltage of the TFT 32 decreases and the off-current increases.
<Electronic equipment>
Next, the case where the above-described liquid crystal device which is an electro-optical device is applied to various electronic devices will be described with reference to FIG. FIG. 19 is a plan view showing a configuration example of the projector. Hereinafter, a projector using the liquid crystal device according to the present embodiment as a light valve will be described.

  As shown in FIG. 19, a projector 1100 includes a lamp unit 1102 made of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R and 1110B.

  Since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 19, a mobile personal computer, a mobile phone, a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, and an electronic notebook , Calculators, word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), The present invention can also be applied to an organic EL display, a digital micromirror device (DMD), an electrophoresis apparatus, and the like.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or concept of the invention that can be read from the claims and the entire specification. The manufacturing method and the electronic apparatus provided with the electro-optical device are also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on 1st Embodiment. It is the HH 'sectional view taken on the line of FIG. It is a block diagram which shows the structure of the principal part of the liquid crystal device which concerns on 1st Embodiment. 2 is an equivalent circuit diagram of a pixel portion of the liquid crystal device according to the first embodiment. FIG. 2 is a plan view of a plurality of adjacent pixels of the liquid crystal device according to the first embodiment. FIG. FIG. 6 is an enlarged plan view showing an enlarged configuration of the pixel shown in FIG. 5. It is AA 'sectional drawing of FIG. It is sectional drawing of TFT for the drive circuits of the liquid crystal device which concerns on 1st Embodiment. It is process drawing (1) which shows each process of the manufacturing method of the liquid crystal device which concerns on 1st Embodiment. It is process drawing (2) which shows each process of the manufacturing method of the liquid crystal device which concerns on 1st Embodiment. It is process drawing (3) which shows each process of the manufacturing method of the liquid crystal device which concerns on 1st Embodiment. It is process drawing of the same meaning as FIG. 10 in a 1st modification. It is process drawing of the same meaning as FIG. 12 (a) in a 2nd modification. It is sectional drawing with the same meaning as FIG. 7 in 2nd Embodiment. It is process drawing (1) which shows each process of the manufacturing method of the liquid crystal device which concerns on 2nd Embodiment. It is process drawing (2) which shows each process of the manufacturing method of the liquid crystal device which concerns on 2nd Embodiment. It is process drawing (3) which shows each process of the manufacturing method of the liquid crystal device which concerns on 2nd Embodiment. FIG. 18 is a process diagram having the same concept as in FIG. 17A in a modified example of the second embodiment. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

Explanation of symbols

  2, 2a, 2b ... gate insulating film, 3a ... gate electrode, 6a ... data line, 7 ... sampling circuit, 9a ... pixel electrode, 10 ... TFT array substrate, 10a ... image display area, 11a ... scanning line, 12 ... ground Insulating film, 20 ... counter substrate, 21 ... counter electrode, 23 ... light shielding film, 30 ... TFT for pixel switching, 41a, 41b, 42, 43, 61 ... interlayer insulating film, 50 ... liquid crystal layer, 52 ... sealing material, 53 ... Frame light shielding film, 70 ... Storage capacitor, 71 ... Lower capacitor electrode, 75 ... Dielectric film, 81, 83, 84, 85, 86 ... Contact hole, 93 ... Relay layer, 101 ... Data line driving circuit, 102 ... External circuit connection terminal 104... Scanning line driving circuit 106... Vertical conduction terminal 107. Vertical conduction material 200. TFT for driving circuit 300 300 capacitance line 300 a upper capacitor electrode

Claims (13)

On the board
A plurality of data lines and a plurality of scanning lines intersecting each other;
A pixel electrode defined in correspondence with the intersection of the plurality of data lines and the plurality of scanning lines and formed on each of the plurality of pixels constituting the display region on the substrate;
A first LDD region electrically connected to the pixel electrode and formed between the channel region and the source region; and a second LDD region formed between the channel region and the drain region; A transistor having a semiconductor layer having a gate electrode overlapping with the channel region;
The gate electrode and the insulating layer are disposed in different layers, and are formed so as to at least partially overlap the first and second LDD regions when viewed in plan on the substrate. An electro-optical device comprising: a first light shielding portion electrically connected to the gate electrode.   The electro-optical device according to claim 1, wherein the first light shielding portion is formed as a part of the scanning line. The transistor is formed in a layer different from the transistor, and includes a first portion extending along a first direction in the display region, a second portion extending along a second direction intersecting the first direction, and the plurality of the plurality of the plurality of transistors. A first region extending along the first direction among the non-opening regions separating the opening regions of the pixels from each other, and a second region extending along the second direction among the non-opening regions intersect each other. A second light-shielding portion having an intersection where the first portion and the second portion intersect each other in the region;
The pixel electrode is electrically connected to the drain region; the data line is electrically connected to the source region;
The electro-optical device according to claim 1, wherein at least a part of the second LDD region overlaps the intersecting portion. On the board
A plurality of data lines and a plurality of scanning lines intersecting each other;
A pixel electrode defined in correspondence with the intersection of the plurality of data lines and the plurality of scanning lines and formed on each of the plurality of pixels constituting the display region on the substrate;
A first LDD region electrically connected to the pixel electrode and formed between the first channel region and the source region, and a second LDD region formed between the first channel region and the drain region. A first semiconductor layer having a first LDD region, and a first transistor having a first gate electrode that overlaps the first channel region and at least partially overlaps the first and second LDD regions. An electro-optical device.   The electro-optical device according to claim 4, wherein the first gate electrode is formed as a part of the scanning line. A first portion formed in a different layer from the first transistor and extending along a first direction in the display region; and a second portion extending along a second direction intersecting the first direction; A first region extending along the first direction among non-opening regions separating the opening regions of the plurality of pixels from each other and a second region extending along the second direction among the non-opening regions are mutually connected. A light-shielding portion having a crossing portion where the first portion and the second portion cross each other in an intersecting region,
The pixel electrode is electrically connected to the drain region; the data line is electrically connected to the source region;
The electro-optical device according to claim 4, wherein at least a part of the second LDD region overlaps the intersecting portion.   A second semiconductor layer, which is disposed in a peripheral region located around the display region, and has a third LDD region provided on each side of the second channel region for driving the pixel electrode; And a driving circuit including a second transistor having a second gate electrode that overlaps with the second channel region and does not overlap with the third LDD region. The electro-optical device according to 1.   An electronic apparatus comprising the electro-optical device according to claim 1. A first doping step of doping a semiconductor layer formed in a display region on a substrate with a first conductivity type impurity;
After the first doping step, a gate electrode is formed in a region to be a channel region of the semiconductor layer, and an impurity having a second conductivity type different from the first conductivity type is applied to the semiconductor layer using the gate electrode as a mask. A second doping step of forming the channel region by doping and forming the impurity region of the second conductivity type on both sides of the channel region;
A first insulating film laminating step of laminating a first insulating film on the semiconductor layer and the gate electrode after the second doping step;
On the first insulating film, the channel region, a region to be the first LDD region between the channel region and the source region, and a region to be the second LDD region between the channel region and the drain region are provided. A light shielding part forming step of forming a light shielding part from a light shielding conductive material so as to cover and electrically connect to the gate electrode;
A third doping step of forming the source region, the drain region, and the first and second LDD regions by doping the semiconductor layer with the impurity of the second conductivity type using the light shielding portion as a mask;
A wiring forming step of forming a plurality of data lines and a plurality of scanning lines intersecting each other on the substrate;
And a pixel electrode forming step of forming a pixel electrode in each of the plurality of pixels that are defined corresponding to the intersection of the plurality of data lines and the plurality of scanning lines and that constitute the display region. Manufacturing method of optical device.   The method of manufacturing an electro-optical device according to claim 9, wherein the light shielding part forming step forms the light shielding part as a part of the scanning line. A first doping step of doping a semiconductor layer formed in a display region on a substrate with a first conductivity type impurity;
After the first doping step, a resist film is formed in a region to be a channel region of the semiconductor layer, and an impurity having a second conductivity type different from the first conductivity type is applied to the semiconductor layer using the resist film as a mask. A second doping step of forming the channel region by doping and forming the impurity region of the second conductivity type on both sides of the channel region;
After the second doping step, in the semiconductor layer, the channel region, a region to be a first LDD region between the channel region and the source region, and a second LDD region between the channel region and the drain region Forming a gate electrode from a light-shielding conductive material so as to overlap a region to be formed;
A third doping step of forming the source region, the drain region, and the first and second LDD regions by doping the semiconductor layer with the second conductivity type impurity using the gate electrode as a mask; ,
A wiring forming step of forming a plurality of data lines and a plurality of scanning lines intersecting each other on the substrate;
And a pixel electrode forming step of forming a pixel electrode in each of the plurality of pixels that are defined corresponding to the intersection of the plurality of data lines and the plurality of scanning lines and that constitute the display region. Manufacturing method of optical device. A first doping step of doping a semiconductor layer formed in a display region on a substrate with a first conductivity type impurity;
After the first doping step, a first resist film is formed in a region to be a channel region of the semiconductor layer, and the first resist film is used as a mask to form a first resist film different from the first conductivity type. A second doping step of forming the channel region and forming the second conductivity type impurity region on both sides of the channel region by doping with two conductivity type impurities;
After the second doping step, in the semiconductor layer, the channel region, a region to be a first LDD region between the channel region and the source region, and a second LDD region between the channel region and the drain region Forming a gate electrode from a light-shielding conductive material so as to partially overlap a region to be formed;
A resist film that forms a second resist film on the semiconductor layer and the light shielding film so as to cover the channel region, the region to be the first LDD region, and the region to be the second LDD region Forming process;
Using the second resist film as a mask, the semiconductor layer is doped with the second conductivity type impurity to form the source region, the drain region, and the first and second LDD regions. A dope process;
A wiring forming step of forming a plurality of data lines and a plurality of scanning lines intersecting each other on the substrate;
And a pixel electrode forming step of forming a pixel electrode in each of the plurality of pixels that are defined corresponding to the intersection of the plurality of data lines and the plurality of scanning lines and that constitute the display region. Manufacturing method of optical device. A first doping step of doping a first semiconductor layer formed in a display region on a substrate and a second semiconductor layer formed in a peripheral region located around the display region with an impurity of a first conductivity type;
After the first doping step, a first resist film is formed on a region to be the first channel region of the first semiconductor layer and the entire surface of the second semiconductor layer, and the first resist film is used as a mask. The first channel region is formed by doping the first and second semiconductor layers with an impurity of a second conductivity type different from the first conductivity type, and the second conductivity is formed on both sides of the first channel region. A second doping step for forming a first impurity region of the mold;
After the second doping step, the first semiconductor layer of the first semiconductor layer, the region to be the first LDD region between the first channel region and the first source region, and the first channel Forming a first gate electrode so as to overlap a region to be a second LDD region between the region and the first drain region, and forming a second channel region in the second semiconductor layer in the region to be the second channel region; A gate electrode forming step of forming two gate electrodes;
A second resist film is formed so as to cover the first gate electrode and the first semiconductor layer, and the first and second semiconductor layers are masked by using the second resist film and the second gate electrode as a mask. Doping a second conductivity type impurity different from the one conductivity type forms the second channel region and forms the second conductivity type second impurity region on both sides of the second channel region. A third doping step;
The second resist film is removed, and a third resist is formed so as to overlap with the second channel region of the second semiconductor layer and the regions to be the third LDD regions on both sides of the second channel region. Forming a film, and doping the first and second semiconductor layers with the second conductivity type impurity using the first gate electrode and the third resist film as a mask, thereby forming the first semiconductor layer in the first semiconductor layer; The first source region, the first drain region, and the first and second LDD regions are formed, and the second source region, the second drain region, and the third LDD region in the second semiconductor layer are formed. A third doping step to form
A wiring forming step of forming a plurality of data lines and a plurality of scanning lines intersecting each other on the substrate;
And a pixel electrode forming step of forming a pixel electrode in each of the plurality of pixels that are defined corresponding to the intersection of the plurality of data lines and the plurality of scanning lines and that constitute the display region. Manufacturing method of optical device.

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