JP2008021290A - Storage device, storage controller, and information processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide technology for realizing reduction of power consumption and the time required when executing processing of recording data transmitted from an information processing apparatus to a storage device such as an HDD. <P>SOLUTION: In the processing of recording data transmitted from the information processing apparatus (host) onto a disk of the HDD as a storage drive (SD), a system is configured such that its DMA transfer is pipelined with a write buffer (WB) provided in a memory of the SD as a border, and a command for this operation is added to the SD. An HDC (controller) interprets a command sent from a CPU in the information processing apparatus, attempts DMA read from a main memory to store data in the WB, and writes the predetermined amount of stored data into the disk of a drive part all at once. Immediately after the writing, the HDC writes file management information into an FAT area of the disk, and changes an operation state from an active mode into a standby mode spontaneously to save electricity. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technology of a storage drive or a storage device (storage device) such as a hard disk drive (HDD) capable of writing and reading (recording and reproducing) information data signals with respect to a recording medium. In particular, the present invention relates to a storage device mounted on or connected to an information processing device, an information processing device that reads / writes information data from / to the storage device, data read / write control, power saving (power saving) control, and the like.

  For example, HDDs and optical disk drives (CD drives and DVD drives) exist as storage apparatuses connected to or mounted on the information processing apparatus, and data recording and reproduction operations can be performed on recording media (disks). Yes. In these drives (drive devices), the disk is rotated by a motor or the like, the head is aligned with a track or the like on the disk, and data or signals are read or read / written. The above drive can read or write data only after the motor is started in advance to read or write the actual data, the rotation of the disk is stable, and the head is aligned on the track. . In addition, the drive continues to rotate the disk and possibly align the head even after reading or writing. In other words, the drive requires work before and after reading or writing. This work is associated with the product of power and time.

  Actually, as a conventional technique, for example, in a hard disk device described in JP-A-6-236241 (Patent Document 1), data in a recording medium (hard disk) is stored in a cache memory including a volatile buffer RAM every time it is read. The host CPU writes and holds data that is frequently accessed and that is to be held in the cache memory in a cache memory that is composed of a nonvolatile flash memory. In this configuration, a file with a high access frequency is reliably held in the cache memory for access from the host as compared to the case where the cache memory is configured by the buffer RAM alone, and therefore depends on the capacity of the buffer RAM. The transfer performance could be improved by increasing the cache hit rate. In addition, with this configuration, the opportunity to stop the motor of the hard disk device during reading has increased, contributing to power saving. The above is an effective configuration for reading data from the hard disk.

  On the other hand, considering the case of writing data to the HDD, there are the following conventional techniques. In a configuration in which an HDD is installed in an information processing apparatus, for example, there may be a case where operations (user data recording processing) such as recording of music being recorded, recording of moving images, and downloading from a network are performed. In this case, generally, any transfer such as the bit rate of the broadcast or moving image data, the transfer rate at the time of download, etc. is higher than the media transfer rate (R1: HDD side transfer rate) which is the read / write speed of the HDD recording medium (disk). The speed (R2: information processing apparatus side transfer speed) is often lower (R1> R2). In other words, in the recording process of the same user data amount, the data transfer time (T2) on the information processing apparatus side is often longer than the media transfer time (T1) on the HDD side (T1 <T2).

  Therefore, in the data writing process from the information processing device to the HDD disk, the transfer time (T2) on the information processing device side, which is longer than the media transfer time (T1) on the HDD side, is required from the start to the end of writing. We decided time (T3). Therefore, the conventional required time (T3) becomes longer, and the amount of power consumed by the HDD increases in proportion to the required time (T3). Therefore, for example, by temporarily storing data to be written using the memory of the information processing apparatus as a buffer and writing the data to the HDD when a certain amount is stored, the overall transfer speed is improved and the time required for writing (T3 ) Was shortened.

As another conventional technique, there is a HDD in which a part of a memory is used as a write buffer when a wait such as a head seek occurs.
JP-A-6-236241

  In the method using the memory of the information processing apparatus as a buffer, the CPU of the information processing apparatus manages the file at the time of writing the file to the HDD, so the HDD side cannot predict when the writing of the file will end. Therefore, when the HDD side considers switching the operation mode (known active / standby state, etc.) of the HDD to stop the motor etc. in order to save power, the operation mode is switched without permission. However, it is impossible because it cannot be judged whether there is any problem.

  Further, as described above, the memory mounted on the HDD is sometimes used as a read cache (cache memory at the time of data reading), but this is not very effective for recording, recording, and writing at the time of downloading.

  In the configuration in which a part of the memory of the HDD is used as a write buffer, this buffer is under the control of the hard disk controller (HDC) of the HDD and is open to the CPU outside the HDD. Absent. Even if it is publicly available, this buffer has a capacity of 512 bytes for one sector, and since there is no buffer control command that assumes writing across multiple sectors, it can only write data in units of one sector. Therefore, it cannot cope with large-sized write data (for example, write data of several hundred kilobytes to several megabytes). When a large amount of data is written in one sector at a time, the load is large.

  If the time required for data writing (T3) or the duration of the active state is large, there is a problem that the power consumed by the operation of the motor or the like in the HDD increases accordingly.

  The present invention has been made in view of the problems as described above, and an object thereof is power consumption in processing operation of recording (transferring and writing) data (user data) from an information processing apparatus to a storage apparatus such as an HDD. And providing a technique capable of reducing the required time. Specifically, for example, it relates to a process of writing data to a recording medium of a storage device when recording music or moving images in an information processing device or downloading a file over a network. It is to provide a storage device technology capable of realizing the above. In particular, in the process of writing large-size data and the process of recording data having a relatively low transfer rate (processing speed) in the information processing apparatus on the recording medium of the storage apparatus having a higher transfer speed (processing speed). It provides a technology that can effectively save power.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows. In order to achieve the above object, the present invention is a technology of a storage drive or storage device (storage device) such as an HDD, an information processing device on which a storage device is mounted or connected, and an information processing system. It is characterized by providing an objective means.

  In the prior art, the HDD cannot independently switch its own operation mode, and power saving cannot be performed by spontaneous switching of the operation mode. However, in the present invention, a write buffer provided on the memory of the storage device is not provided. Corresponding to the data writing operation used, the controller of the storage apparatus is configured to save power by switching the operation state (mode) of the storage apparatus. In the prior art, it was not possible to cope with large-size write data. However, in the present invention, write data is temporarily stored in a write buffer secured in the storage device and written to a recording medium at once, thereby writing required time (T3). A method for shortening the power consumption and realizing power saving is used.

  This system is a system in which data is recorded (written) from a host information processing device to a storage medium recording medium. By using a write buffer provided on the memory of the storage apparatus, data can be written to the recording medium. In this configuration, transfer (DMA transfer: direct memory access transfer) is separated or pipelined. With this configuration, the data recording process from the information processing device to the storage device includes the first transfer (DMA transfer) of data from the memory (main storage device) of the information processing device to the write buffer of the storage device, and the write of the storage device. This is divided into a second transfer (writing) of data from the buffer to the recording medium.

  In this system, the above control is realized by processing a command (DMA command) newly added to the storage apparatus. In other words, the controller of the storage apparatus processes the command from the host and controls the first and second transfers. The storage apparatus stores the data read by the first transfer (DMA transfer) from the memory in the information processing apparatus, which is an external device for itself, in the write buffer. Then, the data accumulated in a predetermined amount on the write buffer is written into the recording medium at once by the second transfer.

  Further, in connection with the control operation, a power saving (power saving) control operation regarding the drive hardware unit of the storage apparatus is performed. That is, at the time of the first transfer operation, the operation state of the storage apparatus is set to the first state (active state) in which the drive hardware unit operates. In this configuration, the power saving control of the conventional storage device mainly based on the host CPU is performed as an automatic power saving control operation on the storage device side.

  The transfer size specified by the command in the transfer control corresponds to the size of the first and second transfer speeds (R1, R2) or time (T1, T2) on the information processing apparatus side and the storage apparatus side. Decide.

  The storage apparatus of the present invention has the following configuration, for example. The storage apparatus includes a controller (storage controller) that controls the entire apparatus and each unit, a memory used by the controller, a recording medium (such as a disk) on which data is recorded, and read / write (recording and reproduction) on the recording medium controlled by the controller. ), Etc., signal processing means (signal processing unit) for performing signal processing, a driving hardware unit including a motor and a head that operate on a recording medium and operates on a recording medium, and driving hardware controlled by a controller Drive control means (drive control unit) for the unit. This storage apparatus is mounted on or connected to an information processing apparatus serving as a host. The information processing apparatus includes at least a processor (CPU) and a main storage device (memory). This storage apparatus is, for example, an HDD. The HDD includes an HDC (Hard Disk Controller), a memory, and a drive unit as described above.

  The information processing apparatus according to the present invention has the storage apparatus mounted thereon or connected thereto, and includes a processor, a main storage device, a bridge unit or an interface unit for communication with the storage apparatus, an input / output device, and user data. Input / output means and the like are provided. The user data input / output means is, for example, an input / output device such as a camera, a microphone, or a display, a bearer unit (wireless transmission / reception unit), a tuner (broadcast reception unit), a network communication I / F unit, and an upper application processing unit. is there. The information processing device inputs / outputs user data through the user data input / output means and stores it in, for example, the main storage device.

  When transferring the data (user data) to the storage device for recording (writing), the processor of the information processing device sends information related to the data to be recorded and transferred to the storage device, that is, an address (data storage position). The first command (DMA command) including the transfer size and attributes (file name, file size (s1), etc.) is issued and transmitted. As the transfer size information, in particular, the DMA transfer size (s2) related to the control of the first and second transfers is used.

  The controller interprets the first command from the information processing apparatus side, and performs first transfer (DMA read) to the address buffer in the main storage device of the information processing apparatus to the write buffer secured in the memory. ). The controller secures a write buffer (or a partial area thereof) having a size corresponding to the DMA transfer size (s2) designated by the first command. Then, when a certain amount of data corresponding to the DMA transfer size (s2) is accumulated (filled) in the write buffer, the controller stores the certain amount of data via the control of the signal processing means and the drive control means. Then, the recording medium is written by the second transfer (writing). At the time of the second transfer, the operation state of the storage device becomes the first state (active state).

  When the controller finishes writing a certain amount of data on the write buffer to the recording medium by the second transfer, the controller sets the first management information related to the data to the attribute included in the first command. Are created based on such information and written in the area (FAT area) of the recording medium for updating. The controller grasps the start and end of each transfer and writing by command processing.

  In addition, when the writing of the first management information to the recording medium is completed, the controller promptly instructs the drive control unit to switch the operation state, and so on, so that the drive control unit operates the drive hardware unit. Let me control. As a result, the operation state of the storage apparatus is shifted from the first state (active state) to the second state (standby state) in which the drive hardware unit is stopped.

  When the information processing apparatus attempts to read the first management information on the storage apparatus side corresponding to the data to be recorded and transferred by using a command after the operation state of the storage apparatus is changed to the second state, The controller responds to the information processing apparatus with the second management information (partial information) corresponding to the first management information written in the area of the recording medium and held in the controller or in a part of the memory. ·Send. The information processing apparatus updates the third management information (management information copy) held by itself using the second management information. In the entire user data recording process, the required time (T3) is shortened, and the necessary power consumption is reduced as compared with the prior art, thereby realizing power saving.

  The operation of the first command is based on DMA transfer from the information processing device to the write buffer of the storage device. As another configuration of the present invention, the operation of the second command (PIO command) is as follows: It is configured by PIO (processor input / output) transfer from the information processing device to the write buffer of the storage device.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows. According to the present invention, as a main effect, it is possible to realize a reduction in power consumption and required time in a data recording processing operation from an information processing device to a storage device such as an HDD. In particular, in the process of writing large-size data and the process of recording data having a relatively low transfer rate (processing speed) in the information processing apparatus on the recording medium of the storage apparatus having a higher transfer speed (processing speed). , Can save electricity.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. 7 and 8 show examples of the prior art in order to explain the features of the present invention in an easy-to-understand manner in comparison with the prior art.

(Embodiment 1)
The first embodiment will be described with reference to FIGS. In the first embodiment, as a feature, a user data recording process by a DMA transfer and a power saving control by a process of a newly added command (named as a DMA command as an example) is realized. FIG. 1 shows a system configuration. FIG. 2 shows the operation of the DMA command. FIG. 3 shows the continuous operation of the DMA command. FIG. 4 shows a file management table (FAT) before and after file writing. FIG. 5 shows FAT before and after file deletion.

<System>
The configuration of the system and apparatus will be described with reference to FIG. This system (information processing system 300) has a configuration in which an SD (storage drive) 200 is connected to an information processing apparatus (first information processing apparatus) 100 serving as a host. Further, the present system (300) can also be regarded as an information processing apparatus (second information processing apparatus) in which the SD 200 is mounted. In this example, the former system (300) will be described, but the characteristic operation is the same in the case of the latter second information processing apparatus.

  In this example, the information processing apparatus 100 is a mobile phone used by a user, and the SD 200 is an HDD. The SD 200 has a drive hardware unit, and may be a device such as a CD drive, a DVD drive, a UMD, or an MD in addition to the HDD. The SD 200 is not a semiconductor memory, flash memory, non-volatile memory, card device, or the like.

  The information processing apparatus 100 includes a CPU 11, a main memory (memory) 12, a flash memory card 13, a bridge (or chip set) 14, a bearer unit (bearer chip) 15, a tuner 16, a camera and microphone 17, an LCD (liquid crystal display) and a speaker. 18 and a keypad 19.

  In the information processing apparatus 100, a main memory 12, a bearer unit 15, a tuner 16, and various input / output devices are connected to a CPU 11 via a bridge 14. Further, the HDC 21 of the SD 200 is connected to the CPU 11 of the information processing apparatus 100 via a bridge 14 through a predetermined interface (for example, ATA bus). In this example, the bridge 14 is a north bridge that connects the CPU bus, the IO bus, and the main memory bus. However, the bridge 14 may be a companion chip or bus adapter that connects the ATA bus of the HDD, or a level conversion chip that is a simple discrete component. Absent.

  The CPU 11 can issue commands related to user data recording processing to the SD 200 in addition to the OS and various application processing.

  With this configuration, the information processing apparatus 100 is capable of playing, recording, recording, copying, and the like of music and moving images in addition to a call function as a mobile phone. Call by the bearer unit 15, download of data, broadcast reception by the tuner 16, shooting by the camera, recording by the microphone, image display on the LCD, voice output to the speaker, character input by the keypad, reading and writing of data to the flash memory card 13 Etc. are possible.

  The information processing apparatus 100 (cellular phone) realizes a recording function by, for example, appropriately buffering the terrestrial digital broadcasting one-segment broadcast received by the tuner 16 in the main memory 12 and writing (recording) it as a file in the SD 200. ing. In the information processing apparatus 100, the data stored in the main memory 12 may be stored and saved in another storage device (for example, the flash memory card 13). In the present embodiment, the bandwidth of the one-segment broadcasting of the terrestrial digital broadcasting is a maximum of 312 kbps, which is lower than 24 Mbps (or 3 Mbps) which is the media transfer speed (R1) in the write head (28) of the SD26 disk 26. .

  In addition, the information processing apparatus (mobile phone) 100 can download files via the mobile phone network by the bearer unit 15, receive a content distribution service via the mobile phone network, or use it in a home server at home. It is possible to connect and download video and audio data. In this download, the information processing apparatus 100 realizes a data storage function by temporarily buffering received data in the main memory 12 and writing the data in the SD 200 as a file. In this embodiment, the communication speed of the bearer unit 15 is 14.4 Mbps, which is lower than the media transfer speed (R1) in SD200. That is, the conditions are R1> R2 and T1 <T2, as described above.

  In the present embodiment, due to the above conditions, data to be written as a file in the SD 200 is once buffered in the main memory 12 in any user data input / output process such as recording or downloading. When a certain amount of received data is accumulated by buffering in the main memory 12 or the like, the media transfer rate (R1) on the SD 200 side is collectively written (transferred) to the SD 200 side. This shortens the overall time required for writing (T3).

  The SD 200 includes a controller (HDC) 21, a memory 22, a signal processing unit 24, a drive control unit 25, a recording medium (disk) 26, a motor (spindle motor) 27, a head 28, and the like. A write buffer 23 is secured in the memory 22.

  The HDC 21 controls the entire SD 200 and is mounted as an IC (semiconductor integrated circuit device). The HDC 21 processes newly added commands in addition to conventional command processing. A write buffer 23 is secured in the memory 22 and is used in user data recording processing. The main memory 12 and the memory 22 are volatile memories such as RAM. The flash memory card 13 is used as a secondary storage device for the main memory 12, but is not essential.

  The signal processing unit 24 is controlled by the HDC 21 and reads / writes signals from / to the disk 26 through drive control by the drive control unit 25. The signal processing unit 24 is a circuit such as a DSP (digital signal processor). The signal processing unit 24 may be integrated with the HDC 21. The drive control unit 25 is controlled by the HDC 21 and the signal processing unit 24, and controls driving of drive hardware units such as the motor 27 and the head 28. The drive control unit 25 is a circuit such as a pulse control circuit including a DAC (digital / analog converter). In accordance with drive control by the drive control unit 25, the disk 26 is rotated by the motor 27, the head 28 is moved and aligned with respect to the surface of the disk 26, and the signal on the surface of the disk 26 is processed in accordance with the processing of the signal processing unit 24. Reading and writing are done.

  Since the HDC 21 voluntarily manages the FAT, it always has a part of FAT information, and the information processing apparatus 100 has a copy of the FAT information on the SD 200 side.

  The write buffer 23 has a variable or fixed capacity within the capacity of the memory 22. The capacity of the write buffer 23 may be set in advance, for example, or may be variably assigned according to each processing such as designation of a transfer size by a command.

  An example of control of the state (mode) of the SD 200 in the present embodiment will be described. In this example, transition is made between two types of states, an active state and a standby state. In the active state, corresponding to the read / write operation with respect to the disk 26 of the SD 200, the drive hardware unit that is a power required unit such as the motor 27 and the head 28 is operated (for example, rotation or movement). In the standby state, the drive hardware unit stops operating. The standby state is also referred to as a power saving state by stopping the driving hardware unit, reducing power supply, or the like. In any state, the HDC 21 is in an active state. Other states generally include an idle state (a state in which the driving hardware unit is in operation and no reading / writing with respect to the disk 26), a sleep state (a state in which the driving hardware unit is stopped and the HDC 21 is inactive), and the like. It may be controlled in combination with these.

<Process (1)>
The main memory of the information processing apparatus 100 is used as an operation of user data recording processing using a command (DMA command) newly added to the SD 200 in the present embodiment using the sequences shown in FIGS. A first process of data transfer and writing from 12 to the SD 26 disk 26 will be described. In the figure, “WB” corresponds to the write buffer 23, and “drive unit” corresponds to the drive control unit 25, the drive hardware unit (27, 28), the disk 26, and the like. S201 and the like indicate processing steps. In the first process of FIG. 2, user data is transferred by one transfer control or operation (U1) corresponding to the DMA transfer size (s2) which is a unit for transfer processing between the information processing apparatus 100 and the SD 200 at a time. This is when it is completed. The second process in FIG. 3 is a case where the transfer of user data is completed by two transfer controls (U1, U2).

  The first process in the user data recording process will be described with reference to FIG. The CPU 11 of the information processing apparatus 100 designates an address (DMA transfer start address), a size (s2: DMA transfer size), an attribute (including a file name, the size of the entire user data (s1), and the like) using a DMA command. It is described and issued / transmitted to the SD 200 (HDC 21) (S201). As an example, the DMA transfer size (s2) is assumed to be n data units. The DMA transfer size (s2) specified by the command is determined according to the transfer rate (R1) or time (T1) on the SD 200 side.

  The DMA command from the CPU 11 side is received by the SD 200 and interpreted by the HDC 21. The HDC 21 prepares and secures a write buffer 23 on the memory 22. The HDC 21 secures a write buffer 23 having a capacity corresponding to the designation of the DMA transfer size (s2) in response to reception of the DMA command, or reserves a write buffer 23 having a predetermined capacity in advance.

  The HDC 21 interprets the received DMA command, thereby reading the target data (user data) on the main memory 12 by DMA transfer and temporarily storing it in the write buffer 23 secured on the memory 22. That is, the HDC 21 requests a DMA read from the main memory 12 (“DMA Read”, S202), starts DMA transfer sequentially from the first data (DATA # 1), and stores it in the write buffer 23. go. Then, the transfer up to the nth data (DATA # n) is completed by continuous DMA transfer in units of data, and the amount of data stored in the write buffer 23 is equal to the DMA transfer size specified by the DMA command ( S2) minutes are reached.

  When the DMA transfer processing for the DMA transfer size (s2) is completed, the HDC 21 transfers the data (DATA # 1 to #n) on the write buffer 23 of the memory 22 to the signal processing unit 24 and the drive control unit 25. Through the control, data is written to the disk 26 at once (S203). At the time of writing to the disk 26, the drive unit is in an active state ("ACTIVE").

  When the writing to the disk 26 is finished, that is, when the writing of the nth data (DATA # n) is finished, the HDC 21 updates the FAT information and writes it in the FAT area of the disk 26 (“FAT”, S204). Immediately thereafter, the HDC 21 commands the drive control unit 25 to transition to the standby state (“STANDBY”) (“Stand By”, S206). As a result, the drive control unit 25 makes a transition from the active state to the standby state by stopping (temporarily stopping) the operation of the drive hardware unit such as the motor 27 and the head 28 with respect to the disk 26.

  On the other hand, the HDC 21 returns an acknowledge (ACK) to the DMA command to the CPU 11 immediately after the update of the FAT area (S205). Here, FIG. 2 shows a case where the file transfer of the target user data is completed by the first processing (S202, S203) corresponding to the DMA transfer size (s2) in the DMA command. When receiving the ACK from the HDC 21, the CPU 11 notifies the end of the transfer of user data and notifies the HDC 21 that the data transfer has been completed ("END") (S207). When the HDC 21 receives the data transfer completion notification from the CPU 11 side, it returns ACK.

  When the CPU 11 receives an ACK from the HDC 21 side, it tries to read the data (FAT information) in the FAT area updated by the HDC 21 in order to update the file management table (FAT information copy) managed by the CPU 11 (“Read”). -FAT-entry ", S208). On the other hand, the HDC 21 returns the corresponding data (FAT partial information) of the FAT managed by the HDC 21 to the CPU 11 without reading the data (FAT information) of the corresponding FAT area of the disk 26 (“Reply”). . The CPU 11 updates the FAT information copy with the returned FAT partial information. Thus, a series of processing is completed.

  The HDC 21 knows the FAT information by the DMA command processing, and can return the FAT partial information. This is more efficient than reading from disk 26 and returning. The FAT partial information is stored and managed in the HDC 21 internal memory. Alternatively, it may be stored in a partial area in the memory 22.

  As described above, the CPU 11 newly adds a command (DMA command) to the SD 200 and a read command (“Read-FAT-entry”) of the FAT area of the SD 200 for updating the FAT (FAT information copy). By using these two commands, data such as a moving image file on the main memory 12 can be written and saved on the disk 26 of the SD 200. In this process, the drive unit of the SD 200 is in an active state only when data is written from the write buffer 23 to the disk 26.

<Process (2)>
Next, the second process in the user data recording process will be described with reference to FIG. In the case of the first process of FIG. 2, the target user is written by writing the first to nth data (DATA # 1 to #n) corresponding to the DMA transfer size (s2) (first transfer control: U1). Although the data transfer and writing have been completed, in the case of the second process in FIG. 3, the process is not completed only by the first transfer control (U1), and the process is continued several times, for example, the second transfer control (U2). ) Until the process ends. The first transfer control (U1) process (S301 to S306) is the same as the process shown in FIG.

  After the first transfer control (U1) writes the data up to the nth data (DATA # n) to the disk 26 (S303), the HDC 21 updates the FAT area (S304) and immediately sends an ACK to the DMA command to the CPU 11. Return (S305), and the drive hardware unit is shifted to the standby state (S306). When the CPU 11 receives the ACK from the HDC 21 side, it instructs the HDC 21 that the transfer of the target user data has not been completed or the DMA read of the data after the (n + 1) th data (DATA # n + 1 to 1) (DATA # n + 1) ( S311). Here, this is instructed using the command “Continue”.

  The HDC 21 interprets the received command (“Continue”), thereby requesting a DMA read from the main memory 12 (S312), as in the case of the first transfer control (U1), and the (n + 1) th data DMA transfer is started from (DATA # n + 1) and accumulated in the write buffer 23 of the memory 22. When the transfer up to the 2n-th data (DATA # 2n) corresponding to the DMA transfer size (s2) is completed and the amount of data stored in the write buffer 23 reaches the DMA transfer size (s2), the HDC 21 writes the data in the memory 22 The data (DATA # n + 1 to # 2n) in the buffer 23 is written to the disk 26 at once (S313). When the writing of the 2n-th data (DATA # 2n) is completed, the HDC 21 updates the FAT information managed and writes it in the FAT area of the disk 26 (S314). Immediately thereafter, the HDC 21 commands the drive control unit 25 to transition to the standby state, and stops the drive hardware unit (S316).

  On the other hand, the HDC 21 returns an ACK for the DMA command to the CPU 11 immediately after the update of the FAT area (S315). Here, FIG. 3 shows a case where the transfer of the target user data file is completed by the second processing (S312 and S313) corresponding to the DMA transfer size (s2) in the DMA command. That is, the size (s1) of the entire file of the target user data corresponds to the first to 2n (or n + 1 or more and less than 2n) data units. When receiving the ACK from the HDC 21, the CPU 11 notifies the end of the transfer of the user data and notifies the HDC 21 that the data transfer is complete ("END") (S321). When the HDC 21 receives the data transfer completion notification from the CPU 11 side, it returns ACK.

  When the CPU 11 receives the ACK from the HDC 21 side, the CPU 11 tries to read out the FAT information updated on the HDC 21 side in order to update the FAT information copy managed by the CPU 11 (“Read-FAT-entry”, S322). On the other hand, the HDC 21 returns the corresponding FAT partial information managed by the HDC 21 to the CPU 11 without reading the corresponding FAT information on the disk 26 (“Reply”).

  In the above series of operations, the disk 26 of the SD 200 has a period from the start of writing of the first data (DATA # 1) (S303) to the transition to the standby state (S306) in the first transfer control (U1), In the period from the start of writing (S313) to the transition to the standby state (S316) of the (n + 1) th data (DATA # n + 1) in the second transfer control (U1), the SD 200 is in the active state, and the drive hardware unit Is operating, for example, the motor 27 is rotating. The period from the transition to the standby state (S306) in the first transfer control (U1) to the start of writing (S316) of the (n + 1) th data (DATA # n + 1) in the next second transfer control (U2) In the second transfer control (U2) and the period after the transition to the standby state (S316), the SD 200 is in the standby state. During this time, DMA read processing is performed between the CPU 11 and the main memory 12, and the HDC 21 and the memory 22, but the SD 200 side is conserving power in a standby state.

  The command “Continue” in S311 designates the DMA transfer size (s2) in the next transfer control (U2). That is, in the transfer control (U2) of the last time (second time in this example) that the transfer of the entire size of the target user data file (s1) is completed, the initial (first time) corresponding to the remaining data. The transfer is executed by specifying a value smaller than the specified n. When the DMA transfer size (s2) is not specified, the processing may be performed in such a manner that the specification in the initial transfer control (U1) is taken over.

  The same applies to the case where three or more transfer controls are required. That is, the transfer control from the first time is repeatedly executed with the DMA transfer size (s2) set to n, and the transfer control is executed at the last time with the DMA transfer size (s2) set to n or less to complete the user data recording process. To do.

<FAT>
The management of FAT by the CPU 11 and the HDC 21, maintenance of FAT consistency, and the like will be described with reference to FIGS. FIG. 4 shows an example of the state of the FAT before and after file writing. FIG. 5 shows an example of FAT status before and after file deletion.

  In FIG. 4A, the FAT manages the disk 26 of the SD 200 in a cluster having a plurality of continuous sectors as recording units, not a sector as a minimum recording unit. In the FAT of FIG. 4A, the data file indicated by the file name is written in the continuous cluster for the occupied number starting from the top cluster indicated by the file name. At first glance, it can be seen that, for example, the data file with the file name “c1.dat” occupies a total of 5 clusters, starting with the cluster “0000”. The FAT shown in FIG. 4A includes three files “c1.dat”, “c2.dat”, and “c3.dat”. The clusters after the first cluster “000f” indicated by the null file are stored on the disk 26. It is an unused area.

  When the HDC 21 writes the data read by the DMA in accordance with the DMA command to the disk 26, the HDC 21 writes the data to a continuous cluster after the cluster indicated by the null file. Information) and the FAT area (FAT information) of the disk 26 is thereby updated.

  For example, when writing a new “c4.dat” from the state of FIG. 4A as shown in FIG. 4B, the HDC 21 sequentially stores the data of the file from the first cluster “000f” indicated by the null file. When the writing is completed, the first cluster indicated by the null file is updated.

  As shown in FIG. 4C, the file name “c4.dat” is added to the FAT after writing “c4.dat”, and it can be seen that the leading cluster occupies 6 clusters of “000f”. Further, the unused area pointed to by the null file is updated so as to point to the leading cluster “0015”.

  Next, in FIG. 5, the handling of the null file when the file is deleted will be described. In the FAT of FIG. 5A in the same state as FIG. 4C, for example, as shown in FIG. 5B, “c3” occupied four clusters “000b” to “000e”. When “.dat” is deleted, the file name of the entry occupied by FAT “c3.dat” becomes null as shown in FIG.

  After this deletion, when the CPU 11 writes a file whose number of occupied clusters is 4 or less, the cluster occupied by the “c3.dat” is reused. In addition, when the CPU 11 writes a file having the number of occupied clusters of 5 or more, the CPU 11 does not perform the above-described reuse, but writes it to successive clusters after the first cluster “0015”.

  As described above, the HDC 21 of the SD 200 manages the FAT information, and the CPU 11 side of the information processing apparatus 100 also manages the FAT information (FAT information copy) by reading out the FAT information (FAT partial information) on the SD 200 (HDC 21) side. To do.

<Contrast with conventional technology>
The operation of a command (DMA command) newly added to the SD 200 has been described with reference to FIG. 2, FIG. 3, and FIG. 6, but the period during which the SD 200 is in the active state is shown in FIG. The operation will be described in comparison with the case of the operation according to the prior art shown in FIG. FIG. 7 shows a first operation example of a conventional DMA command. FIG. 8 shows a second operation example of the conventional DMA command. In the prior art system, no write buffer is provided in the SD (HDD).

  In FIG. 7, the CPU of the information processing apparatus instructs the SD (HDD) to perform a DMA transfer from the main memory to the SD disk by the conventional DMA transfer using a “WRITE DMA” command (S 701). The SD HDC interprets the received “WRITE DMA” command and attempts a DMA read to the main memory of the information processing apparatus (S702). When the HDC receives the first data (DATA # 1) from the main memory, the HDC writes it in the disk without storing it in the memory (S703). Thereafter, the same operation is repeated up to the nth data (DATA # n). Note that the memory here is a memory that a conventional SD (HDD) has locally, and has been used as a read buffer in the past, but is not used as a write buffer.

  When the HDC finishes writing the nth data (DATA # n) to the disk, the HDC returns an ACK to the CPU (S704). The CPU that has received the ACK rewrites the data (FAT information) in the FAT area of the SD disk by transmitting the “PIO WRITE” command and the FAT information, thereby updating the file management information (FAT information) (S705). Here, the update is performed by transferring update FAT information (“FAT”) following the “PIO WRITE” command.

  When the rewriting (updating) of the FAT area is completed, the HDC returns ACK to the CPU (S706). Here, it is assumed that the transfer of the target user data is completed by the PIO transfer process (S703). When the CPU receives the ACK, since there is no task for reading / writing the SD disk thereafter, the CPU sends a “Stand By” command to the SD to instruct the transition to the standby state. Transition to the standby state.

  In both the rightmost drive unit in FIGS. 7 and 2, the motor of the drive hardware unit is rotating during the period from the writing of the first data (DATA # 1) until the standby state is instructed. In the active state. In the case of FIG. 7, the period of this active state depends on the main memory or the turnaround time (indicated by t1) between the CPU and SD. Here, the turnaround time is the time from when the command is issued until the ACK is returned.

  On the other hand, in the case of FIG. 2, the period of the active state depends on the processing time (T2) of the HDC 21 of the SD 200, in particular, the speed and time of the write processing from the write buffer 23 to the disk 26 (S203, S204). . When FIG. 7 is compared with FIG. 2, it can be seen that the period of the active state is shorter in FIG. Since the amount of power is the product of the power during operation and the operation time, the amount of power consumption naturally decreases if the active state period is short. Therefore, the SD 200 operated by the newly added DMA command in the present embodiment of FIG. 2 consumes less power and consumes less power than the SD (HDD) operated by the prior art of FIG. The average power consumption calculated by averaging the values over time is also reduced.

  In FIG. 8, the reduction in power consumption is conspicuous when the “WRITE DMA” command is issued repeatedly (when the size of the target user data is large and a plurality of transfer controls are required). In contrast to the operation by the repeated (for example, twice) “WRITE DMA” command shown in FIG. 8 according to the prior art, the implementation example in this embodiment is a plurality of (twice) transfer control (U1, U2) shown in FIG. This is an operation according to U2).

  In the operation of the prior art in FIG. 8, the SD maintains an active state from the writing of the nth data (DATA # n) to the writing of the (n + 1) th data (DATA # n + 1) by the CPU. During this time, after receiving the ACK (S804), the CPU transmits a “WRITE DMA” command (S811), and the HDC that has received the command attempts a DMA read to the main memory. During this time, the CPU does not instruct the SD to transition to the standby state. Further, since the HDC cannot predict the next command instructed by the CPU, it is impossible to instruct the drive unit to transition to the standby state. As a result, during this period, the motor and the like of the SD drive unit continue to maintain the active state without stopping.

  On the other hand, in the case of the operation of the SD 200 of the present embodiment in FIG. 3, the period during which the SD is in the active state is shortened by the operation of the DMA command as compared with the operation of the prior art in FIG. And the average power consumption is low.

  As described above, the system according to the first embodiment uses part of the memory 22 of the SD 200 as the write buffer 23 and writes data on the main memory 12 of the information processing apparatus 100 to the disk 26 of the SD 200 (user data recording process). In this configuration, the DMA transfer in FIG. That is, the first transfer (DMA read) between the main memory 12 and the write buffer 23 and the second transfer (write) between the write buffer 23 and the disk 26 are separated. As a result, the time required for writing to the disk 26 can be minimized, and the SD200 is in an active state only during the second transfer, thereby reducing the amount of work / power during writing, resulting in a reduction in the average power consumption of the SD200. it can.

(Embodiment 2)
Next, Embodiment 2 will be described with reference to FIG. In the second embodiment, as features, PIO transfer by processing of a newly added command (named as a PIO command as an example) and user data recording processing by power saving control are realized. FIG. 6 shows the operation of the PIO command. The system configuration of the second embodiment is the same as that of the first embodiment, and the control operation is different.

  The command (DMA command) added to the SD 200 of the first embodiment attempts a DMA transfer between the main memory 12 and the write buffer 23 on the memory 22. On the other hand, in the configuration and processing of FIG. 6 in the second embodiment, the CPU 11 controls the DMA transfer control operation between the main memory 12 and the write buffer 23 of FIG. 2 from the CPU 11 using the newly added PIO command. It is replaced with the control operation of PIO transfer to

  The user data recording process will be described with reference to FIG. The CPU 11 of the information processing apparatus 100 designates an address (PIO transfer start address), size (s3: PIO transfer size), attributes (including a file name, the size of the entire user data (s1), etc.), etc., with a PIO command. It is described and issued / transmitted to the SD 200 (S601). As an example, the PIO transfer size (s3) is n data units. The transmission of the PIO command and the recording target data may be performed by separately transmitting the command and the data, or may be performed by storing data in the command.

  The HDC 21 interprets the PIO command received from the CPU 11 side, and prepares and secures the write buffer 23 on the memory 22. Thereafter, the first data (DATA # 1) is first transmitted from the CPU 11 to the write buffer 23 of the HDC 21 in accordance with the designation of the transfer size (s3) in the PIO command, and then the nth data (sequentially) Up to DATA # n). When the transfer up to the nth data (DATA # n) corresponding to the PIO transfer size (s3) is completed, the CPU 11 transmits the “FLUSH CACHE” command defined by the ATA to the HDC 21 (S602). ). This command causes the accumulated data (DATA # 1 to #n) to be written at a time.

  Upon receiving this command, the HDC 21 of the SD 200 writes the corresponding data (DATA # 1 to #n) on the write buffer 23 of the memory 22 to the disk 26 at a stretch through the control of the signal processing unit 24 and the drive control unit 25 (S603). ). At the time of writing to the disk 26, the drive unit is in an active state ("ACTIVE"). When the writing of the nth data (DATA # n) is completed, the HDC 21 updates the FAT information (FAT partial information) and writes it in the FAT area of the disk 26 (S604). Immediately thereafter, the HDC 21 commands the drive control unit 25 to transition to the standby state (“STANDBY”), thereby stopping the motor 27 and the like of the drive hardware unit and transitioning to the standby state (S606).

  On the other hand, the HDC 21 returns an ACK for the PIO command to the CPU 11 immediately after the update of the FAT area (S605). Here, FIG. 6 shows a case where the transfer of the target user data file is completed by the first process (S601 to S603) corresponding to the PIO transfer size (s3) in the PIO command.

  When receiving the ACK from the HDC 21, the CPU 11 notifies the end of the transfer of user data and notifies the HDC 21 that the data transfer has been completed ("END") (S607). When the HDC 21 receives the data transfer completion notification from the CPU 11 side, it returns ACK.

  When the CPU 11 receives the ACK from the HDC 21 side, the CPU 11 tries to read the data (FAT information) in the FAT area updated by the HDC 21 in order to update the FAT (FAT information copy) managed by the CPU 11 (“Read-FAT”). -Entry ", S608). On the other hand, the HDC 21 returns the corresponding data (FAT partial information) of the FAT managed by the HDC 21 to the CPU 11 without reading the data (FAT information) of the corresponding FAT area of the disk 26 (“Reply”). . Since the HDC 21 knows the FAT information by processing the PIO command, it can return the FAT partial information, which is more efficient than when it is read from the disk 26 and returned.

  As described above, the CPU 11 uses the two commands, that is, the added command (PIO command) and the FAT area read command for updating the FAT (“Read-FAT-entry”) to thereby store the main memory 12. Data such as the above moving image file can be written and stored in the disk 26 of the SD200. In this process, the drive unit of the SD 200 is in an active state only when data is written from the write buffer 23 to the disk 26.

  The prior art corresponding to the second embodiment is configured to perform a processing operation by transferring data from the CPU and main memory to the SD disk, and the period of the active state depends on the turnaround time. On the other hand, in the case of the second embodiment, as in the first embodiment, the period of the active state is the processing time (T1) of the HDC 21 of the SD 200, in particular, the speed and time of the writing process (S603, S604) to the disk 26. , Depends on. Therefore, the SD 200 operated by the PIO command of the second embodiment is shorter than the prior art, and the active period is shorter, and the power consumption and the average power consumption are also lower.

  As described above, in the system of the second embodiment, the data transfer in the user data recording process is the first transfer (PIO transfer) between the CPU 11 and the main memory 12 of the information processing apparatus 100 and the write buffer 23 of the SD 200. In this configuration, the second transfer (writing) between the write buffer 23 and the disk 26 is separated. Thereby, regardless of the transfer speed between the external device (information processing apparatus 100) and the SD 200, the time required for writing data to the disk 26 with the transfer speed between the write buffer 23 and the disk 26 being substantially constant ( T2) can be made uniform and minimized, and the amount of work / power at the time of writing can be reduced by making the SD 200 active only during the second transfer, and as a result, the average power consumption of the SD 200 can be reduced.

(Embodiment 3)
Next, Embodiment 3 will be described with reference to FIGS. In the third embodiment, as a feature, user data recording processing by processing of a newly added command (DMA command) in the first embodiment and a read command from the host (information processing apparatus 100) according to a read command from the disk This data reading process is performed with priority over data writing to the disk. In other words, prefetch processing of user data to the host is performed. The system configuration of the third embodiment is the same as that of the first embodiment, and the control operation is different.

  In the sequence of FIG. 9, the DMA command similar to the above and the operation using it (user data recording process), the conventional read command (“READ DMA”) following the DMA command, and the operation based thereon are shown. . In this configuration and processing, a DMA command (data write transfer) between the HDC 21 and the main memory 12 and a “READ DMA” between the HDC 21 and the main memory 12 using a read command (“READ DMA”) following the DMA command. Control operation with transfer (data read transfer) is performed. A read command is issued (received) in the middle of the data write process by the first DMA command, the data read process (prefetch process) is preferentially performed, and then the data write process by the previous DMA command is resumed. Is the case.

  Processing such as S901, S902, S9031, S9032, and S904 to S908 using the DMA command is user data recording processing similar to the processing of S201 to S203 in FIG. 2 of the first embodiment. 9 is a case where the transfer of user data is completed by one transfer control / operation (U1) corresponding to the DMA transfer size (s2).

  First, the CPU 11 of the information processing apparatus 100 designates / describes an address, size (s2: DMA transfer size), attribute, and the like with the DMA command, and issues / transmits it to the SD 200 (S901).

  The DMA command from the CPU 11 side is received by the SD 200 and interpreted by the HDC 21. The HDC 21 prepares and secures a write buffer 23 on the memory 22. The HDC 21 interprets the received DMA command, thereby reading the target data (user data) on the main memory 12 by DMA transfer and temporarily storing it in the write buffer 23 secured on the memory 22. That is, the HDC 21 requests DMA read from the main memory 12 (“DMA Read”, S902), starts DMA transfer in order from the first data (DATA # 1), and stores it in the write buffer 23. go. Then, the transfer up to the nth data (DATA # n) is completed, and the amount of data stored in the write buffer 23 reaches the DMA transfer size (S2).

  Next, the HDC 21 writes the data (DATA # 1 to #n) on the write buffer 23 to the disk 26 at a stretch through the control of the signal processing unit 24 and the drive control unit 25 (S9031, S9032). At the time of writing to the disk 26, the drive unit is in an active state ("ACTIVE"). When the DMA transfer processing for the DMA transfer size (s2) is completed, the HDC 21 writes the data (DATA # 1 to #n) on the write buffer 23 to the disk 26 at once (S9031, S9032).

  Here, before and after writing to the disk 26 (S9031), the CPU 11 issues / transmits the conventional “READ DMA” command defined by the ATA bus to the SD 200 (HDC 21) (S911).

  The HDC 21 that has received the “READ DMA” command writes the data (DATA # 1 to #n) on the write buffer 23 to the disk 26 (S9031, S9032) in the middle (between S9031 and S9032 in this example). ). Then, in accordance with the interpretation of the “READ DMA” command, the HDC 21 reads the data to be read designated by the command (which differs from DATA # 1 to #n, etc.) from the disk 26 to the memory 22 (S912).

  When the reading of the target data from the disk 26 (S912) is completed, the HDC 21 resumes writing the corresponding data (DATA # 1 to #n) to the disk 26 that was interrupted earlier (S9032).

  The target data read by the reading from the disk 26 (S912) is transferred from the HDC 21 and the memory 22 to the area (prefetch buffer) on the main memory 12 by the DMA write (“DMA Write”) (S913). ).

  When the operation of the DMA write (S913) of the unit data group of the target data is completed, the HDC 21 notifies the CPU 11 that the target data has been transferred by ACK to the previous read command (“READ DMA”). Return (S914). With this ACK (S914), the transfer control operation (UR) accompanying a series of read commands (“READ DMA”) is completed.

  On the other hand, when the writing of data to the disk 26 resumed from S9032 is finished, that is, when the writing of the nth data (DATA # n) is finished, the HDC 21 updates the FAT information and writes the disk 26 as described above. Are written in the FAT area ("FAT", S904). Immediately thereafter, the HDC 21 commands the drive control unit 25 to transition to the standby state (“STANDBY”) (“Stand By”, S906). Thus, the drive control unit 25 makes a transition from the active state to the standby state by stopping (temporarily stopping) the operation of the drive hardware unit.

  On the other hand, the HDC 21 returns an ACK for the DMA command to the CPU 11 immediately after the update of the FAT area as described above (S905). By this ACK (S905), the transfer control operation (U1) accompanying a series of DMA commands is completed.

  When the operation (U1) associated with the DMA command is compared with the operation (UR) associated with the conventional read command (“READ DMA”), the data read operation ( U2) is being executed (included).

  Here, as described above, the transfer of the target user data file can be completed by the processing (S902, S9031, S9032) for the DMA transfer size (s2) of the DMA command. When receiving the ACK from the HDC 21 (S905), the CPU 11 notifies the end of the transfer of user data to the HDC 21, and upon receiving the notification, the HDC 21 returns an ACK (S907). Thereafter, as described above, the CPU 11 tries to read the data in the FAT area updated by the HDC 21 in order to update the FAT (“Read-FAT-entry”, S908), and the HDC 21 reads the corresponding data (FAT partial information). ) Is returned to the CPU 11 (“Reply”), and the CPU 11 updates the FAT with the returned information. Thus, a series of processing is completed.

  As described above, the CPU 11 writes and saves data such as a moving image file on the main memory 12 to the disk 26 of the SD 200 by using the two commands of the DMA command and the FAT update command. be able to. At the same time, when a read command (“READ DMA”) is issued from the CPU 11 while the SD 200 writes and saves data on the disk 26 (when the DMA command and the read command are consecutive), the writing is interrupted and the data is read. Is given priority, and after the reading is completed, the suspended writing is resumed. In other words, “READ DMA” data reading and DMA transfer priority control are realized. In this series of processes, the drive unit of the SD 200 becomes active only during the data write process from the write buffer 23 to the disk 26 and the read process from the disk 26. That is, the average power consumption can be reduced by the transition to the standby state by the DMA command. As described above, the system according to the third embodiment can efficiently perform the data prefetching process together with the user data recording process.

  Moreover, the following is similarly possible as another configuration example related to the third embodiment. FIG. 9 shows a case where “READ DMA”, that is, a data read command by DMA transfer continues to the DMA command, but when a conventional “PIO READ”, that is, a data read command by PIO transfer, continues to the DMA command. The same processing is possible in Specifically, when the HDC 21 receives “PIO READ” instead of “READ DMA” in S911, writing to the disk 26 by the DMA command (S9031, S9032) is interrupted, and processing of the “PIO READ” command is performed. , And the interrupted writing (S9031, S9032) is resumed when the processing of the “PIO READ” command is completed. When the resumed writing is completed, the standby state is entered.

  In the case where the PIO command described in the second embodiment is used instead of the DMA command in FIG. 9, the same processing can be performed. Specifically, data written to the SD 200 by the PIO command is temporarily stored in the write buffer 23 managed by the HDC 21. In this state, when the CPU 11 instructs to read data using the “READ DMA” or “PIO READ” command, the HDC 21 once writes the data to the disk 26 even if the data has not been written to the disk 26 yet. The data reading instructed by the command is preferentially executed, and after the reading is completed, the writing to the disk 26 which has been interrupted is resumed. When the resumed writing is completed, the standby state is entered.

  Next, as a comparison between the third embodiment and the prior art, the period during which the SD 200 is in the active state by the DMA command and the read command is shown in the case of the operation of the third embodiment of FIG. 9 and the conventional one shown in FIG. A description will be given in comparison with the case of operating with technology.

  In FIG. 10, the processes of S1001 to S1006 are the same as S701 to S706 of FIG. That is, the CPU of the information processing apparatus writes data to the SD (HDD) disk by a “WRITE DMA” command, and writes FAT information to the disk by a “PIO WRITE” command. When the rewriting (updating) of the FAT area is completed, the SD HDC returns ACK to the CPU (S1006). Here, it is assumed that the transfer of the target user data has been completed by the PIO transfer process (S1003).

  When receiving the ACK (S1006), the CPU next moves to the operation of reading data from the disk. The CPU instructs the SD to perform the DMA transfer from the SD disk to the main memory by the conventional DMA transfer by the conventional “READ DMA” command (S1011).

  The SD HDC interprets the received “READ DMA” command, and the HDC reads the first data in the instructed data to be read from the disk, and attempts a DMA write to the main memory of the information processing apparatus (S1012). ). This DMA write operation is repeated until the transfer of the amount of data specified by the “READ DMA” command (S1011) is completed. When this operation ends, the HDC returns ACK to the CPU (S1013).

  When the CPU receives the ACK, since there is no task for reading / writing the SD disk thereafter, the CPU sends a “Stand By” command to the SD to instruct the transition to the standby state. Transition to the standby state (S1014).

  10 and 9 are both in the active state during the period from the writing of the first data (DATA # 1) until the standby state is instructed. In the case of the conventional operation shown in FIG. 10, the period of this active state depends on the total amount of turnaround time (indicated by the sum of t1 and tr) between the main memory or the CPU and SD. tr indicates the turnaround time corresponding to the processing of the “READ DMA” command.

  On the other hand, in the case of the operation of the third embodiment shown in FIG. 9, the period of the active state is the processing time (T2) of the HDC 21 of the SD 200, particularly the writing and reading processing between the write buffer 23 and the disk 26 (S9031, S912, S9032, S913, S904, etc.) and the time. Comparing FIG. 10 and FIG. 9, it can be seen that the period of the active state is shorter in FIG. Therefore, the SD 200 of the third embodiment shown in FIG. 9 consumes less power and has a lower average power consumption than the SD (HDD) operated by the conventional technique shown in FIG.

  As described above, according to each embodiment, the user data recording process from the information processing apparatus 100 to the SD 200 can be made efficient, and the power-saving SD 200 can be realized and provided. Hereinafter, other effects and operations according to the present embodiment will be described.

  Since the HDC 21 updates the FAT area instead of the host (CPU 11), the load until the FAT area is updated after data is written to the disk 26 can be reduced, and the amount of power required to update the FAT area can be minimized. . After the data is written from the write buffer 23 of the SD 200 to the disk 26 by the operation of the newly added command, the HDC 21 of the SD 200 can voluntarily write and update the file management information in the FAT area, and the SD 200 is voluntarily in the standby state. Can be transitioned to. Since SD200 can voluntarily perform operations related to file management without relying on commands from the CPU 11 of the information processing apparatus 100, the required time can be minimized and the workload / power consumption can be reduced in both FAT update and transition to the standby state. Can be reduced. By switching the operation state of the SD 200 and stopping the motor 27 and the like immediately after updating the FAT area without waiting for an instruction from the host (CPU 11), optimal power saving is possible. Until the next command is received from the host (CPU 11), the SD 200 can reliably maintain the low power consumption state in which the motor 27 and the like are stopped, and the average power consumption can be reduced.

  As shown in the third embodiment, since the HDC 21 manages the write buffer 23 of the SD 200 instead of the host (CPU 11), transfer of data to be written to the disk 26 from the host (main memory 12) to the write buffer 23 is completed. When the host (CPU 11) performs reading at this point, writing to the disk 26 can be interrupted spontaneously. The HDC 21 can voluntarily prioritize this reading. By giving priority to reading, the access time at the time of reading in the host (CPU 11) can be apparently shortened, the time during which arithmetic processing in the host (CPU 11) is interrupted can be shortened, and the performance is improved. The HDC 21 can write the data stored in the write buffer 23 to the disk 26 after the reading from the disk 26 is completed. After completion of the writing, the HDC 21 of the SD 200 can voluntarily write and update the file management information in the FAT area, and can voluntarily shift the SD 200 to the standby state. The HDC 21 can schedule writing and reading, and can reduce the average power consumption by transitioning to the standby state after the writing is completed.

  In addition, the power-saving SD (HDD, etc.) 200 makes the read / write head (28) of the disk 26 inactive by transitioning to a standby state, and is a retreat zone (shipping zone) that is less susceptible to impact according to a known technique. Move to. Therefore, even if an impact is applied to the SD200 (disk 26), the recording surface of the disk (26) is hit to damage the recording surface or the head (28) itself, or the head (28) is attracted to the disk (26). The probability of becoming inoperable can be reduced, and the reliability of the product can be improved and the life can be extended.

  In addition, since the SD200 transitions to the standby state, the increase in the accumulated operating time can be suppressed, the arrival time of the product life represented by the mean time interval (MTBF) can be postponed, and the reliability of the product can be improved. Rise. Further, as a result of transitioning the SD 200 to the standby state, the power consumption of the SD 200 is reduced, so that heat generated by the power consumption of the SD 200 can be suppressed, the temperature during operation can be reduced, MTBF can be improved, and a mechanism for heat dissipation can be omitted Not only can the cost be reduced, but the structure can be simplified, maintainability is improved, and the weight is reduced. Further, the battery life is extended by reducing the power consumption, and when the battery life is constant, the number of battery cells can be reduced and the weight can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

It is a figure which shows the block configuration of the information processing system (information processing apparatus and storage drive) of Embodiment 1 of this invention. It is a sequence diagram which shows the 1st process of the user data recording process by the operation | movement of the newly added 1st command (DMA command) in the information processing system of Embodiment 1 of this invention. It is a sequence diagram which shows the 2nd process of the user data recording process by the continuous operation | movement of the newly added 1st command (DMA command) in the information processing system of Embodiment 1 of this invention. It is a figure which shows the example of a state of the file management table (FAT) before and behind file writing in the information processing system of Embodiment 1 of this invention. It is a figure which shows the example of a state of the file management table (FAT) before and behind file deletion in the information processing system of Embodiment 1 of this invention. It is a sequence diagram which shows the user data recording process by operation | movement of the newly added 2nd command (PIO command) in the information processing system of Embodiment 1 of this invention. It is a sequence diagram which shows the 1st process example by operation | movement of the command for DMA transfer in the information processing system of a prior art. It is a sequence diagram which shows the 2nd processing example by the continuous operation | movement of the command for DMA transfer in the information processing system of a prior art. It is a sequence diagram which shows the example of the user data recording process by the continuous operation | movement of a 1st command (DMA command) and a DMA read command, and the read-out process in the information processing system of Embodiment 3 of this invention. It is a sequence diagram which shows the process example by the continuous operation | movement of the DMA write command and DMA read command in the information processing system of a prior art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... CPU, 12 ... Main memory (memory), 13 ... Flash memory card, 14 ... Bridge, 15 ... Bearer part, 16 ... Tuner, 17 ... Camera and microphone, 18 ... LCD and speaker, 19 ... Keypad, 21 ... Controller (HDC), 22 ... memory, 23 ... write buffer, 24 ... signal processing unit, 25 ... drive control unit, 26 ... recording medium (hard disk), 27 ... motor, 28 ... head, 100 ... information processing apparatus (first Information processing apparatus), 200... SD (storage drive), 300.

Claims (18)

A controller, a memory, a recording medium, signal processing means for operations including reading and writing to the recording medium, a drive hardware unit including a motor and a head, and a drive control means for the drive hardware unit, A storage device mounted on or connected to a host information processing device,
A first command including an address, a transfer size, and an attribute is issued and transmitted as information related to data to be recorded and transferred from the information processing apparatus to the storage apparatus,
The controller interprets the first command from the information processing apparatus side, and transfers the data at the address in the information processing apparatus to the write buffer secured in the memory by a first transfer process. When a certain amount of data corresponding to the transfer size is accumulated in the write buffer, the certain amount of data is transferred to the recording medium via the control of the signal processing means and the drive control means. The storage apparatus, wherein writing is performed by the second transfer, and the operation state of the storage apparatus is set to a first state in which the drive hardware unit operates in the second transfer. The storage device according to claim 1,
When the controller finishes writing the fixed amount of data on the write buffer to the recording medium by the second transfer, the controller sends first management information related to the data to the first command. The storage apparatus is created based on information included in the storage medium and written to the area of the recording medium. The storage device according to claim 2,
When the writing of the first management information to the recording medium is completed, the controller controls the drive hardware unit through the drive control unit, thereby changing the operation state of the storage device to the drive hardware. A storage apparatus, wherein a transition is made from a first state in which a hardware unit is operated to a second state in which the drive hardware unit is stopped. The storage device according to claim 3,
When the information processing apparatus attempts to read the first management information corresponding to the data to be recorded and transferred after transitioning the operation state of the storage apparatus to the second state,
The controller responds to the information processing apparatus with second management information corresponding to the first management information and held in the controller or in a part of the memory. A controller, a memory, a recording medium, a signal processing unit for operations including reading and writing to the recording medium, a driving hardware unit including a motor and a head for the recording medium, and a driving control unit for the driving hardware unit A storage device mounted on or connected to an information processing device as a host,
A second command including an address, a transfer size, and an attribute as information related to data to be recorded and transferred from the information processing apparatus to the storage apparatus, and the data to be recorded and transferred are Sent by the transfer process,
The controller interprets the second command from the information processing apparatus side, receives the data to be recorded and transferred, accumulates it in a write buffer secured on the memory, and stores the data in the write buffer. When a certain amount of data corresponding to the transfer size is accumulated, the certain amount of data is written to the recording medium by a second transfer via the control of the signal processing means and the drive control means, In the second transfer, the storage apparatus is set to a first state in which the drive hardware unit is operated in an operation state of the storage apparatus. The storage device according to claim 5,
When the controller finishes writing the predetermined amount of data on the write buffer to the recording medium by the second transfer, the controller sends first management information related to the data to the second command. The storage apparatus is created based on information included in the storage medium and written to the area of the recording medium. The storage apparatus according to claim 6, wherein
When the writing of the first management information to the recording medium is completed, the controller controls the drive hardware unit through the drive control unit, thereby changing the operation state of the storage device to the drive hardware. A storage apparatus, wherein a transition is made from a first state in which a hardware unit is operated to a second state in which the drive hardware unit is stopped. The storage apparatus according to claim 7, wherein
When the information processing apparatus attempts to read the first management information corresponding to the data to be recorded and transferred after transitioning the operation state of the storage apparatus to the second state,
The controller responds to the information processing apparatus with second management information corresponding to the first management information and held in the controller or in a part of the memory. A storage controller; a memory; a recording medium; a signal processing unit for operations including reading and writing to the recording medium; a driving hardware unit including a motor and a head; and a driving control unit for the driving hardware unit. The storage controller in a storage device mounted on or connected to an information processing device as a host,
The storage controller controls the memory, the signal processing means, and the drive control means for operations including reading and writing with respect to the recording medium, and is connected to a processor and a main storage device of the information processing apparatus through a predetermined interface. And
The information processing apparatus issues and transmits a first command including an address, a transfer size, and an attribute as information related to data to be recorded and transferred to the storage apparatus,
The storage controller interprets the first command from the information processing apparatus side, and processes the first transfer of the data at the address in the information processing apparatus to the write buffer secured in the memory. And when a certain amount of data corresponding to the transfer size is accumulated in the write buffer, the certain amount of data is stored in the recording medium via the control of the signal processing means and the drive control means. On the other hand, the storage controller is written by the second transfer, and in the second transfer, the operation state of the storage apparatus is set to the first state in which the drive hardware unit operates. Storage controller, memory, recording medium, signal processing means for operations including reading and writing to the recording medium, driving hardware unit including motor and head for the recording medium, and driving control for the driving hardware unit A storage controller in a storage device mounted on or connected to an information processing device serving as a host,
The storage controller controls the memory, the signal processing means, and the drive control means for operations including reading and writing with respect to the recording medium, and is connected to a processor and a main storage device of the information processing apparatus through a predetermined interface. And
The information processing apparatus sends, to the storage apparatus, a second command including an address, a transfer size, and an attribute as information relating to data to be recorded and transferred, and the data to be recorded and transferred to the first Sent by the transfer process,
The storage controller interprets the second command from the information processing apparatus side, receives the data to be recorded and transferred, accumulates it in a write buffer secured on the memory, and stores it in the write buffer. When a certain amount of data corresponding to the transfer size is accumulated, the certain amount of data is written to the recording medium by a second transfer through the control of the signal processing means and the drive control means. In the second transfer, the storage controller sets the operation state of the storage device to a first state in which the drive hardware unit operates. A storage controller; a memory; a recording medium; a signal processing unit for operations including reading and writing to the recording medium; a driving hardware unit including a motor and a head; and a driving control unit for the driving hardware unit. An information processing apparatus comprising a storage device and at least a processor and a main storage device,
The processor sends a first command including an address, a transfer size, and an attribute as information related to the data to be recorded and transferred to the storage device when transferring the data to the storage device for recording. Issue and send,
The storage controller interprets the first command from the processor side, accumulates the address data in a write buffer secured on the memory by a first transfer process, and stores the write buffer. When a certain amount of data corresponding to the transfer size is accumulated, the certain amount of data is written to the recording medium by a second transfer through the control of the signal processing means and the drive control means. In the second transfer, the information processing apparatus is characterized in that the operation state of the storage apparatus is set to a first state in which the drive hardware unit operates. Storage controller, memory, recording medium, signal processing means for operations including reading and writing to the recording medium, driving hardware unit including motor and head for the recording medium, and driving control for the driving hardware unit An information processing apparatus comprising: a storage device comprising: means; and at least a processor and a main storage device;
A second command including an address, a transfer size, and an attribute as information relating to the data to be recorded and transferred to the storage device when transferring the data for recording to the storage device; Sending the data to be recorded and transferred by the first transfer process,
The storage controller interprets the second command from the processor side, receives the data to be recorded and transferred, accumulates it in a write buffer secured on the memory, and transfers the data to the write buffer When a certain amount of data corresponding to the size is accumulated, the certain amount of data is written to the recording medium by a second transfer via the control of the signal processing means and the drive control means, In the second transfer, the information processing apparatus is characterized in that the operation state of the storage apparatus is set to a first state in which the drive hardware unit operates. The information processing apparatus according to claim 11 or 12,
A wireless transmission / reception unit that performs transmission / reception processing via radio is provided, and user data received or downloaded from outside through the processing of the wireless transmission / reception unit is temporarily stored in the main storage device, and recorded in the storage device using the command An information processing apparatus that performs processing. The information processing apparatus according to claim 11 or 12,
A process comprising: a broadcast receiving unit that receives a broadcast wirelessly; and storing user data received from outside through the process of the broadcast receiving unit in the main storage device while recording the user data in the storage device using the command. An information processing apparatus characterized by performing. The information processing apparatus according to claim 11 or 12,
A camera and a microphone are provided, and user data input by imaging and recording from outside through the camera and microphone is temporarily stored in the main storage device, and recorded in the storage device using the command. Information processing apparatus. The information processing apparatus according to claim 11 or 12,
When the storage controller receives an instruction to read data from the processor during the writing by the second transfer from the write buffer to the recording medium, the writing by the second transfer is interrupted and the reading has priority. And reading out data instructed to the processor from the recording medium. The information processing apparatus according to claim 16, wherein
In the storage controller, when the reading of the data instructed to the processor is completed, the interrupted writing by the second transfer is resumed, and when the resumed writing is completed, the operation state of the storage device is changed to the drive An information processing apparatus that is in a second state in which the hardware unit is not operated. A storage controller; a memory; a recording medium; a signal processing unit for operations including reading and writing to the recording medium; a driving hardware unit including a motor and a head; and a driving control unit for the driving hardware unit. An information processing apparatus comprising a storage device and at least a processor and a main storage device,
The storage device
It has an operating state where data can be read and written and an operating state where data cannot be read and written.
At the time of transfer for recording data on the recording medium, the write buffer that holds the data of the recording is secured in the memory, the data received by the transfer for recording of the data is held in the write buffer, When the transfer for recording the data is completed, the data is written from the write buffer to the recording medium,
Following the transfer for recording the data, upon receiving an instruction to read new data, the writing to the recording medium is interrupted, and the specified data is read from the recording medium to read the new data. Make a transfer for and
When reading from the recording medium is completed, the writing to the recording medium that was interrupted is resumed,
When the resumed writing is completed, the storage controller shifts the storage device to a state where the data cannot be read and written.

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