JP2008016729A - Manufacturing method for semiconductor device with double-sided electrode structure - Google Patents
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
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- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
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- Physics & Mathematics (AREA)
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Abstract
Description
本発明は、半導体チップを含む回路素子を配置して樹脂封止すると共に、該回路素子に接続される外部接続用電極をおもて面と裏面の両面に配置した両面電極構造の半導体装置及びその製造方法に関する。 The present invention relates to a semiconductor device having a double-sided electrode structure in which circuit elements including a semiconductor chip are arranged and resin-sealed, and external connection electrodes connected to the circuit elements are arranged on both the front surface and the back surface. It relates to the manufacturing method.
LＳＩチップの高集積化に伴い、パッケージサイズの縮小化も強く要求されており、様々な実装パッケージ構造が提案されている。近年、半導体ベアチップに貫通電極を形成して積層しようとする開発が盛んに行われている。一方、リアルサイズの両面電極パッケージもこれから製品化される可能性が高い。いずれの技術においても、従来の両面電極パッケージは常に貫通電極構造を必要としているが（特許文献１，特許文献２参照）、現在の貫通孔の絶縁方法は、高温で処理されるため半導体の実装プロセスへの適用は困難であった。このように、半導体基板への貫通孔の形成とその絶縁方法にはまだ課題が残されていて、貫通電極を必要とせずに配線することが望まれる。 Along with the high integration of LSI chips, there is a strong demand for reducing the package size, and various mounting package structures have been proposed. 2. Description of the Related Art In recent years, developments for forming and stacking through electrodes on a semiconductor bare chip have been actively conducted. On the other hand, real size double-sided electrode packages are also likely to be commercialized. In either technique, the conventional double-sided electrode package always requires a through-electrode structure (see Patent Document 1 and Patent Document 2). However, since current insulation methods for through-holes are processed at high temperatures, semiconductor mounting Application to the process was difficult. As described above, there is still a problem in the formation of the through hole in the semiconductor substrate and the insulating method thereof, and it is desired to perform wiring without requiring the through electrode.
特許文献３は、積層型半導体パッケージ用の多層基板において、その個別単層のパッケージを薄くする技術を開示する。このため、下部配線基板と上部配線基板に分けて別々に製作し、後で貼り合わせる。上部配線基板は上面への電極取出しと再配線を同時に兼ね備えているが、低コストで製造することは困難である。 Patent Document 3 discloses a technique for thinning an individual single layer package in a multilayer substrate for a stacked semiconductor package. For this reason, the lower wiring board and the upper wiring board are separately manufactured and bonded together later. The upper wiring board has both electrode extraction and rewiring at the same time, but it is difficult to manufacture at low cost.
また、特許文献４は、積層型半導体において、その個別単層のパッケージの突起電極を形成する技術を開示する。突起電極のパターン形成をフィルムで行い、開口部に半田ペーストを充填し、過熱することによって突起電極を形成する。工程的に、圧倒的に複雑でコスト高となる。
本発明は、係る問題点を解決して、貫通電極技術を必要とすること無く、簡潔にしかもコスト的にも安く両面電極パッケージを製造し、供給することを目的としている。これによって、有機基板タイプ両面電極パッケージ、リードフレームタイプ両面電極パッケージ、或いはテープ基板タイプ両面電極パッケージの製造を可能にして、従来の携帯電話への応用以外に各種センサー（音、磁気、圧力、等）用パッケージとしても有効となる。 An object of the present invention is to solve such problems and to manufacture and supply a double-sided electrode package simply and inexpensively without requiring a through electrode technology. This makes it possible to manufacture organic substrate type double-sided electrode packages, lead frame type double-sided electrode packages, or tape substrate type double-sided electrode packages, and various sensors (sound, magnetism, pressure, etc.) in addition to conventional mobile phone applications. ) Is also effective as a package.
本発明の両面電極構造の半導体装置及びその製造方法は、半導体チップを含む回路素子を配置して樹脂封止すると共に、該回路素子に接続される外部接続用電極をおもて面と裏面の両面に配置する。回路素子を有機基板上に配置して、該有機基板に設けた配線パターンと接続する。連結板により一体に構成した複数の内部接続用電極のそれぞれの一端を、配線パターン上の所定位置に接続する。回路素子を樹脂封止した後、連結板が無くなるまでおもて面側を研磨或いは研削して平坦化することにより個々の内部接続用電極に分離して構成する。複数の内部接続用電極のそれぞれの他端をおもて面における外部接続用電極として用いる。有機基板に設けたスルーホール内部の導体層を介して、裏面における外部接続用電極を配線パターンに接続する。 A semiconductor device having a double-sided electrode structure and a method for manufacturing the same according to the present invention include arranging a circuit element including a semiconductor chip and sealing with resin, and connecting external connection electrodes connected to the circuit element on the front and back surfaces. Place on both sides. A circuit element is disposed on an organic substrate and connected to a wiring pattern provided on the organic substrate. One end of each of the plurality of internal connection electrodes configured integrally with the connecting plate is connected to a predetermined position on the wiring pattern. After the circuit element is resin-sealed, the front surface side is polished or ground and flattened until the connecting plate disappears, thereby being separated into individual internal connection electrodes. The other end of each of the plurality of internal connection electrodes is used as an external connection electrode on the front surface. The external connection electrode on the back surface is connected to the wiring pattern through the conductor layer inside the through hole provided in the organic substrate.
また、本発明の両面電極構造の半導体装置及びその製造方法は、回路素子をリードフレーム上に配置して、該リードフレームのインナーリード部と接続する。連結板により一体に構成した複数の内部接続用電極のそれぞれの一端を、リードフレームの所定位置に接続する。回路素子を樹脂封止した後、連結板が無くなるまでおもて面側を研磨或いは研削して平坦化することにより個々の内部接続用電極に分離して構成する。複数の内部接続用電極のそれぞれの他端をおもて面における外部接続用電極として用いる。リードフレームに設けたアウターリード部を、裏面における外部接続用電極として用いる。 In the semiconductor device having a double-sided electrode structure and a manufacturing method thereof according to the present invention, the circuit element is arranged on the lead frame and connected to the inner lead portion of the lead frame. One end of each of the plurality of internal connection electrodes configured integrally with the connecting plate is connected to a predetermined position of the lead frame. After the circuit element is resin-sealed, the front surface side is polished or ground and flattened until the connecting plate disappears, thereby being separated into individual internal connection electrodes. The other end of each of the plurality of internal connection electrodes is used as an external connection electrode on the front surface. The outer lead portion provided on the lead frame is used as an external connection electrode on the back surface.
また、本発明の両面電極構造の半導体装置及びその製造方法は、回路素子を、後に剥離されるテープ基板上に配置し、連結板により一体に構成した複数の内部接続用電極のそれぞれの一端を、このテープ基板の所定位置に配置する。回路素子を樹脂封止した後、連結板が無くなるまでおもて面側を研磨或いは研削して平坦化することにより個々の内部接続用電極に分離して構成して、複数の内部接続用電極のそれぞれの他端をおもて面における外部接続用電極として用いる。テープ基板を剥離した後、この剥離により露出した面上において、回路素子及び内部接続用電極間の配線を行い、複数の内部接続用電極のそれぞれの一端を裏面における外部接続用電極として用いる。 Further, according to the semiconductor device having a double-sided electrode structure of the present invention and a manufacturing method thereof, the circuit element is arranged on a tape substrate to be peeled later, and one end of each of the plurality of internal connection electrodes formed integrally with the connecting plate is provided. The tape substrate is disposed at a predetermined position. After the circuit element is resin-sealed, the front side is polished or ground and flattened until the connecting plate disappears, and is separated into individual internal connection electrodes, and a plurality of internal connection electrodes The other end of each is used as an external connection electrode on the front surface. After the tape substrate is peeled off, wiring between the circuit elements and the internal connection electrodes is performed on the surface exposed by the peeling, and one end of each of the plurality of internal connection electrodes is used as an external connection electrode on the back surface.
本発明によれば、両面電極パッケージの内部接続型構造において、貫通電極技術を必要とすること無く、簡潔にしかもコスト的にも安く実現することが可能となる。これによって、電子機器の携帯電話等の小型実装分野、及び電子機器で3次元接続が有効なセンサー用パッケージとして有効となる。 According to the present invention, the internal connection type structure of the double-sided electrode package can be realized simply and inexpensively without requiring a through electrode technique. This makes it effective as a sensor package in which a three-dimensional connection is effective in a small packaging field such as a mobile phone of an electronic device and an electronic device.
また、本発明によれば、任意の数だけ基板上部及び下部の任意の箇所に配線を取り出して、基板上面を任意に再配線可能にし、上部接続ＩＣとの接続パターンに融通性を持たせることができる。 Further, according to the present invention, an arbitrary number of wirings can be taken out at arbitrary locations on the upper and lower sides of the substrate, the upper surface of the substrate can be arbitrarily rewired, and the connection pattern with the upper connection IC can be made flexible. Can do.
図１は、本発明の両面電極構造の半導体装置の第１の例を示す有機基板タイプの両面電極パッケージの断面図を示している。なお、図示したように、有機基板タイプの両面電極パッケージの有機基板側を裏面として、その上に配置される回路素子側をおもて面とする。ＬＳＩチップのような半導体チップは、多層有機基板上にダイボンド材により接着して、有機基板の最上層の配線パターンとはボンディングワイヤ（ワイヤボンド接続方式）により接続する。この有機基板の配線パターンには、本発明の特徴とする内部接続用電極が固定され、かつ電気的に接続される。内部接続用電極の接続の詳細は、図３〜図５を参照して後述する。有機基板の上面は、ＬＳＩチップ及びボンディングワイヤを覆うように樹脂封止され、この樹脂封止上面には、再配線を行うこともできる。内部接続用電極の配置から、例えばエリア配置に持っていくためにインクジェットあるいはスクリーン印刷で、若しくはシード層パターン形成後に無電解メッキすることによって再配線を行うことができる。 FIG. 1 is a cross-sectional view of an organic substrate type double-sided electrode package showing a first example of a semiconductor device having a double-sided electrode structure according to the present invention. As shown in the drawing, the organic substrate side of the organic substrate type double-sided electrode package is the back surface, and the circuit element side disposed thereon is the front surface. A semiconductor chip such as an LSI chip is bonded to a multilayer organic substrate with a die bonding material, and connected to a wiring pattern on the uppermost layer of the organic substrate by a bonding wire (wire bonding connection method). The internal connection electrode, which is a feature of the present invention, is fixed and electrically connected to the wiring pattern of the organic substrate. Details of the connection of the internal connection electrodes will be described later with reference to FIGS. The upper surface of the organic substrate is resin-sealed so as to cover the LSI chip and the bonding wire, and rewiring can be performed on the resin-sealed upper surface. Rewiring can be performed by ink-jet or screen printing, for example, to bring the internal connection electrodes into an area arrangement, or by electroless plating after forming the seed layer pattern.
次に、図１に示した両面電極構造の半導体装置（有機基板タイプの両面電極パッケージ）の製造工程を、図２〜図８を参照しつつ順を追って説明する。図２は、多層有機基板上にＬＳＩチップを接着しかつ接続した状態で示す図である。ＬＳＩチップは、多層有機基板上にダイボンド材により接着して、有機基板の最上層の配線パターンとはボンディングワイヤにより接続するものとして例示している。多層または単層有機基板の最上層の配線パターンに、ボンディングワイヤ接続電極となるボンディング用金属パッド部が形成されると共に、該パッド部への配線が形成される。この多層または単層有機基板のおもて面の金属パッド部と、ＬＳＩチップは、Ａｕボンディングワイヤにより接続される。１個のＬＳＩチップを例示したが、複数のチップを積層することも可能である。 Next, a manufacturing process of the semiconductor device having the double-sided electrode structure (organic substrate type double-sided electrode package) shown in FIG. 1 will be described in order with reference to FIGS. FIG. 2 is a diagram showing a state in which an LSI chip is bonded and connected to a multilayer organic substrate. The LSI chip is illustrated as being bonded to a multilayer organic substrate with a die bond material and connected to the uppermost wiring pattern of the organic substrate by a bonding wire. In the uppermost wiring pattern of the multilayer or single layer organic substrate, a bonding metal pad portion to be a bonding wire connection electrode is formed, and wiring to the pad portion is formed. The metal pad portion on the front surface of the multilayer or single layer organic substrate and the LSI chip are connected by an Au bonding wire. Although one LSI chip has been illustrated, a plurality of chips can be stacked.
或いは、ＬＳＩチップは、有機基板に対してフリップチップボンド接続することもできる（図示省略）。この場合、ＬＳＩチップは、多層または単層有機基板の最上層の配線パターンに、通常の技術を用いて、フリップチップボンド接続される。 Alternatively, the LSI chip can be flip-chip bonded to the organic substrate (not shown). In this case, the LSI chip is flip-chip bonded to the uppermost wiring pattern of the multilayer or single-layer organic substrate using a normal technique.
多層または単層有機基板は、単層２層配線構造や複数層から成る基板の各層に、それぞれ配線パターンを形成した後これらの基板を貼り合わせ、必要に応じて各層の配線パターンを接続するためのスルーホールを形成したものである。このスルーホールの内部には導体層が形成され、この導体層が裏面側に形成された端面電極部であるランドと接続されている。即ち、スルーホールの導体層は、必ずしもそのままランドにはならない。さらに、このランドには、ハンダ材料を付着させて、外部接続用のバンプを形成することができる。このような多層または単層有機基板は、例えば、「ハンダボール」と呼ばれる小さいハンダ材料を丸めたもの（バンプ）を裏面に実装した（BGA：Ball Grid Array）一括封止有機基板として知られている。 Multi-layer or single-layer organic substrates are used to form a wiring pattern on each layer of a single-layer / two-layer wiring structure or a substrate composed of a plurality of layers, and then bond these substrates together to connect the wiring patterns of each layer as necessary. Through-holes are formed. A conductor layer is formed inside the through hole, and the conductor layer is connected to a land which is an end face electrode portion formed on the back surface side. That is, the through hole conductor layer is not necessarily a land as it is. Further, a solder material can be attached to the land to form a bump for external connection. Such a multi-layer or single-layer organic substrate is known as a packaged organic substrate (BGA: Ball Grid Array) in which a small solder material called “solder ball” rolled (bump) is mounted on the back surface. Yes.
図３は、内部接続用電極構造を固定し、接続した状態で示す図である。有機基板の配線パターンの所定の位置には、本発明の特徴とする内部接続用電極が固定されかつ電気的に接続される。内部接続用電極構造を固定及び接続する手法としては、（１）超音波による接合、（２）銀ペースト等の導電性ペーストによる接続、（３）半田接続、（４）有機基板側に設けた接続電極用金属パッド部に凹部を設ける一方、内部接続用電極構造側は凸部を設けて挿入圧着あるいは挿入しカシメる方法、により行うことができる。 FIG. 3 is a diagram showing the internal connection electrode structure fixed and connected. An internal connection electrode, which is a feature of the present invention, is fixed and electrically connected to a predetermined position of the wiring pattern of the organic substrate. As a method for fixing and connecting the internal connection electrode structure, (1) ultrasonic bonding, (2) connection using a conductive paste such as silver paste, (3) solder connection, (4) provided on the organic substrate side. While the connection electrode metal pad portion is provided with a recess, the internal connection electrode structure side can be formed by a method of providing a protrusion and inserting / crimping or inserting and crimping.
内部接続用電極が有機基板の配線パターン上の所定の位置に配置した接続電極用金属パッド部（図２参照）に固定された段階では、全ての内部接続用電極が、連結板により一体に連結されている。 At the stage where the internal connection electrodes are fixed to the connection electrode metal pads (see FIG. 2) arranged at predetermined positions on the wiring pattern of the organic substrate, all the internal connection electrodes are connected together by the connection plate. Has been.
図４は、一体に連結されている内部接続用電極構造の詳細を示す図であり、図４（Ａ）及び（Ｂ）は１個の両面電極パッケージのための単体パターンの側面断面図及び斜視図をそれぞれ示し、また図４（Ｃ）は４個の両面電極パッケージのための４個の単体パターンを１個に連結したパターンの斜視図を示している。これら単体パターン或いは連結パターンは、複数の内部接続用電極を連結板により一体に連結して構成される。内部接続用電極は、例示したような円柱形状に限らず、矩形、多角形状等を含む柱状（棒状）形状であれば良い。パターン中央部は、例示したように中抜きにすることに限らず、ベタ板でも可能である。一体連結の内部接続用電極パターンの製造はエッチング、或いは削り出し、或いはプレスによって行うことができ、また、その材料としては銅を用いることができる。 FIG. 4 is a diagram showing details of the electrode structure for internal connection connected together, and FIGS. 4A and 4B are a side sectional view and a perspective view of a single pattern for one double-sided electrode package. FIG. 4C shows a perspective view of a pattern in which four single patterns for four double-sided electrode packages are connected to one. These single patterns or connection patterns are configured by integrally connecting a plurality of internal connection electrodes with a connection plate. The internal connection electrode is not limited to the cylindrical shape as illustrated, and may be a columnar (bar-shaped) shape including a rectangular shape, a polygonal shape, and the like. The center portion of the pattern is not limited to being hollowed out as illustrated, but may be a solid plate. The integrally connected electrode pattern for internal connection can be manufactured by etching, cutting, or pressing, and copper can be used as the material thereof.
図５は、樹脂封止した状態で示す図である。一体に連結されている内部接続用電極が固定された後、この状態で、有機基板の上面は、少なくとも連結板下面まで、望ましくは、製造上の表面平坦精度を考慮して連結板上面までトランスファーモールドされ、或いは液状樹脂（材質は、例えばエポキシ系）を用いて樹脂封止される。 FIG. 5 is a diagram showing the resin-sealed state. After the integrally connected internal connection electrodes are fixed, in this state, the upper surface of the organic substrate is transferred to at least the lower surface of the connection plate, preferably to the upper surface of the connection plate in consideration of surface flatness accuracy in manufacturing. Molded or resin-sealed using a liquid resin (material is, for example, an epoxy resin).
図６は、表面研磨又は研削後の状態で示す図である。表面研磨又は研削することにより、内部接続用電極が個々に分離されると共に、表面平坦化が行われる。この表面研磨又は研削は、少なくとも連結板が全て取り除かれるまで行われる。表面平坦化をして、内部接続用電極の上面を露出させた状態の上面図を、図７に示している。この段階の構成により、完成製品として使用可能である。 FIG. 6 is a diagram showing a state after surface polishing or grinding. By surface polishing or grinding, the internal connection electrodes are individually separated and the surface is flattened. This surface polishing or grinding is performed at least until all the connecting plates are removed. FIG. 7 shows a top view of the state where the surface is flattened and the upper surface of the internal connection electrode is exposed. With this stage configuration, it can be used as a finished product.
さらに、図１を参照して前述したように、この樹脂封止上面には再配線を行うこともできる。図６に示す内部接続用電極の配置のままを外部接続電極として利用してもよいが、内部接続用電極の配置から、例えばエリア配置に持っていくためにインクジェットあるいはスクリーン印刷で再配置をすることもできる。或いは、上面の再配線のために、シード層パターン形成後に無電解メッキすることによっても行うことができる。これら手法によって、内部接続用電極の頭部露出位置と異なったところに電極を配置することが可能となる。この再配線後の状態を示す上面図を、図８に示している。さらに、この再配線の上に、保護膜（材質は、例えばソルダーレジスト）を塗布した後、再配線上のバンプ形成部上の保護膜に開口を設け、またはインクジェットにより保護膜をバンプ部以外に選択的に塗布することによって、ここに、外部接続用のバンプ電極を形成することができる。製品として完成させるときは、チップ個片化のための切断が行われる。 Further, as described above with reference to FIG. 1, rewiring can be performed on the resin-encapsulated upper surface. The arrangement of the internal connection electrodes shown in FIG. 6 may be used as the external connection electrode, but rearrangement is performed by inkjet or screen printing in order to bring the internal connection electrodes from the arrangement to the area arrangement, for example. You can also Alternatively, it can be performed by electroless plating after the seed layer pattern is formed for rewiring on the upper surface. By these methods, it is possible to dispose the electrode at a position different from the head exposed position of the internal connection electrode. A top view showing the state after the rewiring is shown in FIG. Furthermore, after applying a protective film (for example, a solder resist) on the rewiring, an opening is formed in the protective film on the bump forming portion on the rewiring, or the protective film is applied to other than the bump portion by inkjet. By selectively applying, a bump electrode for external connection can be formed here. When completed as a product, cutting for chip separation is performed.
次に、図９〜図１２を参照して、本発明の両面電極構造の半導体装置の第２の例を示すリードフレームタイプの両面電極パッケージについて説明する。図９は、リードフレーム上にＬＳＩチップを接着しかつ接続した状態で示す図である。なお、図示したように、リードフレームタイプの両面電極パッケージのリードフレーム側を裏面として、その上に配置される回路素子側をおもて面とする。図示したように、ＬＳＩチップは、リードフレームのダイパッド上にＡｇペースト等によるダイボンド材により接着されている（チップダイボンド）。１個のＬＳＩチップを例示したが、複数のチップを積層することも可能である。リードフレームのインナーリード部と、ＬＳＩチップは、Ａｕボンディングワイヤにより接続される（ワイヤボンド）。このリードフレームを周囲の回路と電気的に接続するためのアウターリード部は、その先端断面が、例示したようなリードフレーム裏面だけでなく、側面にも露出させることができる。リードフレームは、例えば、ＰｄメッキしたＣｕ合金のような金属板から、プレス加工により、多数個同時に形成され、その後の工程で、この多数個同時に形成されたリードフレームが、各個片に切断されることになる。図示のリードフレームは各個片に切断された状態で示され、それ故に、リードフレーム自体も個々に分離されて図示されているが、この製造段階にあるリードフレームは、実際には未だ一体に連結されている。 Next, a lead frame type double-sided electrode package showing a second example of the semiconductor device having a double-sided electrode structure of the present invention will be described with reference to FIGS. FIG. 9 is a diagram showing an LSI chip bonded and connected on a lead frame. As shown in the drawing, the lead frame side of the lead frame type double-sided electrode package is the back surface, and the circuit element side disposed thereon is the front surface. As shown in the figure, the LSI chip is bonded onto the die pad of the lead frame with a die bonding material such as Ag paste (chip die bonding). Although one LSI chip has been illustrated, a plurality of chips can be stacked. The inner lead portion of the lead frame and the LSI chip are connected by Au bonding wires (wire bonding). The outer lead portion for electrically connecting the lead frame to the surrounding circuit can be exposed not only on the back surface of the lead frame as illustrated, but also on the side surface. For example, a large number of lead frames are formed simultaneously from a metal plate such as a Pd-plated Cu alloy by pressing, and in the subsequent process, the multiple lead frames formed simultaneously are cut into individual pieces. It will be. The lead frame shown is shown cut into individual pieces, and therefore the lead frame itself is also shown separately, but the lead frame in this manufacturing stage is actually still connected together. Has been.
図１０は、内部接続用電極構造を固定し、接続した状態で示す図である。リードフレームの所定の位置には、本発明の特徴とする内部接続用電極が固定され、かつ電気的に接続される。内部接続用電極構造を固定及び接続する手法としては、上述した第１の例と同じく、（１）超音波による接合、（２）銀ペースト等の導電性ペーストによる接続、（３）半田接続、（４）リードフレーム側に凹部を設け、電極構造側は凸部を設けて挿入圧着あるいは挿入しカシメる方法、により行うことができる。内部接続用電極がリードフレームの所定の位置に固定された段階では、全ての内部接続用電極が、連結板により一体に連結されている。内部接続用電極構造は、図４を参照して前述したような構造及び材質のものを用いることができる。 FIG. 10 is a diagram showing a state in which the internal connection electrode structure is fixed and connected. The electrode for internal connection, which is a feature of the present invention, is fixed and electrically connected to a predetermined position of the lead frame. As a method for fixing and connecting the electrode structure for internal connection, as in the first example described above, (1) ultrasonic bonding, (2) connection using a conductive paste such as silver paste, (3) solder connection, (4) A concave portion is provided on the lead frame side, and a convex portion is provided on the electrode structure side, and insertion crimping or insertion and crimping can be performed. At the stage where the internal connection electrodes are fixed at predetermined positions of the lead frame, all the internal connection electrodes are integrally connected by the connection plate. As the internal connection electrode structure, the structure and material described above with reference to FIG. 4 can be used.
図１１は、樹脂封止した状態で示す図である。一体に連結されている内部接続用電極が接着された後、この状態で、有機基板の上面は、少なくとも連結板下面まで、望ましくは連結板上面までトランスファーモールドされ、或いは液状樹脂を用いて樹脂封止される。 FIG. 11 is a view showing a resin-sealed state. After the integrally connected internal connection electrodes are bonded, in this state, the upper surface of the organic substrate is transfer-molded to at least the lower surface of the connecting plate, preferably the upper surface of the connecting plate, or sealed with a liquid resin. Stopped.
図１２は、表面研磨又は研削後の状態を示す図である。表面研磨又は研削することにより、内部接続用電極が個々に分離されると共に、表面平坦化が行われる。この表面研磨又は研削は、少なくとも連結板が全て取り除かれるまで行われる。 FIG. 12 is a diagram showing a state after surface polishing or grinding. By surface polishing or grinding, the internal connection electrodes are individually separated and the surface is flattened. This surface polishing or grinding is performed at least until all the connecting plates are removed.
この後、チップ個片化のための切断が行われて、製品として完成するが、さらに、上述した例と同じ手法を用いて、この樹脂封止上面に再配線を行うこともできる。 Thereafter, cutting for chip separation is performed to complete the product, but rewiring can also be performed on the resin-encapsulated upper surface using the same technique as in the above-described example.
次に、図１３〜図１８を参照して、本発明の両面電極構造の半導体装置の第３の例を示すテープ基板タイプの両面電極パッケージについて説明する。まず、図１３に示すように、テープ基板上の所定位置に、半導体チップ（ＩＣチップ）、抵抗Ｒ、及びコンデンサＣのような回路素子を、絶縁性があり、剥離性のよい粘着材を用いて接着配置する。この状態で、各回路素子間の電気的な接続は行われていない。テープ基板は、ポリイミドテープなどに代表される薄膜フィルムの絶縁基材により作成することができる。なお、図示したように、テープ基板タイプの両面電極パッケージのテープ基板側を裏面として、その上に配置される回路素子側をおもて面とする。 Next, a tape substrate type double-sided electrode package showing a third example of the semiconductor device having the double-sided electrode structure of the present invention will be described with reference to FIGS. First, as shown in FIG. 13, circuit elements such as a semiconductor chip (IC chip), a resistor R, and a capacitor C are used at predetermined positions on the tape substrate, using an adhesive material having insulating properties and good peelability. And place them together. In this state, no electrical connection is made between the circuit elements. The tape substrate can be made of an insulating base material of a thin film represented by a polyimide tape or the like. As shown in the figure, the tape substrate side of the double-sided electrode package of the tape substrate type is the back surface, and the circuit element side disposed thereon is the front surface.
図１４は、内部接続用電極構造を接着した状態で示す図である。内部接続用電極がテープ基板上の所定の位置に接着された段階では、全ての内部接続用電極が、連結板により一体に連結されている。この内部接続用電極も未だ、回路素子との電気的接続はなされていない。一体連結の内部接続用電極は、図４を参照して前述したような材質及び構成のものを用いることができる。 FIG. 14 is a diagram showing the state where the internal connection electrode structure is adhered. At the stage where the internal connection electrodes are bonded to predetermined positions on the tape substrate, all the internal connection electrodes are integrally connected by the connection plate. The internal connection electrodes are not yet electrically connected to the circuit elements. The integrally connected internal connection electrodes may be made of the materials and structures described above with reference to FIG.
図１５は、樹脂封止した状態で示す図である。一体に連結されている内部接続用電極が接着された後、この状態で、テープ基板の上面は、各回路素子を覆うように少なくとも連結板下面まで、望ましくは連結板上面までトランスファーモールドされ、或いは液状樹脂を用いて樹脂封止される。 FIG. 15 is a diagram showing the resin-sealed state. After the internal connection electrodes which are integrally connected are bonded, in this state, the upper surface of the tape substrate is transfer-molded to at least the lower surface of the connection plate, preferably to the upper surface of the connection plate so as to cover each circuit element, or Resin sealing is performed using a liquid resin.
図１６は、表面研磨又は研削後の状態で示す図である。表面研磨又は研削することにより、内部接続用電極が個々に分離されると共に、表面平坦化が行われる。この表面研磨又は研削は、少なくとも連結板が全て取り除かれるまで行われる。 FIG. 16 is a diagram showing a state after surface polishing or grinding. By surface polishing or grinding, the internal connection electrodes are individually separated and the surface is flattened. This surface polishing or grinding is performed at least until all the connecting plates are removed.
図１７は、テープ基板を剥離した状態で示す図である。図示したように、パッケージ全体を上下反転させた後、テープ基板を剥離する。なお、回路素子を接着した接着剤（粘着剤）は、テープ基板剥離時にはテープ基板側に付くような材質が望ましい。 FIG. 17 is a view showing a state where the tape substrate is peeled off. As shown in the figure, after the entire package is turned upside down, the tape substrate is peeled off. The adhesive (adhesive) to which the circuit elements are bonded is preferably a material that adheres to the tape substrate side when the tape substrate is peeled off.
図１８は、最終的に完成した両面電極パッケージを示す断面図である。テープ基板を剥離した後、剥離後の面上で、既に配置済みのＩＣチップ、抵抗Ｒ、コンデンサＣのような回路素子、及び内部接続用電極の間で所望の配線（表面再配線）を行う。この配線は、インクジェットあるいはスクリーン印刷によって、或いはシード層パターン形成後に無電解メッキすることによって行うことができる。この再配線の上に、保護膜を塗布した後、再配線上のバンプ形成部上の保護膜に開口を設け、またはインクジェットにより保護膜をバンプ部以外に選択的に塗布することによって、ここに、外部接続用のバンプ電極を形成することができる。さらに、他の回路部品（図中には、抵抗Ｒ及び他の半導体パッケージを例示）を保護膜上に配置して、それらの配線を行うこともできる。最後に、チップ個片化のための切断が行われて、製品として完成する。 FIG. 18 is a cross-sectional view showing the finally completed double-sided electrode package. After the tape substrate is peeled off, desired wiring (surface rewiring) is performed between the already disposed IC chip, the circuit element such as the resistor R and the capacitor C, and the internal connection electrode on the peeled surface. . This wiring can be performed by ink jet or screen printing, or by electroless plating after the seed layer pattern is formed. After applying a protective film on the rewiring, an opening is formed in the protective film on the bump forming portion on the rewiring, or the protective film is selectively applied to the portion other than the bump portion by inkjet. A bump electrode for external connection can be formed. Furthermore, other circuit components (in the figure, resistor R and other semiconductor packages are illustrated) can be arranged on the protective film, and their wiring can be performed. Finally, cutting for chip separation is performed to complete the product.
本発明は、半導体チップを含む回路素子を配置して樹脂封止すると共に、該回路素子に接続される外部接続用電極をおもて面と裏面の両面に配置した両面電極構造の半導体装置の製造方法に関する。
The invention, together with a resin sealing by placing a circuit element including a semiconductor chip, a semiconductor equipment double-sided electrode structure in which external connection electrodes connected to the circuit elements disposed on both sides of the front surface and the back surface It relates to the manufacturing method.
本発明の両面電極構造の半導体装置の製造方法は、半導体チップを含む回路素子を配置して樹脂封止すると共に、該回路素子に接続される外部接続用電極をおもて面と裏面の両面に配置する。回路素子を有機基板上に配置して、該有機基板に設けた配線パターンと接続する。連結板により一体に構成した複数の柱状或いは棒状に形成した内部接続用電極のそれぞれの一端を、配線パターン上の所定位置に接続する。回路素子を樹脂封止した後、有機基板側を裏面としてその上に配置される回路素子側のおもて面を、前記連結板が無くなるまで研磨或いは研削して平坦化することにより個々の内部接続用電極に分離して構成する。複数の内部接続用電極のそれぞれの他端をおもて面における外部接続用電極として用いる。有機基板に設けたスルーホール内部の導体層を介して、裏面における外部接続用電極を配線パターンに接続する。 Semiconductor equipment manufacturing method of the double-sided electrode structure of the present invention is to resin sealing by placing a circuit element including a semiconductor chip, the external connection electrodes connected to the circuit element front surface and the back surface of the Place on both sides. A circuit element is disposed on an organic substrate and connected to a wiring pattern provided on the organic substrate. One end of each of the internal connection electrodes formed in a columnar shape or a bar shape integrally formed by the connecting plate is connected to a predetermined position on the wiring pattern. After the circuit element is resin-sealed, the inner surface of each circuit element is disposed by polishing or grinding the front surface of the circuit element disposed on the organic substrate side as a back surface until the connecting plate is removed. Separated into connection electrodes. The other end of each of the plurality of internal connection electrodes is used as an external connection electrode on the front surface. The external connection electrode on the back surface is connected to the wiring pattern through the conductor layer inside the through hole provided in the organic substrate.
また、本発明の両面電極構造の半導体装置の製造方法は、回路素子をリードフレーム上に配置して、該リードフレームのインナーリード部と接続する。連結板により一体に構成した複数の柱状或いは棒状に形成した内部接続用電極のそれぞれの一端を、リードフレームの所定位置に接続する。回路素子を樹脂封止した後、リードフレーム側を裏面としてその上に配置される回路素子側のおもて面を、前記連結板が無くなるまで研磨或いは研削して平坦化することにより個々の内部接続用電極に分離して構成する。複数の内部接続用電極のそれぞれの他端をおもて面における外部接続用電極として用いる。リードフレームに設けたアウターリード部を、裏面における外部接続用電極として用いる。 The semiconductor equipment manufacturing method of the double-sided electrode structure of the present invention, by arranging the circuit elements on a lead frame and is connected to the inner lead portion of the lead frame. One end of each of the internal connection electrodes formed in a columnar shape or a rod shape integrally formed by the connecting plate is connected to a predetermined position of the lead frame. After sealing the circuit element with resin, the inner surface of each circuit element is flattened by polishing or grinding the front surface of the circuit element disposed on the lead frame side as the back surface until the connecting plate is removed. Separated into connection electrodes. The other end of each of the plurality of internal connection electrodes is used as an external connection electrode on the front surface. The outer lead portion provided on the lead frame is used as an external connection electrode on the back surface.
また、本発明の両面電極構造の半導体装置の製造方法は、回路素子を、後に剥離されるテープ基板上に配置し、連結板により一体に構成した複数の柱状或いは棒状に形成した内部接続用電極のそれぞれの一端を、このテープ基板の所定位置に配置する。回路素子を樹脂封止した後、テープ基板側を裏面としてその上に配置される回路素子側のおもて面を、前記連結板が無くなるまで研磨或いは研削して平坦化することにより個々の内部接続用電極に分離して構成して、複数の内部接続用電極のそれぞれの他端をおもて面における外部接続用電極として用いる。テープ基板を剥離した後、この剥離により露出した面上において、回路素子及び内部接続用電極間の配線を行い、複数の内部接続用電極のそれぞれの一端を裏面における外部接続用電極として用いる。 The semiconductor equipment manufacturing method of the double-sided electrode structure of the present invention, the internal connecting the circuit elements, arranged on the tape substrate to be peeled off after, and formed into a plurality of columnar or rod which is integrally formed by a connecting plate One end of each electrode is disposed at a predetermined position on the tape substrate. After the circuit element is resin-sealed, the inner surface of each circuit element is flattened by polishing or grinding the front surface of the circuit element disposed on the tape substrate side as the back surface until the connecting plate is removed. The connection electrodes are separated from each other, and the other ends of the plurality of internal connection electrodes are used as external connection electrodes on the front surface. After the tape substrate is peeled off, wiring between the circuit elements and the internal connection electrodes is performed on the surface exposed by the peeling, and one end of each of the plurality of internal connection electrodes is used as an external connection electrode on the back surface.
Claims (16)
前記回路素子を有機基板上に配置すると共に該有機基板に設けた配線パターンと接続し、
該配線パターンに接続される各一端を有する複数の内部接続用電極を備え、該複数の内部接続用電極のそれぞれの他端をおもて面における前記外部接続用電極として用い、
前記複数の内部接続用電極は連結板により一体に構成して前記配線パターン上に接続し、前記有機基板の上面を樹脂封止した後、前記連結板を研磨或いは研削することにより個々の内部接続用電極に分離して構成し、
前記有機基板に設けたスルーホール内部の導体層を介して、裏面における前記外部接続用電極を前記配線パターンに接続した、
ことから成る両面電極構造の半導体装置。 In a semiconductor device having a double-sided electrode structure in which circuit elements including a semiconductor chip are arranged and sealed with resin, and external connection electrodes connected to the circuit elements are arranged on both the front surface and the back surface,
The circuit element is disposed on an organic substrate and connected to a wiring pattern provided on the organic substrate,
A plurality of internal connection electrodes each having one end connected to the wiring pattern, and the other end of each of the plurality of internal connection electrodes is used as the external connection electrode on the front surface;
The plurality of internal connection electrodes are integrally formed by a connecting plate and connected to the wiring pattern, and the upper surface of the organic substrate is sealed with resin, and then the connecting plate is polished or ground to provide individual internal connections. Separated into electrodes,
Through the conductor layer inside the through hole provided in the organic substrate, the external connection electrode on the back surface was connected to the wiring pattern,
A semiconductor device having a double-sided electrode structure.
前記回路素子をリードフレーム上に配置すると共に該リードフレームのインナーリード部と接続し、
該リードフレームの所定位置に接続される各一端を有する複数の内部接続用電極を備え、該複数の内部接続用電極のそれぞれの他端をおもて面における前記外部接続用電極として用い、
前記複数の内部接続用電極は連結板により一体に構成して前記リードフレームの所定位置に接続し、リードフレームの上面を樹脂封止した後、前記連結板を研磨或いは研削することにより個々の内部接続用電極に分離して構成し、
前記リードフレームに設けたアウターリード部を、裏面における前記外部接続用電極として用いる、
ことから成る両面電極構造の半導体装置。 In a semiconductor device having a double-sided electrode structure in which circuit elements including a semiconductor chip are arranged and sealed with resin, and external connection electrodes connected to the circuit elements are arranged on both the front surface and the back surface,
The circuit element is disposed on the lead frame and connected to the inner lead portion of the lead frame,
A plurality of internal connection electrodes each having one end connected to a predetermined position of the lead frame, and the other end of each of the plurality of internal connection electrodes is used as the external connection electrode on the front surface;
The plurality of internal connection electrodes are integrally formed by a connecting plate and connected to a predetermined position of the lead frame, and after sealing the upper surface of the lead frame with a resin, the connecting plate is polished or ground to provide individual internal electrodes. Separated into connection electrodes,
The outer lead portion provided on the lead frame is used as the external connection electrode on the back surface.
A semiconductor device having a double-sided electrode structure.
前記回路素子を、後に剥離されるテープ基板上に配置し、
前記テープ基板上に配置される各一端を有する複数の内部接続用電極を備え、該複数の内部接続用電極のそれぞれの他端をおもて面における前記外部接続用電極として用い、
前記複数の内部接続用電極は連結板により一体に構成して前記テープ基板の所定の位置上に配置し、該テープ基板の上面を樹脂封止した後、前記連結板を研磨或いは研削することにより個々の内部接続用電極に分離して構成し、
前記テープ基板を剥離した後、この剥離により露出した面上において、前記回路素子及び前記内部接続用電極間の配線を行うと共に、前記複数の内部接続用電極のそれぞれの前記一端を、裏面における前記外部接続用電極として用いる、
ことから成る両面電極構造の半導体装置。 In a semiconductor device having a double-sided electrode structure in which circuit elements including a semiconductor chip are arranged and sealed with resin, and external connection electrodes connected to the circuit elements are arranged on both the front surface and the back surface,
The circuit element is disposed on a tape substrate to be peeled later,
A plurality of internal connection electrodes each having one end disposed on the tape substrate, and the other end of each of the plurality of internal connection electrodes is used as the external connection electrode on the front surface;
The plurality of internal connection electrodes are integrally formed by a connecting plate and disposed on a predetermined position of the tape substrate, and after sealing the upper surface of the tape substrate with resin, the connecting plate is polished or ground. Separated into individual internal connection electrodes,
After peeling off the tape substrate, wiring between the circuit element and the internal connection electrode is performed on the surface exposed by the peeling, and each one end of the plurality of internal connection electrodes is connected to the back surface on the back surface. Used as an external connection electrode,
A semiconductor device having a double-sided electrode structure.
前記回路素子を有機基板上に配置して、該有機基板に設けた配線パターンと接続し、
連結板により一体に構成した複数の内部接続用電極のそれぞれの一端を、前記配線パターン上の所定位置に接続し、
前記回路素子を樹脂封止した後、前記連結板が無くなるまでおもて面側を研磨或いは研削して平坦化することにより個々の内部接続用電極に分離して構成し、
前記複数の内部接続用電極のそれぞれの他端をおもて面における前記外部接続用電極として用い、
前記有機基板に設けたスルーホール内部の導体層を介して、裏面における前記外部接続用電極を前記配線パターンに接続した、
ことから成る両面電極構造の半導体装置の製造方法。 In the method of manufacturing a semiconductor device having a double-sided electrode structure in which circuit elements including a semiconductor chip are arranged and resin-sealed, and external connection electrodes connected to the circuit elements are arranged on both the front surface and the back surface,
The circuit element is disposed on an organic substrate and connected to a wiring pattern provided on the organic substrate.
One end of each of the plurality of internal connection electrodes configured integrally with the connecting plate is connected to a predetermined position on the wiring pattern,
After sealing the circuit element with resin, the front side is polished or ground until the connection plate disappears, and is configured to be separated into individual internal connection electrodes,
Using the other end of each of the plurality of internal connection electrodes as the external connection electrode on the front surface,
Through the conductor layer inside the through hole provided in the organic substrate, the external connection electrode on the back surface was connected to the wiring pattern,
A method of manufacturing a semiconductor device having a double-sided electrode structure.
前記回路素子をリードフレーム上に配置して、該リードフレームのインナーリード部と接続し、
連結板により一体に構成した複数の内部接続用電極のそれぞれの一端を、前記リードフレームの所定位置に接続し、
前記回路素子を樹脂封止した後、前記連結板が無くなるまでおもて面側を研磨或いは研削して平坦化することにより個々の内部接続用電極に分離して構成し、
前記複数の内部接続用電極のそれぞれの他端をおもて面における前記外部接続用電極として用い、
前記リードフレームに設けたアウターリード部を、裏面における前記外部接続用電極として用いる、
ことから成る両面電極構造の半導体装置の製造方法。 In the method of manufacturing a semiconductor device having a double-sided electrode structure in which circuit elements including a semiconductor chip are arranged and resin-sealed, and external connection electrodes connected to the circuit elements are arranged on both the front surface and the back surface,
The circuit element is disposed on a lead frame and connected to an inner lead portion of the lead frame,
One end of each of the plurality of internal connection electrodes configured integrally with the connecting plate is connected to a predetermined position of the lead frame,
After sealing the circuit element with resin, the front side is polished or ground until the connection plate disappears, and is configured to be separated into individual internal connection electrodes,
Using the other end of each of the plurality of internal connection electrodes as the external connection electrode on the front surface,
The outer lead portion provided on the lead frame is used as the external connection electrode on the back surface.
A method of manufacturing a semiconductor device having a double-sided electrode structure.
前記回路素子を、後に剥離されるテープ基板上に配置し、
連結板により一体に構成した複数の内部接続用電極のそれぞれの一端を、前記テープ基板の所定位置に配置し、
前記回路素子を樹脂封止した後、前記連結板が無くなるまでおもて面側を研磨或いは研削して平坦化することにより個々の内部接続用電極に分離して構成して、前記複数の内部接続用電極のそれぞれの他端をおもて面における前記外部接続用電極として用い、
前記テープ基板を剥離した後、この剥離により露出した面上において、前記回路素子及び前記内部接続用電極間の配線を行い、前記複数の内部接続用電極の前記それぞれの一端を裏面における前記外部接続用電極として用いる
ことから成る両面電極構造の半導体装置の製造方法。
In the method of manufacturing a semiconductor device having a double-sided electrode structure in which circuit elements including a semiconductor chip are arranged and resin-sealed, and external connection electrodes connected to the circuit elements are arranged on both the front surface and the back surface,
The circuit element is disposed on a tape substrate to be peeled later,
One end of each of the plurality of internal connection electrodes configured integrally with the connecting plate is disposed at a predetermined position of the tape substrate,
After the circuit element is resin-sealed, the front side is polished or ground and flattened until the connecting plate is eliminated, and separated into individual internal connection electrodes. Using the other end of each of the connection electrodes as the external connection electrode on the front surface,
After peeling off the tape substrate, wiring between the circuit element and the internal connection electrode is performed on the surface exposed by the peeling, and each one end of the plurality of internal connection electrodes is connected to the external connection on the back surface. A method for manufacturing a semiconductor device having a double-sided electrode structure comprising use as a working electrode.
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