JP2007335717A - Non-volatile memory and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a non-volatile memory that can be manufactured by a standard CMOS process. <P>SOLUTION: The non-volatile memory has a memory cell comprising a transistor and a capacitor in a MOS structure. The first transistor is composed of a source and a drain formed on the main surface of a semiconductor substrate, and a floating gate formed on the main surface between the source and the drain via an insulation film. The capacitor is composed of a first electrode comprising an impurity region formed as a control gate of the transistor on the main surface of the semiconductor substrate, and a second electrode formed integrally with the floating gate on the impurity region via an insulation film. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile memory and a manufacturing method thereof, and more particularly to a technique for realizing a nonvolatile memory by a standard CMOS process.

  Nonvolatile memories represented by EEPROM (Electrically Erasable Programmable Read Only Memory) are used for many purposes because stored data does not disappear even when the power is turned off. For example, a typical application of an EEPROM is an IC card. Also, because of the convenience of rewriting at any time according to the application, EEPROM or flash memory is used as a replacement for the mask ROM in the microcomputer. Further, in recent years, there has been a growing demand for a so-called embedded embedded memory in which a nonvolatile memory is incorporated in a part of a system LSI or logic IC.

  However, in general, the nonvolatile memory has a cell structure using two-layer polysilicon or three-layer polysilicon, and the manufacturing process is more than a standard CMOS process (one-layer polysilicon process) used for manufacturing a logic IC. Complex and many processes. For this reason, when the nonvolatile memory and the standard logic are simultaneously embedded in one chip, there are problems that the manufacturing process increases, the yield decreases, and the price (cost) of the product increases.

As a conventional technique for solving such a problem, an EEPROM using a single-layer polysilicon has been proposed (see Patent Document 1). According to the EEPROM using the one-layer polysilicon process, the number of manufacturing steps can be reduced as compared with the case of using the two-layer polysilicon process.
JP-A-10-289959

  However, according to the above-described EEPROM using the single-layer polysilicon, the second-layer polysilicon used as the control gate is omitted, so that the semiconductor substrate under the floating gate is made of a diffusion layer. There is a problem that it is necessary to embed a control gate, and a more complicated manufacturing process is required than a standard CMOS process used for manufacturing a logic IC. Furthermore, since the quality of the oxide film produced by oxidizing the diffusion layer embedded at a high concentration is lowered, there is a problem that the probability of occurrence of a defect is increased and the reliability is also lowered.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a nonvolatile memory that can be manufactured by a standard CMOS process used for manufacturing logic ICs.

The present invention has been made to solve the above problems, and a nonvolatile memory according to the present invention is a nonvolatile memory including a memory cell including a transistor having a MOS structure and a capacitor, and the transistor includes: A source and drain formed on a main surface of a semiconductor substrate; and a floating gate formed on the main surface between the source and drain via an insulating film, and the capacitor is formed on the semiconductor substrate. A first electrode comprising an impurity region formed as a control gate of the transistor on a main surface of the transistor, and a second electrode formed integrally with the floating gate on the impurity region via an insulating film. The

  In the nonvolatile memory, the transistor and the capacitor are formed using a standard CMOS process.

  In the above nonvolatile memory, a memory array in which the memory cells are arranged in a matrix, a plurality of bit lines formed along each column of the memory array and connected to the drains of the transistors, and the memory array And a plurality of control lines formed along each column of the memory array and connected to the first electrode as the control gate. And the impurity region constituting the first electrode is integrally formed between adjacent memory cells in the same row.

  In the non-volatile memory, the memory cell is supplied with a predetermined first positive voltage to the control gate line, a predetermined second positive voltage to the bit line, and a ground to the source line during writing. A voltage is applied, a ground voltage is applied to the control gate line during erasing, a predetermined third positive voltage is applied to the bit line, the source line is opened, and the control gate line is read during reading. A predetermined fourth positive voltage is applied to the bit line, a predetermined fifth positive voltage is applied to the bit line, and a ground voltage is applied to the source line.

  In the nonvolatile memory, the source of the transistor is integrally formed between adjacent memory cells in the same row.

  In the above nonvolatile memory, the source and drain of the transistor are integrally formed between memory cells belonging to adjacent rows.

  In the non-volatile memory, the second electrode is formed such that a corner portion thereof is positioned on a field oxide film for element isolation.

  In the nonvolatile memory, the capacitor is formed of a MOS capacitor.

  The non-volatile memory manufacturing method includes a step of forming the impurity region serving as the first electrode of the capacitor in a predetermined region of the semiconductor substrate, a step of forming a field oxide film for element isolation, Forming a gate oxide film and an oxide film serving as an insulating layer of the capacitor; forming a floating gate of the transistor and a second electrode of the capacitor; forming a source and drain of the transistor; and interlayer insulation Forming a film; forming a contact hole in the interlayer insulating film that leads to the impurity region and the source and drain; and forming a metal wiring.

  In the method for manufacturing a nonvolatile memory, an impurity having the same conductivity type as that of the impurity region is further implanted after the impurity region is formed.

  According to the present invention, it is possible to manufacture a nonvolatile memory by a standard CMOS process used for logic IC manufacturing. Therefore, a logic embedded memory having high reliability can be realized easily and inexpensively.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1A is a plan view of an EEPROM cell which is a memory cell of a nonvolatile memory according to the present invention. 1B is an equivalent circuit diagram of the present EEPROM cell, FIG. 1C is a cross-sectional view taken along the line AA ′ of FIG. 1A, and FIG. It is sectional drawing along BB 'of).

  As shown in the equivalent circuit diagram of FIG. 1B, the present EEPROM cell is composed of a transistor Tr and a capacitor Cp on an electric circuit. The transistor Tr includes a source S, a drain D, and a gate, and the capacitor Cp includes a pair of electrodes that are opposed to each other via an insulator (dielectric). Here, one electrode of the capacitor Cp is connected to the gate of the transistor Tr, and one electrode of the capacitor Cp and the gate of the transistor Tr function as the floating gate FG of the present EEPROM cell. The other electrode of the capacitor Cp functions as a control gate CG of the EEPROM cell.

1A, 1C, and 1D show the device structure of the present EEPROM cell.
In the figure, 1 is an n-type well (impurity region, hereinafter referred to as n-well) which is an n-type semiconductor region formed in a p-type semiconductor substrate 0, and 2 is an n + formed in n-well 1 Diffusion layer, 3 is a polysilicon gate serving as the floating gate FG, 4 is an n + diffusion layer serving as the drain D of the transistor Tr, 5 is an n + diffusion layer serving as the source S of the transistor Tr, and 6 is a transistor Tr. , 7 is a contact for connecting the metal wirings 8 and 9 and the n + diffusion layers 4 and 5, 8 is a metal wiring connected to the drain D, 9 is a metal wiring connected to the source S, 10 Is a capacitor part to be a capacitor Cp, 11 is a metal wiring to be the control gate CG, 12 is a contact for connecting the n + diffusion layer 2 and the metal wiring 11, and 13 is an element. An isolation field oxide film 14 represents a thin oxide film (gate oxide film) which becomes a gate oxide film of the transistor Tr and an insulating layer of the capacitor Cp. The gate portion 6 indicates a portion of the polysilicon gate 3 that functions as the gate of the transistor Tr.

  Here, the polysilicon gate 3 (gate portion 6), n + diffusion layer 4, n + diffusion layer 5, contact 7, metal wiring 8, metal wiring 9, and thin oxide film 14 form an n-type MOS. A transistor Tr having a structure is configured, and this structure is the same as the MOS transistor structure of the logic IC.

Further, the capacitor Cp is configured with the polysilicon gate 3 as the upper electrode and the n-well 1 as the lower electrode across the thin oxide film 14. Using the n + diffusion layer 2 formed in the n-well 1 that is the lower electrode of the capacitor Cp and the contact 12, the n-well 1 is connected to the metal wiring 11 to form the control gate CG. That is, n-well 1 becomes the control gate CG of the transistor Tr.
Note that there is no diffusion layer immediately below the polysilicon gate 3 that becomes the upper electrode of the capacitor Cp. This is the same as the fact that there is no diffusion layer directly under the gate of a well-known MOS structure transistor. That is, in this embodiment, the capacitor Cp is realized by a so-called MOS capacitor.

  Since the polysilicon gate 3 of the transistor Tr is commonly used to form the upper electrode of the capacitor Cp and the gate portion 6 of the transistor Tr, the polysilicon gate 3 is surrounded by an insulator and electrically It becomes a floating state that is not connected anywhere. The polysilicon gate 3 functions as a floating gate FG of the EEPROM cell, and data can be recorded (held) by accumulating charges in this portion.

  As described above, this EEPROM cell can be realized only with a MOS transistor Tr and a capacitor Cp having a general structure using one-layer polysilicon, and does not require a special device structure. It can be manufactured by a CMOS process. Details of the manufacturing process of the EEPROM cell will be described later.

  Next, the operation of the present EEPROM cell will be described with reference to Table 1. Table 1 shows the voltage relationship of each terminal during the write operation, the erase operation, and the read operation.

  At the time of the write operation, for example, control gate CG = 5V, drain D = 3V, and source S = 0V are set. In this state, the voltage of the floating gate becomes about 3V by the coupling capacitor Cp, and the transistor Tr is turned on. At this time, since the voltage of the floating gate FG and the drain D is 3 V, the transistor Tr operates in a saturation region and an excessive voltage is applied, so hot electrons are generated and electrons are injected into the floating gate FG. This state is referred to as a write state.

  On the other hand, for example, if the control gate CG = 5 V, the drain D = 0 V, and the source S = 0 V, no current flows through the transistor Tr, so that hot electrons are not generated and electrons are not injected into the floating gate. That is, by controlling the voltage of the drain D of each cell, it is possible to selectively write only to an arbitrary EEPROM cell.

  In the erase operation, for example, the conditions are set such that the control gate CG = 0V, the drain D = 7V, and the source S = open (electrically floating state). In this state, since the voltage of the floating gate FG is fixed to approximately 0 V by the coupling capacitor Cp, the potential difference between the floating gate FG and the drain D becomes 7 V, and Fauler-Northeim (Fauler-Northeim) ) Tunnel current flows, electrons are discharged from the floating gate FG to the drain D, and data is erased.

  On the other hand, if the drain D = 0V at this time, the electrons accumulated in the floating gate FG are not emitted, and data is not erased. That is, by controlling the voltage of the drain D of each cell, it is possible to selectively erase data from only an arbitrary EEPROM cell.

In the read operation, for example, by setting the control gate CG = 3 V, the drain D = 0.5 V, and the source S = 0 V, the drain current (the channel of the transistor Tr) can be obtained if data is written in the target EEPROM cell. Since no drain current flows and a drain current flows if the current is erased, the presence or absence of the drain current can be used to determine whether the current state is the write state or the erase state.
Note that the present invention is not limited to the above example, and the voltage applied to each terminal is not limited to the above voltage as long as a write operation, an erase operation, and a read operation are performed.

Here, the above read operation will be described in more detail with reference to FIG.
FIG. 2 is a gate voltage-drain current characteristic diagram (constant drain voltage) of the transistor Tr used in the present EEPROM cell. The horizontal axis of the graph represents the gate voltage VG, and the vertical axis represents the drain current I. The gate voltage-drain current characteristic in the written state and the gate voltage-drain current characteristic in the erased state are shown simultaneously.

  Of these two characteristics, the apparent threshold value increases in the characteristic indicating the write state, so that it is difficult for the drain current to flow, and the apparent threshold value decreases in the characteristic indicating the erased state, so that the drain current easily flows. . For example, when the gate voltage is 3 V, the drain current does not flow in the write state, and the drain current flows in the erase state. Since the transistor used in this EEPROM cell has such transistor characteristics, it can be determined whether data is written or erased in the EEPROM cell as described above.

Next, application examples of various layouts in which a memory array is configured by combining the EEPROM cells will be described.
FIG. 3 is a structural diagram showing a first application example of a memory array in which EEPROM cells (memory cells) of the present invention are arranged in a matrix. Originally, a plurality of EEPROM cells are arranged in a matrix, but a 4-bit configuration is used to simplify the description.

Basic floating gates are indicated by 3-1 to 3-4. In this application example, all the EEPROM cells are arranged in the same direction, and the drain wirings 8-1 (D1) and 8-2 (D2) (which are referred to as bit lines) made of metal wiring are connected to each memory array. The drains are connected along the columns, and the source wirings 9-1 (S1) and 9-2 (S2) (referred to as source lines) connect the sources along each column of the memory array. Control gates 6-1 (CG1) and 6-2 (CG2) (referred to as control gate lines) connect the control gates along each row of the memory array.
Further, the EEPROM cells arranged next to each other in the same row of the memory array are integrated with n-well 1-1, 1-2 and n + diffusion layers 2-1, 2-2 constituting the lower electrode of the capacitor, respectively. It is formed to reduce the layout area.

FIG. 4 is an equivalent circuit diagram of the memory array shown in FIG.
The upper left EEPROM cell shown in the structural diagram of FIG. 3 corresponds to Cell1, the upper right EEPROM cell corresponds to Cell2, the lower left EEPROM cell corresponds to Cell3, and the lower right EEPROM cell corresponds to Cell4. Further, as described above, the control gates CG1 of Cell1 and Cell2 and the control gates CG2 of Cell3 and Cell4 are connected to each other. Further, the source S1 and the drain D1 of Cell1 and Cell3 are connected to each other, and the source S2 and the drain D2 of Cell2 and Cell4 are connected to each other.

  Next, Table 2 shows the operation of the memory array shown in FIGS. Table 2 shows a state in which a predetermined set of voltages is applied to each node of CG1, CG2, D1, D2, S1, and S2 in each of the write operation, the erase operation, and the read operation. The hatched portion of each cell is the voltage applied to the three terminals of the corresponding cell.

  In the example shown in Table 2, the voltage is applied so that CG1 = 5V, D1 = 3V, S1 = 0V, CG2 = D2 = S2 = 0V at the time of the write operation. The other cells 2 to 4 indicate that the injection condition is not satisfied and the electron injection does not occur. For example, since CG1 = 5V and S2 = D2 = 0V are applied to Cell2, writing is not performed without electron injection.

  Here, for example, when the applied voltage is changed to CG1 = 5V, D1 = S1 = 0V, CG2 = 0V, D2 = 3V, S2 = 0V, only Cell2 is selected, and writing is performed in an electron injection state. . In this case, the injection conditions of the other cells 1, 3, and 4 are not satisfied, and electron injection does not occur. Similarly, by controlling the voltage applied to each electrode, it is possible to selectively write only to Cell 3 or only to Cell 4.

  In the erase operation, as shown in Table 2, when CG1 = 0V, D1 = 7V, S1 = open, CG2 = 5V, D2 = 0V, S2 = open, Cell1 is in an electron emission state as described above. However, the other cells 2 to 4 are not erased because the erase conditions are not satisfied. In particular, for Cell3, CG2 = 5V, D1 = 7V, and the floating gate FG is about 3V. Therefore, the potential difference between the floating gate and the drain is 4V, and erasure is not achieved.

Also, at the time of read operation, if CG1 = 3V, D1 = 0.5V, S1 = 0V, CG2 = 0V, D2 = open, S2 = 0V as shown in Table 2, only Cell1 is selected and read It is.
Even during the erasing operation and the reading operation, by controlling the voltage applied to each electrode, it is possible to selectively erase and read out one of the cells 1 to 4.
As described above, the voltage applied to each electrode is not limited to the voltage described in the example.

Next, a second application example of the EEPROM cell according to the present invention will be described with reference to FIG.
FIG. 5 is a structural diagram showing a second application example of the memory array using the EEPROM cell of the present invention. In this example as well, a 4-bit configuration is used to simplify the description.
In this application example, in the memory array shown in the first application example, the sources of the transistors are integrally formed between adjacent memory cells in the same row and shared.
In other words, the adjacent transistors in the same row are reversed left and right so that the sources face each other, so that two adjacent source regions (n + diffusion layers) are integrally formed and shared, A source line 9-12, which is a common metal wiring, is provided there. By making the two source regions and source wirings common to one, a more compact arrangement than the memory array according to the first application example can be realized.

  Also in this application example, the cells arranged next to each other in the same row are formed by integrally forming n-well and n + diffusion layers constituting the lower electrode of the capacitor, respectively, to reduce the area, and to each of the control gates. 6-1, 6-2 are connected.

Next, a third application example of the EEPROM cell according to the present invention will be described with reference to FIG.
FIG. 6 is a structural diagram showing a third application example of the memory array using the EEPROM cell of the present invention. In this example as well, a 4-bit configuration is used to simplify the description.
In this application example, in the memory array shown in the second application example, the sources and drains of the transistors belonging to adjacent rows are formed integrally.

  In other words, the source and drain of the transistor are alternately switched, the transistors are arranged in a row in the row direction, and the capacitors connected to the transistors are alternately arranged in parallel one row above and below the row where the transistors are arranged. ing. As a result, the source region (n + diffusion layer) and drain region (n + diffusion layer) of adjacent transistors in the same row can be integrally formed and shared, whereby the bit lines 8-1 and 8 which are metal wirings. -2 and the source line 9-2 can be connected in common.

Therefore, in the first application example and the second application example, the transistors need to be arranged in two rows in the row direction. However, in this application example, the same number of transistors can be arranged in one row, and a more compact memory array can be obtained. realizable.
Also in this application example, the cells arranged next to each other in the same row are formed by integrally forming n-well and n + diffusion layers constituting the lower electrode of the capacitor, respectively, to reduce the area, and to each of the control gates. 6-1, 6-2 are connected.

Next, a modification of the EEPROM cell according to the present invention will be described with reference to FIG.
FIG. 7A is a structural diagram of an EEPROM cell in which the reliability of the oxide film is improved, and FIG. 7B is a cross-sectional view taken along line AA ′ of FIG. 7A.
The present EEPROM cell differs from the structure shown in FIG. 1 in that the corner of the polysilicon gate 3 constituting the floating gate is formed on the n-well 1. This portion is a circled region 70 in FIG. 7B.

  In this region 70, the four corners and edges of the polysilicon gate 3 are not arranged on the thin oxide film 14, but are arranged on the field oxide film 13 for element isolation which is a thick oxide film. Therefore, there is an effect of preventing the phenomenon that the thin oxide film 14 is broken due to the concentration of the electric field at the corners and edges of the polysilicon gate 3, and the reliability of the oxide film can be improved.

Next, a method for manufacturing the above-described EEPROM cell according to the present invention will be described.
FIG. 8 is a manufacturing process diagram of the EEPROM cell according to the present invention. In the constituent elements shown in the figure, the same elements as those in FIG.
First, as shown in FIG. 8A, a resist is patterned on a p-type silicon substrate 0 through a mask PEP (Photo Engraving Process) (not shown), and n which becomes a lower electrode of the capacitor by ion implantation or the like. -The well1 region is formed.

  Next, as shown in FIG. 8B, a field oxide film 13 for element isolation is formed, and then a thin oxide film 14 that becomes the gate portion 6 and the capacitor portion 10 of the transistor Tr is formed. Thereafter, a polysilicon gate 3 which is the gate of the transistor Tr and the upper electrode of the capacitor Cp and serves as the floating gate FG is formed.

  Next, as shown in FIG. 8C, an n-type impurity (such as arsenic) is implanted by ion implantation 15, and then heat is applied to form an n + diffusion layer 2 in the n-well 1 region. This n + diffusion layer 2 becomes a connection region to n-well 1. Although not shown in the cross-sectional view, the n + diffusion layer 5 serving as the source S and the n + diffusion layer 4 serving as the drain D of the transistor Tr are simultaneously formed by this process.

  Next, as shown in FIG. 8D, an interlayer insulating film 16 is formed, and holes for selectively forming contacts 12 on the interlayer insulating film 16 on the n + diffusion layer 2 using a mask and a resist (not shown). Can be opened. Although not shown in the cross-sectional view, the contact 7 is simultaneously formed in the interlayer insulating film 16 on the n + diffusion layer 5 serving as the source S and the n + diffusion layer 4 serving as the drain D by this process. A hole is opened.

Next, as shown in FIG. 8E, a metal wiring 11 for wiring (Al, Cu or the like) is connected to the n + diffusion layer 2 through the contact 12 and formed in a necessary region. Although not shown in the cross-sectional view shown in the figure, by this step, the metal wiring 8 connected to the drain D of the transistor Tr and the metal wiring 9 connected to the source S are also formed simultaneously.
As described above, the manufacturing of the EEPROM according to the present invention does not require any special process, and can be realized by using a single-layer polysilicon CMOS process that is used as a standard for manufacturing a logic IC.

  This EEPROM cell uses the lower electrode of the capacitor Cp composed of the n-well 1 and the n + diffusion layer 2 as a control gate CG. Under normal conditions, the n-well 1 region immediately below the capacitor unit 10 is accumulated. The operation is performed in the region, but when the impurity concentration of n-well 1 is low, the operation may be performed in the depletion region.

  When operating in the depletion region, the frequency response characteristic of the capacitor Cp deteriorates. Therefore, when high-speed operation is required, a low-concentration n is added to the n-well 1 region in the step of FIG. If a type impurity (for example, As) is implanted by implantation, the operation can be performed in a sufficient accumulation region in any situation. In addition, since only one implantation process is added to the standard manufacturing process, the yield does not deteriorate and the price increases due to an increase in processes.

  As mentioned above, although embodiment of this invention was explained in full detail, the concrete structure is not restricted to this embodiment, The design change etc. of the range which does not deviate from the summary of this invention are included. For example, the EEPROM may be configured using an n-type semiconductor substrate. Further, a low resistance material such as tungsten silicide may be used as the gate material.

  The present invention is suitable for use in a nonvolatile memory.

1 is a structural diagram of an EEPROM cell which is a memory cell of a nonvolatile memory according to the present invention. It is a gate voltage-drain current characteristic figure (drain voltage constant) of the transistor Tr used for the EEPROM cell same as the above. FIG. 3 is a structural diagram showing a first application example of a memory array in which EEPROM cells of the present invention are arranged in a matrix. It is an equivalent circuit diagram of a memory array same as the above. It is a structural diagram showing a second application example of the memory array using the EEPROM cell of the present invention. It is a structural diagram which shows the 3rd example of application of the memory array using the EEPROM cell same as the above. 3 is a structural diagram of an EEPROM cell in which the reliability of an oxide film is improved. FIG. It is a manufacturing-process figure of the EEPROM cell based on this invention.

Explanation of symbols

0 p-type semiconductor substrate, 1 n-type well, 2 n + diffusion layer, 3 polysilicon gate, 4 n + diffusion layer, 5 n + diffusion layer, 6 gate part, 7 contact, 8 metal wiring, 9 metal wiring, 10 capacitor part 11 metal wiring, 12 contacts, 13 field oxide film, 14 thin oxide film, 15 ion implantation, 16 interlayer insulation film, Tr transistor, D drain, S source, CG control gate, FG floating gate, Cp capacitor, 3- 1-3-4 Floating gate, 8-1, 8-2 Drain wiring, 9-1 to 9-3, 9-12 Source wiring, 6-1, 6-2 Control gate, 1-1, 1-2 n -Well, 2-1, 2-2 n + diffusion layer

Claims (10)

A nonvolatile memory including a memory cell composed of a MOS transistor and a capacitor,
The transistor is
A source and a drain formed on the main surface of the semiconductor substrate;
A floating gate formed on the main surface between the source and drain via an insulating film;
Consisting of
The capacitor is
A first electrode comprising an impurity region formed as a control gate of the transistor on the main surface of the semiconductor substrate;
A second electrode integrally formed with the floating gate via an insulating film on the impurity region;
Nonvolatile memory composed of The non-volatile memory according to claim 1.
The non-volatile memory, wherein the transistor and the capacitor are formed using a standard CMOS process. The non-volatile memory according to claim 1,
A memory array in which the memory cells are arranged in a matrix;
A plurality of bit lines formed along each column of the memory array and connected to the drains of the transistors;
A plurality of source lines formed along each column of the memory array and connected to the sources of the transistors;
A plurality of control gate lines formed along each row of the memory array and connected to the first electrode as the control gate;
With
A nonvolatile memory, wherein the impurity region constituting the first electrode is integrally formed between adjacent memory cells in the same row. The non-volatile memory according to claim 3,
The memory cell is
At the time of writing, a predetermined first positive voltage is applied to the control gate line, a predetermined second positive voltage is applied to the bit line, and a ground voltage is applied to the source line,
At the time of erasing, a ground voltage is applied to the control gate line, a predetermined third positive voltage is applied to the bit line, and the source line is opened.
A nonvolatile semiconductor memory device, wherein a predetermined fourth positive voltage is applied to the control gate line, a predetermined fifth positive voltage is applied to the bit line, and a ground voltage is applied to the source line during reading. Sex memory. The non-volatile memory according to claim 3,
A nonvolatile memory characterized in that a source of the transistor is integrally formed between adjacent memory cells in the same row. The non-volatile memory according to claim 3,
A non-volatile memory, wherein a source and a drain of the transistor are integrally formed between memory cells belonging to adjacent rows. The non-volatile memory according to claim 1,
The non-volatile memory according to claim 2, wherein the second electrode is formed such that a corner portion thereof is positioned on a field oxide film for element isolation.   The nonvolatile memory according to claim 1, wherein the capacitor is formed of a MOS capacitor. A method for manufacturing the non-volatile memory according to claim 1, comprising:
Forming the impurity region to be the first electrode of the capacitor in a predetermined region of the semiconductor substrate;
Forming a field oxide film for element isolation;
Forming an oxide film to be a gate oxide film of the transistor and an insulating layer of a capacitor;
Forming a floating gate of the transistor and a second electrode of the capacitor;
Forming a source and a drain of the transistor;
Forming an interlayer insulating film;
Forming a contact hole communicating with the impurity region and the source and drain in the interlayer insulating film;
Forming a metal wiring;
A method for manufacturing a nonvolatile memory including: In the manufacturing method of the non-volatile memory according to claim 9,
A method for manufacturing a nonvolatile memory, wherein an impurity having the same conductivity type as that of the impurity region is further implanted after the impurity region is formed.

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