JP2007313121A - Slot machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a slot machine capable of preventing a game from being continuously played in a state where an abnormality is happening in RAM data. <P>SOLUTION: When unusage interrupt occurs, a CPU 41a inactivates the game till the RAM 41c is initialized and a setting value is newly set by a setting change operation. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a slot machine capable of generating a predetermined winning according to a display result of a variable display device capable of variably displaying a plurality of types of symbols each identifiable.

  This type of slot machine is equipped with a control unit composed of a microcomputer or the like, and the game is controlled by this control unit. In addition, the control unit has a memory (ROM) for storing a program and data for controlling the game in a non-rewritable manner and a memory (RAM) for storing a data for controlling the game in a rewritable manner (RAM). Is provided.

  The microcomputer installed in the control unit has multiple interrupt input terminals that generate external interrupts. When a signal is input to the interrupt input terminal and an interrupt occurs, the interrupt is generated. An instruction written from a predetermined address on the ROM is executed as the corresponding start address of the interrupt process.

  Some of these interrupt input terminals are used and some are unused. When a signal is input to an unused interrupt input terminal due to noise and an unused interrupt occurs, the interrupt The microcomputer executes the instruction from the address specified as the start address of the interrupt process corresponding to the interrupt, but the correct instruction is issued after the start address of the interrupt process corresponding to the unused interrupt and the address. Because it is not written, the microcomputer runs away and eventually hangs (stops).

  If the microcomputer goes out of control or hangs up, normal game progress cannot be made in the slot machine. As a result, problems such as giving distrust to the player and losing the trust of the game store arise.

  For this reason, in the conventional slot machine, only the instruction to return to the processing at the time of occurrence of the interrupt is written at the start address of the interrupt processing corresponding to the unused interrupt, and the unused interrupt is caused by noise. If it occurs, the processing immediately returns to the processing at the time of occurrence of the interrupt (for example, see Patent Document 1).

JP 2003-325909 A

  However, there is a case where an abnormality has occurred in the RAM data due to noise that triggered the occurrence of unused interrupts. In the slot machine described in Patent Document 1, after the unused interrupt processing is performed, Since the processing immediately returns to the processing at the time of the occurrence of the interrupt, there is a possibility that the game may be performed in a state where the abnormality of the RAM data remains generated.

  The present invention has been made paying attention to such problems, and an object of the present invention is to provide a slot machine capable of preventing a game from being played in a state in which an abnormality has occurred in RAM data. To do.

In order to solve the above-described problem, a slot machine according to claim 1 of the present invention provides:
A variable display device capable of starting a game by setting a predetermined number of bets for one game using a game value (medal), and capable of variably displaying a plurality of types of identification information each of which can be identified A slot machine (slot machine 1) in which one game is completed by displaying and displaying the display results of (reels 2L, 2C, 2R), and a winning can be generated according to the display results of the variable display device. And
Consists of a microcomputer having a plurality of interrupt input terminals (INT, NMI) that generate an external interrupt when a signal is input, and includes main control means (main control unit 41) for controlling a game,
The main control means includes
A work area (important work, general work, special work) having a storage area for storing data so as to be readable and writable, and storing data for operating the microcomputer constituting the main control means as the storage area A data storage means (RAM 41c) to which at least a set value work and a non-saved work) are assigned,
Initialization means for initializing at least a part of the storage area in the data storage means (initialization of the RAM 41c in initialization 1 by the CPU 41a);
When a signal is input to an unused interrupt input terminal (INT, NMI) among the plurality of interrupt input terminals and an external interrupt (maskable interrupt, non-maskable interrupt) occurs, the game progresses. Disabling means for disabling (unused interrupt processing by the CPU 41a);
When the progress of the game is disabled by the disabling means, the progress of the game is disabled on the condition that the work area in the data storage means is initialized by the initializing means. A disabling canceling means for canceling and allowing the game to proceed (transition to the game processing in the startup processing by the CPU 41a);
It is characterized by including.
According to this feature, when an unused interrupt occurs, the progress of the game is disabled until the work area of the data storage means is initialized, so that noise caused by the occurrence of an unused interrupt may occur. Even if an abnormality occurs in the data stored in the data storage means, it is possible to prevent the game from being played in a state where the abnormality occurs in the data stored in the data storage means.
In addition, in claim 1, the predetermined number of bets is at least one bet number, and a game can be started by setting a bet number of two or more or a maximum bet number. You may do it. Further, the game may be started by setting a bet amount determined according to a plurality of game states.

A slot machine according to claim 2 of the present invention is the slot machine according to claim 1,
The initialization means (initialization of the RAM 41c in the initialization 1 by the CPU 41a) is based on an operation of a predetermined initialization operation means (an operation to turn on the setting key switch 37), the data storage means (RAM 41c). It is characterized by initializing the work area (important work, general work, special work, set value work, unsaved work).
According to this feature, the progress of the game is disabled until a predetermined initialization operation means is operated. There is a possibility that the unused interrupt that triggered the progress of the game has been caused by noise accompanying fraud. In such cases, it is necessary for the amusement shop employee to perform the operation in order to resume the game by making the prescribed operation only an operation that can be performed by the amusement shop employee. Can be effectively prevented.
Further, it is preferable that the operation of the predetermined initialization operation means for canceling the state where the progress of the game is disabled is a time-consuming operation that requires, for example, the power to be turned on again. By doing so, such illegal acts can be prevented more effectively.

A slot machine according to claim 3 of the present invention is the slot machine according to claim 1 or 2,
Based on an operation of a predetermined setting operation means (setting key switch 37), a plurality of types of allowable stages (setting values) having different ratios (winning probabilities) for determining whether or not winning is allowed is determined. , An allowable stage selection means (setting change process by the CPU 41a) for selecting any of the allowable stages;
Permissible step setting means (set in the setting change process by the CPU 41a) for setting the data indicating the permissible step selected by the permissible step selection means in the permissible step storage area (set value work) assigned to the storage area of the data storage means. To store the set value in the set value work),
With
The initialization means (initialization of the RAM 41c in the initialization 1 by the CPU 41a) stores the data storage on the condition that the allowable stage is newly set by the allowable stage setting means based on the operation of the setting operation means. Initialize the work area (important work, general work, special work, set value work, unsaved work) in the means (RAM 41c).
It is characterized by that.
According to this feature, the state where the progress of the game is disabled is canceled by newly selecting and setting an allowable stage (set value) based on an operation of a predetermined setting operation means. For this reason, even if an abnormality occurs in the data storage means data indicating the permissible stage due to noise that triggers the occurrence of an unused interrupt, the permissible stage selected and set based on the operation of the predetermined setting operation means (In general, since the operation of the setting operation means is operated by an employee of a game shop, which is an allowable stage selected by the game shop side), it is ensured that the game is played. Can be achieved.
Moreover, there is a possibility that the unused interrupt that triggered the progress of the game is caused by noise associated with fraud. In such a case, in order to resume the game, it is necessary to perform an operation of changing the permissible stage, which is more time-consuming than the reset operation for canceling the normal error. Can do.
Further, it is preferable that the operation of the predetermined setting operation means for canceling the state where the progress of the game is disabled is a time-consuming operation that requires, for example, the power to be turned on again. By doing so, such illegal acts can be prevented more effectively.
The initialization unit may be any unit that initializes the work area in response to the operation of the predetermined setting operation unit. For example, the time when the operation of the predetermined setting operation unit becomes valid or the allowable stage is newly set. Any timing may be used as long as it is set to.

A slot machine according to claim 4 of the present invention is the slot machine according to any one of claims 1 to 3,
An unused interrupt input terminal (INT, NMI) in the microcomputer (main control unit 41) is pulled up to a predetermined power supply (+ 5V).
According to this feature, since the unused interrupt input terminal of the microcomputer is pulled up to a predetermined power source, it is possible to reduce the possibility of an unused interrupt occurring even when noise occurs.

  Examples of the present invention will be described below.

  An embodiment of a slot machine to which the present invention is applied will be described with reference to the drawings. A slot machine 1 according to the present embodiment is rotatable to a housing (not shown) whose front surface is open and a side end of the housing. It consists of a pivoted front door.

  Inside the casing of the slot machine 1 of this embodiment, reels 2L, 2C, 2R (hereinafter also referred to as a left reel, a middle reel, and a right reel) in which a plurality of types of symbols are arranged on the outer periphery are arranged in parallel in the horizontal direction. As shown in FIG. 1, three consecutive symbols out of the symbols arranged on the reels 2L, 2C, and 2R are arranged so as to be seen from the see-through window 3 provided on the front door.

  On the outer peripheries of the reels 2L, 2C, and 2R, “red 7 (black 7 in the figure)”, “blue 7 (shaded 7 in the figure)”, “BAR”, “replay”, “watermelon”, “cherry”, respectively. , “Bell”, and 21 types of mutually distinguishable symbols are drawn in a predetermined order. The symbols drawn on the outer peripheries of the reels 2L, 2C, and 2R are displayed in the upper, middle, and lower three stages in the see-through window 3, respectively.

  The reels 2L, 2C, and 2R are provided in correspondence with each other and are rotated by reel motors 32L, 32C, and 32R (see FIG. 2), so that the symbols of the reels 2L, 2C, and 2R are continuously formed in the see-through window 3. In addition to being displayed while changing, by stopping the rotation of the reels 2L, 2C, and 2R, three consecutive symbols are derived and displayed on the fluoroscopic window 3 as display results.

  Further, on the front door, a medal insertion portion 4 capable of inserting medals, a medal payout exit 9 from which medals are paid out, and credits (the number of medals stored as a player's own game value) are used for one medal. 1 bet switch 5 that is operated when setting the number of bets, and using a credit, a specified number of bets determined according to the gaming state within the range (in this embodiment, in the normal gaming state described later) 3 is a MAXBET switch 6 that is operated when setting a regular bonus to be described later, 1), and the medals stored as credits and the medals used for setting the bets are settled (for setting credits and bets). The payout switch 10 operated when the medal used is returned), the start switch 7 operated when starting the game, the reels 2L, 2C, 2 Stop switch 8L is operated to each stop of the rotation, 8C, 8R are provided.

  The front door also displays a credit indicator 11 for displaying the number of medals stored as credits, the number of medals acquired in a big bonus, which will be described later, and an error code indicating the contents when an error occurs. An auxiliary indicator 12 and a payout indicator 13 for displaying the number of medals paid out due to the occurrence of a prize are provided.

  Also, on the front door, 1 BET LED 14 that notifies that the bet number is set by 1 is lit, 2 BET LED 15 that notifies that the bet number is 2 is lit, and that 3 bets are set 3BETLED 16 to notify, the insertion request LED 17 to notify that the medal can be inserted by lighting, the start effective LED 18 to notify that the game start operation by the operation of the start switch 7 is effective, and the weight (previous game) (Waiting for starting reel rotation since a certain period of time has not elapsed since the start) LED 19 during waiting to notify that it is on, LED 20 during replay notifying that it is in a replay game to be described later Is provided.

  Further, inside the MAXBET switch 6, there is provided a BET switch valid LED 21 (see FIG. 2) for notifying by light that the betting number setting operation by the operation of the single BET switch 5 and the MAXBET switch 6 is valid. In the stop switches 8L, 8C, 8R, left, middle, and right stop effective LEDs 22L, 22C, 22R that notify that the reel stop operation by the corresponding stop switches 8L, 8C, 8R is effective are turned on. (See FIG. 2).

  Further, inside the front door, a reset switch 23 for detecting a reset operation for canceling an error state excluding a RAM abnormality error described later and a stop state described later by a predetermined key operation, changing a set value described later And a set value indicator 24 for displaying the set value at that time during confirmation of the set value, and a flow path for medals inserted from the medal insertion unit 4, which will be described later, is provided in a hopper tank (not shown). ) Side or medal payout outlet 9 side, a flow path switching solenoid 30 for selectively switching, and a medal insertion sensor 31 for detecting a medal inserted from the medal insertion unit 4 and flowing down to the hopper tank side are provided. ing.

  Inside the casing, a reel unit (not shown) comprising the reels 2L, 2C and 2R, the reel motors 32L, 32C and 32R, and the reel sensor 33 capable of detecting the respective reel reference positions of the reels 2L, 2C and 2R. , A hopper tank (not shown) for storing medals inserted from the medal insertion unit 4, a hopper motor 34 for paying out medals stored in the hopper tank from the medal payout opening 9, and paying out by driving the hopper motor 34. A payout sensor 35 for detecting a medal and a power supply box (not shown) are provided.

  On the front of the power supply box is a stop switch for selecting whether to enable / disable a stop function for controlling the stop state (a state in which the progress of the game is restricted until a reset operation is performed) at the end of a big bonus, which will be described later 36, a setting key switch 37 for switching to the setting change mode at the time of startup, and functioning as a reset switch for canceling an error state and a stop state except for a RAM abnormality error in a normal state. There are provided a reset / setting switch 38 functioning as a setting switch for changing the setting value of the winning probability (out-run rate) of the lottery, and a power switch 39 operated when turning on / off the power.

  When a game is played in the slot machine 1 of the present embodiment, first, medals are inserted from the medal insertion unit 4 or a bet number is set using credits. In order to use credits, the single BET switch 5 or the MAX BET switch 6 may be operated. When a predetermined number of bets determined according to the gaming state are set, the pay lines L1 to L5 (see FIG. 1) become effective, and the operation of the start switch 7 is effective, that is, the game can be started. It becomes a state. In the present embodiment, as the prescribed number of bets, three are determined in the normal gaming state described later, and one is determined in the regular bonus described later. If medals are inserted beyond the prescribed number corresponding to the gaming state, the amount is added to the credit.

  When the start switch 7 is operated in a state where the game can be started, the reels 2L, 2C, and 2R rotate, and the symbols of the reels 2L, 2C, and 2R continuously vary. When any one of the stop switches 8L, 8C, 8R is operated in this state, the rotation of the corresponding reels 2L, 2C, 2R is stopped, and the display result is derived and displayed on the fluoroscopic window 3.

  Then, when all the reels 2L, 2C, 2R are stopped, one game is completed, and a predetermined symbol combination (hereinafter also referred to as a combination) is placed on any of the activated pay lines L1 to L5. When the reels 2L, 2C, and 2R are stopped as a display result, a winning occurs, and a predetermined number of medals are given to the player and added to the credit. Further, when the credit reaches the upper limit (50 in this embodiment), medals are paid out directly from the medal payout opening 9 (see FIG. 1). If a combination of symbols with payout of medals is arranged on a plurality of activated pay lines, the total number of payouts determined for each combination of symbols aligned on the activated pay line is totaled. The total number of medals will be awarded to the player. However, an upper limit (15 in this embodiment) is set for the number of medals to be awarded in one game. When the total number of medals exceeds the upper limit, the upper limit number of medals is awarded. The Rukoto. In addition, when a combination of symbols accompanying the transition of the gaming state is stopped as a display result of each reel 2L, 2C, 2R on any of the activated pay lines L1 to L5, a game corresponding to the combination of symbols Transition to the state.

  FIG. 2 is a block diagram showing a configuration of the slot machine 1. The slot machine 1 is provided with a game control board 40, an effect control board 90, and a power supply board 100. The game state is controlled by the game control board 40, and the effect according to the game state is controlled by the effect control board 90. The power supply board 100 generates drive power for the electrical components that constitute the slot machine 1 and supplies the drive power to each unit.

  The power supply board 100 is supplied with AC100V power from the outside, and from this AC100V power supply, a DC voltage necessary for driving electrical components constituting the slot machine 1 is generated, and the game control board 40 and the game control board 40 are generated. It is supplied to the production control board 90 connected through the. Further, the above-described hopper motor 34, payout sensor 35, stop switch 36, setting key switch 37, reset / setting switch 38, and power switch 39 are connected to the power supply substrate 100.

  Connected to the game control board 40 are the above-described one-sheet BET switch 5, MAXBET switch 6, start switch 7, stop switches 8L, 8C, 8R, settlement switch 10, reset switch 23, insertion medal sensor 31, and reel sensor 33. In addition, the above-described payout sensor 35, stop switch 36, setting key switch 37, and reset / setting switch 38 are connected via the power supply substrate 100, and detection signals of these connected switches are input. It is like that.

  Further, the game control board 40 includes the credit display 11, the game auxiliary display 12, the payout display 13, 1 to 3 BET LEDs 14 to 16, the insertion request LED 17, the start valid LED 18, the waiting LED 19, the replaying LED 10, and the BET. The switch effective LED 21, left, middle, and right stop effective LEDs 22L, 22C, and 22R, the set value display 24, the flow path switching solenoid 30, and the reel motors 32L, 32C, and 32R are connected, and the power supply board 100 is used as described above. The hopper motor 34 is connected, and these electric components are driven based on control of a main control unit 41 described later mounted on the game control board 40.

  As shown in FIG. 3, the game control board 40 includes a microcomputer having a CPU 41a, a ROM 41b, a RAM 41c, and an I / O port 41d, and a main control unit 41 for controlling the game, a predetermined range (in this embodiment, 0 to 16383), random number generating circuit 42 for generating random numbers, sampling circuit 43 for acquiring random numbers from the random number generating circuit, detection signals input from switches connected to game control board 40 directly or via power supply board 100 In addition, a switch detection circuit 44 that detects a reset signal input from the power interruption detection circuit 48 described later and outputs the detection state of these signals to the input / output terminal DATA of the main control unit 41, reel motors 32L, 32C, and 32R. A motor drive circuit 45 that controls the drive of the fluid and a solenoid that controls the drive of the flow path switching solenoid 30. Id drive circuit 46, various display devices connected to game control board 40, LED drive circuit 47 for controlling the drive of LEDs, power supply voltage supplied to slot machine 1 is monitored, and when a voltage drop is detected, A power interruption detection circuit 48 that outputs a voltage drop signal indicating that to the main control unit 41, a reset circuit 49 that provides a reset signal to the CPU 41a when the power is turned on or when an operation detection signal described later from the CPU 41a is not input, Is equipped with an output conversion circuit 410 that receives a signal output indicating that the device is operating and continuously outputs an operation detection signal generated by converting the signal to the reset circuit 49, and various other devices and circuits. ing.

  Note that the operation detection signal input to the reset circuit 49 is the signal converted by the output conversion circuit 410, but the present invention is not limited to this and indicates that the CPU 41a is operating. Any signal can be used. In the slot machine 1 of the present embodiment, display of any LED or indicator, for example, the credit indicator 11 or the payout indicator 13 is always performed according to the progress of the game. A drive signal for driving is constantly output. The drive signal that is constantly output may be branched from an output signal line to the LED or the display, and these may be used as an operation detection signal input to the reset circuit 49.

  As shown in FIG. 3, the reset circuit 49 includes a watch dog circuit 411. The watchdog circuit 411 outputs a signal to the reset output terminal RESET on the condition that a predetermined period has passed in a state where no signal input to the watchdog input terminal WD of the reset circuit 49 is detected, and the watchdog input terminal This is a circuit that performs measurement for a predetermined period from 0 again on condition that a signal input to WD is detected. As described above, the operation detection signal output from the output conversion circuit 410 is input to the watchdog input terminal WD of the reset circuit 49. The reset circuit 49 is only a circuit that outputs a reset signal when the power is turned on. It is also a circuit that outputs a reset signal to the CPU 41a on condition that a predetermined period or more has elapsed since the operation of the CPU 41a stopped.

  The CPU 41a has an interrupt function (including an interrupt prohibition function) such as a timekeeping function and a timer interrupt, and executes a program (described later) stored in the ROM 41b to perform processing related to the progress of the game. Each part of the control circuit mounted on the control board 40 is controlled directly or indirectly. The ROM 41b stores fixed data such as programs executed by the CPU 41a and various tables. The RAM 41c is used as a work area when the CPU 41a executes a program. The I / O port 41d inputs / outputs a control signal to / from each circuit connected via a signal input / output terminal included in the main control unit 41.

  The main control unit 41 includes a signal input / output terminal DATA, and detection states of various switches connected to the game control board 40 are input to the input port via the signal input / output terminal DATA. The input states of these signal input / output terminals DATA are monitored by the CPU 41a, and the CPU 41a executes a basic process that shifts in stages according to the input states of the signal input / output terminals DATA, that is, the detection states of various switches. .

  In addition, the CPU 41a has an interrupt function as described above, and can execute an interrupt process by interrupting the basic process when an interrupt occurs. In this embodiment, four types of interrupts of interrupts 1 to 4 can be executed. For each interrupt, a counter mode (a trigger terminal CLK / TRG2 or CLK / provided separately from the signal input / output terminal DATA) is provided. An interrupt mode that generates an external interrupt in response to a signal input from the TRG 3 and a timer mode (an interrupt mode that generates an internal interrupt depending on the number of clock inputs of the CPU 41a) can be selected and set. It has become.

  In the present embodiment, among the interrupts 1 to 4, interrupt 2 is set to the counter mode, interrupt 3 is set to the timer mode, and interrupts 1 and 4 are unused. The trigger terminal CLK / TRG2 corresponding to the interrupt 2 is connected to the power interruption detection circuit 48 described above, and the CPU 41a generates the interrupt 2 according to the input of the voltage drop signal output from the power interruption detection circuit 48. Then, a power interruption interrupt process to be described later is executed. Further, the CPU 41a generates an interrupt 3 every time the number of clock inputs reaches a certain number, that is, every certain time interval (about 0.56 ms in this embodiment), and executes a timer interruption process described later.

  Note that the interrupt 3 that is in the timer mode in this embodiment can also be used as a counter mode. In this case, a trigger signal is input to the trigger terminal CLK / TRG3 corresponding to the interrupt 3. On the other hand, when interrupt 3 is used as a timer mode as in this embodiment, the corresponding trigger terminal CLK / TRG3 is grounded (connected to GND) as shown in FIG.

  The CPU 41a is set to prohibit other interrupts during execution of interrupt processing based on the occurrence of any one of interrupts 1 to 4, and a plurality of interrupts occurred simultaneously. In this case, interrupts to be executed with priority in the order of interrupts 2, 3, 1, 4 are set. In other words, when interrupt 2 and other interrupts occur simultaneously, interrupt 2 is prioritized and when interrupt 3 and interrupt 1 or 4 occur simultaneously, interrupt 3 is prioritized. To run.

  Further, the CPU 41a temporarily stores the data in use stored in the register in a later-described stack area provided in the RAM 41c at the start of interrupt processing based on the occurrence of any of the interrupts 1 to 4. The data saved in the stack area at the end of the interrupt process is returned to the register.

  On the other hand, in addition to these interrupts 1 to 4, the CPU 41 a can generate a maskable interrupt or non-maskable interrupt by an external signal input and execute a corresponding interrupt process. As shown in FIG. 3, the interrupt input terminal corresponding to the maskable interrupt is INT, and the interrupt input terminal corresponding to the non-maskable interrupt is NMI. In this embodiment, these maskable interrupts and non-maskable interrupts are unused interrupts. However, as will be described later, these interrupts may occur due to noise or the like. For this reason, when a maskable interrupt or a non-maskable interrupt occurs, the CPU 41a immediately executes an unused interrupt process (to be described later) that immediately shifts the CPU 41a to the disabled (runaway) state.

  Here, an example in which unused interrupts occur due to noise will be described.

  First, an example in which noise is directly detected as an unused interrupt will be described. When voltage fluctuation due to noise is applied to an interrupt input terminal corresponding to an unused interrupt, the CPU 41a interrupts this noise. May be detected as the occurrence of

  It is preferable that these unused interrupts do not occur. In this embodiment, INT and NMI which are unused interrupt input terminals are used as power sources for various circuits such as the main control unit 41 as shown in FIG. + 5V, which is a stable voltage with relatively little fluctuation, is applied. In other words, INT and NMI, which are unused interrupt input terminals, are pulled up to the power supply (+ 5V), and even if noise or the like occurs in these interrupt input terminals, the voltage fluctuation is small. In some cases, the occurrence of an interrupt is difficult to detect.

  Next, an example in which noise is indirectly detected as an unused interrupt will be described.

  When the CPU 41a of this embodiment detects a signal input to one of the interrupt input terminals, the CPU 41a accesses a predetermined address on the RAM 41c in association with the detected interrupt input terminal and stores the stored data. To get. The acquired data is an address on the ROM 41b. The ROM 41b stores an interrupt processing program corresponding to the interrupt with the acquired address as a head address. That is, the RAM 41c stores the start address of the interrupt processing program corresponding to each interrupt.

  At this time, it is assumed that the start address of the interrupt processing program corresponding to each of these interrupts stored in the RAM 41c is rewritten due to noise. For example, in this embodiment, the start address of the interrupt process (interruptible interrupt process) corresponding to interrupt 2 (CLK / TRG2) is the interrupt process corresponding to the maskable interrupt (INT) (not yet processed). Suppose that it has been rewritten to the start address of the program of use interrupt processing.

  As described above, in the state where the start address of the interrupt processing program corresponding to the interrupt 2 is changed from the start address of the power interruption interrupt processing program to the start address of the unused interrupt processing program, the CPU 41a. When the CPU 41a detects the signal input to the trigger terminal CLK / TRG2, the CPU 41a acquires the start address of the program for the power interruption interrupt process. In some cases, it is detected that a maskable interrupt (INT), which is an unused interrupt, has occurred in order to acquire the start address of the program of the interrupt process, and the unused interrupt process is executed.

  Even in such a case, in this embodiment, unused interrupt input terminals INT and NMI are supplied with power (+5 V) by +5 V, which is a stable voltage with relatively little fluctuation, as shown in FIG. Therefore, when noise or the like occurs at these interrupt input terminals, the possibility of changing the RAM 41c can be reduced if the voltage fluctuation is small, and the occurrence of unused interrupts can be reduced. It is difficult to detect.

  The above is a specific example when an unused interrupt occurs due to noise.

  As the RAM 41c, a DRAM (Dynamic RAM) is used, and a refresh operation is required to maintain the stored data contents. The CPU 41a is provided with a refresh register 41R for performing this refresh operation. The refresh register 41R is composed of 8 bits, and the lower 7 bits are automatically incremented every time the CPU 41a fetches an instruction from the ROM 41b. The value is updated every execution time of one instruction. Is called.

  The main control unit 41 is also supplied with backup power even during a power failure, and while the backup power is being supplied, the CPU 41a performs a refresh operation to hold the data stored in the RAM 41c. It is like that.

  The random number generation circuit 42 is configured by a counter that counts up and updates the value every time a predetermined number of pulses are generated, as will be described later, and the sampling circuit 43 acquires the numerical value counted by the random number generation circuit 42. . The random number generation circuit 42 defines a range of numerical values to be counted for each type of random number. In this embodiment, 0 to 16383 is defined as the range. The CPU 41a sends an instruction to the sampling circuit 43 in accordance with the processing to acquire the numerical value indicated by the random number generation circuit 42 as a random number (this function is hereinafter referred to as a hardware random number function). Random numbers for internal lottery, which will be described later, are not used as they are extracted by the hardware random number function, but are processed and used by software. Details thereof will be described in detail. The CPU 41a also has a function of updating a numerical value of a specific register by the above-described timer interrupt process and acquiring the updated numerical value as a random number (hereinafter, this function is referred to as a software random number function).

  The CPU 41a transmits various commands to the effect control board 90 via the I / O port 41d. A command transmitted from the game control board 40 to the effect control board 90 is sent in only one direction, and no command is sent from the effect control board 90 to the game control board 40. The transmission line of the command transmitted from the game control board 40 to the effect control board 90 is composed of a strobe (INT) signal line, a data transmission line, and a ground line, and is connected via the effect relay board 80. The game control board 40 and the effect control board 90 are not directly connected.

  Electrical components such as a liquid crystal display 51 (see FIG. 1), a rendering effect LED 52, speakers 53 and 54, and a reel LED 55 disposed on the front door of the slot machine 1 are connected to the rendering control board 90. The components are driven based on control by a later-described sub-control unit 91 mounted on the effect control board 90.

  Similar to the main control unit 41, the effect control board 90 includes a microcomputer having a CPU 91a, ROM 91b, RAM 91c, and I / O port 91d. The effect control board 90 includes a sub control unit 91 for effect control and an effect control board 90. A liquid crystal driving circuit 92 that controls the driving of the connected liquid crystal display 51, a lamp driving circuit 93 that controls the driving of the effect LED 52 and the reel LED 55, an audio output circuit 94 that controls audio output from the speakers 53 and 54, and a power source A reset circuit 95 that gives a reset signal to the CPU 91a when it is turned on or when an initialization command is not input from the CPU 91a, and other circuits are mounted. The CPU 91a receives a command transmitted from the game control board 40. In addition to performing various controls for production, mounted on production control board 90 Directly or indirectly controls each unit of the control circuit.

  Similar to the CPU 41a of the main control unit 41, the CPU 91a has an interrupt function (including an interrupt prohibition function) such as a timer interrupt. An interrupt terminal (not shown) of the sub-control unit 91 is connected to a strobe (INT) signal line that is output when the main control unit 41 transmits a command among command transmission lines. An interrupt is generated based on the input to acquire a command from the main control unit 41 and execute a command reception interrupt process to be stored in the buffer. The CPU 91a executes a timer interrupt process (sub) to be described later by generating an interrupt every time the number of clock inputs reaches a certain number, that is, every certain interval. Also, when an unused interrupt occurs in the CPU 91a, an unused interrupt process for immediately returning to the original process is executed.

  Further, unlike the CPU 41a, when an interrupt is generated based on the input of the strobe signal (INT), the CPU 91a interrupts the process even when an interrupt process based on another interrupt is being executed. The command reception interrupt process is executed at the top, and even if another interrupt occurs at the same time, the command reception interrupt process is executed with the highest priority.

  The sub-control unit 91 is also supplied with backup power at the time of a power failure, and while the backup power is supplied, the CPU 91a performs a refresh operation so that the data stored in the RAM 91c is retained. It has become.

  In the slot machine 1 of this embodiment, the medal payout rate changes according to the set value, and the winning probability of the internal lottery described later is determined according to the set value. Hereinafter, the setting value changing operation will be described.

  In order to change the setting value, it is necessary to turn on the power of the slot machine 1 after the setting key switch 37 is turned on. When the power is turned on with the setting key switch 37 in the ON state, 1 is displayed as the initial value of the setting value on the setting value display 24, and the setting change mode in which the setting value can be changed by operating the reset / setting switch 38 is set. Transition. When the reset / setting switch 38 is operated in the setting change mode, the setting value displayed on the setting value display 24 is updated one by one (when further operation is performed from the setting 6, the setting value is returned to the setting 1). . When the start switch 7 is operated, the set value is confirmed, and the confirmed set value is stored in the RAM 41c of the main control unit 41. Then, when the setting key switch 37 is turned off, the state shifts to a state in which the game can proceed.

  In the slot machine 1 of the present embodiment, when the CPU 41a of the main control unit 41 detects a voltage drop signal, a power interruption interrupt process is executed. In the power interruption interrupt processing, the register is saved in a stack of a RAM 41c, which will be described later, and data for destructive diagnosis (5AH in this embodiment) in which any bit is 1 in the RAM 41c of the main control unit 41, that is, other than 0 In addition to storing specific data, the RAM parity adjustment data is calculated so that the RAM parity based on the data stored in all areas of the RAM 41c becomes 0, and stored in the RAM 41c. The RAM parity is a value calculated as an exclusive OR of values stored in each bit of the corresponding area (all areas in this embodiment) of the RAM 41c. Therefore, if the RAM parity based on the data stored in all areas of the RAM 41c is 0, the RAM parity adjustment data is 0, and the RAM parity based on the data stored in all areas of the RAM 41c is 1. In this case, the RAM parity adjustment data is 1.

  The CPU 41a calculates the RAM parity based on the data stored in all areas of the RAM 41c at the time of activation, confirms the value of the destructive diagnosis data, the RAM parity is 0, and the destructive diagnosis On the condition that the data value is also correct, the processing state of the CPU 41a is restored to the state before the power interruption based on the data stored in the RAM 41c, but when the RAM parity is not 0 (in the case of 1) or for destructive diagnosis If the data value is not correct, it is determined that the RAM is abnormal, and a RAM abnormal error code is set in the register to control the RAM abnormal error, thereby disabling the progress of the game. Unlike the other error states, the RAM abnormal error state is not canceled even if the reset switch 23 or the reset / setting switch 38 is operated, and a new set value is set in the setting change mode described above. It will not be released until

  Further, the CPU 41a determines whether or not the bet number set in the internal lottery process described later is a bet number according to the gaming state, and whether or not the set value used for the internal lottery is an appropriate value. judge.

  Even when the set bet number is not the bet number according to the gaming state, or when the set value used for the internal lottery is not an appropriate value, it is determined that the RAM is abnormal and the RAM abnormal error code is set and the RAM is set. The game is controlled to an abnormal error state and the progress of the game is disabled. As described above, unlike the other error states, the RAM abnormal error state is not canceled even if the reset switch 23 or the reset / setting switch 38 is operated, and a new setting is made in the setting change mode described above. It will not be released until a value is set.

  In the slot machine 1 according to the present embodiment, the prescribed number of bets that can be set according to the gaming state is determined as described above, and the prescribed number of bets that are determined according to the gaming state is set. It becomes possible to start the game on the condition. In this embodiment, there are a regular bonus and a normal gaming state as the gaming state. Among these, 1 is defined as the prescribed number of bets corresponding to the regular bonus, and the prescribed number of bets corresponding to the normal gaming state is as follows. 3 is defined. For this reason, when the gaming state is a regular bonus, the game can be started when the betting number is set to 1, and when the gaming state is the normal gaming state, the game is started when the betting number is set to 3. Can be started. In this embodiment, when a specified number of bets corresponding to the gaming state is set, all winning lines L1 to L5 are activated, and the specified number corresponding to the gaming state is If it is 1, all winning lines L1 to L5 are activated when 1 is set as the bet number, and if the specified number is 3 according to the gaming state, 3 is set as the bet number. All winning lines L1 to L5 are activated.

  In the slot machine 1 of this embodiment, when all the reels 2L, 2C, 2R are stopped, the activated pay line (in the present embodiment, all the pay lines are always enabled. The activated winning line is simply referred to as a winning line), and a winning combination is obtained when a combination of symbols called “comb” is arranged. The type of winning combination is determined according to the game state, but it can be roughly divided into a small role with payout of medals and a replay that can start the next game without the need to set the number of bets. There are a game combination and a special combination with a transition of the game state. Below, a small role and a re-playing role are collectively called a general role. In order for winning of each combination determined according to the gaming state to occur, it is necessary to win an internal lottery to be described later and set a winning flag of the combination in the RAM 41c.

  Of the winning flags for each of these combinations, the winning flag for the small role and the re-playing role is valid only in the game in which the flag is set, and is invalid in the next game. It is valid until the combination of combinations permitted by the flag is complete, and is invalid in a game having the combination of combinations permitted. In other words, once the winning flag for a special role is won, even if the combination of characters allowed by the flag cannot be aligned, the winning flag is not invalidated and is carried over to the next game. It becomes.

  In the slot machine 1, as a special role, a big bonus (1), a big bonus (2), a regular bonus, a cherry, 1 (1), 1 (2), and a bell as a small role are replayed. Replay is defined as a role. In addition, combinations of combinations in the slot machine 1 include big bonus (1) + cherry, big bonus (2) + cherry, big bonus (1) +1 (1), big bonus (2) +1 (1), Big bonus (1) +1 (2) and big bonus (2) +1 (2) are defined.

  In the slot machine 1 of the present embodiment, the combination and combination of combinations that are the objects of the lottery differ depending on whether the gaming state is a normal gaming state or a regular bonus. Furthermore, when the gaming state is the normal gaming state, it depends on whether any special role is being carried over (whether any special role has already been set in the winning flag of the special role). The combination of combinations and combinations that are subject to lottery are also different. In this embodiment, a state number corresponding to the gaming state is assigned, and when performing an internal lottery, a state number corresponding to the current gaming state is set, and a role to be a lottery object is determined according to this state number. It becomes possible to specify. Specifically, when no special combination is carried over in the normal gaming state, “0” is set as the state number, and when any special combination is carried over in the normal gaming state, “1” is set as the state number, and “2” is set as the state number in the case of a regular bonus.

  When the gaming state is the normal gaming state and no special roles are carried over, that is, when the state number is set to “0”, the big bonus (1), big bonus (2), regular bonus Big Bonus (1) + Cherry, Big Bonus (2) + Cherry, Big Bonus (1) + 1 (1), Big Bonus (2) + 1 (1), Big Bonus (1) + 1 (2), Big Bonus (2) +1 (2), Replay, Cherry, 1 (1), 1 (2), and Bell are subject to internal lottery. When the game state is the normal game state and any special role is carried over, that is, when the state number is set to “1”, replay, cherry, 1 (1), 1 The sheet (2) and the bell are subject to internal lottery. When the game state is a regular bonus, that is, “3” is set as the state number, cherry, 1 (1), 1 (2), bell, that is, the role and the combination of the combination after the combination number 11 The combination is subject to internal lottery.

  Cherry is awarded when the “Cherry” symbol is derived on one of the winning lines for the left reel in any gaming state, and two medals are paid out in the normal gaming state. 15 medals are paid out. If the “Cherry” symbol stops at the upper or lower level of the left reel, the combination of cherries will be aligned on the two winning lines L2 and L4 or the winning lines L3 and L5. Since you won the cherry on the winning line, 4 medals will be paid out in the normal gaming state, but in the regular bonus, even if you win the cherry on the 2 winning lines, one game Since the upper limit of the number of medals to be paid out at 15 is set to 15, only 15 medals are paid out. One (1) is awarded when the combination of “Blue 7-Red 7-Watermelon” is aligned on any of the winning lines in any gaming state, and one medal is paid out in the normal gaming state. In the regular bonus, 15 medals are paid out. One (2) is awarded when the combination of “Red 7-Blue 7-Watermelon” is aligned on any of the winning lines in any gaming state, and one medal is paid out in the normal gaming state. In the regular bonus, 15 medals are paid out. A bell is awarded when a combination of “Bell-Bell-Bell” is placed on any of the winning lines in any gaming state, and in the normal gaming state, 8 medals are paid out. 15 medals are paid out.

  Replay is awarded when a combination of “Replay-Replay-Replay” is arranged on any of the winning lines in the normal gaming state, but with the regular bonus, even if this combination is arranged, the replay is not won. When a replay is won, the medals will not be paid out, but the next game can be started without setting the number of bets again, so the number of bets no longer required to be set in the next game (the regular bonus will not be replayed and will always be 3) This is substantially the same as when three corresponding medals are paid out.

  The regular bonus is awarded when a combination of “red 7-red 7-BAR” is arranged on any of the winning lines in the normal gaming state. When the regular bonus is won, the gaming state shifts from the normal gaming state to the regular bonus. The regular bonus ends when 12 games are consumed, or when 8 games are won (any kind of combination is possible), whichever comes first. While the game state is in the regular bonus, the regular bonus medium flag is set in the RAM 41c.

  The big bonus is awarded when a combination of “red 7-red 7-red 7” or a combination of “blue 7-blue 7-blue 7” is arranged on any of the winning lines in the normal gaming state. When the big bonus is won, the gaming state shifts to the big bonus. When transitioning to the big bonus, the transition to the regular bonus is performed at the same time as the transition to the big bonus, and when the regular bonus ends, if the big bonus is not terminated, the transition is made to the regular bonus again and repeated until the big bonus is terminated. Controlled by regular bonus. That is, during the big bonus, the regular bonus is always controlled. The big bonus ends when the total number of medals paid out to the player in the big bonus reaches 466. At this time, the regular bonus is ended regardless of whether the regular bonus end condition is satisfied. While the game state is the big bonus, the big bonus medium flag is set in the RAM 41c.

  When it is necessary to distinguish between the big bonus by “red 7-red 7-red 7” and the big bonus by “blue 7-blue 7-blue 7”, the big bonus (1) and the big bonus (2 ). Further, the regular bonus, the big bonus (1), and the big bonus (2) described above may be collectively referred to simply as “bonus”.

  Hereinafter, the internal lottery of the present embodiment will be described. In the internal lottery, it is determined whether or not the above winning combination is permitted before the display results of all the reels 2L, 2C, and 2R are derived and displayed (actually, when the start switch 7 is detected). To do. In the internal lottery, first, a random number for internal lottery (an integer from 0 to 16383) is acquired as described later. And, for each combination of combinations and combinations determined according to the gaming state, according to the obtained random number for internal lottery and the number of judgment values of each combination of combinations and combinations determined according to the gaming state and setting value Done. In this embodiment, based on the number of judgment values for each combination and combination of combinations, a range of determination values for each of the general combination and special combination, and a range of determination values for the combination of general combination and special combination is won. And the winning in the internal lottery is not exclusive, and a general combination and a special combination may be won simultaneously in one game.

  When winning of any combination or combination of combinations is determined, a winning flag corresponding to the combination or combination of combinations determined to be selected is set in the special combination storing work and the general combination storing work assigned to the RAM 41c. To do. Specifically, when a special combination is won, a special combination winning flag indicating that the special combination is won is set in the special combination storing work, and the winning flag set in the general combination storing work is cleared. In addition, when a special role + general role is won, a special role winning flag indicating that the special role is won is set in the special role storage work, and a general role winning indicating that the general role is won Set the flag in the general role storage work. When a general combination is won, a winning flag for the general combination indicating that the general combination is won is set in the general combination storing work. If no winning combination is selected, only the general winning combination work is cleared.

  The big bonus (1), the big bonus (2), and the regular bonus winning are accompanied by a transition of the gaming state, and are not eligible for paying out medals. The replay does not involve the payout of medals, but it is substantially the same as the payout of 3 medals since it is not necessary to insert medals used for setting the bet amount in the next game (always the normal gaming state).

  FIG. 3 is a circuit diagram for explaining a configuration around the main control unit 41 in the game control board 40.

  First, a circuit for automatically resetting the slot machine 1 upon power interruption will be described.

  The + 5V DC voltage supply line in the game control board 40 branches on the game control board 40 to form a + 5V (VBB) DC voltage supply line, as shown in FIG. The +5 V (VBB) DC voltage supply line is connected to the backup power supply input terminal VBB via a backflow prevention diode 312.

  Further, of the DC voltage output from the power supply board 75, + 25V DC voltage is reduced by the resistor 311 in the game control board 40 as shown in FIG. 3 (about 6.6% reduction in this embodiment). Then, it is input to the monitoring voltage input terminal VSB included in the power interruption detection circuit 48. The power interruption detection circuit 48 outputs a voltage drop signal from the voltage drop signal output terminal RESET when the voltage input to the monitoring voltage input terminal VSB becomes a predetermined level (+1.2 V in this embodiment) or less. It is configured to output.

  The voltage drop signal output terminal RESET is connected to the trigger terminal CLK / TRG2 of the main control unit 41 as described above, and when the voltage input to the monitoring voltage input terminal VSB becomes a predetermined level or less. The voltage drop signal is input to the trigger terminal CLK / TRG2 of the main control unit 41. That is, the CPU 41 a of the main control unit 41 can detect the occurrence of power interruption based on the input of the voltage drop signal from the power interruption detection circuit 48 and can execute a power interruption interrupt process to be described later. In this embodiment, when the + 25V DC voltage becomes about + 18V or less, the voltage reduced by the resistor 311 becomes + 1.2V or less and a voltage drop signal is output. Therefore, the CPU 41a is based on the input of the voltage drop signal. Thus, the occurrence of power interruption can be detected when the + 25V DC voltage becomes + 18V or less.

  Further, the voltage drop signal output terminal RESET branches in the middle and is input to the switch detection circuit 44, converted as appropriate by the switch detection circuit 44, and output to the signal input / output terminal DATA of the main control unit 41. When the voltage input to the monitoring voltage input terminal VSB becomes less than a predetermined level, the voltage drop signal is input to the signal input / output terminal DATA in addition to the trigger terminal CLK / TRG2 of the main control unit 41. It has become so. In addition, the power interruption detection circuit 48 becomes inoperable or the voltage is not supplied after the voltage input to the monitoring voltage input terminal VSB becomes a predetermined level (+1.2 V) or less. The voltage drop signal is continuously output until it exceeds a predetermined magnitude (+1.2 V). Therefore, the CPU 41a can monitor the input state of the voltage drop signal even during the power interruption interrupt process based on the input of the voltage drop signal from the power interruption detection circuit 48.

  Next, a circuit for automatically resetting the slot machine 1 when the CPU 41a is disabled will be described.

  The signal input / output by the main control unit 41 via the signal input / output terminal DATA is composed of a plurality of signal lines, all of which are data input terminals of the output conversion circuit 410 as shown in FIG. Input to IN. Among the signals output from the main control unit 41, there are signals output when the CPU 41a is operating normally. The output conversion circuit 410 to which this signal is input operates the CPU 41a normally. Is continuously output from the data output terminal OUT. It is assumed that the operation detection signal is output at a time interval shorter than a later-described watchdog time limit.

  The operation detection signal output from the data output terminal OUT is input to the watchdog input terminal WD of the reset circuit 49. Here, the watchdog circuit 411 mounted on the reset circuit 49 will be described. The watchdog circuit 411 has passed a predetermined watchdog time limit in a state where a signal input to the watchdog input terminal WD is not detected. This is a circuit that outputs a reset signal to the reset output terminal RESET on the condition that the elapsed time is measured again from 0 on condition that a signal input to the watchdog input terminal WD is detected. Note that the watchdog time limit is based on a CR circuit (capacitance of the resistor R and the capacitor C) formed between the power supply terminal Vcc, the sub power supply terminal Tc, and the ground terminal GND of the reset circuit 49, as shown in FIG. It is determined.

  The reset signal output from the reset output terminal RESET of the reset circuit 49 is input to the reset input terminal RESET of the main control unit 41. The main control unit 41 performs the activation process shown in FIG. 7 on condition that an input signal to the reset input terminal RESET is detected.

  As described above, when the CPU 41a is not operating normally (in a runaway state), the operation detection signal is not output from the data output terminal OUT of the output conversion circuit 410, and the signal to the watchdog input terminal WD of the reset circuit 49 is output. Input is interrupted. The watchdog circuit 411 of the reset circuit 49 measures the elapsed time from the previous signal input to the WD, and when the elapsed time reaches the watchdog limit time, the reset signal is sent to the reset terminal of the main control unit 41. Output to RESET to reset the main control unit 41. That is, the slot machine 1 of the present embodiment is automatically reset when the CPU 41a is disabled (runaway) and a predetermined time elapses.

  FIG. 4 is a timing chart of processing for automatically resetting the slot machine 1 when an unused interrupt occurs.

  As described above, in this embodiment, when a signal input is detected with respect to INT or NMI that is an interrupt input terminal due to noise or the like, a maskable interrupt or a non-maskable interrupt that is a corresponding unused interrupt is detected. Then, the CPU 41a immediately executes an unused interrupt process (to be described later) that immediately shifts the CPU 41a to the disabled (runaway) state. After the CPU 41a shifts to the disabled (runaway) state, the slot machine 1 is automatically reset by the reset circuit 49 when the aforementioned watchdog time limit elapses.

  More specifically, as shown in FIG. 4, when the CPU 41a is in a normal state, an operation detection signal is continuously output from the data output terminal OUT of the output conversion circuit 410 and input to the watchdog input terminal WD of the reset circuit 49. Is done. In the reset circuit 49, since the elapsed time is measured again from 0 every time a signal input to the watchdog input terminal WD is detected, no signal is output to the reset output terminal RESET of the reset circuit 49.

  At this time, when a maskable interrupt (INT) or a non-maskable interrupt (NMI) that is an unused interrupt occurs, an unused interrupt process described later is executed, and the CPU 41a shifts to an impossible (runaway) state. As a result, the operation detection signal is not output from the data output terminal OUT of the output conversion circuit 410, and the signal input to the watchdog input terminal WD of the reset circuit 49 is interrupted. When the watchdog time limit elapses in this state, a signal is output to the reset output terminal RESET of the reset circuit 49, and the signal input is detected at the reset input terminal RESET of the main control unit 41. The main control unit 41 that has detected the signal input to the RESET executes the activation process of the slot machine 1 (see FIG. 7).

  Next, initialization of the RAM 41c of the main control unit 41 will be described. The RAM 41c of the main control unit 41 has a 512-byte storage area. As shown in FIG. 5, addresses 7E00 (H) to 7FFF (H) are assigned to each byte, and important work , General work, special work, set value work, unsaved work, unused area, stack area.

  The important work is an area of 40 bytes from 7E00 (H) to 7E27 (H), and it is a big bonus such as various display and LED display data, I / O port 41d input / output data, game time counter, etc. This work stores data that is inconvenient if it is initialized at the end.

  The general work is a 178-byte area of 7E28 (H) to 7E8E (H), 7EBA (H) to 7F04 (H), stop symbol data, the number of medals to be paid out, a winning combination flag, and a medal in a big bonus This work stores data that can be initialized at the end of the big bonus, such as the total number of payouts.

  The special work is a 39-byte area from 7E8F (H) to 7EB5 (H), and data for transmitting commands to the effect control board 90, various software random numbers, etc., are initialized only before the start of setting. The work to be stored.

  The set value work is a 1-byte area of 7EB6 (H) and is a work in which the set value is stored. After 0 is stored in the initialization before the setting is started (before the transition to the setting change mode), It is corrected to 1, and the set value newly set at the end of the setting (at the end of the setting change mode) is stored.

  The unsaved work is a 3-byte area of 7EB7 (H) to 7EB9 (H), and is a work that holds the state of various switches as the state of the stop switch 36. The data in the RAM 41c is destroyed at the time of startup. A value is always set regardless of whether it is present or not.

  The unused area is a 205-byte area from 7F05 (H) to 7FD1 (H) and is an unused area in the storage area of the RAM 41c, and any one of a plurality of initialization conditions to be described later is satisfied. Then it will be initialized.

  The stack area is a 46-byte area from 7FD2 (H) to 7FFF (H), and the area from 7FD2 (H) to stack pointer-1 is an unused stack area in the stack area. The area of the stack pointer to 7FFF (H) is an in-use stack area in which data saved from the register of the CPU 41a is stored. Of these, the unused stack area is initialized as long as any one of a plurality of initialization conditions to be described later is satisfied, as in the unused area. Therefore, it is not initialized.

  In this embodiment, as shown in FIG. 6A, the CPU 41a of the main control unit 41 does not destroy the data in the RAM 41c before the start of setting (before the transition to the setting change mode), at the end of the big bonus, or at the time of activation. At the time, when four initialization conditions at the end of one game are satisfied, four types of initializations with different areas initialized according to each initialization condition are performed.

  Initialization 1 is an initialization that is performed before the setting key switch 37 is turned on at the time of startup and shifts to the setting change mode. In the initialization 1, the use of the storage area of the RAM 41c is used. All areas except the middle stack area (including unused areas and unused stack areas) are initialized. Initialization 2 is initialization performed at the end of the big bonus. In initialization 2, the general work, the unused area, and the unused stack area are initialized in the storage area of the RAM 41c. Initialization 3 is initialization that is performed when the setting key switch 37 is in an OFF state at the time of startup and the data in the RAM 41c is not destroyed. The used stack area is initialized. Initialization 4 is initialization performed at the end of one game. In initialization 4, an unused area and an unused stack area in the storage area of the RAM 41c are initialized.

  In the ROM 41b, the start address of the area to be initialized and the initialization size indicating the size of the area to be initialized are registered corresponding to each of initializations 1 to 4, and when the CPU 41a initializes the RAM 41c. Refers to the initialization table, acquires the start address and initialization size corresponding to any of initializations 1 to 4 according to the initialization condition, sets a pointer to the start address, and sets the initialization size . If the initialization size includes the size of the unused stack area, the size of the unused stack area (stack pointer-7FD2 (H)) is calculated and the initialization size is set. Then, the area of the address corresponding to each byte from the initialization address where the pointer is set is cleared to 0, and each time the byte is cleared, the initialization size is decremented by 1 and the pointer is advanced by 1. Run until zero. That is, when the CPU 41a initializes the RAM 41c, it does not initialize each area according to the initialization condition, but initializes an area of a specified size from a specified address.

  FIG. 6B shows an initialization table. In the initialization table, the start address and the initialization size are registered corresponding to the initializations 1 to 4 as described above.

  In initialization 1, 7E00 (H) is registered as the start address, and 1D3 (H) + M (size of unused stack area: (stack pointer−7FD2)) bytes are registered as the initialization size. 7E00 (H) to 1D3 (H) + M bytes are initialized. Then, as shown in FIG. 16, important work, general work, special work, set value work, unsaved work, general work, unused area, and unused stack area are allocated to address areas that are continuous from 7E00 (H). The sum of the sizes of these areas is 1D3 (H) + M bytes. Therefore, in initialization 1, 7D00 (H) is initialized to 1D3 (H) + M bytes, so that These areas are initialized in the order of general work, special work, set value work, non-saved work, general work, unused area, and unused stack area.

  In initialization 2, two start addresses and initialization sizes for each address are registered. This is because the general work initialized in the initialization 2 is allocated to two separate address areas. In initialization 2, 7E28 (H) is registered as the start address of the area to be initialized first, 67 (H) bytes are registered as the initialization size, and 7EB7 (H) is set as the start address of the area to be initialized next. Since 119 (H) + M bytes are registered as the conversion sizes, in initialization 2, an area for 7E28 (H) to 67 (H) bytes and an area for 7EB7 (H) to 119 (H) + M bytes Is initialized. The size of the general workpieces 7E28 (H) to 7E8E (H) is 67 (H) bytes. As shown in FIG. 16, the remaining general workpiece area, unused area, and unused stack area are 7EB7 ( H) are allocated to consecutive address areas, and the total size of these areas is 119 (H) + M bytes. Therefore, in initialization 2, 7E28 (H) to 67 (H) bytes are initialized, By initializing 7EB7 (H) to 119 (H) + M bytes, these areas are initialized in the order of general work, unused area, and unused stack area.

  Also in the initialization 3, two start addresses and initialization sizes for each address are registered. This is because the non-saved work initialized in the initialization 3 and the unused area and the unused stack area are allocated to two separate address areas. In initialization 3, 7EB7 (H) is registered as the start address of the area to be initialized first, 3 (H) bytes are registered as the initialization size, and 7F05 (H) is set as the start address of the area to be initialized next. Since CE (H) + M bytes are respectively registered as the conversion size, in initialization 3, an area from 7EB7 (H) to 3 (H) bytes and an area from 7F05 (H) to CE (H) + M bytes Is initialized. As shown in FIG. 16, the unsaved work is an area for 3 bytes from 7EB7 (H), and the unused area and the unused stack area are allocated to address areas that are continuous from 7F05 (H). Since the sum of the sizes of these areas is CE (H) + M bytes, in initialization 3, 7EB7 (H) to 3 (H) bytes are initialized, and 7F05 (H) to CE (H) + M bytes. When the minutes are initialized, these areas are initialized in the order of the non-saved work, the unused area, and the unused stack area.

  In initialization 4, 7F05 (H) is registered as the start address, and CE (H) + M bytes are registered as the initialization size. Therefore, in initialization 4, an area from 7F05 (H) to CE (H) + M bytes is registered. Is initialized. As shown in FIG. 16, the unused area and the unused stack area are allocated to address areas that are continuous from 7F05 (H), and the total size of these areas is CE (H) + M bytes. Therefore, in initialization 4, the CE (H) + M bytes from 7F05 (H) are initialized, so that these areas are initialized in the order of the unused area and the unused stack area. .

  In addition, initializations 1 and 3 among initializations 1 to 4 are processes performed after the CPU 41a is started and before an interrupt is permitted. On the other hand, the initializations 2 and 4 are processes performed in a state where interrupts are permitted, but interrupts are prohibited during the execution of these initializations 2 and 4. That is, interrupts are always prohibited during the initializations 1-4.

  In this embodiment, to initialize the storage area of the RAM 41c is to clear the data in the target area to 0, that is, to update the value of the target area to 0. The area data may be rewritten to a predetermined initial value.

  Next, initialization of the RAM 41c of the main control unit 41 will be described. The storage area of the RAM 41c of the main control unit 41 is divided into an important work, a general work, a special work, a set value work, a non-saved work, an unused area, and a stack area.

  The important work is a work that stores data that is inconvenient to be initialized at the end of the big bonus, such as various display devices and LED display data, input / output data of the I / O port 41d, and a game time counter. The general work is a work that stores data that can be initialized at the end of the big bonus, such as a stop control table, a stop symbol, the number of medals paid out, and the total number of medals paid out during the big bonus. The special work is a work that stores data to be initialized only before the start of setting, such as data for transmitting a command to the effect control board 90 and various software random numbers. The set value work is a work in which a set value used when performing lottery in the internal lottery process is stored, and is set to 1 after 0 is stored in the initialization before the setting is started (before the transition to the setting change mode). The set value that has been corrected and newly set at the end of the setting (at the end of the setting change mode) is stored. The unsaved work is a work that holds the state of various switches, and a value is always set regardless of whether or not the data in the RAM 41c is destroyed at the time of activation. The unused area is an unused area in the storage area of the RAM 41c, and is initialized if any one of a plurality of initialization conditions described later is satisfied. The stack area is an area in which data saved from the register of the CPU 41a is stored, and the unused stack area is satisfied by any one of a plurality of initialization conditions to be described later, like the unused area. However, the used stack area is not initialized because the program continues.

  In this embodiment, the CPU 41a of the main control unit 41 starts from the four at the end of one game when the data in the RAM 41c is not destroyed before the start of setting (before the transition to the setting change mode), at the end of the big bonus, and at the start. When the initialization condition is satisfied, four types of initializations with different areas initialized according to each initialization condition are performed.

  Initialization 1 is an initialization that is performed before the setting key switch 37 is turned on at the time of startup and shifts to the setting change mode. In the initialization 1, the use of the storage area of the RAM 41c is used. All areas except the middle stack area (including unused areas and unused stack areas) are initialized. Initialization 2 is initialization performed at the end of the big bonus. In initialization 2, the general work, the unused area, and the unused stack area are initialized in the storage area of the RAM 41c. Initialization 3 is initialization that is performed when the setting key switch 37 is in an OFF state at the time of startup and the data in the RAM 41c is not destroyed. The used stack area is initialized. Initialization 4 is initialization performed at the end of one game. In initialization 4, an unused area and an unused stack area in the storage area of the RAM 41c are initialized.

  Next, various control contents executed by the CPU 41a of the main control unit 41 in the present embodiment will be described below with reference to FIGS.

  When a reset signal is input from the reset circuit 49, the CPU 41a performs a startup process shown in the flowchart of FIG. Since the reset signal is a signal output when the power is turned on and when the operation of the main control unit 41 is disabled (runaway), the activation process is performed when the CPU 41a is activated when the power is turned on and when the CPU 41a is activated. This process is performed when restarting due to a problem.

  In the start-up process, first, the built-in device, peripheral IC, interrupt mode, stack pointer, etc. are initialized (Sa1), then the voltage drop signal detection data is acquired from the input port, and whether or not the voltage drop signal is input. That is, it is determined whether or not the voltage is stable (Sa2), and if the voltage drop signal is input, any processing is performed except for determining whether or not the voltage drop signal is input. There is no loop processing.

  If it is determined in step Sa2 that the voltage drop signal is not input, the values of the I register and IY register are initialized (Sa3), the state of the stop switch 36 is acquired, and a specific register of the CPU 41a is acquired. The valid / invalid of the stop function is set in (Sa4). By the initialization of the I register and the IY register, the address of the interrupt table to be referred to when an interrupt occurs is set in the I register, and the reference address for referring to the storage area of the RAM 41c is set in the IY register. . These values are fixed values and are always initialized at startup.

  Next, access to the RAM 41c is permitted (Sa5), and it is determined whether or not the setting key switch 37 is in an ON state (Sa6). If the setting key switch 37 is not in the ON state in step Sa6, the RAM parity of all storage areas (including the unused area and the unused stack area) of the RAM 41c is calculated (Sa7). Is determined (Sa8). If the power interruption interrupt processing is normally performed, the RAM parity should be 0. If the RAM parity is not 0 in the step of Sa8, the data stored in the RAM 41c is not normal. An error code indicating abnormality is set in the register (Sa10), and the process proceeds to error processing shown in FIG.

  If the RAM parity is 0 in step Sa8, it is further determined whether or not the destructive diagnosis data is normal (Sa9). If power interruption interrupt processing is performed normally, the data for destruction diagnosis should be set. If the data for destruction diagnosis is not normal in step Sa9 (the data for destruction diagnosis is stored at the time of power interruption. In the case other than 5A (H), the data in the RAM 41c is not normal, so an error code indicating a RAM abnormality is set in the register (Sa10), and the process proceeds to the error processing shown in FIG.

  In the error processing, as shown in FIG. 8, the current display state of the game auxiliary display 12 is saved in the stack (Sb1), and the error code stored in the register is displayed on the game auxiliary display 12 (Sb2). .

  Next, the error code stored in the register is confirmed, it is determined whether or not the error code is an error code indicating a RAM abnormal error (Sb3), and the error code indicates an error code indicating a RAM abnormal error. In this case, after initialization 1 is performed to initialize all the storage areas except the used stack area in the storage area of the RAM 41c (Sb4), the process proceeds to a loop process in which no process is performed.

  If it is determined in step Sb3 that the error code is not an error other than a RAM abnormality, it is determined whether an operation of the reset / setting switch 38 is detected (Sb5), and the reset / setting switch 38 is detected. If the operation of the reset switch 23 is not detected, it is further determined whether or not the operation of the reset switch 23 is detected (Sb6). If the operation of the reset switch 23 is not detected, the process returns to the step Sb4. That is, the game waits in a state where the progress of the game is impossible until the operation of the reset / setting switch 38 or the reset switch 23 is detected.

  When the operation of the reset / setting switch 38 is detected in the step Sb5, or when the operation of the reset switch 23 is detected in the step Sb6, the error code stored in the register is cleared (Sb7 ), The display state of the game auxiliary display 12 is returned to the display state saved in the stack in the step Sb1 (Sb8), and the process returns to the original process.

  As described above, in the error processing, if the error processing is other than the RAM abnormality error, the reset / setting switch 38 or the reset switch 23 is operated to return to the original processing even if the error state is canceled. In the case of error processing due to a RAM abnormality error, the error state is not canceled even if the reset / setting switch 38 or the reset switch 23 is operated.

  Returning to FIG. 7, if it is determined in step Sa9 that the data for destructive diagnosis is normal, the data in the RAM 41c is normal. Therefore, the non-saved work, unused area, and unused stack area in the RAM 41c are initialized. After performing initialization 3 (Sa11), the destruction diagnosis data is cleared (Sa12). Next, each register is restored to the state before the power interruption, that is, the state saved in the stack (Sa13), the interrupt is permitted (Sa14), and the process that was executed last before the power interruption is returned.

  If the setting key switch 37 is in the ON state in the step of Sa6, after executing initialization 1 for initializing all storage areas in the storage area of the RAM 41c except the used stack area (Sa15), The value (0 at this time) stored in the set value work is corrected to 1 (Sa16). Next, interrupts are permitted (Sa17), and the setting change process shown in FIG. 9, that is, the setting change mode is entered (Sa18). After the setting change process is completed, the game process is entered.

  In the setting change process, as shown in FIG. 9, the setting value stored in the setting value work of the RAM 41c (the value of the setting value work is corrected to 1 before shifting to the setting changing process. Is read out (Sc1).

  Thereafter, the operation waits for detection of the operation of the reset / setting switch 38 and the start switch 7 (Sc2, Sc3). When the operation of the reset / setting switch 38 is detected in the step of Sc2, the setting value read in the step of Sc1. 1 is added (Sc4), and it is determined whether or not the set value after addition is 7, that is, whether or not the settable range is exceeded (Sc5). If the set value after addition is not 7, After returning to the detection waiting state for the operation of the reset / setting switch 38 and the start switch 7 in the steps Sc2 and Sc3 again, if the setting value after addition is 7 in the step Sc5, the setting value is corrected to 1 (Sc6). ), The process returns to the detection waiting state for the operation of the reset / setting switch 38 and the start switch 7 in the steps Sc2 and Sc3.

  When the operation of the start switch 7 is detected in the step of Sc3, the changed set value selected at that time is stored in the set value work of the RAM 41c and the set value is confirmed (Sc7). Wait until the setting key switch 37 is turned off (Sc8). If it is determined in step Sc8 that the setting key switch 37 is OFF, the process returns to the flowchart of FIG.

  As described above, in the startup process, when the setting key switch 37 is not in the ON state, it is stored in the RAM 41c by determining whether or not the RAM parity is 0 and whether or not the destructive diagnosis data is normal. It is determined whether or not the stored data is normal. If the data in the RAM 41c is not normal, the process proceeds to an abnormal error process. In the error processing due to the RAM abnormal error, an error code indicating the RAM abnormal error is displayed on the game auxiliary display 12, and then the process proceeds to a loop process in which no processing is performed, so that the progress of the game is disabled. If the data in the RAM 41c is not normal, interrupts are not permitted. Therefore, once the process shifts to error processing due to a RAM error, the setting key switch 37 is activated and interrupts are permitted. Until it is interrupted, no power interruption processing is performed even if the power is interrupted. That is, the RAM adjustment data is not calculated and stored so that the RAM parity is newly set to 0 in the power interruption interrupt process, and the destruction diagnosis data is not newly set. Even if the game is started, the game cannot be resumed even if the CPU 41a is restarted except when the setting key switch 37 is turned on.

  Once the process shifts to error processing due to a RAM abnormality error, the setting key switch 37 is activated in the ON state, and after all the areas except the used stack area of the RAM 41c are initialized, a setting change process is performed. The game cannot be progressed until a new set value is selected and set by operating the reset / setting switch 38. In other words, in the state where the error processing due to the RAM abnormality error is started, the state in which the game cannot be progressed is canceled and the game is resumed on the condition that a new set value is selected and set by operating the reset / setting switch 38. It becomes possible to make it.

  FIG. 10 is a flowchart showing the control contents of the game process executed by the CPU 41a.

  In the game process, a BET process (Sd1), an internal lottery process (Sd2), a reel rotation process (Sd3), a winning determination process (Sd4), a payout process (Sd5), and a game end process (Sd6) are executed in order. When the end-time process ends, the process returns to the BET process again.

  In the BET process in the step of Sd1, the process waits in a state where the bet number can be set, sets a predetermined number of bets according to the gaming state, and executes a process of determining the bet number when the start switch 7 is operated. To do.

  In the internal lottery process in step Sd2, a random number for internal lottery is extracted simultaneously with the start of the game by the detection of the start switch 7 in step Sd1, and the winning of each above-described combination is permitted based on the extracted random number value. Process to determine whether or not. In this internal lottery process, a winning flag is set in the RAM 41c based on the respective lottery results.

  In the reel rotation process in the step of Sd3, the process of rotating each reel 2L, 2C, 2R, and the operation of the stop switch 8L, 8C, 8R by the player is detected. A process for stopping the rotation is executed. In addition, when a predetermined automatic stop time has elapsed from the start of rotation of the reel, the rotation of the reels 2L, 2C, and 2R is automatically stopped without waiting for detection of the operation of the stop switches 8L, 8C, and 8R. Execute the process.

  In the winning determination process in the step Sd4, when it is determined in the step Sd3 that the rotation of all the reels 2L, 2C, and 2R is stopped, the winning is determined according to the display result derived for each reel 2L, 2C, and 2R. A process of determining whether or not it has occurred is executed.

  In the payout process in step Sd5, when it is determined that a prize is generated in step Sd4, processing such as addition of credits and payout of medals is performed based on the number of payouts according to the win.

  In the game end process in the step of Sd6, a process for setting a gaming state in preparation for the next game is executed.

  FIG. 11 is a flowchart showing the control contents of the internal lottery process executed by the CPU 41a in step Sd2.

  In the internal lottery process of the present embodiment, first, a prescribed number that is a predetermined number of medals inserted according to the game state of the game is read (Sg1), and the process proceeds to step Sg2. The prescribed number is 3 in the normal gaming state and 1 in the regular bonus gaming state.

  In step Sg2, it is determined whether or not the inserted number of medals, that is, the value of the BET counter is the specified number read in step Sg1, and if the inserted number of medals is the specified number, the process proceeds to step Sg3. If the input number is not the specified number, the process proceeds to step Sg4.

  In step Sg3, it is determined whether or not the set value stored in the set value work of the RAM 41c is in the range of 1 to 6, that is, whether or not the set value stored in the set value work is an appropriate value. If the set value is in the range of 1-6, the process proceeds to step Sg5, and if not, the process proceeds to step Sg4.

  In step Sg4, since it is determined that the data stored in the RAM 41c is not normal, an error code indicating a RAM abnormality is stored in the register, and the process proceeds to the error process shown in FIG.

  In the step of Sg5, a random number is acquired from the random number generation circuit 42, and a lottery process for lottery of whether each of the above-mentioned winning combinations is won based on the random number is performed, and a winning flag of the winning combination is set in the RAM 41c.

  In FIG. 12A, when a maskable interrupt (INT) or a non-maskable interrupt (NMI), which is an unused interrupt in the present embodiment, is generated, the CPU 41a interrupts and executes the activation process and the game process. It is a flowchart which shows the control content of an unused interruption process.

  The unused interrupt process shifts the CPU 41a to the disabled (runaway) state immediately after execution. Specifically, data that cannot be executed by the CPU 41a may be written in an area on the ROM 41c for storing a program corresponding to unused interrupt processing. As a result, the CPU 41a reads the program corresponding to the unused interrupt process, but cannot execute the program and thus becomes inoperable. Alternatively, an invalid address that does not exist on the ROM 41c may be set as an address indicating an area on the ROM 41c for storing a program corresponding to an unused interrupt process. As a result, the CPU 41a tries to read the program corresponding to the unused interrupt process, but cannot operate because it cannot read the program. In this way, the CPU 41a can be immediately shifted to the disabled (runaway) state when the unused interrupt process is performed.

  In this embodiment, in the unused interrupt process, the CPU 41a is shifted to the disabled (runaway) state. However, the present invention is not limited to this, and the unused interrupt process is normally terminated. In the process of returning from the unused interrupt process, the CPU 41a may be shifted to the disabled (runaway) state.

  Explaining the method, the interrupt process is originally performed by interrupting the activation process and the game process, and always returns to the process before the interrupt when the interrupt process ends. Specifically, the value of the program counter that is the return address at the start of interrupt processing is saved in the stack area, and the value of the program counter that was saved at the end of interrupt processing is restored and restored. By executing the program stored in the return address indicated by the program counter, the processing before the interruption is restored.

  Therefore, for example, in the step immediately after the start of the unused interrupt processing, if the value of the program counter serving as the return destination address is rewritten to an address on the ROM 41b in which data that shifts to the disabled (runaway) state is stored, After normal termination of the unused interrupt process, the CPU 41a can be shifted to the disabled (runaway) state. Specifically, as described above, the address on the ROM 41b in which data that cannot be executed by the CPU 41a or the address on the non-existing ROM 41b may be written as the value of the program counter serving as the return address.

  FIG. 13 shows the control contents of the power interruption processing executed when the CPU 41a interrupts and executes the activation processing and the game processing when the interruption 2 occurs, that is, when the voltage drop signal from the power interruption detection circuit 48 is input. It is a flowchart which shows.

  In the power interruption interruption process, first, interruption is prohibited (Sq1). That is, other interrupt processing is prohibited from being executed at the start of the power interruption interrupt processing. Next, all registers that may be in use are saved in the stack area (Sq2). Note that the values of the I register and IY register described above are used, but are not saved here because the same fixed value is always set with the initialization at the time of startup.

  Next, the detection data of the voltage drop signal is acquired from the input port, and it is determined whether or not the voltage drop signal is input (Sq3). At this time, if the voltage drop signal is not input, the register saved in the stack area in Sq2 is restored (Sq4), the interrupt prohibited in the step of Sq1 is permitted (Sq5), and the process before the interrupt is performed. Return.

  If a voltage drop signal is input in step Sq3, destruction diagnosis data (5A (H) in this embodiment) is set (Sq6), and all output ports are initialized (Sq7). . Next, RAM parity adjustment data is calculated and set so that the exclusive OR of all storage areas (including unused areas and unused stack areas) of the RAM 41c becomes 0 (Sq8), and access to the RAM 41c is performed. It is prohibited (Sq9).

  Then, except for the determination of whether or not the voltage drop signal is input (Sq10, where Sq10 is the same processing as Sq3), the processing enters a loop processing in which no processing is performed. That is, when the voltage decreases as it is, the operation is stopped internally. Therefore, the CPU 41a reliably stops operation when the power is interrupted. Further, in this loop processing, when the voltage recovers and the voltage drop signal is not input, the above-described startup processing is executed, and if the RAM parity is 0 and the destructive diagnosis data is normal, the original processing is performed. It will return to.

  In this embodiment, after the access to the RAM 41c is prohibited, the output state of the voltage drop signal is monitored, and when the voltage drop signal is not input, it is determined that the voltage is restored, and the process proceeds to the startup process. However, no processing is performed in the loop processing, and the voltage is recovered while the loop processing is being performed, and the process proceeds to the start-up processing based on the input of the reset signal from the reset circuit 49. You may make it do.

  Next, the control contents of initialization 1 to 4 executed by the CPU 41a in response to the establishment of the initialization condition will be described with reference to the flowcharts of FIGS.

  FIG. 14 is a flowchart showing the control contents of initialization 1 executed by the CPU 41a before shifting to the setting change mode in the startup process.

  In the initialization 1, first, the initialization table of the ROM 41b is referred to, and the start address and the initialization size registered corresponding to the initialization 1 are read (Sr1). A pointer is set to the read start address (7E00 (H)) (Sr2). Next, the size of the unused stack area (M = stack pointer−7FD2 (H)) is calculated (Sr3), and the number of bytes (1D3 (H) + M) of the area to be initialized is set (Sr4). Then, a RAM clear process for clearing data from the start address set in Sr2 over the number of bytes set in Sr4 is executed (Sr5). When the RAM clear process is completed, the initialization 1 is completed. Return to.

  FIG. 15 is a flowchart showing the control contents of the RAM clear process executed in step Sr5 of FIG.

  In the RAM clear process, 1 byte data indicated by the address indicated by the pointer is cleared to 0 (Sr101), and 1 is subtracted from the initialization byte number (the number of bytes set as an area to be initialized) (Sr102). Next, it is determined whether or not the number of initialized bytes after subtraction has become 0, that is, whether or not the initialization of all the specified number of bytes has been completed (Sr103). If the initialized byte number after subtraction is not 0, the pointer is advanced by 1 (Sr104), the process returns to Sr101, and the processes of Sr101 to Sr4 are repeated until the initialized byte number becomes 0. If the initialization byte number after subtraction in step Sr103 is 0, the initialization of all the specified number of bytes is completed, so the RAM clear process is terminated and the process returns to the original process. .

  FIG. 16 is a flowchart showing the control contents of initialization 2 executed by the CPU 41a at the end of the big bonus in the game end processing of Sd8.

  In the initialization 2, first, interrupts are prohibited (Sr11), and then the start address and the initialization size registered corresponding to the initialization 2 are read with reference to the initialization table of the ROM 41b (Sr12). In initialization 2, since two start addresses and initialization sizes corresponding to the two start addresses are registered, a pointer is set at the start address (7E28 (H)) of the area to be initialized first among the read start addresses. (Sr13), the number of bytes (67 (H)) of the area to be initialized first is set (Sr14), and the RAM clear process for clearing data from the start address set in Sr13 over the number of bytes set in Sr14 (See FIG. 15) is executed (Sr15). When the RAM clear process is completed, the pointer is set to the start address (7EBA (H)) of the second area to be initialized among the read start addresses (Sr16), and the size of the unused stack area (M = stack pointer− 7FD2 (H)) is calculated (Sr17), and the number of bytes (119 (H) + M) of the second area to be initialized is set (Sr18). Then, a RAM clear process (see FIG. 15) for clearing data from the start address set in Sr16 to the number of bytes set in Sr18 is executed (Sr19). When the RAM clear process is completed, the process is prohibited in the Sr11 step. The interrupt that has been made is permitted (Sr20), and the process returns to the original process even after the initialization 2 is completed.

  FIG. 17 is a flowchart showing the control contents of initialization 3 executed when the data in the RAM 41c is normal in the startup process by the CPU 41a.

  In the initialization 3, first, the initialization table of the ROM 41b is referred to, and the start address and the initialization size registered corresponding to the initialization 3 are read (Sr21). Since two start addresses and initialization sizes corresponding to the two start addresses are registered in initialization 3, a pointer is set at the start address (7EB7 (H)) of the area to be initialized first among the read start addresses. (Sr22), the number of bytes (3 (H)) of the area to be initialized first is set (Sr23), and the data is cleared from the start address set in Sr22 over the number of bytes set in Sr23. (See FIG. 15) is executed (Sr24). When the RAM clear process is completed, the pointer is set to the start address (7F05 (H)) of the second area to be initialized among the read start addresses (Sr25), and the size of the unused stack area (M = stack pointer− 7FD2 (H)) is calculated (Sr26), and the number of bytes (CE (H) + M) in the second area to be initialized is set (Sr27). Then, a RAM clear process (see FIG. 15) for clearing data from the start address set in Sr25 to the number of bytes set in Sr27 is executed (Sr28). When the RAM clear process is completed, initialization 3 is ended. Return to the original process.

  FIG. 18 is a flowchart showing the control contents of initialization 4 executed for each game by the CPU 41a in the game end process of Sd8.

  In the initialization 4, first, interrupts are prohibited (Sr31), and then the start address and the initialization size registered corresponding to the initialization 4 are read with reference to the initialization table of the ROM 41b (Sr32). A pointer is set to the read start address (7F05 (H)) (Sr33). Next, the size of the unused stack area (M = stack pointer-7FD2 (H)) is calculated (Sr34), and the number of bytes (CE (H) + M) of the area to be initialized is set (Sr35). Then, a RAM clear process (see FIG. 15) for clearing data from the start address set in Sr33 over the number of bytes set in Sr5 is executed (Sr36). When the RAM clear process is completed, it is prohibited in the step of Sr31. The interrupt is permitted (Sr37), and the process returns to the original process even after the initialization 4 is completed.

  As described above, in the slot machine 1 of the present embodiment, the game is disabled when it is determined that the RAM is abnormal, and the disablement of the game is canceled on condition that various processes including the RAM clear process (see FIG. 15) are performed. is doing.

  More specifically, when a startup process (see FIG. 7) that is performed when the CPU 41a is started when the power is turned on and when the CPU 41a is restarted due to a malfunction of the CPU 41a is executed, the slot machine 1 has a RAM parity that is not 0 (at Sa8). If the failure diagnosis data is not normal (determined as N in Sa9), an error code indicating a RAM abnormality is set (Sa10) and the process proceeds to error processing. To do. In the error process shown in FIG. 8, it is determined as a RAM abnormality error (determined as Y in Sb3), and the process proceeds to initialization 1 (Sb4). In the initialization 1 shown in FIG. 14, a RAM clear process (see FIG. 15) is performed to clear a work area other than the used stack area of the RAM 41c based on the initialization table shown in FIG. 6B. The After that, the slot machine 1 returns to the error processing shown in FIG.

  In this disabled state, when the slot machine 1 is activated by the operation of the reset switch 23 and the activation process shown in FIG. 7 is executed again, the RAM 41c is cleared and the RAM parity is determined to be 0 (Y in Sa8). On the other hand, since the storage area of the destructive diagnosis data (5AH in this embodiment) in which any bit is 1 is also cleared, it is determined that the destructive diagnosis data is abnormal (Sa9). In step S10, the error code indicating the RAM abnormality is set again (Sa10), and the error processing shown in FIG. 8 and the initialization 1 shown in FIG. 14 are performed.

  That is, once an error code indicating a RAM abnormality is set, as long as the setting key switch 37 is in an OFF state, it is determined as N in the step Sa6 of the startup process shown in FIG. Only the steps of Sa10 and error processing (see FIG. 8) are executed, and the steps of Sa11 to Sa14 are not executed. As a result, the interrupt permission which is the step of Sa14 is not performed, and even when there is a power interruption, the power interruption interrupt processing shown in FIG. 13 is not performed, so normal destruction diagnosis data is set (Sq6 is performed) ) Is never done. In other words, when an error code indicating a RAM abnormality is set, as long as the setting key switch 37 is in an OFF state, it cannot return to the original process (in most cases, a game process), and the startup process, error process, Only the RAM clear process is executed.

  On the other hand, after the error code indicating the RAM abnormality is set, the setting key switch 37 is turned on, so that the slot machine 1 is determined to be Y in the step Sa6 of the startup process shown in FIG. Thereafter, steps Sa15 to Sa18 are executed, and the process proceeds to game processing. In other words, it is determined that the setting key switch 37 is in the ON state (Y in Sa6), initialization 1 (Sa15) shown in FIG. 14, setting value work is set to 1 (Sa16), and interrupt permission (Sa17) is set. A series of processes for performing the setting change process (Sa18) shown in FIG. 9 is a process for recovering from a RAM abnormality.

  Next, a case where an error code indicating a RAM abnormality is set in this embodiment will be described.

  First, an error code indicating a RAM abnormality is generated in the start-up process shown in FIG. 7 when the power interruption interrupt process shown in FIG. 13 is not performed normally and the RAM parity and the data for destruction diagnosis are not set normally. Is set. Further, the error code indicating the RAM abnormality is set when the number of inserted medals is not the prescribed number (determined as N in Sg2) in the internal lottery process shown in FIG. Further, the error code indicating the RAM abnormality is set when the set value is not in the range of 1 to 6 (determined as N in Sg3) in the internal lottery process shown in FIG.

  Furthermore, an error code indicating a RAM abnormality is also set when a maskable interrupt (INT) and an unmaskable interrupt (NMI) that are unused interrupts occur. The setting method will be described in detail. As described above, the slot machine 1 performs the unused interrupt processing shown in FIG. 12A or 12B in accordance with the occurrence of the unused interrupt. The state shifts to an impossible (runaway) state, and then restarted by the reset circuit 49 equipped with the watchdog circuit 411. As a result, the start-up process shown in FIG. 7 is executed, but the RAM parity and the destructive diagnosis data are not normally set as in the case after the power interruption interrupt process (see FIG. 13). It is determined that the failure diagnosis data is not normal (N in Sa9), and finally an error code indicating a RAM abnormality is set in step Sa10.

  In other words, if the power interruption interrupt processing is not performed normally, the number of inserted medals is not the specified number, the setting value is not in the range of 1 to 6, and the maskable interrupt that becomes an unused interrupt When an interrupt (INT) and a non-maskable interrupt (NMI) occur, an error code indicating a RAM abnormality is set, so that a common RAM abnormality recovery process (Sa15 to Sa18) has been performed. As a condition, the game processing is started.

  As described above, in the slot machine 1 of this embodiment, when a maskable interrupt (INT) and a non-maskable interrupt (NMI) that become unused interrupts occur, an error code indicating a RAM abnormality is set. In addition, in the start-up process shown in FIG. 7, the process does not proceed to the game process until an area other than the used stack area that is the work area of the RAM 41c is initialized by initialization 1 (Sa15) shown in FIG. Since the progress of the game is disabled, even if an abnormality occurs in the data in the RAM 41c due to noise that can trigger an unused interrupt, the game is played with the abnormality in the data in the RAM 41c. Can be prevented.

  Further, in the slot machine 1 of the present embodiment, the progress of the game is disabled until the setting key switch 37 is turned on (determined as Y in Sa6). There is a possibility that the unused interrupt that triggered the progress of the game has been caused by noise accompanying fraud. In this embodiment, the operation to turn on the setting key switch 37 is an operation for resuming the game, and it is necessary for an employee of the amusement shop to perform the operation in order to resume the game. Actions can be effectively prevented.

  Further, in the slot machine 1 of this embodiment, unless the setting key switch 37 is turned on when the power is turned on, it is not determined that the setting key switch 36 is turned on, and the progress of the game is disabled. It is necessary to turn on the power again as an operation for canceling the state. That is, the operation of the predetermined initialization operation means in the present embodiment is a troublesome operation, and in this way, it is possible to more effectively prevent such an illegal act.

  Further, in the slot machine 1 of the present embodiment, when the progress of the game is disabled, the setting change process (Sa18) shown in FIG. 9 which is an operation of a predetermined setting operation means (setting key switch 37) is performed. On the basis of this, the permissible stage (set value) is canceled by being newly selected and set. For this reason, even if an abnormality occurs in the data of the RAM 41c indicating the permissible stage due to noise that triggers the occurrence of an unused interrupt, the permissible stage (generally selected and set based on the operation of the setting key switch 37) In addition, since the operation of the setting key switch 37 is operated by an employee of the amusement store, it is ensured that the game is played based on the permissible stage selected by the amusement store side), so that the fairness of the game is achieved. be able to.

  Further, in the slot machine 1 of the present embodiment, the unused interrupt that triggered the progress of the game may have occurred due to noise accompanying fraud. In such a case, in order to restart the game, the setting change process (Sa18) shown in FIG. 9, which is a change operation at an allowable stage, which is more troublesome than the operation of the reset switch 23 for canceling the normal error, is performed. Since it is necessary to do so, such fraud can be effectively prevented.

  The initialization 1 shown in FIG. 14 only needs to initialize the work area in response to the operation of the setting key switch 37. For example, the operation of the setting key switch 37 becomes effective as in this embodiment. Any timing may be used, such as a time point (determined as Y in Sa6) or a time point (Sc7) in which an allowable stage is newly set in the setting change process shown in FIG.

  Further, the slot machine 1 shifts to an inoperable (runaway) state when a maskable interrupt (INT) and a non-maskable interrupt (NMI) that become unused interrupts occur, and a recovery process from a RAM abnormality is performed. Game processing on condition that initialization 1 (Sa15) shown in FIG. 14, set value work is set to 1 (Sa16), interrupt permission (Sa17), and setting change processing (Sa18) shown in FIG. However, the present invention is not limited to this, and only the initialization of the RAM 41c that may have caused an abnormality due to noise or the like that triggered the occurrence of unused interrupts. Specifically, it may be configured to return to the game process on condition that the initialization 1 shown in FIG. 14 is performed.

  In this case, for example, a RAM initialization switch is provided inside the housing of the slot machine 1, and the RAM initialization switch is operated by an amusement store employee, and initialization 1 is performed after the power is turned on again. If it is configured to return to the game process on the condition, a troublesome operation is required to return to the game process, and illegal acts can be more effectively prevented.

  Further, in this embodiment, the state where the progress of the game is disabled is canceled by initializing all the areas (work areas) except the stack area of the RAM 41c in response to the operation of the setting key switch 37. However, at least a part of the work area (for example, the set value work in which the set value is stored, the area in which the internal winning flag is stored among the general work, the important work and the special work, the number of bets is stored. The area where the progress of the game is disabled is initialized by initializing the area where the data is broken, such as the area where the payout number in the big bonus is stored, etc. Anyway.

  Further, in the slot machine 1 of this embodiment, the maskable interrupt (INT) and the non-maskable interrupt (NMI) which are unused interrupt input terminals of the main control unit 41 are pulled up to +5 V which is a predetermined power source. Therefore, it is possible to reduce the possibility of an unused interrupt occurring even when noise occurs.

  Further, in the slot machine 1 of this embodiment, a process for determining whether or not the value read from the set value work is in the range of 1 to 6, that is, whether or not the set value used for the internal lottery is in the proper range. If it is executed for each game and the value read from the set value work is not in the range of 1 to 6, it is controlled to an error state due to a RAM abnormality error, and the progress of the game is disabled. In this embodiment, the value stored in the set value work, that is, the range of the set value that can be selected by the setting change process is a value of 1 to 6, and thus the value stored in the set value work is in the range of 1 to 6. If the value is not, the progress of the game is disabled.

  Further, a process for determining whether or not the set bet number is a bet number according to the gaming state is executed for each game, and the set bet number is not the bet number according to the game state. Control of the error state due to the RAM abnormal error disables the progress of the game. In this embodiment, the number of bets corresponding to each gaming state is determined, but if the game is played with a bet number different from the bet number, is the data stored in the RAM 41c broken? Or, since there is a possibility that an unauthorized program is operating, even if the set bet number is not the bet number according to the game state, the progress of the game is disabled.

  Then, once controlled to an error state due to a RAM abnormality error, the game cannot be progressed unless the setting change mode is entered and a setting value is newly selected and set based on the setting changing operation. Is not released. In other words, if the set value is not appropriate due to garbled data or illegal program operation, or if the set bet number is not the bet number according to the gaming state, the set value automatically set by the slot machine The game is executed based on the setting value selected and set based on the setting change operation (generally, since the setting change operation is performed by an employee of the amusement store, the setting value selected by the amusement store side). Since it is guaranteed that the game will be played, the fairness of the game can be improved.

  In this embodiment, when it is determined that the winning prize is determined in the internal lottery process and it is determined that the value is not an appropriate setting value, the RAM 41c is controlled to be in a RAM abnormal error state. When the set value stored in the set value work is not an appropriate value (a value in the range of 1 to 6), the winning of the winning is determined with a probability based on the initial value of the set value (for example, the set value 1). You may do it.

  Further, in the slot machine 1 of the present embodiment, the unused area in the RAM 41c of the main control unit 41 is initialized for each game. Therefore, even if an illegal program is stored using the unused area of the RAM 41c, It is possible to prevent unauthorized programs from being resident.

  Further, in this embodiment, the unused stack area in the stack area is initialized for each game in addition to the unused area in the RAM 41c, so that all the unused areas in the RAM 41c at that time are stored for each game. For example, even if it is attempted to store an illegal program using an unused stack area without using an unused area of the RAM 41c, there is no room for the illegal program to reside. Therefore, it is possible to more reliably prevent the unauthorized program from being resident, and for example, to add unauthorized data (such as an address specified by the unauthorized program) to the unused stack area, causing the microcomputer to malfunction when the data is restored. By rewriting the register to an illegal one, the original program Fraud can be prevented that would carry out the operation different from the. Further, by storing illegal data in the unused stack area, an area where the saved data should be stored can be compressed, the stack area overflows, and the micro that configures the main control unit 41 is stored. Problems such as the computer running away can be prevented.

  In this embodiment, the unused area and the unused stack area of the RAM 41c are initialized for each game. However, at least one of the unused area and the unused stack area of the RAM 41c is initialized for each game. Anything that can be initialized is acceptable.

  Further, in this embodiment, by executing the initialization 4 for initializing the unused area and the unused stack area of the RAM 41c at the end of the game, the unused area and the unused stack area of the RAM 41c are set for each game. If the unused area and / or the unused stack area of the RAM 41c is initialized at least once per game, but the unused area and / or the unused stack area of the RAM 41c is initialized. The timing for performing the conversion may be any timing during one game. For example, the unused area and / or the unused stack area of the RAM 41c may be initialized at the start of the game or when a process that is always executed for each game is executed. It may be one that performs the conversion.

  Also, before the start of setting (before transition to the setting change mode), at the end of the big bonus, when the data in the RAM 41c is not destroyed at the time of activation, when the four initialization conditions at the end of one game are satisfied, In addition to performing four types of initialization 1 to 4 which are initialized in different areas depending on each initialization condition, any of the four types of initialization conditions is satisfied, and an unused area in the RAM 41c is always Since the unused stack area in the stack area is initialized, it is possible to more reliably prevent the illegal program from being resident.

  In particular, when the data in the RAM 41c is not destroyed at the time of startup, the unused area in the RAM 41c and the unused stack area in the stack area are always initialized. Therefore, the unused area and the unused stack area in the RAM 41c are used. Even when an unauthorized program or unauthorized data is stored, it is possible to prevent the control state of the main control unit 41 from returning based on the data in the RAM 41c while the unauthorized program or the unauthorized data is stored.

  In addition, in the power interruption interrupt processing, after destructive diagnosis data with any bit set to 1 is stored in a predetermined address of the RAM 41c, the RAM parity based on all data including the unused area and the unused stack area of the RAM 41c. RAM parity adjustment data is calculated and stored so that becomes 0, and RAM parity calculated based on data stored in all areas including the unused area and unused stack area in the RAM 41c at the time of restoration Whether or not destructive diagnosis data is stored, and if the RAM parity is not 0, or even if the RAM parity is 0, the destructive diagnosis data is stored normally. If not, an error occurs due to a RAM error, and the setting key switch 37 is turned on and the power is turned on. Until the initialization 1 for initializing all areas except the used stack area of the RAM 41c is performed, the progress of the game is impossible. Therefore, the unused area and / or the unused stack area of the RAM 41c at the time of startup. Even if a malicious program is stored in the computer, the malicious program can be found and initialized.

  Further, when it is determined that the data stored in the RAM 41c is not normal and a RAM abnormal error state occurs, initialization 1 is performed to initialize all areas except the used stack area of the RAM 41c. Even when it is determined that the data stored in the RAM 41c is not normal, and when the setting key switch 37 is turned on after that, all the areas except the used stack area of the RAM 41c Since the initialization 1 is performed, the malicious program that may be stored in the RAM 41c can be surely removed.

  Further, in this embodiment, when an abnormality occurs in the data stored in the RAM 41c, the error state due to the RAM abnormality error is controlled, the progress of the game is disabled, and the error state once caused by the RAM abnormality error. If it is controlled, the state in which the progress of the game is disabled will not be released unless the setting change mode is entered and the setting value is newly selected and set based on the setting changing operation. That is, even if an abnormality occurs in the data stored in the RAM 41c, it is not the setting value automatically set by the slot machine, but the setting value selected and set based on the setting change operation (generally, the setting change Since the operation is performed by an employee of the amusement store, it is ensured that the game is performed based on the setting value selected by the amusement store side), so that the fairness of the game can be achieved.

  Further, the data stored in the RAM 41c is abnormal in most cases when the control cannot be continued due to a malfunction such as a power failure or the CPU 41a running out of control. For this reason, in this embodiment, since it is determined whether or not the data is normal only when the CPU 41a is activated after recovering from these states, it is determined whether or not the data stored in the RAM 41c is normal. The determination can be made only in a situation where there is a high possibility that an abnormality has occurred in the data. That is, in a situation where there is a low possibility that an abnormality has occurred in the data, it is not necessary to perform the determination, and the load on the CPU 41a can be reduced.

  In this embodiment, the RAM parity adjustment data is calculated and stored so that the result of the exclusive OR operation is 0 based on all the data in the RAM 41c in the power interruption processing, that is, Since it is determined whether or not the data in the RAM 41c is normal by determining whether or not the RAM parity calculated based on the data stored in all the areas in the RAM 41c at the time of recovery is 0, the determination is made as follows. It can be performed accurately and conveniently.

  In the present embodiment, in the interruption interrupt process, destruction diagnosis data (5AH in this embodiment) in which any bit is 1, that is, specific data other than 0 is stored in a predetermined address of the RAM 41c. After that, adjustment data for which the RAM parity is 0 based on all the data of the RAM 41c including the destructive diagnosis data is stored, and in addition to the determination as to whether the RAM parity is 0 or not at the start, Is determined to be normal, and the RAM 41c is determined to be normal on the condition that the RAM parity is 0 and the destructive diagnosis data is also normally stored. The control state is restored based on the data stored in. As a result, when 00H is stored in all areas, that is, when the data in the RAM 41c is cleared to 0 even if the data in the RAM 41c is not normal, it is normal by the determination of the RAM parity at startup. If the data in the RAM 41c is cleared to 0, the area in which the destructive diagnosis data is to be stored is also 0, and it is determined that the data in the RAM 41c is not normal. Therefore, it is possible to further improve the accuracy of determining whether or not the data in the RAM 41c has the correct contents at the time of activation.

  Further, when the CPU 41a determines that the RAM parity is 0 at startup and the data for destructive diagnosis is also normally stored, and determines that the data in the RAM 41c is normal, the destructive diagnosis stored in the RAM 41c. Since the data for destruction diagnosis is still stored in the RAM 41c even after the activation, the data in the RAM 41c is not normal at the next activation, but the data is destroyed. Since diagnostic data is stored, it is possible to prevent erroneous determination as normal.

  Further, in this embodiment, when an abnormality occurs in the data in the RAM 41c and the progress of the game is disabled, a setting value changing operation as a condition for canceling the disabled state of the game is effective. As a result of the transition to the setting change mode (setting change processing), all the areas except the used stack area of the RAM 41c are initialized, so that the initial data of the RAM 41c due to the occurrence of an abnormality And initialization of data associated with selection / setting of set values can be performed at once, and unnecessary processing can be omitted. Further, when the CPU 41a is activated, it is determined whether or not the setting key switch 37 is ON before determining whether the data in the RAM 41c is normal. At that time, the setting key switch 37 is ON. If it is determined that there is, the determination as to whether the data in the RAM 41c is normal is not performed, and the mode shifts to the setting change mode, where a new setting value is selected and set. It can be omitted.

  Further, in this embodiment, when the power interruption interrupt processing is not normally performed, when the number of inserted medals is not a prescribed number, when the set value is not within the range of 1 to 6, When a maskable interrupt (INT) and a non-maskable interrupt (NMI) are generated, an error code indicating a RAM abnormality is set and the game is disabled. Thereafter, the disabling of the game is canceled on the condition that the return processing (Sa15 to Sa18) from the common RAM abnormality is performed. In other words, in situations where the fairness of the game has been compromised or where there is a concern about fraud, the game is disabled, and appropriate measures are taken for the slot machine before the game is disabled. However, it is not necessary to provide a separate process for each situation because the recovery process from the common RAM abnormality is applied in these multiple situations.

  In this embodiment, initialization 1 for initializing all areas except the used stack area of the RAM 41c is performed before shifting to the setting change process. However, along with the shift to the setting change process. Initialization 1 may be performed, for example, after the setting change process is completed, or may be performed when the setting value is confirmed in the setting change process. In this case, since the inconvenience arises when the determined set value is changed, in initialization 1, all areas except the used stack area and the set value work of the RAM 41c are initialized. Become.

  Further, in this embodiment, once the error state due to the RAM abnormality error is controlled, the game is disabled until the setting change process is performed, but the error state due to the RAM abnormality error occurs. When initialization is performed, all areas except the used stack area of the RAM 41c are initialized, and a set value is set to an initial value (for example, set value 1), and a reset operation is performed in this state. Thus, the game may be restarted.

  Further, in this embodiment, when the voltage drop signal is input to the trigger terminal CLK / TRG, the CPU 41a interrupts the process being executed and executes the power interruption process. In the process including the process for setting the data for destructive diagnosis and the process for calculating and setting the data for adjusting the RAM parity, the process for making it possible to determine whether the data in the RAM 41c is normal at the time of recovery or the initial setting of the output port Before performing the conversion, it is determined whether or not a voltage drop signal is input to the signal input / output terminal DATA. If the voltage drop signal is also input to the signal input / output terminal DATA, the data in the RAM 41c is restored at the time of restoration. If the voltage drop signal is not input to the signal input / output terminal DATA, the process for making it possible to determine whether the signal is normal or the initialization of the output port is performed. It is adapted to return to processing.

  That is, the voltage drop signal is input to the two systems of the input unit to the main control unit 41, and the CPU 41a does not perform the power interruption interrupt process when the voltage drop signal is input to one of the input units. Before the process for enabling determination of whether the data in the RAM 41c is normal, the initialization of the output port, or the like is performed, it is determined again whether or not the voltage drop signal is input to the other input unit. These processes are executed only when a voltage drop signal is also input to the input section of this, and when power failure is detected by mistake, whether or not the data in the RAM 41c is normal at the time of recovery is detected. Since it is possible to prevent the process for enabling the determination and the process such as the initialization of the output port from being performed, the control of the CPU 41a may be interrupted for an unnecessarily long time due to erroneous detection of power interruption. More than necessary Possible to prevent the load is applied to.

  In this embodiment, the CPU 41a transmits a command corresponding to the progress of the game to the effect control board 90, and the sub-control unit 91 mounted on the effect control board 90 receives the command transmitted from the game control board 40. Since the CPU 41a does not need to control the presentation only by sending a command, the processing load on the CPU 41a can be reduced and the presentation can be made various. .

  Further, a command transmission line for transmitting a command from the game control board 40 to the effect control board 90 is connected between the game control board 40 and the effect control board 90 via the effect relay board 80, and the game control board Since the production control board 90 is not directly connected to 40, it is possible to prevent an illegal signal from being input from the command transmission line to the CPU 41a from the outside and affecting the control of the game.

  Although the embodiments of the present invention have been described with reference to the drawings, the present invention is not limited to these embodiments, and modifications and additions within the scope of the present invention are included in the present invention. Needless to say.

  For example, in the embodiment, as shown in FIG. 12A, the game is disabled in the slot machine 1 by shifting the CPU 41a to the disabled (runaway) state based on the execution of the unused interrupt process. Although the start-up process shown in FIG. 7 is performed by the reset circuit 49 equipped with the dog circuit 411, the disabling of the game is canceled on condition that the above-described RAM abnormality recovery process is performed, but the present invention is not limited to this. Instead, it is only necessary to cancel the disabling of the game on condition that the game is disabled when an unused interrupt occurs and the above-described RAM abnormality recovery process is performed.

  Specifically, as shown in the modified example of the unused interrupt process in FIG. 12B, in the step (Sx1) immediately after the start of the unused interrupt process, the value of the program counter serving as the return address is If it is rewritten to the step after initialization 1 (Sb4) in the error processing shown in FIG. 8 (step of disabling the game by causing the CPU 41a to execute an infinite loop), the CPU 41a after normal termination of the unused interrupt processing The game can be disabled in the slot machine 1 though is moving. Specifically, in the step of Sx1, the value of the program counter may be rewritten to an address on the ROM 41c in which a program corresponding to the step after initialization 1 (Sb4) in error processing is stored.

  In this state, the power can only be turned on again by operating the reset switch 33 or the like, but the RAM parity and the destruction diagnosis data are not normally set as after the power interruption processing (see FIG. 13). Therefore, it is determined that the RAM parity is not 0 (N at Sa8), or the data for destructive diagnosis is not normal (N at Sa9), and finally an error code indicating a RAM abnormality is set at step Sa10. Is done. In this way, even if no special hardware such as the watchdog circuit 411 is installed, the game is disabled when an unused interrupt occurs, and the above-described RAM abnormality recovery process is performed. In addition, since the slot machine can be configured such that the disabling of the game is released, manufacturing costs can be reduced.

  Next, a modified example of the initialization of the RAM 41c will be described.

  In the first embodiment, when the CPU 41a initializes the RAM 41c, the initialization table of the ROM 41b is referred to, and the start address and initialization size corresponding to one of initializations 1 to 4 are set according to the initialization conditions. , Set the pointer to the start address, set the initialization size, clear the area of the corresponding address by 1 byte from the initialization address where the pointer is set, and initialize each time 1 byte is cleared The area of the RAM 41c corresponding to the initialization condition is initialized by executing the process of decrementing the size by 1 and advancing the pointer by 1 until the initialization size becomes 0. The area to be initialized is set as a continuous address area, and the initialization table indicates one of initializations 1 to 4 according to the initialization condition. The start address and the end address common to all of initializations 1 to 4 are registered, and the CPU 41a refers to the initialization table when initializing the RAM 41c, and initializes according to the initialization condition. The start address corresponding to any one of 1 to 4 is acquired, the pointer is set to the start address, and the area of the corresponding address is cleared to 0 by 1 byte from the initialization address to which the pointer is set, and 1 byte is cleared. Each time the pointer is advanced, the area of the RAM 41c corresponding to the initialization condition may be initialized by executing the process of advancing the pointer until the end address area common to the initializations 1 to 4 is cleared. .

  In this case, each time 1 byte is cleared, it is determined whether the address indicated by the pointer is the end address. If the address is the end address, the initialization may be terminated. The initialization byte number from the start address to the common end address is calculated and set, and every time 1 byte is cleared from the start address, the initialization byte number is decremented by 1 and the pointer is advanced by 1. It is preferable that the process is executed until the number reaches zero, and it is determined that the end address area has been cleared when the number of initialization bytes reaches zero, and the initialization is terminated. This is because the process of determining whether the number of initialization bytes is 0 is higher than the process of comparing the address indicated by the pointer and the end address for each byte.

  19A is a diagram showing a modification of the storage area of the RAM 41c, FIG. 19B is a diagram showing a modification of the initialization table, and FIG. 20 is a modification of initialization 1. It is a flowchart to show.

  As shown in FIG. 19 (a), in this modification, the storage area of the RAM 41c is 7E00 (H), the set value work, special work, important work, non-saved work, general work, unused area, unused The stack area is allocated in the order of the stack area in use. For this reason, even if any of initialization 1, 2, and 4 is performed, the area | region initialized is a continuous address area | region. Specifically, the areas initialized in the initialization 1 are all areas except the in-use stack area, that is, set value work, special work, important work, unsaved work, general work, unused area, unused stack. These areas are continuous address areas from 7E00 (H) to the stack pointer. The areas initialized in the initialization 2 are general work, unused area, and unused stack area, and these areas are continuous address areas from 7E53 (H) to the stack pointer. The areas initialized in the initialization 4 are an unused area and an unused stack area. These areas are continuous address areas from 7F05 (H) to the stack pointer. In initialization 2, general work, unused area, and unused stack area are initialized. In initialization 3, non-saved work, unused area, and unused stack area are initialized. The unused area and the unused stack area that are initialized in the initialization 3 are continuous address areas, but the non-saved work is a non-continuous address area.

  As shown in FIG. 19B, in the initialization table applied in this modification, start addresses are registered corresponding to initializations 1 to 4, and end addresses common to initializations 1 to 4 are registered. Is registered. In addition, since the initialization 3 is an address area where non-saved work is not continuous, the initialization size is registered corresponding to the start address of the non-saved work.

  Next, a modification of the initialization 1 executed by the CPU 41a will be described based on the flowchart shown in FIG.

  In this initialization 1, first, the initialization address in the ROM 41b is referred to, and the start address registered corresponding to the initialization 1 is read (Sr1001). Then, a pointer is set at the read start address (7E00 (H)) (Sr1002). Next, the initialization address common to the initializations 1 to 4 is read by referring to the initialization table of the ROM 41b (Sr1003). Then, the number of bytes from the start address (7E00 (H)) read in Sr1001 to the end address (stack pointer) read in Sr1003 is calculated (Sr1004), and the number of bytes in the area for initializing the calculated number of bytes is set. (Sr1005). Then, a RAM clear process for clearing data from the start address set in Sr1002 over the number of bytes set in Sr1005 is executed (Sr1006), and when the RAM clear process is completed, the initialization 1 is completed. Return to.

  The initialization 2 and 4 are almost the same processing as the initialization 1 shown in FIG. 20, and the initialization 2 or initialization 4 start address registered in the initialization table is acquired. Then, the number of bytes from the start address to the common end address is calculated, and the data is cleared over the calculated number of bytes from the start address. In the modification of initialization 3, first, the start address and initialization size of the non-saved work registered in the initialization table are acquired, and after the data is cleared from the start address over the number of bytes corresponding to the initialization size, Get the start address of the unused area and unused stack area registered in the initialization table, calculate the number of bytes from the start address to the common end address, and clear the data over the calculated number of bytes from the start address Perform the process.

  According to the modification of the initialization of the RAM 41c as described above, for a plurality of initialization conditions, only the start address corresponding to the initialization table and the end address common to the plurality of initialization conditions are set. Because it is possible to initialize areas corresponding to multiple initialization conditions without individually setting end addresses corresponding to multiple initialization conditions, the program capacity for performing multiple types of initialization Can be reduced.

  In the embodiment, the RAM parity adjustment data is stored so that the RAM parity of the RAM 41c becomes 0 in the power interruption processing, and it is determined whether or not the RAM parity of the RAM 41c is 0 at the time of restoration. Although it is determined whether or not the data in the RAM 41c is normal, of course, the RAM parity adjustment data is stored so that the RAM parity of the RAM 41c becomes 1 in the power interruption processing, and the RAM parity of the RAM 41c becomes 1 at the time of restoration. Whether or not the data in the RAM 41c is normal may be determined. Further, the checksum (exclusive OR of the data stored in the corresponding area) of all areas of the RAM 41c is calculated in the power interruption processing, and is stored in a specific area, and at the time of recovery, the RAM 41c is restored. The checksum of all the areas including the specific area where the checksum is stored is calculated. If the result is 00 (H), it is determined that the data in the RAM 41c is normal, and must be 00 (H). For example, it may be determined that the data in the RAM 41c is abnormal.

  If the checksum is stored normally in the power interruption processing, the checksum of the area excluding the specific area and the data stored in the specific area (the checksum calculated at the time of power interruption) ) Should take the same value, and if the checksum of the area excluding the specific area matches the data stored in the specific area, the result of calculating the exclusive OR of both data is Since the result of calculating the checksum of all the areas including the specific area where the checksum of the RAM 41c is stored is 00 (H), it is determined that the data of the RAM 41c is normal. This is because it can.

  In this case as well, in the power interruption interrupt processing, before the checksum is calculated, the destructive diagnosis data (for example, 5A (H)) in which any bit is 1 is stored at a predetermined address, and at the time of restoration In addition to determining whether or not the checksum is 00 (H), it is also determined whether or not the data for destructive diagnosis is normally stored. The checksum is 00 (H) and the destructive diagnosis is performed. It is preferable to determine that the data in the RAM 41c is normal on the condition that the business data is also normal. Even if the data in the RAM 41c is not normal, if 00 (H) is stored in all areas, it will be determined to be normal by the checksum determination at the time of startup, After storing the destructive diagnostic data with the bit set to 1, calculate the checksum and store it in a specific area, and also check the destructive diagnostic data in addition to checking the checksum at startup, For example, even if all areas are cleared to 0 at startup, and the checksum is 00 (H) and determined to be normal, the destruction diagnosis data does not match the value stored at the time of power failure, Since the determination is made, it is possible to improve the accuracy of determining the abnormality of the data stored in the RAM 41c.

  In the above, the RAM parity or checksum of the RAM 41c is calculated in the power interruption processing and stored in the RAM 41c, and whether or not the RAM parity calculated based on all areas of the RAM 41c at the time of restoration is 0. Or whether the data in the RAM 41c is normal based on whether or not the checksum calculated based on all areas of the RAM 41c is 00 (H). RAM parity or checksum of the RAM 41c is calculated and stored in a specific area, and the RAM parity or checksum excluding the specific area of the RAM 41c is calculated at the time of recovery, and the RAM parity or checksum stored in the specific area is calculated. The data in the RAM 41c depends on whether the comparison result matches It may be determined whether normal or not. In this case as well, as described above, before the RAM parity or checksum is calculated, the destructive diagnosis data in which any bit is 1 is stored at a predetermined address. In addition to determining whether or not the sums match, it is determined whether or not the data for destructive diagnosis is stored normally, the RAM parity and checksum match, and the destructive diagnostic data is also normal. It is preferable to determine that the data in the RAM 41c is normal under the above conditions.

  In the above-described embodiment, 5A (H) is stored in the RAM 41c as the failure diagnosis data in the power interruption processing. However, any data other than 0 may be stored and can be confirmed at the time of startup.

  In the above embodiment, when the CPU 41a is started, the RAM parity of the RAM 41c is calculated, it is determined whether or not the result is 0, and the destructive diagnosis data is normal on the condition that the RAM parity is 0. However, first, it is determined whether or not the data for destructive diagnosis is stored normally, and on condition that the data for destructive diagnosis is stored normally. The RAM parity of the RAM 41c may be calculated and it may be determined whether or not the result is 0. In this way, if the destructive diagnosis data is not normally stored, the RAM parity is calculated. Without calculation, it can be determined that the data in the RAM 41c is abnormal.

  In the embodiment, the main control unit 41 is activated based on a reset signal from a reset circuit 49 provided separately from the main control unit 41. However, the reset circuit is connected to the main control unit 41. The microcomputer which comprises may be mounted.

  In the above-described embodiment, the RAM 41c is mounted on the microcomputer constituting the main control unit 41. However, a RAM used as a work of the microcomputer may be mounted outside the microcomputer.

  In the embodiment, the power interruption detection circuit 48 monitors the DC voltage used in the slot machine 1 and detects the power interruption when the DC voltage becomes a certain voltage or lower. You may make it detect a power interruption, when the period when the said DC voltage became below a fixed voltage continued for a fixed period. Alternatively, the AC voltage supplied to the slot machine 1 may be monitored to detect a power interruption when a disturbance in the waveform of the AC voltage is detected or when the period continues for a certain period.

  Further, in the above embodiment, the power interruption detection circuit 48 is mounted on the game control board 40, but it may be mounted in other places. For example, the game control board 40 may be mounted from the power supply board 100 or the power supply board 100. It may be mounted on a relay board or the like through which a power supply line is connected.

  In the embodiment, the slot machine for setting bets using medals and credits is used. However, the present invention is not limited to this, and the slot machine for setting bets using game balls. Alternatively, it may be a complete credit type slot machine that uses only credits to set the number of bets.

  Further, as shown in FIG. 21, in addition to the medal insertion mechanism such as the flow path switching solenoid 30 and the insertion medal sensor 31, a ball capturing device 30 ′ and a ball capturing device 30 ′ for capturing game balls are used. In addition to a medal payout mechanism such as a hopper motor 34 and a payout sensor 35, a ball payout device 34 ′ for paying out a game ball, a ball payout, and the like are provided. A payout ball detection switch 35 ′ for detecting a game ball paid out by the device 34 ′ is provided, and it is possible to play a game by setting the number of bets using both medals and game balls, and generating a prize. The present invention may be applied to a slot machine in which medals and game balls are paid out.

It is a front view of the slot machine of the Example to which this invention was applied. It is a block diagram which shows the structure of a slot machine. It is a circuit diagram for demonstrating the structure around the main control part in a game control board. It is a timing chart which shows the operation | movement condition when an unused interruption generate | occur | produces. It is a figure which shows the structure of the storage area of RAM of a main control part. (A) is a figure which shows the area | region initialized in initialization 1-4 performed by CPU of a main control part. (B) is a figure which shows the initialization table stored in ROM of the main control part. It is a flowchart which shows the control content of the starting process which CPU of a main control part performs at the time of starting. It is a flowchart which shows the control content of the error process performed when CPU of a main control part generate | occur | produces an error. It is a flowchart which shows the control content of the setting change process which CPU of a main control part performs in a starting process. It is a flowchart which shows the control content of the game process which CPU of a main control part performs after a starting process. It is a flowchart which shows the control content of the internal lottery process which CPU of a main control part performs in a game process. (A) is a flowchart which shows the control content of the unused interrupt process which CPU of a main control part performs when an unused interrupt generate | occur | produces. (B) is a flowchart showing a control content of a modified example of an unused interrupt process executed by the CPU of the main control unit when an unused interrupt occurs. It is a flowchart which shows the control content of the interruption interruption process performed when CPU of a main control part inputs a voltage drop signal from an interruption detection circuit. It is a flowchart which shows the control content of the initialization 1 which CPU of a main control part performs in a starting process. It is a flowchart which shows the control content of the RAM clear process which CPU of the main control part performs in initialization 1-4. It is a flowchart which shows the control content of the initialization 2 which CPU of a main control part performs at the time of the end of a big bonus. It is a flowchart which shows the control content of the initialization 3 which CPU of a main control part performs in a starting process. It is a flowchart which shows the control content of the initialization 4 which CPU of a main control part performs whenever one game is complete | finished. (A) is a figure which shows the modification of the storage area of RAM in a main control part. (B) is a figure which shows the modification of an initialization table. It is a figure which shows the modification of the initialization 1 which CPU of a main control part performs. It is a block diagram which shows the modification of a structure of a slot machine.

Explanation of symbols

1 Slot machine 2L, 2C, 2R Reel 8L, 8C, 8R Stop switch 40 Game control board 41 Main controller 41a CPU
41b ROM
41c RAM
48 power interruption detection circuit 49 reset circuit 410 output conversion circuit 411 watchdog circuit

Claims (4)

A game can be started by setting a predetermined number of bets for one game using the game value, and a display result of a variable display device capable of variably displaying a plurality of types of identification information that can be identified by each game Is a slot machine in which one game is ended by being derived and displayed, and a winning can be generated according to the display result of the variable display device,
Consists of a microcomputer having a plurality of interrupt input terminals that generate external interrupts when a signal is input, and includes main control means for controlling a game,
The main control means includes
Data storage means having a storage area for storing data in a readable and writable manner, and at least a work area for storing data for operation of a microcomputer constituting the main control means as the storage area; ,
Initialization means for initializing at least a part of a storage area in the data storage means;
Disabling means for disabling the progress of the game when a signal is input to an unused interrupt input terminal among the plurality of interrupt input terminals and an external interrupt occurs;
When the progress of the game is disabled by the disabling means, the progress of the game is disabled on the condition that the work area in the data storage means is initialized by the initializing means. Disabling means for releasing and allowing the game to progress,
A slot machine characterized by including.   2. The slot machine according to claim 1, wherein the initialization unit initializes a work area in the data storage unit based on an operation of a predetermined initialization operation unit. An allowable stage selection means for selecting one of the allowable stages from a plurality of allowable stages having different ratios for determining whether or not the generation of the winning is permitted based on an operation of the predetermined setting operation means; ,
A permissible stage setting means for setting data indicating a permissible stage selected by the permissible stage selection means in a permissible stage storage area assigned to the storage area of the data storage means;
With
The initialization means initializes a work area in the data storage means on the condition that the allowable stage is newly set by the allowable stage setting means based on the operation of the setting operation means.
The slot machine according to claim 1 or 2, characterized by the above-mentioned.   4. The slot machine according to claim 1, wherein an unused interrupt input terminal in the microcomputer is pulled up to a predetermined power source.

Images