JP2007227654A - Wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board which is possible to make good a solder bump formed in a resin insulation layer (solder resist layer), serving for high density wiring and high pin-count. <P>SOLUTION: The wiring board 1 is equipped with a wiring lamination L1 having a main surface CP and a solder resist layer SR1. The thickness of the solder resist layer SR1 is made to be more than 25μm, an exposure opening 9 is provided to expose a conductor pad 10 formed in the main surface CP of the wiring lamination portion L1 in the solder resist layer SR1, a solder bump 11 connected to the conductor pad 10 is formed in the exposure opening 9, the inside wall 9c of the exposure opening 9 is a tapered plane whose diameter becomes large as it goes toward the opening side in the direction of the board thickness, and the difference in diameter of the tapered plane is more than 5μm between the upper surface 9a of the exposure opening 9 and the bottom surface 9b of the exposure opening 9. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a wiring board.

The wiring board has a large number of conductors (electrodes) used for mounting electronic components such as LSIs and IC chips on one main surface thereof, and a large number of conductors for connection to a mother board or the like on the other main surface. (Electrode) and a connection terminal installed on the electrode. In such a type of wiring board, in order to achieve high-density integration of electronic components such as LSI, IC chip or chip capacitor to be mounted, high-density wiring and multi-terminals are required.
JP 11-26892 A

  Conventionally, for example, when an IC chip is mounted on a wiring board, a plurality of solder bumps are formed in a grid shape or a staggered pattern on the connection surface of the IC chip and the wiring board, and the IC chip is overlaid on the predetermined surface. A so-called flip chip connection method is known in which both are connected via solder bumps by heating to a connection temperature.

  As a method of forming solder bumps on the wiring board as described above, solder paste is printed in an opening (exposed hole) provided at a predetermined position on the board through a screen mask (or metal mask), A solder paste printing method is known in which solder bumps are formed on a substrate by heating (reflowing) this to melt the solder paste.

  However, in the method of forming solder bumps in these openings by the solder paste printing method, the volume of the applied solder paste is likely to vary. For example, when the volume is excessive with respect to the opening (exposed hole) Due to the surface tension of the solder melted during reflow, the solder floats to the upper side of the opening and may not be welded to the conductor (electrode) on the bottom side, resulting in defective solder bump defects. If the volume is insufficient, the reliability of electrical connection can be obtained because the solder bump height is insufficient when mounting an IC chip or the like on the board, leading to poor connection between terminals during component mounting. There is no problem.

  Therefore, it is conceivable to enlarge these openings in order to satisfactorily form solder bumps, but if it is too large, there is a dilemma that hinders high-density wiring of the wiring board, and the main surface of the board on which the openings are provided Although it is conceivable to reduce the thickness of the resin insulating layer (solder resist layer), there is a dilemma that if it is too thin, reliability such as protection of conductors and maintenance of insulation between conductors cannot be obtained.

  An object of the present invention is to provide a wiring board capable of improving the solder bumps formed on a resin insulating layer (solder resist layer) and achieving high-density wiring and multiple terminals.

Means and effects for solving the problems

In order to solve the above problems, the wiring board of the present invention is:
A wiring board comprising a wiring laminate having a main surface and a solder resist layer,
The solder resist layer has a thickness of more than 25 μm;
The solder-resist layer is provided with an exposed hole for exposing a conductor pad formed on the main surface of the wiring laminated portion, and a solder bump connected to the conductor pad is formed in the exposed hole,
The exposed hole is a tapered surface having a diameter that increases toward the opening in the thickness direction, and a difference in diameter between the upper surface of the exposed hole and the bottom surface of the exposed hole is a tapered surface of 5 μm or more. And

  According to the present invention, the solder resist layer is formed to be thicker than 25 μm, and the taper surface whose diameter increases as the inner peripheral wall of the exposure hole moves toward the opening side in the plate thickness direction (in other words, the inner peripheral wall is on the bottom side in the plate thickness direction). Since the diameter difference between the upper surface and the bottom surface of the exposed hole is 5 μm or more, specifically, the solder resist layer is thickened. Even when formed, high-density wiring can be realized, and since the opening of the exposed hole is provided large, the formed solder bump can be made favorable. In addition, since the solder resist layer is formed thick, reliability can be obtained by preventing adhesion of solder, protecting conductors, maintaining insulation between conductors, and the like. On the other hand, when the difference in diameter between the top and bottom surfaces of the exposed hole is less than 5 μm, when the solder resist layer is formed thick, the opening of the exposed hole cannot be provided sufficiently large, and a good solder bump is formed. Can not be.

The wiring board of the present invention is
A wiring board comprising a wiring laminate having a main surface and a solder resist layer,
The solder-resist layer is provided with an exposed hole for exposing a conductor pad formed on the main surface of the wiring laminated portion, and a solder bump connected to the conductor pad is formed in the exposed hole,
The inner peripheral wall of the exposed hole is a tapered surface whose diameter increases toward the opening in the thickness direction,
When the thickness of the solder resist layer is L and the difference in diameter between the top and bottom surfaces of the exposed hole is d, L / d is in the range of 10 or less.

  According to the present invention, the inner peripheral wall of the exposed hole is formed with a tapered surface whose diameter increases toward the opening in the plate thickness direction, the thickness of the solder resist layer is L, the difference in diameter between the upper surface and the bottom surface of the exposed hole (hereinafter, By setting L / d to 10 or less when d is simply the diameter difference, a contact area of the solder paste by the taper surface can be sufficiently secured. Even when surface tension occurs, the solder can be prevented from floating above the opening, and the melted solder can easily enter during reflow and reach the bottom of the exposed hole, making it easy to weld to the conductor pad. Become. When L / d is greater than 10, the exposed hole slope becomes steeper (approx. Almost perpendicular), so that sufficient opening is provided to print the solder paste against the thickness of the solder resist layer. There is a risk that the connection with the reliable conductor pad cannot be performed. It should be noted that solder bumps can be formed by repeatedly performing the solder paste printing process in this opening. However, in this case, the work efficiency may deteriorate and the manufacturing cost may increase. On the other hand, L / d is desirably 1 or more. If it is smaller than 1, the opening of the exposed hole is excessively widened, and the wiring area is reduced, which hinders high density wiring.

The wiring board of the present invention is
A wiring board comprising a wiring laminate having a main surface and a solder resist layer,
The solder-resist layer is provided with an exposed hole for exposing a conductor pad formed on the main surface of the wiring laminated portion, and a solder bump connected to the conductor pad is formed in the exposed hole,
The inner peripheral wall of the exposed hole is a tapered surface whose diameter increases toward the opening in the thickness direction,
When the thickness of the solder resist layer is L, the bottom diameter of the exposed hole is r, and the diameter difference between the top and bottom surfaces of the exposed hole is d, the range is 7d + 0.7r ≧ 32 + 2L.

  According to the present invention, the inner peripheral wall of the exposed hole is formed with a tapered surface whose diameter increases toward the opening in the thickness direction, the thickness of the solder resist layer is L, the bottom diameter of the exposed hole (hereinafter simply referred to as the bottom diameter). Where r is the diameter difference between the upper surface and the bottom surface of the exposed hole, and d is 7d + 0.7r ≧ 32 + 2L. For example, when the solder resist layer is formed with a predetermined thickness, it is exposed. Increasing the bottom diameter of the hole can reduce the difference in diameter between the top and bottom surfaces of the exposed hole, and conversely, increasing the diameter difference can reduce the bottom diameter. Therefore, since it is possible to form a high-density wiring and to form an exposed hole having a sufficiently large opening, the solder bump formed in the exposed hole becomes good. Also, corresponding to the thickness of the solder resist layer, the size (bottom diameter) of the exposed hole is provided and the shape (tapered surface). When the thickness is reduced, the bottom surface diameter or the difference in diameter can be formed small, so that an exposed hole having a sufficient opening with respect to the thickness of the solder resist layer can be formed. Therefore, the solder formed in the exposed hole Bumps are good.

  Since the exposed hole is formed in the solder resist layer under the above conditions, the volume and shape of the obtained solder bump can be stabilized, and a good solder bump can be formed. The process yield can be improved, and the workability is excellent. Furthermore, since the solder does not easily flow out of the exposed hole, for example, the occurrence of a solder bridge that is short-circuited with the solder provided in the adjacent exposed hole is suppressed, and electrical connection reliability can be obtained.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 schematically shows a cross-sectional structure of a wiring board 1 according to an embodiment of the present invention. As described above, the wiring board 1 includes both surfaces MP1 and MP2 of the plate-like core 2 made of a heat-resistant resin plate (for example, a bismaleimide-triazine resin plate) or a fiber reinforced resin plate (for example, a glass fiber reinforced epoxy resin). In addition, core conductor layers M1 and M11 having a predetermined wiring pattern are formed. These core conductor layers M1 and M11 are formed as a plane conductor pattern that covers most of the surface of the plate-like core 2, and are used as a power supply layer or a ground layer. On the other hand, the plate-like core 2 is formed with a through-hole 12 drilled by a drill or the like, and an inner wall surface plating layer (through-hole conductor) 30 for connecting the core conductor layers M1 and M11 to each other is formed on the inner wall surface. Has been. The through hole 12 is filled with a resin filling material 31 such as an epoxy resin inside the through hole conductor 30.

  In the upper layer of the core conductor layers M1 and M11, wiring laminated portions L1 and L2 are formed including the core conductor layers M1 and M11. Specifically, first resin insulation layers (build-up resin insulation layers) V1 and V11 made of a photosensitive or thermosetting resin composition 6 are formed. Further, first conductor layers M2 and M12 having metal wirings 7 each having a predetermined pattern are formed on the surface by Cu plating. The core conductor layers M1 and M11 and the first conductor layers M2 and M12 are interconnected by vias 34, respectively. Similarly, second resin insulation layers (build-up resin insulation layers) V2 and V12 using the photosensitive or thermosetting resin composition 6 are formed on the first conductor layers M2 and M12, respectively. On the surface, second conductor layers M3 and M13 having metal terminal pads (conductor pads) 10 and 17 are formed. The first conductor layers M2, M12 and the second conductor layers M3, M13 are connected to each other through vias 34. The via 34 includes a via hole 34h, a via conductor 34s provided on the inner peripheral surface thereof, a via pad 34p provided so as to be electrically connected to the via conductor 34s on the bottom surface side, and a via conductor 34h on the opposite side of the via pad 34p. Via land 34l projecting outward from the peripheral edge of the opening. When the photosensitive resin is used for each resin insulating layer, the via hole 34h is formed by being masked with a predetermined pattern, exposed to ultraviolet light, developed, and the like. Further, when a thermosetting resin is used, it is formed by drilling with a laser or plasma.

  Also, solder resist layers SR1 and SR11 using photosensitive or thermosetting resin compositions 8 and 18 are formed on the second conductor layers M3 and M13 and the second resin insulation layers V2 and V12, respectively. Exposed holes 9 and 19 are provided at positions corresponding to the metal terminal pads 10 and 17 to expose the pads. Further, at least in the exposure hole 9, the inner peripheral wall described later has a tapered surface whose diameter increases toward the opening in the plate thickness direction. In the case where a photosensitive resin is used for the solder resist layers SR1 and SR11 as in the case of the via hole 34h, the exposure holes 9 and 19 are formed by being masked with a predetermined pattern and exposed to ultraviolet light, developed, or the like. Further, when a thermosetting resin is used, it is formed by drilling with a laser or plasma.

  Thus, on the surface MP1 of the plate-like core 2, the core conductor layer M1, the first resin insulation layer V1, the first conductor layer M2, the second resin insulation layer V2, and the second conductor layer M3 are laminated to form the first. The wiring laminated portion L1 is formed. On the surface MP2 of the plate-like core 2, the core conductor layer M11, the first resin insulation layer V11, the first conductor layer M12, the second resin insulation layer V12, and the second conductor layer M13 are laminated to form the second wiring. A stacked portion L2 is formed. Each of the wiring laminated portions L1 and L2 is formed by alternately laminating resin insulating layers and conductor layers, and a plurality of metal terminal pads 10 and 17 and a main surface CP far from the plate-like core 2 are provided on the main surface CP. Solder resist layers SR1 and SR11 are respectively formed.

  The metal terminal pad 10 on the first wiring laminated portion L1 side constitutes a solder land that is a pad (FC pad) for flip-chip connection of an IC chip or the like. Further, the metal terminal pad 17 on the second wiring laminated portion L2 side is a back surface land (PGA pad, BGA pad) for connecting the wiring board itself to a mother board or the like by a pin grid array (PGA) or a ball grid array (BGA). It is used as. As shown in FIG. 2, the metal terminal pads (solder lands) 10 are arranged in a lattice shape or a staggered pattern at a substantially central portion of the main surface CP of the wiring board 1, and solder bumps 11 (FIG. 1) formed thereon, respectively. The chip mounting part 40 is formed together with the reference. The solder bump 11 can be composed of, for example, Sn—Pb solder or solder that does not substantially contain Pb (Pb-free solder) such as Sn—Ag, Sn—Cu, Sn—Ag—Cu, or Sn—Sb. As shown in FIG. 3, the metal terminal pads (back surface lands) 17 in the second conductor layer M13 are also arranged in a grid pattern. In the wiring board 1, the signal transmission path extends from the metal terminal pad 10 formed on one main surface side (first wiring laminated portion L 1 side) of the plate-like core 2 to the other main surface side (second wiring laminated portion). L2 side) is formed so as to reach the metal terminal pad 17 formed on the L2 side.

  FIG. 4 is an enlarged schematic view showing the exposure hole 9. As shown in FIG. 4, the exposed hole 9 formed on the first wiring laminated portion L1 side penetrates the resin composition 8 constituting the solder resist layer SR1 in the plate thickness direction at a position corresponding to the metal terminal pad 10. An upper surface 9a that is open, a bottom surface 9b on which the surface of the metal terminal pad 10 is located, and an inner peripheral wall 9c that is formed through the upper surface 9a and the bottom surface 9b. The inner peripheral wall 9c has a substantially circular shape in each cross section and has a tapered surface whose diameter increases from the bottom surface 9b toward the top surface 9a. Further, the bottom surface 9b is located inside the outer peripheral edge of the metal terminal pad 10, and at least a part of the metal terminal pad 10 is exposed on the entire bottom surface 9b. Thereby, the part including the inner peripheral wall 9c of the exposed hole 9 of the solder resist layer SR1 is a metal terminal pad outer edge covering portion. The exposed holes 9 are filled with the solder bumps 11 described above and connected to the metal terminal pads 10.

  The thickness L of the portion of the solder resist layer SR1 located on the surface of the metal terminal pad 10 (in this embodiment, this thickness L is referred to as the thickness of the solder resist layer) can be 20 μm or more and 30 μm or less. The diameter r of the bottom surface 9b of the exposure hole 9 can be set to 80 μm or more and 120 μm or less. Further, the diameter difference d between the upper surface 9a and the bottom surface 9b of the exposure hole 9 can be 5 or more and 10 μm or less. Since the exposed holes 9 are formed in the solder resist layer SR1 under such conditions, for example, the solder bumps 11 (see FIG. 1) can be easily formed by the inner peripheral wall (tapered surface) 9c, and the volume of the obtained solder bumps 11 can be reduced. Since the shape can be stabilized, it can be improved.

  Next, the manufacturing process of the wiring board 1 of the present invention will be described with reference to FIG. First, conductor layers and resin insulating layers are alternately laminated on both surfaces of the plate-like core 2 by a known build-up method or the like to form the wiring laminated portions L1 and L2. Next, on the main surface (each main surface CP of the first wiring stacked portion L1 and the second wiring stacked portion L2) of the resin insulating layer 6 located on the outermost (uppermost layer) of the wiring stacked portions L1 and L2, Metal terminal pads 10 and 17 are formed (see step 1). Specifically, each main surface CP of the first wiring laminated portion L1 and the second wiring laminated portion L2 is subjected to electroless Cu plating, and a mask material made of photoresist or the like is formed on the metal terminal by a photolithography process. The conductive layer including the pads 10 and 17 is covered so as to be exposed and subjected to electrolytic Cu plating, and then the mask material is removed and the electroless Cu plating is removed by etching. In this way, the pattern plating process is performed to form a conductor layer (Cu plating layer) having the metal terminal pads 10 and 17.

  Next, as shown in Steps 2 to 4 in FIG. 5, the conductor layer having the main surface CP of the resin insulating layer 6 and the metal terminal pads 10 constituting the wiring laminated portion L <b> 1 is covered with the solder resist layer 8. Subsequently, the surface of the solder resist layer 8 is covered with a mask material 70 patterned corresponding to the metal terminal pad 10, and exposed holes 9 are formed by exposure and development with ultraviolet rays through the mask material 70. At this time, the exposure holes 9 for individually exposing the metal terminal pads 10 are formed, and the peripheral edge of the bottom surface of the exposure holes 9 is formed so as to protrude from the outer peripheral edge of the surface of the metal terminal pad 10. . In addition, when a negative type is used as the solder resist layer, the exposure and development time is longer than the normal exposure and development time (when the exposed holes are formed vertically), and the positive type is used. In contrast, the inner peripheral wall 9c of the exposure hole 9 is formed in a tapered shape by shortening the exposure and development.

  Next, as shown in step 5, the surface of the solder resist layer 8 is covered with a mask material corresponding to the exposed holes 9, and a solder paste is filled in the exposed holes 9 by a printing method. Then, the solder bump 11 can be satisfactorily formed on the metal terminal pad 10 by removing the mask material and performing a reflow process.

  6 and 7 are diagrams showing another example in forming the exposure hole 9. As shown in FIG. 6, when the mask material 70 is placed at a predetermined distance t from the surface of the solder resist layer 8 and the exposure holes 9 are formed by exposure and development using ultraviolet rays, the ultraviolet rays that have passed through the mask material 70 are reduced. Since the partial diffusion is performed, the surface of the solder resist layer 8 is irradiated more widely than in the case where the exposed hole 9 is formed in close contact with the mask material. Therefore, the inner peripheral wall 9c of the obtained exposed hole 9 is directed toward the metal terminal pad 10. The taper can be reduced in diameter. Moreover, since the magnitude | size which irradiates the surface of the soldering resist layer 8 can be adjusted by adjusting the predetermined distance t suitably, by extension, the shape of a taper surface can be adjusted.

  Moreover, as shown in FIG. 7, the exposure hole 9 can also be formed in the form of burning the solder resist layer 8 from the surface side by laser beam irradiation. Here, by appropriately setting the focal point of the laser beam, for example, the inner peripheral wall 9c of the exposed hole 9 obtained by moving the focal point away from the exposed hole forming position is tapered toward the metal terminal pad 10. It can be. If the intensity of the laser beam is set lower than usual, the amount of heat input from the laser beam to the solder resist layer 8 is distributed in the depth direction so as to increase toward the surface side. As a result, since the volume of the resin composition (solder resist layer 8) to be burned out increases toward the surface side, the inner peripheral wall 9c of the exposed hole 9 obtained has a tapered shape that decreases in diameter toward the metal terminal pad 10. can do.

  In addition, as a formation method of the exposure hole 9, it is not limited to the said manufacturing method, A various change is possible. For example, since the smear is removed by desmearing and the surface (inner wall) of the resin can be dissolved and removed, a part of the inner wall is melted and tapered by appropriately adjusting the desmear treatment method and time. It can be made into a shape.

Hereinafter, the following experiment was performed in order to confirm the effect of the present invention. The test products used are as follows.
First, as described above, conductor layers and resin insulating layers are alternately laminated on both surfaces of the plate-shaped core to form the respective wiring laminated portions, and then the main wiring laminated portion on the side on which the IC chip or the like is mounted is formed. The surface (a conductor layer having a resin insulating layer and a metal terminal pad) is covered with a 26.3 μm thick solder resist layer. Next, after 1000 holes of each 1000 samples were formed in positions corresponding to the metal terminal pads of the solder resist layer under two conditions, the solder paste was printed and filled in the exposed holes so as to be connected to the metal terminal pads. The yield of solder bumps was measured. The results are shown in Table 1. In addition, the magnitude | size of the upper surface diameter and bottom face diameter in each condition is an average value in 1000 samples. Further, whether the solder bump was good or not was judged by whether or not the solder yield was 90% or more.

  As a result of the example, when the solder resist layer was above 25 μm, the solder yield was good when the inner peripheral wall of the exposed hole was a tapered surface. Specifically, as can be seen from the results in Table 1, when L / d (see FIG. 4) is 3.1 (10 or less) as in the example (specifically, the thickness of the solder resist layer is 26.3 μm (above 25 μm) and diameter difference of 8.4 μm (5 μm or more) Compared with the solder yield of 95.6%, L / d (FIG. 4) When reference is 12.5 (above 10) (specifically, when the thickness of the solder resist layer is 26.3 μm (above 25 μm) and the diameter difference is 2.1 μm (less than 5 μm)) However, the solder yield tends to be as low as 20.5%. That is, the solder bumps were not welded to the metal terminal pads, but floated upward, resulting in defective solder bumps.

  FIG. 8 shows the evaluation of the solder yield under each condition. As shown in FIGS. 8 (a) and 8 (b), when the bottom surface diameter of the exposed hole was increased, a good solder yield could be obtained even if the diameter difference was reduced. Moreover, when the diameter difference was increased, a good solder yield could be obtained even if the bottom surface diameter was reduced. Furthermore, when the thickness of the solder resist layer was reduced, a good solder yield could be obtained even if the exposed holes (bottom diameter and diameter difference) were reduced (in other words, the thickness of the solder resist layer was increased). Even when formed, a good solder yield could be obtained by increasing the exposed hole (bottom diameter and diameter difference).

  It should be noted that the present invention is not limited to these, and various modifications based on the knowledge of those skilled in the art can be made according to the purpose and application without departing from the gist of the claims.

The figure which shows an example of the cross-section of the wiring board which concerns on this invention. Surface view of a wiring board according to the present invention Back view in FIG. Explanatory drawing showing exposure holes Explanatory drawing which shows a part of manufacturing process of the wiring board based on this invention Explanatory drawing 1 showing another example of the manufacturing process Explanatory drawing 2 showing another example of the manufacturing process Diagram showing the relationship between solder resist layer, exposed holes and solder yield

Explanation of symbols

1 Wiring board (resin wiring board)
2 Plate Core 8 (SR1) Solder Resist Layer 9 Exposed Hole 9c Inner Wall 10 Conductor Pad (Metal Terminal Pad)
11 Solder bump

Claims (4)

A wiring board comprising a wiring laminate having a main surface and a solder resist layer,
The solder resist layer has a thickness of more than 25 μm;
The solder-resist layer is provided with an exposed hole for exposing a conductor pad formed on the main surface of the wiring laminated portion, and a solder bump connected to the conductor pad is formed in the exposed hole,
The exposed hole is a tapered surface having a diameter that increases toward the opening in the thickness direction, and a difference in diameter between the upper surface of the exposed hole and the bottom surface of the exposed hole is a tapered surface of 5 μm or more. Wiring board.   The wiring board according to claim 1, wherein L / d is in a range of 10 or less, where L is a thickness of the solder resist layer and d is a difference in diameter between the top and bottom surfaces of the exposed hole. A wiring board provided with a wiring laminated portion having a main surface and a solder resist layer,
The solder-resist layer is provided with an exposed hole for exposing a conductor pad formed on the main surface of the wiring laminated portion, and a solder bump connected to the conductor pad is formed in the exposed hole,
The inner peripheral wall of the exposed hole is a tapered surface whose diameter increases toward the opening in the thickness direction,
A wiring board, wherein L / d is in the range of 10 or less, where L is the thickness of the solder resist layer and d is the difference in diameter between the top and bottom surfaces of the exposed hole.   4. The range of 7d + 0.7r ≧ 32 + 2L, where L is the thickness of the solder resist layer, r is the bottom diameter of the exposed hole, and d is the diameter difference between the top and bottom surfaces of the exposed hole. Wiring board.

Images