JP2006302369A - Semiconductor integrated circuit apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit apparatus in which read-out margin can be increased. <P>SOLUTION: The semiconductor integrated circuit apparatus is provided with a bank 12 arranged in an array state and memory cells being re-writable electrically and respectively, a wiring 16 for read-out to which a read-out signal from the bank is input, a first sense amplifier 14 to which the read-out signal is input, a wiring 15 for write-in/erasure performing write-in/erasure for the memory cell, and bank constituting circuits 11-1 to 11-5 provided with a power supply selecting circuit 13 supplying write-in voltage and erasing voltage to the wiring for write-in/erasure. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and is applied to, for example, a NOR type flash memory.

  Conventionally, for example, noise is generated by a high potential (about 15 V) when writing / erasing a memory cell such as a NOR flash memory (for example, see Patent Document 1) or a decode signal for decoding the cell. Are known.

  When the memory cell is read, if such noise propagates to the read signal line, a read system circuit such as a sense amplifier connected to the signal line malfunctions. For this reason, erroneous cell data is output due to a malfunction caused by such noise. As a result, there is a problem that the read margin of the sense amplifier or the like is lowered.

As described above, the conventional semiconductor integrated circuit device has a situation in which the read margin decreases.
JP 2001-325795 A Specification

  In view of the above circumstances, the present invention provides a semiconductor integrated circuit device capable of increasing a read margin.

  According to one aspect of the present invention, banks that are arranged in an array and each have electrically rewritable memory cells, a read wiring to which a read signal from the bank is input, and the read signal are A bank configuration circuit comprising: a first sense amplifier that is input; a write / erase wiring for writing and erasing the memory cell; and a power supply selection circuit for supplying a write voltage and an erase voltage to the write / erase wiring A semiconductor integrated circuit device can be provided.

  According to the present invention, a semiconductor integrated circuit device capable of increasing the read margin can be obtained.

  Embodiments of the present invention will be described below with reference to the drawings. In this description, common parts are denoted by common reference symbols throughout the drawings.

[First Embodiment]
A semiconductor integrated circuit device according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a plan view showing the semiconductor integrated circuit device according to the first embodiment.

  As illustrated, a plurality of bank configuration circuits 11-1 to 11-4 are provided in an array. The bank configuration circuits 11-1 to 11-4 are configured such that a write operation / erase operation and a read operation can be performed in the bank configuration circuit.

  The bank configuration circuits 11-1 to 11-4 are the smallest units constituting the chip cell array. Each of the bank configuration circuits 11-1 to 11-4 includes a bank 12, a Voldec circuit (power selection circuit) 13, a sense amplifier (S / A) 14, a write / erase wiring 15, and a read bit. Line 16 is provided.

  The bank 12 includes a memory cell array 22 and a cell decoder circuit 17 for selecting a memory cell MC in the memory cell array 22.

  The memory cell array 22 has a plurality of memory cells MC provided at intersections of the read bit lines 16 and the word lines WL. In this embodiment, the memory cell MC is a non-volatile memory cell having a stacked gate structure as an example.

  The cell decode circuit 17 includes a selection transistor TR1 that selects a memory cell column (1PAGE) along the column direction, and a transfer transistor TR2 that transfers a write voltage / erase voltage to the memory cell MC.

  One of the gate and the source / drain of the selection transistor TR1 is connected to the write / erase wiring 15, and the other of the source / drain is connected to the source of the memory cell MC. One of the gate and the source / drain of the transfer transistor TR2 is connected to the write / erase wiring 15, and the other of the source / drain is connected to the gate of the memory cell MC.

  The boldic circuit (power supply selection circuit) 13 includes a write circuit, an erase circuit, and its control circuit, and is configured to supply a cell decode signal 18 serving as a write voltage and an erase voltage to a predetermined cell decode circuit 17. .

  The sense amplifier 14 is configured to amplify and read data read from the bank 12.

  The write / erase wiring 15 electrically connects the cell decoder circuit 17 and the boldic circuit 13 along the row direction, and receives a cell decode signal 18 serving as a write voltage and an erase voltage.

  The read bit line 16 electrically connects the memory cell array 22 and the sense amplifier 14 along the row direction, and receives a read signal of the memory cell MC.

  The number of the write / erase wirings 15 and the read bit lines 16 is only an example, and it is needless to say that there may be more than one.

  Next, the operation of the semiconductor integrated circuit according to this embodiment will be described.

  An example will be described in which the bank configuration circuit 11-1 performs a read operation and the bank configuration circuit 11-3 performs a write / erase operation.

  First, cell data read from the selected memory cell MC in the bank 12 of the bank configuration circuit (read bank) 11-1 is input to the read bit line 16, amplified by the sense amplifier 14, and read.

  On the other hand, in order to write / erase a certain memory cell MC in the bank 12 of the bank configuration circuit (write / erase bank) 11-3, the write / erase voltage is supplied from the Bordic circuit 13 to the write / erase wiring 15. To be applied. Then, a write / erase operation is performed on a desired memory cell MC of the bank configuration circuit 11-3. Here, at the time of the write / erase operation, noise may be generated by the cell decode signal 18 which becomes the write voltage / erase voltage applied to the wiring 15 of the bank configuration circuit 11-3.

  As described above, the semiconductor integrated circuit device according to this embodiment includes the sense amplifiers 14 for the respective bank configuration circuits 11-1 to 11-4.

  For this reason, the read operation is performed even when noise occurs due to the cell decode signal 18 that becomes the write voltage / erase voltage applied to the wiring 15 of the bank configuration circuit 11-3 during the write / erase operation. The sense amplifier 14 of the bank configuration circuit 11-1 does not read data affected by such noise. As a result, erroneous reading can be prevented and desired cell data can be read.

  As a result, it is advantageous in that a read margin can be increased and erroneous data output can be prevented.

  Here, since the read bit line 16 and the write / erase wiring 15 intersect each other on the boldic circuit 13, the cell data may be affected by noise. However, as described above, since the bank configuration circuits 11-1 to 11-4 do not perform the read operation and the write / erase operation at the same time, such an intersecting portion does not cause a problem regarding erroneous read.

  As described above, according to the configuration according to this embodiment, the read operation and the write / erase operation can be performed in a single bank configuration circuit 11-1 to 11-4. This is advantageous in that it can be prevented from being affected by noise during the write / erase operations of the other bank configuration circuits 11-1 to 11-4, and erroneous reading can be prevented.

[Second Embodiment]
Next, a semiconductor integrated circuit device according to a second embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a plan view showing the semiconductor integrated circuit device according to this embodiment. FIG. 3 is a plan view showing an extracted bank configuration circuit 11-3 in FIG. In this description, the description of the same parts as those in the first embodiment is omitted.

  As illustrated, bank configuration circuits 11-1 to 11-12 similar to those in the first embodiment are arranged in an array. And each sense amplifier 14 is arrange | positioned between the bank 12 and the Bordic circuit 13, and the power supply wiring 21-1, 21-2 is arrange | positioned on the Bordic circuit 13 along a column direction, This is different from the semiconductor integrated circuit device according to the first embodiment.

  Further, as shown in FIG. 3, the bank configuration circuit 11-3 includes a plurality of cell arrays 22-1 to 22-8 provided in the bank 12, and a row direction on the cell arrays 22-1 to 22-8. A read bit line 16 is provided. Read signals from the cell arrays 22-1 to 22-8 input to the read bit line 16 are output to the sense amplifier 14. The read signal is amplified and read by the sense amplifier 14.

  The power supply wirings 21-1 and 22-2 are not limited to power supply wirings, and may be any wiring used in the Bordic circuit 13, and may be control wirings, for example.

  As described above, according to the semiconductor integrated circuit device of this embodiment, the same effects as those of the first embodiment can be obtained.

  Further, the sense amplifiers 14 of the bank configuration circuits 11-1 to 11-12 are arranged between the bank 12 and the boldic circuit 13. The power supply wiring 21-1 and the bit line 16 arranged on the Boldic circuit 13 along the column direction do not intersect.

  Therefore, read signals from the cell arrays 22-1 to 22-8 can be directly input to the sense amplifier 14 via the bit line 16. As a result, even if noise occurs when writing and erasing operations are performed on the power supply wiring 21-1 by the other bank configuration circuits 11-1 to 11-6, the sense amplifier 14 is affected by this noise. This is advantageous in that the read margin can be increased.

[Third Embodiment]
Next, a semiconductor integrated circuit device according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a plan view showing the semiconductor integrated circuit device according to this embodiment. In this description, the description of the same parts as those in the first embodiment is omitted.

  As shown in the figure, the bank configuration circuits 11-1 and 11-2 include shield lines 25-1 and 25-2, noise reduction transistors 31-1 and 31-2, and a main power supply line 30. This is different from the first embodiment.

  The shield line 25-1 is arranged in the row direction between the read bit lines 16-1 to shield the read bit lines (metal wiring) 16-1 from the memory cell array 22-1 to the sense amplifier 14-1 at the ground level. It is provided along. The shield line 25-2 is provided along the row direction between the read bit lines 16-2 in order to shield the read bit lines 16-2 from the memory cell array 22-2 to the sense amplifier 14-2 at the ground level. It has been.

  In the noise reduction transistor 31-1, one end of the current path is connected to the shield line 25-1, and the other end of the current path is connected to the main power supply line 30. In the noise reduction transistor 31-2, one end of the current path is connected to the shield line 25-2, and the other end of the current path is connected to the main power supply line 30. In the transistors 31-1 and 31-2, a desired potential is constantly applied to the control terminal, and the current path is always in a conductive state (ON).

  The main power supply line 30 is connected to the Bordic circuits 13-1 and 13-2, and is connected to a so-called VSS power supply.

  FIG. 5 is a diagram showing a noise reduction element that can be changed to the transistors 31-1 and 31-2. (A) is an example of capacitor 32, (b) is an example of resistance element 33, and (c) is a figure showing a noise reduction element. The capacitor 32 has one end and the other end of the electrode connected between the shield line and the main power line. One end and the other end of the resistance element 33 are connected between the shield line and the main power supply line.

  As described above, according to the semiconductor integrated circuit device of this embodiment, the same effects as those of the first embodiment can be obtained.

  Further, the bank constituent circuits 11-1 and 11-2 have noise reduction transistors 31-1 having one end of the current path connected to the shield lines 25-1 and 25-2 and the other end connected to the main power supply line 30. 31-2. The transistors 31-1 and 31-2 are always in a conductive state.

  For example, if a write operation / erase operation is performed on the bank configuration circuit 11-1 while a read operation is being performed on the memory cell array 22-1 of the bank configuration circuit 11-2, the read operation is performed. In some cases, the VSS noise 28 may occur in the Bordic circuit 13-1 of the circuit 11-1. In this case, if the VSS noise 28 propagates to the shield line 25-2 of the bank configuration circuit 11-2 that is performing the read operation, the read bit line 16-2 malfunctions due to coupling and outputs incorrect data. Is also possible.

  However, the noise reduction transistors 31-1 and 31-2 are provided between the shield lines 25-1 and 25-2 and the main power supply line 30. Therefore, the noise 28 can be “smoothed” and reduced by the so-called on-resistance of the transistors 31-1 and 31-2. As a result, the noise 28 caused by the operation of the bank configuration circuit 11-1 other than the read bank configuration circuit 11-2 can be reduced and the noise propagated to the shield line 16-2 of the read bank configuration circuit 11-2 can be reduced. Is advantageous in that it can be read out.

  As shown in FIGS. 5A to 5C, the same effect can be obtained not only by the transistors 31-1 and 31-2 but also by the noise reduction element 34 such as the capacitor 32 and the resistance element 33, for example. can get.

[Fourth Embodiment]
Next, a semiconductor integrated circuit device according to a fourth embodiment of the present invention will be described with reference to FIG. In this description, the description of the same parts as those in the first embodiment is omitted.

  As shown in the figure, the semiconductor integrated circuit device according to this embodiment includes basic power supply lines 30, 40, 41, 42, VSS pads 45, 47, VDD pads 46, 48, wirings 51, 52, and a charge pump peripheral circuit 43. Is different from the first embodiment.

  The main power supply line 30 is provided along the column direction in order to supply VSS power to the Bordic circuits 13-1 and 13-2, and is connected to the VSS pad 45 through the wiring 51. The main power supply line 40 is provided along the column direction in order to supply VDD power to the Bordic circuits 13-1 and 13-2, and is connected to the VDD pad 46 through the wiring 52.

  The main power supply line 41 is provided along the column direction in order to supply VSS power to the sense amplifiers 14-1 and 14-2, and is connected to the VSS pad 47. The main power supply line 42 is provided along the column direction to supply VDD power to the sense amplifiers 14-1 and 14-2, and is connected to the VDD pad 48.

  The charge pump peripheral circuit 43 includes a logic circuit, an output buffer, and the like, and is connected to the main power supply lines 30 and 40 via wirings 51 and 52.

  As described above, according to the semiconductor integrated circuit device of this embodiment, the same effects as those of the first embodiment can be obtained.

  Further, main power supply lines 41 and 42 for applying VSS and VDD power to the sense amplifiers 14-1 and 14-2 are provided, and VSS and VDD power are supplied to other circuits such as the Bordic circuits 13-1 and 13-2. The main power supply lines 30 and 40 to be applied are provided, and the main power supply lines of the sense amplifier circuit and the other circuits are separated from the pads.

  Therefore, the VSS and VDD power supply lines of the sense amplifiers 14-1 and 14-2 can be electrically separated from the VSS and VDD power supply lines in the other circuits 13-1 and 13-2. As a result, for example, the noise 28 generated during the write / erase operation of the bank configuration circuit 11-1 can be prevented from propagating to the sense amplifier 14-2 of the bank configuration circuit 11-2 performing the read operation. This is advantageous in that erroneous determination of the sense amplifier 14-2 can be prevented and desired correct cell data can be read out.

  Also, pads 45, 46, 47, 48 corresponding to the main power supply lines 30, 40, 41, 42 are provided. Therefore, the thickness of the power supply line such as the main power supply line 30 can be reduced to the width of the corresponding pad 45 or the like, which is advantageous in that the voltage value to be applied can be increased to an allowable range of the thickness.

[Modification 1]
Next, a semiconductor integrated circuit device according to Modification 1 of the fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a diagram showing a semiconductor integrated circuit device according to the first modification. In this description, the description of the same parts as those in the fourth embodiment is omitted.

  As shown, the main power supply lines 30 and 41 are connected to the VSS pad 45, and the main power supply lines 40 and 42 are connected to the VDD pad 46, which is different from the fourth embodiment. That is, the pads 45 and 46 themselves are common to the sense amplifiers 14-1 and 14-2 system circuits and the other circuits 13-1 and 13-2 systems. -2 system circuit and the other circuits 13-1 and 13-2 are separated. Therefore, the main power supply lines 41 and 42 are drawn out from the pads 45 and 46 in the row direction and separated.

  According to the above configuration, the same effect as in the fourth embodiment can be obtained.

  Furthermore, according to this embodiment, since the pair of pads 48 and 47 in the fourth embodiment are unnecessary, the pad area for the pads 48 and 47 can be reduced. Therefore, it is advantageous for miniaturization. In addition, as described above, it is advantageous in that erroneous reading due to noise can be prevented and desired correct cell data can be read.

[Modification 2]
Next, a semiconductor integrated circuit device according to Modification 2 of the fourth embodiment of the present invention will be described with reference to FIG. In this description, the description of the same parts as those in the fourth embodiment is omitted.

  As shown in the figure, this embodiment is different from the fourth embodiment in that it further includes main power supply lines 59, 60, 61, 62 and wirings 55, 56.

  The main power supply line 59 is connected to the VSS pad 45, and the main power supply line 61 is connected to the common VSS pad 45 via the wiring 55. The main power supply line 60 is connected to the VDD pad 46, and the main power supply line 62 is connected to the common VDD pad 46 via the wiring 56.

  That is, the pads 45 and 46 themselves are common to the sense amplifiers 14-1 and 14-2 system circuit and the other circuits 13-1 and 13-2 system, and the pads 45 and 46 are connected to the sense amplifiers 14-1 and 14-2. The system circuit and the other circuits 13-1 and 13-2 are electrically separated. Therefore, the main power supply lines 59, 60, 61, 62 are further drawn out from the pads 45, 46 in the row direction and separated.

  According to the above configuration, the same effect as the semiconductor integrated circuit device according to Modification 1 can be obtained. Furthermore, it is possible to adopt such a configuration as necessary.

[Fifth Embodiment]
Next, a semiconductor integrated circuit device according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 9 is a plan view showing the semiconductor integrated circuit device according to this embodiment. In this description, the description of the same parts as those in the first embodiment is omitted.

  As shown in the figure, the semiconductor integrated circuit device according to this embodiment includes bank arrays 77-1 and 77-2, data lines 65-1 and 65-2, a two-stage sense amplifier 72, and a power supply / control circuit 67. This is different from the first embodiment.

  The bank arrays 77-1 and 77-2 are obtained by arranging a plurality of the bank configuration circuits 11-1 to 11-12 in the column direction.

  The data line 65-1 is provided in common to the sense amplifiers 14 (not shown) of the bank configuration circuits 11-1 to 11-6 in the bank array 77-1 along the column direction. 14 is output to the two-stage sense amplifier 72.

  The data line 65-2 is provided in common to each sense amplifier 14 (not shown) of the bank configuration circuits 11-7 to 11-12 in the bank array 77-2 along the column direction. 12 is output to the two-stage sense amplifier 72.

  The two-stage sense amplifier 72 is arranged in the peripheral region of the bank configuration circuits 11-1 to 11-12, and further amplifies the read signals input from the data lines 65-1 and 65-2 to read the cell data. It is configured.

  The power supply / control circuit 67 is arranged in the peripheral region, and is configured to generate a power supply voltage and the like used in the Bordic circuit 13 (not shown) in the bank configuration circuits 11-1 to 11-12. .

  The power supply / control circuit 67 transfers a power supply voltage used in the Bordic circuit 13 via a wiring 69 drawn in the row direction. The wiring 69 has a portion 70-1 that intersects with the data line 65-1 and a portion 70-2 that intersects with the data line 65-2. This portion 70-2 is a portion extending in the row direction from the viewpoint of preventing unbalance of the sense amplifier 72 due to noise on the data line.

  As described above, according to the semiconductor integrated circuit device of this embodiment, the same effects as those of the first embodiment can be obtained.

  Further, the wiring 69 has a portion 70-1 that intersects with the data line 65-1 and a portion 70-2 that intersects with the data line 65-2.

  Here, a case where only the portion 70-1 intersects with the data line and noise is generated in any one of the data lines 65-1 and 65-2 at the time of data reading will be considered. In this case, since only the portion 70-1 intersects with the data line 65-1, the degree of influence of such noise differs between the data lines 65-1 and 65-2. Therefore, the setting of the sense amplifier 72 with respect to noise becomes unbalanced in the data lines 65-1 and 65-2, and a margin difference is generated.

  However, as described above, since the wiring 69 further has a portion 70-2 that intersects with the data line 65-2, no noise environment is generated for any of the data lines 65-1 and 65-2. The same can be done. Therefore, it is advantageous in that the same noise is put on the data lines 65-1 and 65-2 and the influence of the noise is made uniform, so that the settings for the noise of the sense amplifier 72 can be made uniform and the read margin can be increased. is there. In other words, in view of the fact that it is difficult to make the configuration in which the noise of the data lines 65-1 and 65-2 does not absolutely occur, as described above, the same noise is applied to the data lines 65-1 and 65-2. It is configured to put on.

[Sixth Embodiment]
Next, a semiconductor integrated circuit device according to a sixth embodiment of the present invention will be described with reference to FIGS. FIG. 10 is a plan view schematically showing a semiconductor chip 81 for explaining the semiconductor integrated circuit device according to this embodiment. FIG. 11 is a plan view showing the vicinity of the two-stage sense amplifier 72 in FIG. This embodiment relates to the capacity of the data line 69 in the fifth embodiment. In this description, the description of the same parts as those in the fifth embodiment is omitted.

  As shown in the figure, the semiconductor integrated circuit device is further provided with bank arrays 77-3 and 77-4, data lines 65-3 and 65-4, and wirings 69-2 to 69-5. This is different from the embodiment.

  The power supply / control circuit 67 is a power supply used in the Bordic circuit 13 (not shown) in the bank arrays 77-1 to 77-4 via the wirings 69-1 to 69-5 drawn in the row direction. Voltage etc. are being transferred.

  Here, as shown in FIG. 11, the layout (planar shape) of the wirings 69-1 to 69-5 is provided in the vicinity of the two-stage sense amplifier 72. More specifically, for example, the coverage of the sparse part in the wiring 69-1 is increased to the same level as that of the dense part, and a dummy wiring 69-1a is provided in this part. The coverage of 69-1 is made uniform, and the layout is the same.

  Similarly, the layout (planar shape) of the data lines 69-2 to 69-5 is provided in the vicinity of the two-stage sense amplifier 72. More specifically, in the wirings 69-2 to 69-5, the coverage of the sparse part is increased to the same level as that of the dense part, and dummy wirings 69-2a to 69 are provided in the part. -5a is provided, the coverage of the wires 69-2 to 69-5 is made uniform, and the layout is provided in the vicinity of the two-stage sense amplifier 72.

  As described above, according to the semiconductor integrated circuit device of this embodiment, the same effects as those of the fifth embodiment can be obtained.

  Further, by providing dummy wirings 69-1a to 69-5a in the portions where the coverage is sparse in the wirings 69-1 to 69-5, the wirings 69-1 to 69-5 in the vicinity of the two-stage sense amplifier 72 are provided. The layout (planar shape) is the same.

  Therefore, it is advantageous in that the capacitances of the wirings 69-1 to 69-5 can be made uniform and the read margin by the two-stage sense amplifier 72 can be increased. Further, since the capacitances of the wirings 69-1 to 69-5 can be made uniform, the reading setting of the two-stage sense amplifier 72 can be facilitated.

  As described above, the present invention has been described using the first to sixth embodiments, the first modification, and the second modification. However, the present invention is not limited to each of the above-described embodiments and each modification. In the stage, various modifications can be made without departing from the scope of the invention. Moreover, various inventions are included in each of the above embodiments and modifications, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in each embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. In a case where at least one of the obtained effects can be obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

1 is a plan view showing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 6 is a plan view showing a semiconductor integrated circuit device according to a second embodiment of the present invention. The top view which extracts and shows the bank structure circuit in FIG. FIG. 5 is a plan view showing a semiconductor integrated circuit device according to a third embodiment of the present invention. FIGS. 4A and 4B show other examples that can be replaced with the noise reduction transistor in FIG. 4, where FIG. 4A is a plan view showing a capacitor, FIG. 4B is a plan view showing a resistance element, and FIG. Plan view. FIG. 6 is a plan view showing a semiconductor integrated circuit device according to a fourth embodiment of the present invention. The top view which shows the semiconductor integrated circuit device which concerns on the modification 1 of this invention. The top view which shows the semiconductor integrated circuit device which concerns on the modification 2 of this invention. FIG. 9 is a plan view showing a semiconductor integrated circuit device according to a fifth embodiment of the present invention. FIG. 9 is a plan view showing a semiconductor integrated circuit device according to a sixth embodiment of the present invention. FIG. 11 is a plan view showing the vicinity of a sense amplifier in FIG. 10.

Explanation of symbols

  11-1 to 11-5: Bank configuration circuit, 12: Bank, 13: Boldic circuit, 14: Sense amplifier, 15: Write / erase wiring, 16: Read bit line.

Claims (5)

Banks arranged in an array and each having electrically rewritable memory cells; a read wiring to which a read signal from the bank is input; a first sense amplifier to which the read signal is input; A semiconductor comprising: a bank configuration circuit including a write / erase wiring for writing and erasing the memory cell; and a power supply selection circuit for supplying a write voltage and an erase voltage to the write / erase wiring. Integrated circuit device. The semiconductor integrated circuit device according to claim 1, wherein the first sense amplifier is disposed between the bank and the power supply selection circuit. The bank configuration circuit includes a first main power supply line that supplies a power supply voltage to the power supply selection circuit, a shield line that shields the readout wiring, and one end of a current path connected to the first main power supply line. The semiconductor integrated circuit device according to claim 1, further comprising: a noise reduction element connected to the shield line. The semiconductor integrated circuit device according to claim 3, wherein the bank configuration circuit includes a second main power supply line that supplies a power supply voltage to the first sense amplifier. A first data line provided in common to each of the first sense amplifiers of the plurality of bank configuration circuits arranged along the first direction, to which a read signal from the first sense amplifier is input;
A second data line provided in common to each of the first sense amplifiers of the plurality of bank configuration circuits arranged along the first direction, to which a read signal from the first sense amplifier is input;
A second sense amplifier disposed in a peripheral region of the bank configuration circuit and to which the read signal from the first data line and the second data line is input;
A wiring that is arranged in the peripheral region so as to intersect the first data line and the second data line, and that supplies a power supply voltage to each of the power supply selection circuits of the bank configuration circuit. The semiconductor integrated circuit device according to any one of claims 1 to 4.

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