JP2006292854A - Electrooptical device, method for driving the same, and electronic appliance - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent lowering of display quality caused by crosstalk and noise. <P>SOLUTION: Pixels 116 are arranged corresponding to intersections of scanning lines 311 and columns of first data lines 211 and second data lines 212. Each pixel 116 has a pixel capacitor Cpix to hold a difference of voltages applied to respective first and second pixel electrodes 231, 232, a first TFT 241 of which the gate, the source, and the drain are respectively connected to the scanning line 311, the first data line 211 and the first pixel electrode 231, and a second TFT 242 of which the gate, the source, and the drain are respectively connected to the scanning line 311, the second data line 212 and the second pixel electrode 232. Wherein, in the case the scanning line 311 of a certain row i is selected, the difference voltage between the first data line 211 and the second data line 212 of a column j is made to be a value corresponding to a gray scale of a pixel of i row, j column. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a technique for preventing deterioration in display quality due to crosstalk and noise.

In particular, in an electro-optical device that displays an image using an electro-optical material such as liquid crystal, in a type in which a pixel is switched by a thin film transistor (hereinafter simply referred to as TFT), an individual pixel electrode is provided for each pixel. On the other hand, the common electrode (counter electrode) is commonly opposed across the pixels across the liquid crystal, and when the scanning line is selected, the TFT is turned on between the data line and the pixel electrode. In this configuration, when the scanning line is selected and the TFT is turned on, if a voltage corresponding to the gray level of the pixel is supplied to the data line, the voltage is applied to the pixel electrode. Even when the selection of the scanning line is completed and the TFT is turned off, the voltage is held until the scanning line is selected again by the pixel capacitor having the liquid crystal sandwiched between the pixel electrode and the common electrode. become.

By the way, in this configuration, during the period when the scanning line is selected, a voltage corresponding to the gradation is applied to each pixel electrode, so that the potential of the common electrode capacitively coupled to the pixel electrode varies. When the potential of the common electrode fluctuates, the voltage held in the pixel capacitance is affected, so that the gradation (brightness) of the pixel deviates from the target value, and so-called crosstalk occurs.
In view of this, a technique has been proposed in which the potential of the common electrode is stabilized by detecting the potential variation of the common electrode and applying a voltage that cancels the potential variation to the common electrode.
JP-A-9-218388

However, since this technique is a so-called coping therapy technique that cancels the potential fluctuation of the common electrode, crosstalk occurs if the cancellation of the potential fluctuation is not in time.
Therefore, in the present invention, the voltage fluctuation of the data line and the pixel electrode does not affect the holding voltage of the pixel capacitance, and the electric quality capable of radically preventing the display quality from being deteriorated due to crosstalk or noise. To provide an optical device, a driving method, and an electronic apparatus.

In order to achieve the above object, the present invention provides a plurality of scanning lines and a plurality of columns of first and second lines.
A pixel provided corresponding to an intersection with a pair of data lines, each pixel having a first and a second pixel electrode, and a voltage applied to each of the first and second pixel electrodes. When the corresponding scanning line is selected with the pixel capacitance holding the difference, the first switching element that is in a conductive state between the first data line and the first pixel electrode and the corresponding scanning line are selected. A pixel having a second switching element that is conductive between the second data line and the second pixel electrode, and a scanning line that selects the plurality of rows of scanning lines in a predetermined order. Data line driving for supplying a data signal corresponding to a gradation of a pixel to the first data line and supplying a predetermined voltage to the second data line when the driving circuit and the corresponding scanning line are selected And a circuit. According to the present invention, even if a voltage change of the scanning line or external noise is applied to the first and second data lines, the potentials of the first and second data lines change by the same amount in the same direction. As a result of canceling out the fluctuations, the voltage held in the pixel capacitance is not affected.

In the present invention, the second data line is common to each column, and the data line driving circuit sets the first data line to a level higher than the predetermined voltage by a voltage corresponding to a pixel gradation. Alternatively, a state in which the voltage on one side of the lower level and a state in which the voltage on the other side higher or lower than the predetermined voltage is set according to the gradation of the pixel are alternately repeated at a predetermined cycle. It is good. In the present invention, the data line driving circuit may be configured such that the first data line is set to a predetermined voltage, and the second data line paired with the first data line is set to have a pixel gradation higher than the predetermined voltage. A state in which the voltage on one side is higher or lower by a voltage corresponding to the first data line, and the voltage on the one side higher or lower than the predetermined voltage by a voltage corresponding to the gradation of the pixel. A state in which the voltage is set and the second data line paired with the first data line is set to the predetermined voltage may be alternately repeated at a predetermined cycle. Further, in the present invention, the data line driving circuit makes the voltage of the first data line and the voltage of the second data line symmetrical with each other with respect to the predetermined voltage, A configuration in which a low voltage is inverted may be employed.

In the present invention, a configuration having an auxiliary capacitor in parallel with the pixel capacitor is preferable. With this configuration, it is possible to suppress the charge that leaks when the first and second switching elements are off. Here, the auxiliary capacitor may be a stacked structure of the first pixel electrode, the insulating layer and the second pixel electrode, or a capacitor having a stacked structure of the first pixel electrode, the insulating layer and the conductive layer, A series connection with a capacitor having a stacked structure of a conductive layer, the insulating layer, and the second pixel electrode may be employed.
The present invention can be conceptualized not only as an electro-optical device, but also as a driving method of the electro-optical device, and further as an electronic apparatus having the electro-optical device.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention.
As shown in this figure, the electro-optical device 10 includes a liquid crystal panel 100, a data line driving circuit 250, a scanning line driving circuit 350, and a control circuit 400. Of these, the liquid crystal panel 10
At 0, the first data line 211 and the second data line 212 form a pair, and 240 columns each extend in the column (Y) direction, while 320 scanning lines 311 extend in the row (X) direction. It is extended and provided.
The pixels 116 are arranged corresponding to the intersections between the pair of the first data line 211 and the second data line 212 and the 320 scanning lines 311. Therefore, in this embodiment, the pixels 116 are arranged in a matrix of 320 vertical rows × 240 horizontal columns. However, the present invention is not limited to this.
In the present embodiment, the second data lines 212 are common to each other, and the voltage Vc described later is used.
Are commonly applied.

Here, a detailed configuration of the pixel 116 will be described. FIG. 2A is a plan view showing the configuration of the pixel 116, and FIG. 2B is a diagram showing the electrical configuration of the pixel 116. In either case, a configuration of a total of four pixels of 2 × 2 corresponding to the intersection of the i row and the (i + 1) row adjacent thereto, the j column and the (j + 1) column adjacent thereto is shown.
Note that i and (i + 1) are symbols for generally indicating a row in which the pixels 116 are arranged, and are integers of 1 to 320, and j and (j + 1) are columns in which the pixels 116 are arranged. It is a symbol in the general case, and is an integer from 1 to 240.

As shown in FIG. 2B, each pixel 116 includes a pixel capacitor Cpix, an n-channel first TFT 241, and an n-channel second TFT 242.
Here, since each pixel 116 has the same configuration, the i-th row and j-th column will be described as representative. In the pixel 116 in the i-th row and j-th column, the gate of the first TFT 241 is connected to the i-th scanning line 311. On the other hand, its source is connected to the first data line 211 in the j-th column, and its drain is connected to the first pixel electrode 231. In the pixel 116 in the same i row and j column, the gate of the second TFT 242 is connected to the scanning line 311 in the i row, the source is connected to the second data line 212 in the j column, and the drain is connected to the second row. The two pixel electrodes 232 are connected.
The first TFT 241 and the second TFT 242 are designed to have the same element characteristics.

The liquid crystal panel 100 has a configuration in which a pair of substrates of an element substrate and a counter substrate are bonded together with a certain gap therebetween, and liquid crystal is sandwiched between the gaps. Further, the element substrate is provided with a scanning line 311, a first data line 211, a second data line 212, a first pixel electrode 231, a second pixel electrode 232, a first TFT 241 and a second TFT 242, and this electrode formation surface Are bonded so as to face the counter substrate. FIG. 2A shows a plan view of the electrode forming surface of the element substrate in this configuration.
As can be seen from this figure, the liquid crystal panel 100 uses a so-called IPS (in plane switching) system in which the direction of the electric field applied to the liquid crystal is the substrate surface direction.
More specifically, a scanning line 311 is formed on the element substrate by patterning the gate electrode layer, and an insulating layer and a semiconductor layer (not shown) are deposited thereon to form the first TFT 241 and the second TFT 2.
After the formation of 42, the first data line 211, the second data line 212, the first pixel electrode 231 and the second pixel electrode 232 are further formed by patterning the first metal layer via the insulating layer. It has become.
Here, the first pixel electrode 231 and the second pixel electrode 232 are both formed in a comb-like shape, and are disposed so as to face each other with a certain distance. Therefore, in the present embodiment, the pixel capacitance Cpix is represented by a capacitance generated when the first pixel electrode 231 and the second pixel electrode 232 face each other through the liquid crystal.
Note that one of the first pixel electrode 231 and the second pixel electrode 232 is rectangular, for example, and the other has a comb shape, and the other comb is formed on one rectangular pixel electrode via an insulating layer. FFS (fringe field s), which is a modification of the IPS system, in which a tooth-shaped pixel electrode is formed.
(witching) method may be adopted.

In the pixel capacitor Cpix, the electric field has a strength corresponding to the holding voltage and is vertical (Y
) Direction and the alignment state of the liquid crystal changes. For this reason, the amount of light passing through the polarizer (not shown) is a value corresponding to the effective voltage value.
In the present embodiment, the effective voltage value applied to the pixel capacitor Cpix is the first pixel electrode 231.
Therefore, in order to set the pixel in i row and j column to the target gradation, a selection voltage is applied to the scanning line 311 in the i row, and the first TFT 241 and the second TFT 24 are determined.
2 is made conductive (ON), and the voltage difference between the first data line 211 and the second data line 212 in the j-th column may be set to a value corresponding to the gradation of the pixel in the i-th row and j-th column. become.
In the present embodiment, for convenience of explanation, if the voltage effective value is close to zero, the light transmittance is maximized to display white, while the amount of transmitted light decreases as the voltage effective value increases. Finally, a normally white mode in which the black display with the minimum transmittance is set.
2B, a capacitance Cgd1 is parasitic between the gate and drain of the first TFT 241, and similarly, a capacitance Cgd2 is parasitic between the gate and drain of the second TFT 242.

Returning to FIG. 1 again, the control circuit 400 controls the liquid crystal panel 100 according to various control signals such as a latch pulse LP defining the start of one horizontal scanning period, a polarity instruction signal POL, a start pulse DY, and a clock signal CLY. Is controlled.

As shown in FIG. 3, the scanning line driving circuit 350 generates a start pulse DY supplied at the beginning of the vertical scanning period (1F) at the rising edge of the clock signal CLY in which one period is one horizontal scanning period (1H). Sequentially captures and shifts, and shifts the shift signal to the scanning signals Y1, Y2, Y
3,..., Y320, the scanning lines 3 in the first, second, third,.
11 is supplied. For this reason, the scanning lines 311 of 1 to 320 rows are selected one by one for each horizontal scanning period (1H), and the voltage V corresponding to the H level when selected.
While dd is applied, a voltage Vss (= Gnd) corresponding to the L level is applied when not selected.

Next, the data line driving circuit 250 will be described. The data line driving circuit 250 includes a data supply circuit 252 and a D / A conversion circuit 254 corresponding to each column, and applies a voltage Vc to the second data line 212 common to each column.
The data supply circuit 252 has storage areas (not shown) corresponding to a matrix arrangement of 320 vertical rows × 240 horizontal columns, and in each storage area, the gradation value (brightness) of the corresponding pixel 116 is specified. The gradation data Da is stored. The gradation data Da is supplied from a host device (not shown), and when the display content is changed, the gradation data Da stored in the corresponding storage area is rewritten.
Further, the data supply circuit 252 causes the scanning line driving circuit 350 to perform the scanning line 3 in the i-th row.
11 is selected, the pixels 11 of 1 to 240 columns located in the scanning line 311 of the i-th row
6 gradation data are simultaneously read from the storage area and output.

The D / A conversion circuit 254 in each column converts the gradation data read by the data supply circuit 252 into an analog signal having a polarity specified by the polarity instruction signal POL with the voltage Vc as a reference, and a corresponding first signal. One data line 211 is supplied as a data signal. 1, 2
,..., The data signals supplied to the first data lines 211 in the 240th column are respectively X1,
X2, X3,..., X240, and in particular, when a general explanation is given without specifying a column,
Indicated as Xj.

Here, the polarity instruction signal POL is a signal for designating the positive polarity writing of the pixel capacitor Cpix if it is H level, and the signal for designating the negative polarity writing of the pixel capacitance Cpix if it is L level. As shown in FIG. 3, the polarity is inverted every vertical scanning period (1H).
In the present embodiment, the writing polarity of the pixel capacitor Cpix is set to the first pixel electrode 2 for convenience.
A case where 31 is higher than the second pixel electrode 232 is positive, and a case where the first pixel electrode 231 is lower than the second pixel electrode 232 is negative. The reason why the writing polarity of the pixel capacitor Cpix is alternately driven with a positive polarity and a negative polarity (AC driving) is to prevent deterioration of the liquid crystal due to application of a DC component.

By the way, in the case of AC driving, regarding the relationship between the writing polarity for the pixels in one screen,
(1) Scan line inversion (row inversion) for inverting the writing polarity for each scan line;
(2) Data line inversion (column inversion) for inverting the writing polarity for each data,
(3) Pixel inversion (dot inversion) that combines scanning line inversion and data line inversion to invert the writing polarity between pixels that are adjacent vertically and horizontally,
(4) Surface inversion to align all (frame inversion)
There are four possible types.
In the present embodiment, the polarity designation signal POL specifies the writing polarity of each column to be the same, and the polarity designation signal POL is fixed for one vertical scanning period (1F). Frame inversion is adopted. However, the present invention is not limited to this frame inversion method.

The data signal output by the data line driving circuit 250 will be described by using the j-th column as a representative. The data signal Xj supplied to the first data line 211 in the j-th column is shown in FIG.
As shown in That is, the data line driving circuit 250 performs the data signal in the horizontal scanning period in which the first scanning line 311 is selected in one vertical scanning period in which the polarity instruction signal is at the H level and the positive writing is instructed. Xj is output as a higher side by a voltage corresponding to the gradation of the pixel in the first row and jth column with respect to the voltage Vc.
In the horizontal scanning period in which the next second scanning line 311 is selected, the positive polarity writing is instructed, so that the data line driving circuit 250 is in the horizontal scanning period in which the second scanning line 311 is selected. in outputting the data signal Xj, as only the high-side voltage according to the gradation of the pixels in two rows and j-th column with respect to the potential V _C. Hereinafter, this operation is repeated until the horizontal scanning period in which the last scanning line 311 of the 320th row is selected.
The data line driving circuit 250 lowers the data signal Xj by a voltage corresponding to the gradation of the pixel with respect to the voltage Vc in one vertical scanning period in which the polarity instruction signal becomes L level and negative polarity writing is instructed. Output as side.
Therefore, if there is no change in the display contents in the adjacent two vertical scanning periods (if the gradation data stored in each storage area is not updated), the data signal Xj has the voltage Vc as shown in FIG. The reference is symmetrical on the high and low sides.

Here, the voltage relationship in FIG. 3 will be described. The voltage Vss is the ground potential (= Gnd).
In this embodiment, it is a voltage reference (voltage zero), and the voltage Vdd is on the higher power supply voltage side. These voltages Vss and Vdd are respectively supplied to the scanning signals Y1, Y2,
This corresponds to the L level and H level of Y3,.
On the other hand, the voltage Vc, which is the reference for the writing polarity in the pixel capacitor Cpix, is an approximately intermediate value between the voltages Vss and Vdd.
In FIG. 3, the vertical voltage scales of the Y-side scanning signals Y1 to Y320 and the like and the X-side data signal Xj are different for convenience (also in FIGS. 6 and 7 described later). The same).

Next, writing in the electro-optical device having such a configuration will be described. FIG.
These are diagrams showing the writing of pixels in i rows and j columns in relation to the scanning signal Yi.
In FIG. 4, the voltage of the first pixel electrode 231 in the pixel 116 in the i row and j column is indicated by a thick solid line, and the voltage of the second pixel electrode 232 in the pixel 116 in the i row and j column is indicated by a solid solid line. The voltage of the scanning signal Yi is indicated by a thin solid line.
In one horizontal scanning period (1H) in which the scanning signal Yi in the i-th is at the H level, for example, i
When the pixel in the row j column is gray between white and black, the data signal Xj has a higher voltage (Vc + Vg) than the voltage Vc by the voltage Vg if it is positive. Here, the voltage Vg is a voltage specified by the gradation data of i rows and j columns read from the data supply circuit.
When the scanning signal Yi becomes H level, in the pixel 116 in the i-th row, the first TFT 241 is formed.
The second TFT 242 is turned on, and the source and drain are both in a conductive state. For this reason, the first pixel electrode 231 in the i-th row and the j-th column is electrically connected to the first data line 211 in the j-th column, and similarly, the second pixel electrode 232 is in the second data in the j-th column. Line 212
It will be in the state electrically connected to.
Accordingly, in one horizontal scanning period (1H) in which the scanning signal Yi is at the H level, the first pixel electrode 231 is at the voltage (Vc + Vg) and the second pixel electrode 232 is at the voltage Vc in i row and j column.
Thus, the difference voltage becomes a voltage Vg corresponding to the gradation of i rows and j columns.

Incidentally, since the capacitors Cgd1 and Cgd2 are parasitic in the first TFT 241 and the second TFT 242 (see the broken line in FIG. 2B), the selection of the scanning line 311 in the i-th row is completed, and the scanning signal Yi is at the H level. When the level changes from L to L, a phenomenon called pushdown (also called punch-through or field-through) occurs in which the drain voltage changes in the direction of change. Specifically, in the first TFT 241, this push-down occurs due to the charges charged in the capacitors Cpix and Cgd1 being redistributed to each capacitor at the moment when they are turned off. .
Therefore, at the moment when the scanning signal Yi changes to the L level, the drain of the first TFT 241,
That is, the first pixel electrode 231 in the i row and the j column drops from the voltage (Vc + Vg) by the voltage ΔV. Here, ΔV is the amount of change in drain voltage due to pushdown, and the capacitance ratio Cgd1
/ (Cgd1 + Cpix) is multiplied by the gate voltage change (Vdd−Vss).
However, in this embodiment, pushdown occurs also in the drain of the second TFT 242. As described above, since the second TFT 242 is designed to have the same characteristics as the first TFT 241, Cgd2 = Cgd1. For this reason, at the moment when the scanning signal Yi changes to the L level, the same voltage ΔV from the voltage Vc is applied to the second pixel electrode 232 in the i row and j column.
Only drop.

In the case of negative polarity writing, in one horizontal scanning period (1H) in which the scanning signal Yi is at the H level, the data signal Xj is lower than the voltage Vc by the voltage Vg as shown in FIG. Voltage (Vc-Vg).
Therefore, when the scanning signal Yi becomes H level in the case of negative polarity writing, the first pixel electrode 231 in the i row and j column becomes the voltage (Vc−Vg), and the second pixel electrode 232 becomes the voltage Vc. At the moment when the scanning signal Yi changes to the L level, the first pixel electrode 231 decreases from the voltage (Vc−Vg) by the voltage ΔV, and the second pixel electrode 232 decreases from the voltage Vc by the same amount of voltage ΔV.
In addition, although generally described in the j-th column here, such an operation is executed over all of the columns 1 to 240.

In general, in the normally white mode, the pixel capacitance Cpix becomes smaller as the bright state is achieved, that is, the capacitance value changes according to display contents. For this reason, the voltage ΔV that decreases due to pushdown depends on the pixel capacitance Cpix (that is, the gradation of the pixel). However, according to the present embodiment, at the moment when the scanning signal Yi changes to the L level, the first pixel electrode 231 and the second pixel electrode 232 change by the same amount of voltage ΔV and cancel each other. The voltage Vg held in the pixel capacitor Cpix of i row and j column is not affected by pushdown or writing polarity, and is determined only by the gradation.
For this reason, according to the present embodiment, the effective voltage values applied to the pixel capacitor Cpix are the same for the positive polarity and the negative polarity, so that the application of a DC component is prevented, and the occurrence of flicker is suppressed. At the same time, it is possible to prevent deterioration of the liquid crystal.

This point will be described in detail in comparison with the prior art. FIG. 15 is a diagram showing a conventional configuration. As shown in this figure, conventionally, only the data line 215 is provided in each column, and the pixel 117 is arranged corresponding to the intersection of the scanning line 311 and the data line 215.
In this conventional pixel 117, the gate of the n-channel TFT 245 is connected to the scanning line 311, the source is connected to the data line 215, and the drain is connected to the individual pixel electrode 235 for each pixel. A conventional pixel capacitor has a configuration in which liquid crystal is sandwiched between a pixel electrode 235 and a common electrode 108 common to the pixels. The common electrode 108 is maintained at a constant voltage LCcom over time.

In this configuration, AC driving is performed on the higher side (positive polarity) and the lower side (with respect to the common electrode 108).
Alternate writing with negative polarity). However, in the conventional configuration, when alternate writing is performed in a state where the voltage LCcom is matched with the voltage Vc which is the reference for the writing polarity, as shown in FIG. The effective voltage value applied to the pixel capacitor in writing becomes larger than the effective voltage value applied to the pixel capacitor in positive writing.
For this reason, the voltage LCcom of the common electrode 108 is set higher than the voltage Vc, which is a reference for the writing polarity, so that the effective voltage values of the pixel capacitors are equal to each other even when positive polarity / negative polarity writing is performed at the same gradation. ,
If the voltage ΔV that decreases due to pushdown is set lower (see FIG. 16B),
At first glance it seems to be good.

However, with this setting, the decrease in the voltage LCcom of the common electrode 108 is uniform regardless of the gradation. As described above, the voltage ΔV that decreases at the pixel electrode 235 due to the push-down of the TFT 245 fluctuates depending on the pixel capacitance Cpix (pixel gradation), and therefore, positive polarity writing and negative polarity at a certain gradation value. If the voltage LCcom of the common electrode 108 is set so that the voltage effective value of the pixel capacitance is the same in writing, the effective voltage value of the pixel capacitance is positive writing and negative polarity in other gradation values. It will be different from sex writing.
Therefore, in the conventional pixel configuration, the effective voltage applied to the pixel capacitor cannot be set to the same value in the positive polarity writing and the negative polarity writing regardless of the voltage of the common electrode 108. The application of a direct current component cannot be prevented.

On the other hand, in this embodiment, the same amount of pushdown as the pushdown generated in the first TFT 241 occurs in the second TFT 242, and the influences cancel each other. Therefore, the effective voltage value applied to the pixel capacitance is Not affected by the voltage ΔV. For this reason, according to this embodiment, the effective voltage value applied to the pixel capacitor Cpix can be completely matched between the positive polarity writing and the negative polarity writing.

Furthermore, according to the present embodiment, there is an effect as compared with the conventional configuration in terms of reducing crosstalk. Next, the reduction of the crosstalk will be described.
First, in the case of AC driving, as described above, there are four types of relations regarding the writing polarity with respect to the pixels in one screen.
In the conventional pixel configuration shown in FIG. 15, when row inversion and frame inversion are adopted among the four types, so-called lateral crosstalk occurs.
Here, the horizontal crosstalk is, for example, in the case of attempting to display a black area and a white area on a window with a gray background of halftone in the normally white mode as shown in FIG.
As shown in FIG. 7, the black region is a phenomenon in which the gray region adjacent in the horizontal (horizontal scanning) direction becomes slightly brighter, and the white region is a phenomenon in which the gray region adjacent in the horizontal direction becomes slightly darker.

The cause of the occurrence of such horizontal crosstalk will be described. The equivalent circuit for one row of pixels shown in FIG. 15 is as shown in FIG. 18A, and the common electrode 108 has not a little resistance component. Have. FIG. 18A can be simplified as shown in FIG. 18B when each column has the same gradation value. That is, the TFT 245 is replaced with an ideal switch, while the pixel electrodes 235 are collectively referred to as a node A, and the common electrode 108 facing the pixel electrodes 235 is a node B.
Here, in the row inversion and the frame inversion, the writing polarity of the pixels corresponding to the same scanning line (line) 311 is the same, so that the scanning signal Yi becomes the H level as shown in FIG. Thus, when the node A changes from a negative voltage (Vc−Vg) to a positive voltage (Vc + Vg), for example, spike noise appears at the node B.
If the selection of the i-th scanning line is completed and the scanning signal Yi changes to the L level before the noise has converged, the voltage between the node A and the node B, that is, the voltage held in the pixel capacitance is , Will be less than the target value.
In the normally white mode, the noise is lower than when displaying a gray gray.
Since the black display is larger and the white display is smaller, the horizontal crosstalk as shown in FIG. 17 occurs.

In order to eliminate such horizontal crosstalk, column inversion or dot inversion may be employed. The reason for this is that the writing polarity is reversed at least for each column, so when a scanning line in the same row is selected, noise due to a change from one of positive polarity and negative polarity to the other, and positive polarity and negative polarity This is because noise due to a change from the other to one occurs and both noises cancel each other, so that the voltage fluctuation at node B is sufficiently small.
However, even if column inversion or dot inversion is adopted, noise cannot be completely canceled depending on display contents. For example, in the case where only odd-numbered columns (or even-numbered columns) are displayed in black, when a certain scanning line is selected, black pixels are concentrated in either positive polarity writing or negative polarity writing. As a result, horizontal crosstalk occurs similarly to row inversion or frame inversion.

On the other hand, in the case of color display, for example, a red region is displayed in a window in a configuration in which pixels corresponding to R (red), G (green), and B (blue) are repeatedly arranged in the horizontal scanning direction as RGBRGB. In this case, since the odd-numbered red pixels and the even-numbered red pixels coexist, lateral crosstalk can be suppressed by canceling out noise caused by the two red pixels.
However, in recent years, a technique has been proposed for color display using four primary colors in which C (cyan) is added to RGB in addition to RGB. In this technique, when the pixel arrangement is an odd number of rows, R
GRGRG ... is repeated, and BCBCBC ... is repeated in even-numbered rows.
In this pixel array, when the red region is displayed in a window, the red pixels are fixed to odd columns, so that when a certain scanning line is selected, the red pixels are written in positive polarity or negative polarity. Since it concentrates on either of the above, it is still the same as row inversion or frame inversion,
Lateral crosstalk occurs.

On the other hand, in this embodiment, noise (voltage change of the pixel electrode) cancels out by one pixel. Therefore, in any of row inversion, column inversion, dot inversion, and frame inversion,
It is possible to suppress lateral crosstalk without depending on display contents.
Further, in the present embodiment, since the voltage corresponding to the gradation is held for the pixel capacitor Cpix via the first data line 211 and the second data line 212, there is an effect of being resistant to noise. Specifically, since the difference voltage between the first data line 211 and the second data line 212 is held in the pixel capacitor Cpix, the voltage change of the scanning signal with respect to the first data line 211 and the second data line 212, etc. Even if some noise is superposed, the noises cancel each other, and as a result, the voltage held in the pixel capacitor Cpix is not affected.

In the above-described embodiment, the second data line 212 is shared across the columns. However, it is sufficient to hold the voltage corresponding to the gradation while driving each pixel capacitor with AC.
Therefore, for example, as shown in FIG. 5, the second data line 212 may be independent over each column.
In FIG. 5, an output circuit 256 is provided for each column. Here, in general, the output circuit 256 in the j-th column has a data supply circuit in which the difference voltage between the first data line 211 and the second data line 212 in the j-th column has the polarity specified by the polarity instruction signal POL. The data is output so as to have a value corresponding to the gradation data read from 252.
Specifically, as described above, the case where the first pixel electrode 231 is higher than the second pixel electrode 232 is positive, and the case where the first pixel electrode 231 is lower than the second pixel electrode 232 is negative. When the positive polarity writing is designated, the output circuit 256 outputs the first
When the data line 211 is higher than the second data line 212 and negative polarity writing is designated, the first data line 211 is lower than the second data line 212, and in either case, 1
The differential voltage between the data line 211 and the second data line 212 is output so as to have a value corresponding to the gradation data.
For convenience, the data signal output from the output circuit 256 of the j-th column to the first data line 211 of the j-th column is denoted as Xa-j, and the data signal output to the second data line 212 of the j-th column. Xb
Indicated as −j.

Here, as an aspect in which the output circuit 256 outputs the difference voltage corresponding to the gradation to the first data line 211 and the second data line 212, for example, one of the first data line 211 and the second data line 212 is localized. The first mode in which the other is swung alternately, the second mode in which both the first data line 211 and the second data line 212 are swung with respect to the reference voltage, and the like are conceivable.
In FIG. 6, in the case of positive polarity writing, the data signal Xb-j is set to the voltage Vr,
For the data signal Xa-j, the voltage Vr is set to the higher side by a voltage corresponding to the gradation, while in the case of negative writing, the data signal Xa-j is set to the voltage Vr and the data signal X
For b-j, an example of the first mode is shown in which the voltage Vr is used as a reference and the voltage corresponding to the gradation is set to the higher side.
As for the voltage Vr, it is sufficient that the maximum difference voltage corresponding to black can be written between the voltage Vdd and the voltage Vss in the normally white mode. In the example of FIG. 6, since the voltage corresponding to the gradation is shifted to the higher side, the localization voltage Vr is set lower than the intermediate value between the voltage Vdd and the voltage Vss.
Although not particularly illustrated, in the case of positive polarity writing, the data signal Xa-j is set to a localization voltage, and the data signal Xb-j is set to a low-order side by a voltage corresponding to the gradation with reference to the localization voltage. In the case of negative polarity writing, the data signal Xb-j may have a localization voltage, and the data signal Xa-j may have a lower voltage by a voltage corresponding to the gradation with reference to the localization voltage.

In FIG. 7, the data signal Xa-j in the case of positive polarity with respect to the voltage Vc.
For the data signal Xb-j, only half of the voltage corresponding to the gradation is set to the higher side.
On the other hand, in the case of negative polarity, the data signal Xa-j is set to the lower side by half of the voltage corresponding to the gradation, and the data signal Xb-j is set to the lower side. An example of the second mode is shown in which half of the voltage corresponding to the gradation is set to the higher side. In this example, the data signal Xa-j and the data signal Xb-j are shifted by half of the voltage corresponding to the gradation with respect to the voltage Vr when viewed alone. The voltage depends on the key.
As for the amplitude reference, if the maximum difference voltage corresponding to black can be written between the voltage Vdd and the voltage Vss in the normally white mode, the voltage Vc can be written.
Not necessarily.

Thus, according to the first aspect and the second aspect, the amplitude width of the data signal can be reduced to half compared to the example shown in FIG. It is possible to simplify the configuration of the D / A conversion circuit that converts the voltage into an analog signal.

In FIG. 7, the polarity instructing signal POL is inverted every horizontal scanning period (1H), and the polarity is inverted even when attention is paid to the horizontal scanning period in which the same scanning line is selected in the adjacent vertical scanning period. Since this is a relationship, line inversion occurs.
Further, the polarity instruction signal POL is supplied to one of the odd-numbered column and the even-numbered column, and the polarity instruction signal POL logically inverted to the other of the odd-numbered column and the even-numbered column is supplied, respectively, and the polarity instruction signal POL is shown in FIG. If the waveform shown in FIG. 7 is employed, column inversion is performed, and if the waveform shown in FIG. 7 is employed, dot inversion is performed.

In the above-described embodiment, the pixel 116 can have various configurations other than the configuration illustrated in FIG. Therefore, in the following, application / deformation configuration of the pixel will be described. First, the pixel 116 shown in FIG. 8B has a configuration in which an auxiliary capacitor 250 is provided in parallel to the pixel capacitor Cpix in the configuration of the embodiment (see FIG. 2B). For example, as shown in FIG. 8A, the auxiliary capacitor 250 has a structure in which a first pixel electrode 231 and a second pixel electrode 232 are stacked via an insulating layer (not shown).
According to this configuration, the pixel capacitance Cpix apparently increases by the amount of the auxiliary capacitance 250, and therefore, the charge leaked from the pixel capacitance Cpix through the first TFT 241 and the second TFT 242 when off is reduced. For this reason, it is possible to suppress the occurrence of flicker due to a change in the holding voltage of the pixel capacitor Cpix.
However, in the configuration shown in FIG. 8A, after the first pixel electrode 231 and the like are formed by patterning the first metal layer, the second pixel electrode 232 is formed by patterning the second metal layer via the insulating layer. Compared with the configuration of FIG. 2A in which the first pixel electrode 231 and the second pixel electrode 232 can be formed by patterning the same metal, the manufacturing process is complicated.

Therefore, the pixel 116 may have a configuration shown in FIGS. 9A and 9B.
9A, in the auxiliary capacitor 250, the first pixel electrode 231 and the second pixel electrode 232 are separated from each other, and a conductive layer 252 is provided below them via an insulating layer (not shown). It becomes the composition. For this reason, as shown in FIG. 9B, the auxiliary capacitor 250 has the first pixel electrode 231 / insulating layer / conductive layer 2 as viewed from the first pixel electrode 231 side.
In this configuration, a capacitor composed of 52 and a capacitor composed of conductive layer 252 / insulating layer / second pixel electrode 232 are connected in series. The conductive layer 252 can be formed, for example, by patterning the same layer as the scanning line 311 (or the semiconductor layer of the TFT), and therefore FIG. 9A and FIG.
In the configuration shown in b), it is possible to add the auxiliary capacitor 250 without patterning a separate conductive layer.

For the pixel 116, not only the first pixel electrode 231 and the second pixel electrode 232 but also a common electrode may be provided.
For example, as shown in FIG. 10A, the first pixel electrode 231 and the second pixel electrode 23
A common electrode 111 facing each other in a comb shape may be provided so as to be common to each pixel 116. In this configuration, the pixel capacitance is equal to the capacitance of the first pixel electrode 231 / the liquid crystal / common electrode 111 and the common electrode as viewed from the first pixel electrode 231 side, as in the equivalent circuit shown in FIG. Thus, a combined capacitance of 111 / liquid crystal / second pixel electrode 232 is connected in series.
Further, as shown in FIG. 11A, the first pixel electrode 231 and the second pixel electrode 232 are used.
A so-called FFS configuration may be employed in which the common electrode 111 is provided in the lower layer of the region facing each other via an insulating layer (not shown) so as to include the facing region. Note that FIG.
The equivalent circuit of the pixel shown in FIG. 11 is as shown in FIG. 11B and is the same as FIG.

Here, in the pixel configurations of FIGS. 10A and 11A, if the common electrode 111 is maintained at some voltage (for example, voltage Vc), the data signal waveforms shown in FIGS. Since application of a direct current component to the capacity cannot be avoided, the data signal waveform shown in FIG. 7 needs to be obtained.
In addition, the pixel configurations shown in FIGS. 10A and 11A can suppress the occurrence of lateral crosstalk or cancel the influence of noise when viewed from the combined capacitance. Each of them is equivalent to a configuration in which the conventional pixels shown in FIG. 15 are connected in series (and symmetrically), so that it is impossible to prevent application of a direct current component due to pushdown to individual capacitors.
However, if individual intermediate electrodes are provided for each pixel in the figure instead of the common electrode 111, the first pixel electrode 231 and the second electrode are shown in detail in FIG. 12 (a) or FIG. 13 (a).
If the intermediate electrodes 112 are respectively opposed to the pixel electrodes 232, it is possible to prevent application of a DC component by pushdown.
Note that the equivalent circuit of the pixel shown in FIG. 12A or FIG.
As shown in FIG. 12B or FIG. 13B, they are the same as each other. Note that FIG.
The pixel capacitance Cpix shown in FIG. 2 is illusioned to be halved compared to FIG. 2B due to the series connection, but the intermediate electrode 112 and the first pixel electrode 231 (second pixel electrode 232). Since the insulating layer between them is extremely thin, the combined capacitance due to series connection is equal to or greater than that of FIG.

In the embodiments and examples, the first TFT 241 and the second TFT 242 are bottom gates, but may be top gates, and may be polysilicon types instead of amorphous types. Although both transistors are n-channel type, it is of course possible to use p-channel type.
In the above-described embodiment, the change period of the write polarity for the same pixel is set to one vertical scanning period (one frame) because the direct current component is prevented from being applied to the pixel capacitor Cpix. The inversion may be two or more frame periods.
Furthermore, in the embodiment, a normally white mode in which white is displayed in a state in which no voltage is applied is used. However, a normally black mode in which black is displayed in a state in which no voltage is applied may be used. In the normally black mode, the higher the effective voltage value of the pixel capacitance Cpix, the darker the pixel.
The number of gradation display is not particularly limited, and color display may be performed by forming one dot with three pixels of R (red), G (green), and B (blue).
The liquid crystal panel 100 is not limited to the transmissive type, and may be a reflective type or a semi-transmissive / semi-reflective type intermediate between the two.

Next, an electronic apparatus having the electro-optical device 10 according to the above-described embodiment as a display device will be described. FIG. 14 is a perspective view showing a configuration of a mobile phone 1200 using the electro-optical device 10 according to the embodiment.
As shown in this figure, the mobile phone 1200 includes the liquid crystal panel 100 described above together with a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206. In the electro-optical device 10, components other than the liquid crystal panel 100 are built in the telephone, so that they do not appear as appearance.

As an electronic apparatus to which the electro-optical device 10 is applied, in addition to the mobile phone shown in FIG. 14, a digital still camera, a notebook personal computer, a liquid crystal television, a viewfinder type (or monitor direct view type) video recorder, a car Examples include navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, and devices equipped with touch panels. Needless to say, the electro-optical device 10 described above can be applied as a display device of these various electronic devices. In any of the electronic devices, a high-quality display can be realized with a simple configuration while suppressing a reduction in display quality.

1 is a block diagram illustrating a configuration of an electro-optical device according to an embodiment of the invention. FIG. It is a figure which shows the structure of the pixel in the same electro-optical apparatus. It is a figure which shows the scanning signal and data signal in the same electro-optical device. It is a figure which shows the voltage change of the 1st and 2nd pixel electrode in the same electro-optical apparatus. FIG. 10 is a block diagram illustrating a configuration of an electro-optical device according to an application example of the invention. It is a figure which shows the scanning signal and data signal in an application example. It is a figure which shows the scanning signal and data signal in another example. 4 is a diagram illustrating another example of a pixel in the same electro-optical device. FIG. 4 is a diagram illustrating another example of a pixel in the same electro-optical device. FIG. 4 is a diagram illustrating another example of a pixel in the same electro-optical device. FIG. 4 is a diagram illustrating another example of a pixel in the same electro-optical device. FIG. 4 is a diagram illustrating another example of a pixel in the same electro-optical device. FIG. 4 is a diagram illustrating another example of a pixel in the same electro-optical device. FIG. It is a figure which shows the structure of the mobile telephone using the same electro-optical apparatus. It is a figure which shows the structure of the conventional pixel. It is a figure which shows the voltage change of the pixel electrode in the conventional pixel. It is a figure which shows horizontal crosstalk. It is a figure for demonstrating the cause of horizontal crosstalk.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Electro-optical apparatus, 116 ... Pixel, 211 ... 1st data line, 212 ... 2nd data line,
231 ... 1st pixel electrode, 232 ... 2nd pixel electrode, 241 ... 1st TFT, 242 ... 2nd TF
T, 250 ... data line driving circuit, 311 ... scanning line, 350 ... scanning line driving circuit, 400 ... control circuit, 1200 ... mobile phone

Claims (9)

A pixel provided corresponding to the intersection of a plurality of rows of scanning lines and a plurality of columns of first and second data lines;
A pixel capacitor having a separate first and second pixel electrode for each pixel and holding a difference in voltage applied to each of the first and second pixel electrodes;
A first switching element that is conductive between the first data line and the first pixel electrode when a corresponding scan line is selected;
A second switching element that is conductive between the second data line and the second pixel electrode when a corresponding scan line is selected;
A pixel having
A scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order;
A data line driving circuit for supplying a data signal corresponding to a gradation of a pixel to the first data line and supplying a predetermined voltage to the second data line when the corresponding scanning line is selected. An electro-optical device. The second data line is common across the columns,
The data line driving circuit includes:
A state in which the first data line is set to a voltage on one side higher or lower than the predetermined voltage by a voltage corresponding to the gray level of the pixel, and the gray level of the pixel is higher than the predetermined voltage. 2. The electro-optical device according to claim 1, wherein a state in which the voltage on the other side higher or lower by the voltage is alternately repeated at a predetermined cycle. The data line driving circuit includes:
The first data line is set to a predetermined voltage, and the second data line paired with the first data line is set to a voltage on one side higher or lower than the predetermined voltage by a voltage corresponding to the gradation of the pixel. And the state
The first data line is set to a voltage higher or lower than the predetermined voltage by a voltage corresponding to the gray level of the pixel, and the second data line paired with the first data line is set to the first data line. The electro-optical device according to claim 1, wherein a state of a predetermined voltage is alternately repeated at a predetermined cycle. The data line driving circuit includes:
The voltage of the first data line and the voltage of the second data line are made symmetric with respect to the predetermined voltage, and the high or low voltage is inverted at a predetermined cycle. 2. The electro-optical device according to 1. The electro-optical device according to claim 1, further comprising an auxiliary capacitor in parallel with the pixel capacitor. The auxiliary capacity is
The electro-optical device according to claim 5, wherein the electro-optical device has a stacked structure of the first pixel electrode, the insulating layer, and the second pixel electrode. The auxiliary capacity is
A capacitor having a stacked structure of the first pixel electrode, the insulating layer and the conductive layer;
The electro-optical device according to claim 5, wherein the electro-optical device is connected in series with a capacitor having a stacked structure of the conductive layer, the insulating layer, and the second pixel electrode. A pixel provided corresponding to the intersection of a plurality of rows of scanning lines and a plurality of columns of first and second data lines;
A pixel capacitor having a separate first and second pixel electrode for each pixel and holding a difference in voltage applied to each of the first and second pixel electrodes;
A first switching element that is conductive between the first data line and the first pixel electrode when a corresponding scan line is selected;
A driving method of an electro-optical device including a pixel having a second switching element that is conductive between the second data line and the second pixel electrode when a corresponding scanning line is selected,
Selecting the plurality of rows of scanning lines in a predetermined order;
When the corresponding scanning line is selected, a data signal corresponding to a gradation of a pixel is supplied to the first data line and a predetermined voltage is supplied to the second data line. Device driving method. An electronic apparatus comprising the electro-optical device according to claim 1.

Images