JP2006127407A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To deal with various kinds of program ROMs with a single semiconductor integrated circuit. <P>SOLUTION: At reset time, the kind of a program ROM 310 connected to the semiconductor integrated circuit 300 is identified, either a ROM controller A303 or a ROM controller B308 is selected in accordance with the identified kind of the ROM, an access protocol for the ROM is executed, and a memory map is switched between the reset time and a normal time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique for supporting various types of program ROMs in a single semiconductor integrated circuit including a CPU.

  In recent years, the degree of integration of semiconductors has improved, and it has become possible to mount almost all functional modules of a system including a CPU in one semiconductor integrated circuit (for example, Patent Document 1). However, the program ROM for storing the CPU program and the like and the storage device (generally dynamic RAM) constituting the main memory are still often provided outside the semiconductor integrated circuit.

  On the other hand, there are several types of ROM used for the program ROM, such as NOR flash memory, NAND flash memory, mask ROM, serial ROM, etc., but these have different levels of integration, read speed, cost, Whether a program (data rewriting) is possible or not is different.

  For example, among these ROMs, reprogrammable ROMs are NOR flash memory, NAND flash memory, and serial ROM. Among them, mask ROM, NAND flash memory, and serial ROM are generally inexpensive. .

  The NOR flash memory and the mask ROM have substantially the same access protocol for the ROM, but the NAND flash memory and the serial ROM have access protocols that are significantly different from the above two.

  Furthermore, there is a restriction that the NAND flash memory is a ROM based on sequential access (strictly random access is possible, but the ROM device becomes busy on the order of μS each time random access is performed. The serial ROM is not suitable for random access from the viewpoint of reading speed), and the reading speed of the serial ROM is significantly slower than other types of ROM.

  Therefore, conventionally, among these ROMs, an optimal ROM is selected and mounted as a program ROM in accordance with requirements such as system performance and cost.

  FIG. 1 is a schematic block diagram for explaining the prior art. The semiconductor integrated circuit 100 includes at least a CPU bus 101, a CPU 102, a ROM controller 103, a DMA controller 104, and a memory controller 105. Although other modules are also connected to the CPU bus 101, they are omitted to avoid inconvenience.

  A program ROM 110 and a main memory 120 are connected to the outside of the semiconductor integrated circuit 100. Here, it is assumed that the program ROM 110 is configured by a NOR flash memory, and the main memory 120 is configured by SDRAM.

FIG. 2 is a diagram showing a memory map in the prior art. In FIG. 2, the main memory area 202 and the ROM area 201 are shown, but the areas of other modules and devices mapped on the memory map are omitted to avoid inconvenience.
Japanese Patent Laid-Open No. 06-027203

  However, when trying to cover a high-end model of a certain product genre to a low-priced machine with a single semiconductor integrated circuit, the type of program ROM used varies depending on the product. For this reason, it is necessary to support a plurality of access protocols, and the program ROM access protocol must be appropriately selected when the system is booted.

  Further, as described above, since the NAND flash memory is a device based on sequential access, jump instructions (including conditional branch instructions) cannot be executed in a program. Therefore, it is necessary to cope with boot sequence control different from that of the NOR flash memory and the mask ROM.

  Furthermore, even if the hardware can be shared by covering a high-end model from a certain product genre to a low-priced machine with a single semiconductor integrated circuit, if the memory map differs for each system (model), the system Different development tools and development environments had to be prepared for each. In some cases, software development has to be performed again for each system, and there is a problem in terms of software development efficiency.

  The present invention has been made in view of the above problems, and an object of the present invention is to support various types of program ROMs with a single semiconductor integrated circuit.

  According to the present invention, in a semiconductor integrated circuit capable of switching a memory map between a reset time and a normal time, an identification means for identifying a type of ROM connected to the semiconductor integrated circuit at the time of reset is identified by the identification means And control means for controlling to execute an access protocol corresponding to the type of ROM.

  According to the present invention, a single semiconductor integrated circuit can be used for various types of program ROMs.

  The best mode for carrying out the invention will be described below in detail with reference to the drawings.

  FIG. 3 is a schematic block diagram illustrating an example of the configuration of the semiconductor integrated circuit according to the first embodiment. As shown in FIG. 3, the semiconductor integrated circuit 300 includes at least a CPU bus 301, a CPU 302, a ROM controller A303, a DMA controller 304, a memory controller 305, a reset controller 306, a CPU bus multiplexer (MUX) 307, a ROM controller B308, and a ROM. It consists of a bus multiplexer (MUX) 309.

  Although other functional modules are also connected to the CPU bus 301, they are omitted because they are not related to the present invention.

  A program ROM 310 and a main memory 320 are connected to the outside of the semiconductor integrated circuit 300. Further, the reset IC 330 is connected to the system reset terminal reset_L of the semiconductor integrated circuit 300, and the external device 340 is connected to the activation ROM identification terminal gp, and is pulled down on the substrate. The activation ROM identification terminal gp is connected to the reset controller 306 and also to another functional module (not shown) in the semiconductor integrated circuit 300.

  The program ROM 310 is a NOR flash memory, and the main memory 320 is an SDRAM.

  FIG. 4 is a schematic block diagram illustrating an example of a configuration of a semiconductor integrated circuit according to a modification of the first embodiment. The only difference in configuration from FIG. 3 is that the program ROM 310 is replaced with the program ROM 410 and that the activation ROM identification terminal gp is pulled up on the substrate, and the others are the same as FIG. Here, the program ROM 410 is a NAND flash memory.

  FIG. 5 is a diagram illustrating a memory map of the semiconductor integrated circuit according to the first embodiment. In FIG. 5, only the main memory area and the ROM area are shown, but other functional module and device areas mapped on the memory map are omitted for the sake of simplicity.

  In the semiconductor integrated circuit 300 of the first embodiment, when the value of the activation ROM identification terminal gp at the time of releasing the system reset is “0” (in the case of FIG. 3), the NOR type flash memory (first ROM) mode is set. When it is selected and “1” (in the case of FIG. 4), the NAND flash memory (second ROM) mode is selected.

  When the NOR type flash memory mode shown in FIG. 3 is selected, the first memory map 501 shown in FIG. 5 is selected after the system reset is released. This memory map is the same as FIG. 2 described in the prior art.

  On the other hand, when the NAND flash memory mode shown in FIG. 4 is selected, the second memory map 502 shown in FIG. 5 is selected after the system reset is released. As described above, since the NAND flash memory is a memory based on sequential access, jump instructions, conditional branch instructions, and the like cannot be used. Therefore, in this mode, the boot process is performed in two stages.

  First, after canceling the system reset, a program for generating a program code for transferring (copying) the main program from the program ROM 410 to the main memory 320 in the RAM area or the main memory area in the CPU 302 is executed. Thereafter, the generated program code is executed, and a process of transferring (copying) the main program onto the main memory 320 is performed. When the transfer of the main program is completed, the boot process is completed, and thereafter the main program on the main memory 320 is executed.

  Further, when the NAND flash memory mode is selected, when the transfer of the main program onto the main memory 320 is completed, the memory map is switched to the third memory map 503 shown in FIG. This switching process is executed at the end of the boot program.

  In this third memory map, the area corresponding to the first ROM area of the first memory map 501 (that is, the memory map of the system using the NOR type flash memory in FIG. 3) is the main program in the main memory area. Is a shadow of the transferred area. That is, since the main program can be accessed through this shadow area, the memory map is hidden in terms of software whether the program ROM is a NOR flash memory or a NAND flash memory.

  Next, a detailed configuration and operation of the reset controller 306 included in the semiconductor integrated circuit 300 according to the first embodiment will be described.

  FIG. 6 is a block diagram illustrating an example of the configuration of the reset controller 306 according to the first embodiment. FIG. 7 is a diagram showing a truth table inside the reset controller 306.

  In FIG. 6, the rom_sel decoder 601 detects the rising edge of the system reset signal reset_L (that is, cancels the system reset), thereby capturing the value of the activation ROM identification terminal gp and outputting it to the D-type flip-flop 602. The output of the D-type flip-flop 602 is input to each part in the semiconductor integrated circuit 300 as the ROM mode selection signal rom_sel.

  Note that, as in the truth table shown in FIG. 7, the activation ROM identification terminal gp does not affect the operation of the rom_sel decoder 601 after the system reset is released. For this reason, in the first embodiment, the startup ROM identification terminal gp is used as a general-purpose port (that is, a normal signal pin) at the normal time (that is, after the system reset is released), and other function modules (in FIGS. 3 and 4). Used for communication between the external device 340 and the external device 340.

  Thus, by combining the activation ROM identification function and the general-purpose port function, it is possible to provide the activation ROM identification terminal gp without increasing the number of terminals.

  On the other hand, the map_sel decoder 604 outputs “1” to the D-type flip-flop 605 by detecting the rising edge of the system reset signal reset_L. The D-type flip-flop 605 is one of general-purpose registers (map_sel register) for the CPU 302 and can write a value of “0” or “1” via the CPU bus 301 and the CPU bus I / F 603. it can.

  The map_sel decoder 604 also decodes the write control signal from the CPU 302, and when the write enable signal wr_en is asserted from the CPU bus I / F 603, outputs the value of the write data dec2_in to the D-type flip-flop 605 as dec2_out. . The output of the D-type flip-flop 605 is input to the CPU bus multiplexer 307 as the memory map selection signal map_sel.

  That is, the memory map selection signal map_sel becomes active when the system reset is released, and then becomes inactive by writing “0” to the remap register (ie, the D-type flip-flop 605) by the program (ie, the CPU 302). It is configured to be able to.

  Hereinafter, the identification of the boot ROM and the selection of the operation mode, which are the first characteristics in the first embodiment, will be described in detail.

  As described above, the value of the activation ROM identification terminal gp at the time of reset release is captured by the rom_sel decoder 601 and the flip-flop 602 of the reset controller 306. That is, since the activation ROM identification terminal gp is pulled down in the configuration shown in FIG. 3, “0” is taken in, and in the configuration shown in FIG. 4, the activation ROM identification terminal gp is pulled up, so “1”. Is captured.

  In the semiconductor integrated circuit 300 of the first embodiment, when the ROM mode selection signal rom_sel is “0”, the NOR type flash memory mode is selected, and when it is “1”, the NAND type flash memory mode is selected. It is comprised so that.

  That is, only when the ROM mode selection signal rom_sel is “0”, the ROM controller A303 (NOR flash memory controller) becomes active, and only when the ROM mode selection signal rom_sel is “1”, the ROM controller B308 (NAND flash memory). Memory controller) becomes active.

  Further, when the ROM mode selection signal rom_sel is “0”, the ROM bus multiplexer 309 selects the path between the ROM controller A303 and the external program ROM (310 in FIG. 3), and the ROM mode selection signal rom_sel is In the case of “1”, the path between the ROM controller B 308 and the external program ROM (410 in FIG. 4) is selected.

  The memory map selection signal map_sel and the ROM mode selection signal rom_sel are also input to the CPU bus multiplexer 307.

  The CPU bus 301 is composed of, for example, AMBA (Advanced Microcontroller Bus Architecture) and AHB (Advanced High-Performance Bus) specified by ARM, and the CPU bus multiplexer 307 also adopts the AMBA recommended method and configuration. Yes.

  However, when the memory map selection signal map_sel and the ROM mode selection signal rom_sel are both “1” for shadow control of the third memory map, which is the second feature in the first embodiment, the upper bits of the address are changed. Mask and output [0x0000_0000] to [0x07FF_FFFF] in response to address inputs [0xF800_0000] to [0xFFFF_FFFF].

  By adopting the configuration and method as described above, in a system in which either a NOR flash memory or a NAND flash memory is used as a program ROM, processing at the time of booting the system is properly performed, and Even when the main program is executed after booting, both have the same software view.

  This makes it possible to share software development tools. In some cases (depending on the product specifications), the exact same main program can be used. Furthermore, the activation ROM identification terminal gp for performing these processes is also used as a normal signal pin, so that it can be provided without increasing the number of terminals.

  Next, Embodiment 2 according to the present invention will be described in detail with reference to the drawings.

  FIG. 8 is a schematic block diagram illustrating an example of the configuration of the semiconductor integrated circuit according to the second embodiment. As shown in FIG. 8, the semiconductor integrated circuit 800 includes at least a CPU bus 801, a CPU 802, a ROM controller 803, a DMA controller 804, a memory controller 805, a reset controller 806, and a CPU bus multiplexer (MUX) 807.

  Although other functional modules are also connected to the CPU bus 801, they are omitted because they are not related to the present invention.

  A program ROM 810 and a main memory 820 are connected to the outside of the semiconductor integrated circuit 800. Further, a reset IC 830 is connected to the system reset terminal reset_L of the semiconductor integrated circuit 800, an external device 840 is connected to the activation ROM identification terminal gp [1: 0], and the two are pulled down on the substrate. . The activation ROM identification terminal gp [1: 0] is connected to the reset controller 806 and also to other function modules (not shown) in the semiconductor integrated circuit 800.

  The program ROM 810 is a NOR flash memory, and the main memory 820 is an SDRAM.

  The difference from FIG. 3 described in the first embodiment is that the bit width of the activation ROM identification terminal is increased so that four types of ROM modes can be selected, and all ROMs are controlled by one ROM controller 803. This is what I did.

  That is, in the second embodiment, when the two bits of the activation ROM identification terminal gp [1: 0] are [00], the NOR type flash memory mode is selected. In the case of [10], the serial ROM mode is selected, and in the case of [11], the mask ROM mode is selected.

  The memory map of the semiconductor integrated circuit in the second embodiment is the same as that in the first embodiment. That is, as shown in FIG. 5, only the main memory area and the ROM area are shown in FIG. 5, but the areas of other functional modules and devices mapped on the memory map are omitted in order to avoid inconvenience. is doing.

  In the semiconductor integrated circuit 800 according to the second embodiment, the case where a NOR flash memory is used as the program ROM and the case where a NAND flash memory is used are the same as those in the first embodiment. .

  That is, when the value of the activation ROM identification terminal gp [1: 0] at the time of system reset release is [00], the NOR type flash memory (first ROM) mode is selected, and in the case of [01] Is configured so that the NAND flash memory (second ROM) mode is selected. When the NOR type flash memory mode is selected, the first memory map 501 shown in FIG. 5 is selected after the system reset is released. This memory map is the same as in the prior art, Example 1.

  On the other hand, when the NAND flash memory mode is selected, the second memory map 502 shown in FIG. 5 is selected after the system reset is released. As described above, since the NAND flash memory is a memory based on sequential access, jump instructions and conditional branch instructions cannot be used. Therefore, in this mode, the boot process is performed in two stages.

  First, after canceling the system reset, a program for generating a program code for transferring (copying) the main program from the program ROM 810 to the main memory 820 in the RAM area or the main memory area in the CPU 802 is executed. Thereafter, the generated program code is executed, and a process of transferring (copying) the main program onto the main memory 820 is performed. When the transfer of the main program is completed, the boot process is completed, and thereafter the main program on the main memory 820 is executed.

  Further, when the NAND flash memory mode is selected, when the transfer of the main program onto the main memory 820 is completed, the memory map is switched to the third memory map 503 shown in FIG. This switching process is executed at the end of the boot program.

  In the third memory map, the area corresponding to the first ROM area of the first memory map 501 (that is, the memory map of the system using the NOR flash memory) is an area where the main program on the main memory is transferred. It has become a shadow. That is, since the main program can be accessed through this shadow area, the memory map is hidden in terms of software whether the program ROM is a NOR flash memory or a NAND flash memory.

  In the semiconductor integrated circuit 800 according to the second embodiment, the serial ROM mode is set when the value of the activation ROM identification terminal gp [1: 0] is [10], and the mask ROM mode is set when [11]. The first memory map is selected as in the case of the NOR flash memory.

  Next, a detailed configuration and operation of the reset controller 806 included in the semiconductor integrated circuit 800 according to the second embodiment will be described.

  FIG. 9 is a block diagram illustrating an example of the configuration of the reset controller 806 according to the second embodiment. FIG. 10 is a diagram showing a truth table inside the reset controller 806.

  In FIG. 9, the rom_sel decoder 901 captures the value of the activation ROM identification terminal gp [1: 0] by detecting the rising edge of the system reset signal reset_L (that is, canceling the system reset), and the D-type flip-flop 902 Output to. The output of the D type flip-flop 902 is input to each part in the semiconductor integrated circuit 800 as a ROM mode selection signal rom_sel [1: 0].

  As shown in the truth table of FIG. 10, the activation ROM identification terminal gp [1: 0] does not affect the operation of the rom_sel decoder 901 after the system reset is canceled. For this reason, in the second embodiment, the startup ROM identification terminal gp [1: 0] is used as a general-purpose port (that is, a normal signal pin) at the normal time (that is, after the system reset is released), and other function modules (FIG. 8) (not shown in FIG. 8) and an external device 840.

  Thus, by combining the activation ROM identification function and the general-purpose port function, it is possible to provide the activation ROM identification terminal gp [1: 0] without increasing the number of terminals.

  The operations of the map_sel decoder 904 and the D-type flip-flop 905 are the same as those in the first embodiment. That is, the map_sel decoder 904 outputs “1” to the D-type flip-flop 905 by detecting the rising edge of the system reset signal reset_L. The D-type flip-flop 905 is one of general-purpose registers (map_sel register) for the CPU 802 and writes a value of “0” or “1” via the CPU bus 801 and the CPU bus I / F 903. it can.

  The map_sel decoder 904 also decodes the write control signal from the CPU 802, and when the write enable signal wr_en is asserted from the CPU bus I / F 903, the value of the write data dec2_in is output to the D-type flip-flop 905 as dec2_out. . The output of the D-type flip-flop 905 is input to the CPU bus multiplexer 807 as the memory map selection signal map_sel.

  That is, the memory map selection signal map_sel becomes active when the system reset is released, and then becomes inactive by writing “0” to the remap register (ie, the D-type flip-flop 905) by the program (ie, the CPU 802). It is configured to be able to.

  Hereinafter, identification of the boot ROM and selection of the operation mode, which are the first characteristics in the second embodiment, will be described.

  As described above, the value of the activation ROM identification terminal gp [1: 0] at the time of reset release is captured by the rom_sel decoder 901 and the flip-flop 902 of the reset controller 806. That is, in the configuration of the second embodiment, when the ROM mode selection signal rom_sel [1: 0] is [00], the NOR flash memory mode is selected, and when the ROM mode selection signal rom_sel [1: 0] is [01], the NAND flash memory mode is [10]. ], The serial ROM mode is selected, and in the case of [11], the mask ROM mode is selected. Then, the ROM controller 803 accesses the program ROM 810 with an access protocol corresponding to the selected ROM mode. In the example shown in FIG. 8, since both of the activation ROM identification terminals gp [1: 0] are pulled down, [00] is fetched when the system reset is canceled, and the ROM mode selection signal rom_sel [1: 0] Therefore, the NOR type flash memory mode is selected.

  The memory map selection signal map_sel and the ROM mode selection signal rom_sel [1: 0] are also input to the CPU bus multiplexer 807.

  Similarly to the first embodiment, the CPU bus 801 is composed of AMBA and AHB, and the CPU bus multiplexer 807 also adopts the AMBA recommended system and configuration.

  However, for shadow control of the third memory map, which is the second feature in the second embodiment, the memory map selection signal map_sel is “1” and the ROM mode selection signal rom_sel [1: 0] is [01]. If it is, the upper bits of the address are masked, and [0x0000_0000] to [0x07FF_FFFF] are output in response to the address input of [0xF800_0000] to [0xFFFF_FFFF].

  By adopting the configuration and method as described above, even in a system in which various types of ROM are used as the program ROM, processing at the time of booting the system is properly performed and the main program is executed after booting. Even in time, each has the same software view.

  This makes it possible to share software development tools. In some cases (depending on the product specifications), the exact same main program can be used. Furthermore, the activation ROM identification terminal gp [1: 0] for performing these processes is also used as a normal signal pin, so that the number of terminals can be increased.

  Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), it is applied to an apparatus (for example, a copier, a facsimile machine, etc.) composed of a single device. It may be applied.

  Another object of the present invention is to supply a recording medium in which a program code of software realizing the functions of the above-described embodiments is recorded to a system or apparatus, and the computer (CPU or MPU) of the system or apparatus stores it in the recording medium. Needless to say, this can also be achieved by reading and executing the programmed program code.

  In this case, the program code itself read from the recording medium realizes the functions of the above-described embodiment, and the recording medium storing the program code constitutes the present invention.

  As a recording medium for supplying the program code, for example, a floppy (registered trademark) disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like is used. be able to.

  Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an OS (operating system) operating on the computer based on the instruction of the program code. It goes without saying that a case where the function of the above-described embodiment is realized by performing part or all of the actual processing and the processing is included.

  Further, after the program code read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, the function expansion is performed based on the instruction of the program code. It goes without saying that the CPU or the like provided in the board or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.

It is a schematic block diagram for demonstrating a prior art. It is a figure which shows the memory map in a prior art. 1 is a schematic block diagram illustrating an example of a configuration of a semiconductor integrated circuit in Embodiment 1. FIG. FIG. 6 is a schematic block diagram illustrating an example of a configuration of a semiconductor integrated circuit according to a modification example of Example 1. 3 is a diagram illustrating a memory map of a semiconductor integrated circuit in Example 1. FIG. 3 is a block diagram illustrating an example of a configuration of a reset controller 306 according to the first embodiment. FIG. It is a figure which shows the truth table inside a reset controller. FIG. 6 is a schematic block diagram illustrating an example of a configuration of a semiconductor integrated circuit according to a second embodiment. 6 is a block diagram illustrating an example of a configuration of a reset controller 806 in Embodiment 2. FIG. It is a figure which shows the truth table inside a reset controller 806.

Explanation of symbols

100 Semiconductor Integrated Circuit 101 CPU Bus 102 CPU
103 ROM controller 104 DMA controller 105 Memory controller 110 Program ROM
120 Main memory 201 ROM area 202 Main memory area 300 Semiconductor integrated circuit 301 CPU bus 302 CPU
303 ROM controller A
304 DMA controller 305 Memory controller 306 Reset controller 307 CPU bus multiplexer (MUX)
308 ROM controller B
309 ROM bus multiplexer (MUX)
310 Program ROM (NOR flash memory)
320 Main memory 330 Reset IC
340 External device 410 Program ROM (NAND flash memory)
501 First memory map 502 Second memory map 503 Third memory map 601 rom_sel decoder 602 D-type flip-flop 603 CPU bus I / F
604 map_sel decoder 605 D-type flip-flop (map_sel register)
800 Semiconductor integrated circuit 801 CPU bus 802 CPU
803 ROM controller C
804 DMA controller 805 Memory controller 806 Reset controller 807 CPU bus multiplexer (MUX)
810 Program ROM
820 Main memory 830 Reset IC
840 External device 901 rom_sel decoder 902 D-type flip-flop 903 CPU bus I / F
904 map_sel decoder 905 D-type flip-flop (map_sel register)

Claims (6)

In a semiconductor integrated circuit that can switch the memory map between reset and normal,
Identification means for identifying the type of ROM connected to the semiconductor integrated circuit at the time of resetting;
And a control means for controlling to execute an access protocol corresponding to the type of ROM identified by the identification means.   The semiconductor integrated circuit according to claim 1, wherein the identifying unit identifies a value of an external terminal of the semiconductor integrated circuit as a type of the ROM at the time of reset.   3. The semiconductor integrated circuit according to claim 2, wherein the external terminal can be used as a normal signal pin after reset is released. A selection means for selecting the memory map based on a signal that becomes a first level by the reset release and becomes a second level by writing a predetermined value in a predetermined register;
The selection unit selects a memory map at the time of reset for the ROM type during the first level according to the ROM type identified by the identification unit, and the ROM during the second level period. 2. The semiconductor integrated circuit according to claim 1, wherein a normal memory map is selected for each type.   In the normal memory map, the area corresponding to the ROM area in the normal memory map for an arbitrary ROM type is the program storage area on the main memory in the normal memory map for another ROM type. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is configured as a shadow of A ROM controller that executes an access protocol to the ROM;
2. The semiconductor integrated circuit according to claim 1, wherein the control unit controls the ROM controller to execute an access protocol corresponding to a type of ROM identified by the identification unit.

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