JP2006191188A - Image transfer apparatus and image display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a transfer error of pixel data from being displayed on an image display unit with fewer error detection data and a simple circuit configuration, even if the transfer error occurs. <P>SOLUTION: An image display apparatus 110 has: an image receiving unit 101 for receiving the image data and the error detection data from an image transmitting unit 100; an error detecting unit 102 for using the error detection data to detect a transfer error of the image data; an address generating unit 103 for generating the address of a frame memory 107 and storing the address of a transfer error, if the transfer error is detected; an error transfer unit 104 for transferring the stored address of the unit 103 as error information to the unit 100; and a memory control unit 106 for preventing writing of the data from a line memory 105 to the frame memory 107, only when the transfer error is detected. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image transfer device that transfers serial image data from an image transmission unit to an image reception unit at high speed, and an image display device that uses this to display an image on an image display unit.

  Conventionally, when an image is written from the image transmission unit to the frame memory, as shown in FIG. 11A, using a parallel bus access method, the address of the frame memory and the pixel to be written to the address are written. A method of transmitting data simultaneously has been used.

  However, this method has a problem that a wiring area is increased because a wiring for transmitting an address and a wiring for transmitting pixel data are required as wirings connecting the image transmission unit and the image reception unit.

  Therefore, recently, as shown in FIG. 11B, a serial bus access method in which addresses and pixel data are time-divisionally transferred via the same wiring has begun to be used. During this serial transfer, the transfer frequency is increased in order to obtain an image transfer rate equal to or higher than that when parallel transfer is performed. In order to further shorten the transfer time, an area where pixel data is written (for example, a start position and an end position in the frame memory) is set in the address generation unit in advance, as shown in FIG. Systems that do not require address transfer have also been used.

  On the other hand, when data transfer between the image transmission unit and the image reception unit is performed at high speed, a pixel transfer error occurs, and the possibility of affecting display is increasing.

  As a method for avoiding this problem, for example, as shown in FIG. 11D, error detection data represented by a parity code is added for each pixel, and error detection is performed on the receiving side using this error detection data. Possible ways to do this. In this method, when an error is detected on the receiving side, the image transmission unit is notified that a transfer error has occurred as a re-transfer request, and the pixel data is transferred again from the received image transmission unit. it can.

  However, this method requires a time for detecting the presence or absence of a transfer error on the receiving side regardless of whether or not a transfer error has occurred, resulting in a problem that the image transfer rate is lowered.

  Further, as shown in FIG. 11 (e), a method of adding error correction data represented by a Hamming code for each pixel and performing error detection and error correction on the receiving side using this error correction data is also conceivable. . This method does not require time for detecting the presence or absence of a transfer error on the receiving side as shown in FIG.

  However, this method requires a means for generating a Hamming code in the image transmission unit, and it is necessary to provide an error detection unit and an error correction unit on the reception side, resulting in a problem that the circuit becomes complicated. Further, the time required for transferring the Hamming code is also a factor for lowering the image transfer rate.

  Hereinafter, with reference to FIG. 12, consider a case where the image receiving unit receives data with error correction data added for each pixel as shown in FIG.

  FIG. 12 is a block diagram illustrating a configuration example of a main part of a conventional image display device.

  In FIG. 12, a conventional image display apparatus 220 includes an image transmission unit 200 that transmits image data and error correction data, an image reception unit 201 that receives data from the image transmission unit 200, and an error in the received image data. An error detection unit 202 that detects occurrence, an address generation unit 203 that generates an address for the frame memory 207, an error correction unit 204 that corrects pixel data when an error is detected in received image data, and a frame memory A frame memory control unit 206 that controls 207; a frame memory 207; an image output unit 208 that outputs pixel data stored in the frame memory 207; and an image display unit 209 that displays the output image data. have.

  The operation of this conventional image display device 220 will be described below. Here, it is assumed that information on which area of the frame memory 207 is written with the transferred pixel data is already set in the address generation unit 203.

  As shown in FIG. 12, in the image display device 220, first, the image receiving unit 201 receives pixel data bit by bit as image transmission serial image data, and then receives error correction data such as a Hamming code. The image receiving unit 201 collects these as one data and sends it to the error detecting unit 202.

  Next, the error detection unit 202 checks whether or not there is a transfer error from the transmitted data, and sends the result together with the data to the error correction unit 204.

  Further, if there is no transfer error, the error correction unit 204 sends the pixel data to the frame memory control unit 206 as it is. If there is a transfer error, the error correction unit 204 corrects the error and controls only the corrected pixel data by the frame memory control. Send to part 206.

  The frame memory control unit 206 writes the transmitted pixel data in the area of the frame memory 207 corresponding to the address generated by the address generation unit 203. The frame memory control unit 206 also controls reading of pixel data to be sent to the image output unit 208 from the frame memory 207. In addition, the frame memory control unit 206 also arbitrates writing and reading of pixel data to and from the frame memory 207 as necessary.

  The image output unit 208 sends the pixel data sent from the frame memory control unit 206 to the image display unit 209, and the image display unit 209 displays it on the display screen based on the pixel data.

  In the image display device 220, as shown in FIG. 11 (d), when data with error detection data added for each pixel is transferred, the error correction unit 204 is unnecessary and is transferred most recently. Information on whether or not there is an error in the pixel is sent to the image transmission unit 200.

  As one of such conventional techniques, for example, Patent Document 1 discloses a method of transferring image data by adding error detection data for each pixel. In this method, parallel transfer is performed. However, if the same is performed for serial transfer, transfer efficiency is lowered. Further, although Patent Document 1 proposes to add error correction data, it is needless to say that this method further reduces the transfer efficiency.

  Furthermore, when a transfer error occurs in an image display apparatus that does not include the error detection unit 202 and the error correction unit 204 as shown in FIG. 12, incorrect information is displayed on the image display unit 209. Needless to say.

  Furthermore, by completely different means, for example, by taking perfect matching of impedance between the image transmitting unit 200 and the image receiving unit 201, or by shielding the entire device and completely preventing the introduction of external noise, A method that does not cause a transfer error itself is also conceivable.

However, taking perfect matching of impedance is not suitable for mass production, and performing shielding has a problem of directly increasing the cost.
Japanese Patent Laid-Open No. 9-220806

  As in the image display device using the image transfer device described above, there is a problem that when the image transfer is performed between the image transmission unit and the image reception unit by the parallel bus access method, the wiring area becomes large.

  When image transfer is performed by the serial bus access method, it is necessary to increase the transfer frequency in order to obtain an image transfer rate equal to or higher than that of parallel transfer. Here, if data transfer is performed at high speed, a transfer error occurs, and there is a greater risk of adversely affecting the display.

  In order to avoid this problem, as shown in FIG. 11D, in the conventional method of adding error detection data for each pixel, whether or not there is a transfer error on the receiving side regardless of whether or not a transfer error has occurred. Since detection time is required, there is a problem that the image transfer rate is lowered.

  Also, as shown in FIG. 11 (e), the method of adding error correction data for each pixel requires a means for generating a Hamming code in the image transmission unit, and an error detection unit and an error on the reception side. Since it is necessary to provide a correction unit, there is a problem that the circuit becomes complicated. Further, since it takes time to transfer the Hamming code, there is a problem that the image transfer rate is lowered.

  Furthermore, in an image display device that is not provided with the error detection unit 202 and the error correction unit 204 as shown in FIG. 12, erroneous information is displayed on the image display unit 209 when a transfer error occurs. There's a problem.

  Further, the method of perfectly matching impedance between the image transmission unit 200 and the image reception unit 201 is not suitable for mass production, and the method of shielding the entire apparatus has a problem that the cost increases.

  The present invention solves the above-mentioned conventional problems, and is less when image data is transferred at a high transfer rate by serial transfer so that the wiring area connecting the image transmitting unit and the image receiving unit does not become large. Provided is an image transfer device capable of preventing a pixel data transfer error from being displayed on an image display unit by an error detection data and a simple circuit configuration, and an image display device using the image transfer device. For the purpose.

  An image transfer apparatus according to the present invention includes a data receiving unit that receives serial pixel data transmitted from a data transmitting unit and error detection data added for each line, and an error occurs in pixel data received by the data receiving unit. An error detection unit that detects whether or not the data is detected using the error detection data; a line memory that stores pixel data received by the data reception unit in units of lines regardless of the presence or absence of the error; A frame memory for storing the pixel data of each frame and an address for the frame memory, and when the error is detected in the pixel data in the line by the error detection unit, the address of the line is detected as an error An address generation unit for storing information, and the error detection information in the address generation unit after the pixel data of all lines are received as error information. Then, the error transfer unit that transfers to the data transmission unit side, and the line memory and the frame memory are controlled based on the address from the address generation unit, and consists of pixel data for one line in the line memory. A memory control unit that does not write the line data to the frame memory when the line data includes the error and does not write the line data to the frame memory when the error is not included; So that the above object is achieved.

  An image transfer apparatus according to the present invention includes a data receiving unit that receives serial pixel data transmitted from a data transmitting unit and error detection data added for each line, and an error occurs in pixel data received by the data receiving unit. An error detection unit that detects whether or not the data is detected using the error detection data; a line memory that stores pixel data received by the data reception unit in units of lines regardless of the presence or absence of the error; A frame memory for storing the pixel data of each frame and an address for the frame memory, and when the error is detected in the pixel data in the line by the error detection unit, the address of the line is detected as an error An address generator for storing information, and the error detection information in the address generator after the pixel data of all lines are received as error information. Then, the error transfer unit that transfers to the data transmission unit side, and the line memory and the frame memory are controlled based on the address from the address generation unit, and consists of pixel data for one line in the line memory. When the error is included in the line data, the line data is not read from the line memory, and when the error is not included, the line data is read from the line memory and written to the frame memory. And the memory control unit, thereby achieving the above object.

  Further preferably, the error detection unit in the image transfer apparatus of the present invention outputs the error detection information to the memory control unit when an error is detected in the line data for one line.

  Further preferably, the memory control unit in the image transfer apparatus of the present invention generates a read request generation unit that generates a read request for the line data regardless of whether or not the line data includes an error. And a read request masking unit that masks the read request with the error detection information and controls not to read the line data including the error.

  Still preferably, in a case where the line data is not read from the line memory, the memory control unit in the image transfer apparatus according to the present invention performs memory control so that the line memory is overwritten with data. .

  Still preferably, in an image transfer apparatus according to the present invention, the error detection unit includes an addition unit that adds pixel data values for one line, and a comparison unit that compares the addition result obtained by the addition unit with the error detection data. The error is detected only when the addition result does not match the error detection data.

  Further preferably, the line memory in the image transfer apparatus of the present invention is a memory having a first-in first-out configuration.

  Further preferably, the address generation unit in the image transfer apparatus of the present invention uses the address information transmitted from the data transmission unit side when an error is detected in the received pixel data, and the frame memory or An address that does not perform memory control is generated for the line memory.

  Still preferably, in a case where an error is detected in the received pixel data, the address generation unit in the image transfer apparatus of the present invention uses the error detection information stored in the address memory to store the frame memory or the line. An address that does not perform memory control is generated for the memory.

  Further preferably, the address generation unit in the image transfer apparatus of the present invention sets a vertical coordinate and a horizontal coordinate as a start position and an end position in the address on the frame memory, respectively.

  Still preferably, in an image transfer apparatus according to the present invention, the address generation unit counts the number of pixel data in the line direction as an X coordinate, and counts the Y coordinate for each pixel data of one line. A Y-coordinate counter unit, a coordinate conversion unit that converts the counted two-dimensional coordinates composed of the X-coordinates and the Y-coordinates into a one-dimensional address, and stores the Y-coordinate in which a transfer error has occurred as the error detection information. And an error coordinate storage unit.

  Further preferably, the image transfer apparatus according to the present invention further includes a moving image / still image setting unit, and the error transfer unit transfers error information only when the moving image / still image setting unit sets a moving image. Control to not.

  Further, preferably, the error detection unit is controlled not to perform error detection processing only when the moving image / still image setting unit in the image transfer apparatus of the present invention is set as a moving image, or the address generation unit Control is performed so as not to store the error detection information.

  Further preferably, the data transmission unit in the image transfer apparatus of the present invention transmits serial pixel data and error detection data added for each line to the data reception unit, and receives error information from the error transfer unit. In this case, the line data in which an error has occurred is transmitted again.

  An image display device according to the present invention includes an image transfer device according to any one of claims 1 to 14, an image output unit that outputs pixel data stored in a frame memory of the image transfer device, and an output from the image output unit. And an image display unit for displaying an image on the display screen based on the pixel data, thereby achieving the above object.

  The operation of the present invention will be described below with the above configuration.

  In the image transfer apparatus of the present invention, the data reception unit receives the serial pixel data and the error detection data added for each line, and the error detection unit determines whether an error has occurred in the received pixel data. Detected. Before the pixel data is stored in the frame memory, it is temporarily stored in the line memory regardless of whether there is an error.

  The address generation unit generates an address for the frame memory, and stores an address of the line as error detection information when an error is detected.

  The memory control unit does not perform writing to the frame memory when the pixel data stored in the line memory includes an error, and performs writing to the frame memory when the error is not included. Memory and frame memory are memory controlled.

  In the error transfer unit, after all lines of data have been received, the address stored in the address generation unit is transferred as error information to the data transmission unit side, and retransfer processing is performed from the data transmission unit.

  As a result, an error correction code such as a Hamming code is not added to each pixel as in the prior art, and the image transfer rate is not greatly reduced, and a complicated circuit such as an error correction unit is required as in the prior art. In addition, only pixel data for which no transfer error has occurred can be stored in the frame memory. As a result, when serial pixel data is transferred at high speed, even if a transfer error occurs in the pixel data, it is possible to prevent the erroneous image data from being displayed on the display screen of the image display unit. . Furthermore, since error detection data is added for each line, there is no need to detect an error every time data of one pixel is transferred, unlike the prior art in which error detection data is added for each pixel. It is possible to prevent a decrease in transfer rate compared to such a conventional technique.

  In the image transfer apparatus according to the present invention, the memory control unit masks the read request to the line memory using the error detection information notified from the error detection unit, so that the line data including the error is lined. It is possible to control not to read from the memory. As a result, pixel data that should not be written to the frame memory is not read from the line memory, so that it is possible to reduce power consumption by that amount.

  Furthermore, in the image display device of the present invention, when an error is detected in the pixel data, the address generation unit can also generate an address for the frame memory using the error detection information stored by itself. There is no need to set the Y coordinate (line number) from the transmission unit to the address generation unit, and the load on the data transmission unit and the amount of transfer data can be suppressed.

  Furthermore, in the image transfer apparatus of the present invention, a moving image / still image setting unit is provided so that error information is not transferred from the error transfer unit when it is set as a moving image, thereby requiring real-time performance. When displaying a moving image, it is possible to prevent the real-time property of image transfer from being impaired.

  As described above, according to the present invention, an error correction code such as a Hamming code is added to each pixel as in the prior art, and the image transfer rate is not greatly reduced. Only pixel data for which no transfer error has occurred can be stored in the frame memory without requiring a complicated circuit, and this can be read out for good display. In addition, since the transfer rate does not decrease, the power consumption during image transfer can be reduced when transferring the same image as compared with the prior art.

  Further, by controlling the pixel data that should not be written to the frame memory by the memory control unit so as not to be read from the line memory, it is possible to further reduce power consumption.

  Furthermore, when a transfer error occurs, the address generation unit needs to set the Y coordinate from the data transmission unit to the address generation unit by generating an address for the frame memory using the error detection information stored by itself. The load on the data transmission unit and the amount of transfer data can be suppressed.

  Furthermore, when displaying a moving image that requires real-time performance, even if an image transfer error occurs, the real-time performance of image transfer can be prevented from being impaired by not notifying the data transmission section of the transfer error. it can.

The case where the image transfer device according to the first to fourth embodiments of the present invention is applied to an image display device such as a liquid crystal display device will be described in detail below with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram illustrating a configuration example of a main part of an image display apparatus according to Embodiment 1 of the present invention.

  In FIG. 1, an image display device 110 according to the first embodiment includes an image transmission unit 100 as a data transfer unit that transmits pixel data and error detection data for each line, and the transmitted pixel data and error detection data for each line. An image receiving unit 101 as a data receiving unit to receive, an error detecting unit 102 for detecting the presence / absence of an error in received pixel data for each line using error detection data, and generating an address of the frame memory 107 and detecting an error An address generation unit 103 that stores information as an address of the line, an error transfer unit 104 that transfers information to the image transmission unit 100 as error information, a line memory 105 that stores received pixel data in units of lines, a line memory 105, A memory control unit 106 that controls the frame memory 107 and one line When there is no error in the pixel data (line data), the frame memory 107 that stores the pixel data (line data), the image output unit 108 that outputs the pixel data in the frame memory 107, and the output pixel data And an image display unit 109 for displaying an image. The image transmission unit 100, the image reception unit 101, the error detection unit 102, the address generation unit 103, the error transfer unit 104, the line memory 105, the memory control unit 106, and the frame memory 107 constitute an image transfer apparatus.

  With this configuration, in this image display device 110, transfer data including serial image data and error detection data added for each line is transmitted from the image transmission unit 100, and this is received by the image reception unit 101.

  Using this error detection data, the error detection unit 102 detects whether or not an error has occurred in the pixel data received by the image reception unit 101. Further, the image data received by the image receiving unit 101 is stored in the line memory 105 in units of lines regardless of whether there is an error.

  On the other hand, the frame memory 107 stores pixel data stored in the line memory 105 in units of frames. The line memory 105 and the frame memory 107 are subjected to memory control (read / write control) by the memory control unit 106, and when one line of pixel data stored in the line memory 105 includes an error, the line memory 105 and the frame memory 107 When the data is not written to the frame memory 107 and no error is included, the line data is controlled to be written to the frame memory 107.

  The address generation unit 103 generates an address for the frame memory 107, and when an error is detected by the error detection unit 102, the address of the line where the error is detected is stored as error detection information.

  The address stored in the address generation unit 103 is transferred from the error transfer unit 104 to the image transmission unit 100 as error information after all lines of data have been received. When the error information is received, the pixel data of the line where the error has occurred is transmitted again from the image transmission unit 100.

  The pixel data stored in the frame memory 107 is output from the image output unit 108, and the image display unit 109 displays an image on the display screen based on the output pixel data.

  Hereinafter, the image display apparatus 110 according to the present embodiment will be described in detail with more specific examples.

  Here, it is assumed that the address generation unit 103 is given address information necessary to know in which area of the frame memory 107 the pixel data transmitted from the image transmission unit 100 should be written. As this address information, for example, as a start position and an end position at an address on the frame memory 107, there are vertical coordinates and horizontal coordinates, respectively.

  In the following, as an example, the display area of the image display unit 109 and the storage area of the frame memory 107 will be described as VGA (640 × 480 dots), and the display data will be 256 gray scales (8-bit data).

  The image receiving unit 101 receives pixel data and checksum data as error detection data as data from the image transmitting unit 100 in the format shown in FIG. FIG. 2 shows data sent from the image transmission unit 100 to the image reception unit 101 along the time axis, and each pixel data is transferred in a time division manner as 8-bit data as serial data. Further, CheckSum data is added for each line, and is a value obtained by adding pixel data for one line as an 8-bit numerical value.

  The serial data received by the image receiving unit 101 is sent to the error detecting unit 102 as 8-bit data.

  For example, as shown in FIG. 3, the error detection unit 102 adds an adder 21 as an adding means for adding pixel data values (line data) for one line, and compares the addition result with error detection data. And a comparator 22 as means. The adder 21 treats 8 bits of pixel data as a numerical value (gradation value) of 0 to 255, and sequentially adds values for each pixel.

  For example, as illustrated in FIG. 4, the address generation unit 103 counts for each pixel data of one line (640 pixels) and an X coordinate counter unit 31 that counts pixel data of one line (640 pixels). Y-coordinate counter unit 32, coordinate conversion unit 33 that converts two-dimensional coordinates composed of counted X and Y coordinates into one-dimensional addresses, and error coordinate storage unit that stores Y-direction coordinates in which a transfer error has occurred 34.

  In this address generation unit 103, every time the adder 21 sequentially adds values for each pixel, the X coordinate counter 31 in the address generation unit 103 is also incremented. When pixel data for one line (640 pixels) is received by the X coordinate counter 31, the information is sent to the Y coordinate counter unit 32 to prompt the Y coordinate to be incremented, and the information is received by the image receiving unit 101. Sent to. Based on this information, the image receiving unit 101 determines that the next data to be sent is CheckSum data, and the next 18-bit data to be sent is sent to the error detection unit 102 as CheckSum data.

  Here, the natural number that can be represented by the 18-bit CheckSum data is 0 to 262143, and the maximum value 255 when the pixel data is handled as a natural number is multiplied by the horizontal number 640 of the image display unit 109 or the frame memory 107. The value is set to a value larger than the value 163200.

  In the error detection unit 102, the addition result by the adder 21 and the CheckSum data are compared by the comparator 22, and if they do not match, it is assumed that a transfer error has occurred in any of the received pixel data, and the result Is notified to the address generation unit 103.

  During this time, the pixel data is stored in the line memory 106 regardless of whether or not a transfer error has occurred.

  In the address generation unit 103, based on the error information from the error detection unit 102 and the counter value of the Y coordinate counter unit 32, the Y direction coordinate where the transfer error has occurred is stored in the error coordinate storage unit 34.

  The Y-direction coordinates are sent to the image transmission unit 100 by the error transfer unit 104 after all the images for 480 lines have been transferred, and the image transmission unit 100 again transmits pixel data only for the line where the transfer error has occurred. Transfer is performed. Thereafter, the transfer of pixel data is repeated until there is no transfer error in all lines.

  Further, in the address generation unit 103, the coordinate conversion unit 33 converts a two-dimensional coordinate formed by the X coordinate generated by the X coordinate counter unit 31 and the Y coordinate generated by the Y coordinate counter unit 32 into a one-dimensional address. And is supplied to the memory control unit 106. This is because many memories are configured with one-dimensional addresses.

  The line memory 105 is a first-in first-out (FIFO) memory, and pixel data received from the error detection unit 102 is sequentially sent to the frame memory control unit 106.

  Here, when a transfer error has occurred in any of the pixel data for one line sent from the line memory 105 to the memory control unit 106 and the error detection unit 102 determines that there is a transfer error, the memory The control unit 106 performs control so that the pixel data of the line is not written to the frame memory 107. Further, the memory control unit 106 performs control so that the pixel data of the line is written to the frame memory 107 in the case of a line in which no transfer error has occurred.

  Obviously, according to the above processing, the image data stored in the frame memory 107 is all pixel data in which no transfer error has occurred. As a result, the image is read from the frame memory 107, passes through the memory control unit 106 and the image output unit 108, and only the correct image is displayed on the display screen of the image display unit 109.

  An example of the order of lines (0 to 479) transferred from the image transmission unit 100 when a transfer error occurs is shown below. A line to which “*” is added is a line in which a transfer error has occurred.

“0” → “1” → “2 *” → “3” → “4” → “5 *” → “6” → ... → “478” → “479” → “2 *” → “5” → "2"
After the pixel data of the 479th line is transmitted from the image transmission unit 100, the Y coordinate (line number) 2 is set for the address generation unit 103. Similarly, after the pixel data of the second line is transmitted again from the image transmission unit 100, the Y coordinate “5” is set to the address generation unit 103, and the pixel of the fifth line from the image transmission unit 100 is set. After the data is transmitted again, the Y coordinate “2” is set for the address generation unit 103. Pixel data for the second line is transmitted again from the image transmission unit 100. This eliminates all transfer errors.

As described above, according to the present embodiment, an error correction code such as a Hamming code is added to each pixel to greatly reduce the image transfer rate, and further, no complicated circuit such as an error correction unit is required. In addition, only the pixel data for which no transfer error has occurred can be stored in the frame memory. In addition, since the transfer rate does not decrease, the power consumption during image transfer can be reduced when transferring the same image as compared with the prior art.
(Embodiment 2)
In the first embodiment, when a transfer error occurs in any one line of pixel data sent from the line memory 105, the memory control unit 106 transfers the pixel data of that line to the frame memory 107. In the second embodiment, an example in which data is read from a line memory 105 that includes an error will be described.

  As described in the first embodiment, the line memory 105 is a FIFO memory. The pixel data sent from the error detection unit 102 is captured, and the pixel data is sequentially sent to the memory control unit 106. It is. These operations are performed in accordance with a write request from the error detection unit 102 and a read request from the memory control unit 106.

  FIG. 5 is a block diagram illustrating a configuration example of a part that generates a read request to the line memory 105 in the memory control unit 106a of the image display apparatus 110A according to the second embodiment.

  In FIG. 5, the memory control unit 106 a in the image display apparatus 110 </ b> A according to the second exemplary embodiment detects pixel data errors by the read request generation unit 61 that generates a read request (before masking) and the error detection unit 102. And a read request mask unit 62 for outputting a read request (after masking) masked by the error detection information.

  The read request generation unit 61 generates a read request (before masking) regardless of whether or not the pixel data written in the line memory 105 includes a transfer error pixel.

  In the read request mask unit 62, the read request (before masking) is masked by the error detection information sent from the error detection unit 102, and the result is read as a read request (after masking). Sent against.

  As a result, the line memory 105 does not read the data of the line where the pixel data in which the transfer error has occurred.

  At this time, using the fact that the number of pixels that can be stored in the line memory 105 is finite (here, 640 pixels), the error detection unit 102 applies the pixel data for which the data in the line memory 105 has not been read. By overwriting data, the error detection unit 102, the line memory 105, and the memory control unit 106 can match the data.

  As described above, according to the second embodiment, the memory control unit 106 performs control so that pixel data that should not be written to the frame memory 107 is not read from the line memory 105, thereby further reducing power consumption. Can be achieved.

(Embodiment 3)
In the first embodiment, when an error is detected in any of the received pixel data for one line, the information in the error coordinate storage unit in the address generation unit 103 is transmitted from the error transfer unit 104 to the image transmission unit 100. Sent to. Thereafter, the image transmission unit 100 transfers only the line where the transfer error has occurred. At this time, it is necessary to set “how many lines are to be transferred from now” to the Y coordinate counter unit 32. There is.
The coordinate conversion unit 33 generates an address to be written in the frame address based on the Y coordinate set in the Y coordinate counter unit 32. This makes it possible to correctly write to the frame memory 107 even with a skipped line.

  On the other hand, in the third embodiment, an example in which an address for the frame memory is generated based on the error detection information stored in the error coordinate storage unit 34 will be described.

  FIG. 6 is a block diagram illustrating a configuration example of the address generation unit according to the third embodiment.

  As described in the first embodiment, as shown in FIG. 1, as error detection information set as the Y coordinate of the address generation unit 103 by the image transmission unit 100, for example, line numbers “2” and “5” are And stored in the error coordinate storage unit 34 of the address generation unit 103.

The difference from the first embodiment is that the output end of the error coordinate storage unit 34 is connected to the coordinate conversion unit 33 in the address generation unit 103a of the image display device 110B of the third embodiment. Since the Y coordinate stored in the error coordinate storage unit 34 is used as an error occurrence line retransmitted from the image transmission unit 100 when a transfer error occurs, “how many lines will be transferred from now” It is not necessary to set again.
. In the same process, the output end of the error coordinate storage unit 34 is connected to the Y coordinate counter unit 32 to form a Y coordinate counter unit 32a, and the Y coordinate stored in the error coordinate storage unit 34 is changed to the Y coordinate. An address not written in the frame memory 107 can also be set by setting the counter unit 32a.

  As described above, according to the third embodiment, when a transfer error occurs, the address generation unit 103a uses the error detection information stored in itself to write an address to the frame memory 107 (line data is written to the frame memory 107). 2), it is not necessary to set the Y coordinate from the image transmission unit 100 to the address generation unit 103, and the load on the image transmission unit 100 and the amount of transfer data can be suppressed.

(Embodiment 4)
In the first embodiment, the example in which the address stored in the address generation unit 103 is transferred from the error transfer unit 104 to the image transmission unit 100 as error information and a rewrite request is made has been described. An example in which error information is not transferred from the error transfer unit 104 during image display will be described.

  FIG. 7 is a block diagram illustrating a configuration example of the image display apparatus according to the fourth embodiment.

  In FIG. 7, the image display device 110 </ b> C is provided with a moving image / still image setting unit 120, and the moving image / still image setting unit 120 includes an image output from the image transmission unit 100 as a moving image or a still image. It is set whether it is a picture. The moving image / still image selection information is sent to the error detection unit 102a.

  FIG. 8 is a block diagram illustrating a configuration example of the error detection unit 102a in the image display device 110C of FIG.

  In FIG. 8, the error detection unit 102 a includes an adder 21 as an adding unit that adds line data values, and a comparator 22 b as a comparing unit that does not output the comparison result only in the case of “moving image”. ing.

  In the adder 21, the value of the pixel data for one line is added as in the case of the first embodiment.

  In the comparator 22b, the addition result from the adder 21 is compared with the error detection data. If the moving image / still image selection information is “still image”, the comparison result is one as in the case of the first embodiment. If the transfer error has occurred in any of the received pixel data if not, the result is notified to the address generation unit 103. On the other hand, if the moving image / still image selection information is “moving image”, the comparison result is not output from the comparator 22b.

  As a result, pixel data is written to the frame memory 107 regardless of whether or not a transfer error has occurred.

  FIG. 9 is a block diagram illustrating another configuration example of the image display apparatus according to the fourth embodiment.

  In FIG. 9, the image display device 110D is also provided with a moving image / still image setting unit 120. In this moving image / still image setting unit 120, an image output from the image transmission unit 100 is a moving image or a still image. It is set whether it is a picture. This moving image / still image selection information is sent to the address generation unit 103b.

  FIG. 10 is a block diagram illustrating a configuration example of the address generation unit 103b in FIG.

  In FIG. 10, the address generation unit 103 b includes an X coordinate counter unit 31, a Y coordinate counter unit 32, a coordinate conversion unit 33, and an error coordinate conversion unit 34 b.

  In the error coordinate storage unit 34b, if the moving image / still image selection information is “still image”, the error information from the error detection unit 102 and the counter from the Y coordinate counter unit 32 are the same as in the first embodiment. Based on the value, the Y-direction coordinate where the transfer error has occurred is stored. On the other hand, if the moving image / still image selection information is “moving image”, the error coordinate storage unit 34b is controlled not to store the error coordinates.

  This prevents error information from being sent to the image transmission unit 100 regardless of whether or not a transfer error has occurred.

  The image display device 110D shown in FIG. 9 is different from the image display device 110C shown in FIG. 7 in that the image display device 110C shown in FIG. In the image display device 110D shown in FIG. 9, the data of the line where the transfer error has occurred is not written in the frame memory 107.

  In each example of the image display devices 110C and 110D shown in FIGS. 7 and 9 of the fourth embodiment, error information is sent to the image transmission unit 100 when a pixel transfer error occurs, regardless of which configuration is used. There is nothing. Further, it may be possible to select the configuration examples of FIGS. 7 and 9 according to the situation of the operator, but the description thereof is omitted here.

  Therefore, according to the fourth embodiment, even when an image transfer error occurs during the display of a moving image that requires real-time properties, the image transmission unit 100 is not notified of the transfer error, thereby enabling real-time image transfer. It is possible to prevent the loss of sex.

  As described above, according to the first to fourth embodiments, the image display devices 110 and 110A to 110D detect the transfer error and the image reception unit 101 that receives the image data and the error detection data from the image transmission unit 100. Error detectors 102 and 102a, a line memory 105 that stores received data in units of lines, a frame memory 107 that stores data stored in the line memory 105 in units of frames, and an address of the frame memory 107, and a transfer error Is detected, address generation units 103, 103a, 103b for storing the addresses, error transfer unit 104 for transferring the storage addresses of the address generation units 103, 103a, 103b to the image transmission unit 100 as error information, and a line A memory control unit 106 for controlling the memory and the frame memory The memory control unit 106, a line memory 105 when a transfer error is detected writing the data into the frame memory 107, does not perform the data writing into the frame memory 107 from the line memory 105 when a transfer error is detected. As a result, even if a pixel data transfer error occurs with a small amount of error detection data and a simple circuit configuration, it can be prevented from being displayed on the image display unit.

  In addition, as mentioned above, although this invention has been illustrated using preferable Embodiment 1-4 of this invention, this invention should not be limited and limited to this Embodiment 1-4. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range from the description of specific preferred embodiments 1 to 4 of the present invention based on the description of the present invention and the common general technical knowledge. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  The present invention relates to an image transfer device that transmits serial image data from an image transmission unit at a high speed and an image display device that displays an image on the image display unit using the image transfer device, and corrects errors such as a Hamming code for each pixel. Only pixel data in which no transfer error has occurred can be stored in the frame memory without adding a code to greatly reduce the image transfer rate and without requiring a complicated circuit such as an error correction unit. it can. In addition, since the transfer rate does not decrease, the power consumption during image transfer can be reduced when transferring the same image as compared with the prior art. Therefore, it is possible to transfer image data at high speed and with low power consumption by a serial bus access method with a small wiring area, and to perform high-quality image display with little image degradation due to transfer errors.

It is a block diagram which shows the principal part structural example of the image display apparatus which concerns on Embodiment 1 of this invention. FIG. 2 is a diagram illustrating a configuration example of pixel data (with line-unit error detection data CheckSum) transferred in a serial manner in the image display apparatus of FIG. 1. It is a block diagram which shows the principal part structure of the error detection part of FIG. FIG. 2 is a block diagram illustrating a main configuration of an address generation unit in FIG. 1. It is a block diagram which shows the principal part structural example of the memory control part in the image display apparatus which concerns on Embodiment 2 of this invention. It is a block diagram which shows the principal part structural example of the error detection part in the image display apparatus which concerns on Embodiment 3 of this invention. It is a block diagram which shows the principal part structural example of the image display apparatus which concerns on Embodiment 4 of this invention. FIG. 8 is a block diagram illustrating a configuration example of a main part of an error detection unit in FIG. 7. It is a block diagram which shows the other principal part structural example of the image display apparatus which concerns on Embodiment 4 of this invention. FIG. 10 is a block diagram illustrating an exemplary main configuration of an address generation unit in FIG. 9. (A) is a figure which shows the structure of the pixel data transferred by a parallel system, (b) is a figure which shows the structure of the pixel data (address mixture) transferred by a serial system, (c) is a serial system. (D) is a diagram showing a configuration of pixel data (with an error correction code) transferred in a serial manner, (E) is a figure which shows the structure of the pixel data (with an error detection code) transferred by a serial system. It is a block diagram which shows the principal part structure of the conventional image display apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Image transmission part 101 Image receiving part 102,102a Error detection part 21 Adder 22,22b Comparator 103,103a, 103b Address generation part 31 X coordinate counter part 32, 32a Y coordinate counter part 33 Coordinate conversion part 34, 34b Error Coordinate storage unit 104 Error transfer unit 105 Line memory 106, 106a Memory control unit 61 Read request generation unit 62 Read request mask unit 107 Frame memory 108 Image output unit 109 Image display unit 110, 110A to 110D Image display device 120 Movie / still image Setting section

Claims (15)

A data receiving unit for receiving serial pixel data transmitted from the data transmitting unit and error detection data added for each line;
An error detection unit that detects whether or not an error has occurred in the pixel data received by the data reception unit, using the error detection data;
Regardless of the presence or absence of the error, a line memory that stores the pixel data received by the data receiving unit in units of lines;
A frame memory for storing pixel data in the line memory in units of frames;
An address generation unit that generates an address for the frame memory, and stores the address of the line as error detection information when the error is detected in the pixel data in the line by the error detection unit;
An error transfer unit that transfers the error detection information in the address generation unit as error information to the data transmission unit side after pixel data of all lines is received;
The line memory and the frame memory are memory-controlled based on an address from the address generation unit, and the line data when the error is included in line data composed of pixel data for one line in the line memory. And a memory control unit that writes the line data to the frame memory when the error is not included. A data receiving unit for receiving serial pixel data transmitted from the data transmitting unit and error detection data added for each line;
An error detection unit that detects whether or not an error has occurred in the pixel data received by the data reception unit, using the error detection data;
Regardless of the presence or absence of the error, a line memory that stores the pixel data received by the data receiving unit in units of lines;
A frame memory for storing pixel data in the line memory in units of frames;
An address generation unit that generates an address for the frame memory, and stores the address of the line as error detection information when the error is detected in the pixel data in the line by the error detection unit;
An error transfer unit that transfers the error detection information in the address generation unit as error information to the data transmission unit side after pixel data of all lines is received;
The line memory and the frame memory are controlled on the basis of an address from the address generation unit, and the line memory includes the error when the line data including pixel data for one line in the line memory includes the error. And a memory control unit that reads the line data from the line memory and writes the line data to the frame memory when the line data is not read from the line memory and the error is not included.   The image transfer apparatus according to claim 1, wherein the error detection unit outputs the error detection information to the memory control unit when an error is detected in the line data for one line.   The memory control unit generates a read request for generating a read request for the line data to the line memory regardless of whether the line data includes an error; and the error detection for the read request. The image transfer apparatus according to claim 2, further comprising: a read request mask unit configured to perform masking with information and perform control so that line data including the error is not read.   5. The image transfer apparatus according to claim 2, wherein the memory control unit performs memory control so that data is overwritten on the line memory when the line data is not read from the line memory. 6. .   The error detection unit includes addition means for adding pixel data values for one line, and comparison means for comparing the addition result obtained by the addition means with the error detection data. The image transfer device according to claim 1, wherein an error is detected only when the detected data does not match.   The image transfer apparatus according to claim 1, wherein the line memory is a first-in first-out memory.   The address generation unit performs memory control on the frame memory or the line memory using address information transmitted from the data transmission unit side when an error is detected in the received pixel data. The image transfer device according to claim 1, wherein the image transfer device generates the image.   When an error is detected in the received pixel data, the address generation unit generates an address for performing memory control on the frame memory or the line memory using error detection information stored in the address data. The image transfer apparatus according to claim 1 or 2.   The image according to any one of claims 1, 2, 8, and 9, wherein the address generation unit sets a vertical coordinate and a horizontal coordinate as a start position and an end position at an address on the frame memory, respectively. Transfer device.   The address generation unit includes an X coordinate counter unit that counts the number of pixel data in the line direction as an X coordinate, a Y coordinate counter unit that counts a Y coordinate for each line of pixel data, and the counted X 2. A coordinate conversion unit that converts a two-dimensional coordinate composed of coordinates and the Y coordinate into a one-dimensional address, and an error coordinate storage unit that stores the Y coordinate where a transfer error has occurred as the error detection information. 2. The image transfer apparatus according to 2.   3. The apparatus according to claim 1, further comprising a moving image / still image setting unit, wherein the error transfer unit controls not to transfer the error information only when the moving image / still image setting unit sets a moving image. Image transfer device.   Only when the moving image / still image setting unit sets a moving image, the error detection unit is controlled not to perform error detection processing, or the address generation unit is not subjected to error detection information storage processing. The image transfer apparatus according to claim 12, which is controlled.   The data transmission unit transmits serial pixel data and error detection data added to each line to the data reception unit, and receives error information from the error transfer unit, and receives line data in which an error has occurred. The image transfer apparatus according to claim 1, which performs transmission processing again. An image transfer device according to any one of claims 1 to 14,
An image output unit for outputting pixel data stored in the frame memory of the image transfer device;
An image display device comprising: an image display unit configured to display an image on a display screen based on pixel data output from the image output unit.

Images